1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=powerpc64le-- | FileCheck %s
4 declare i8 @llvm.fshl.i8(i8, i8, i8)
5 declare i16 @llvm.fshl.i16(i16, i16, i16)
6 declare i32 @llvm.fshl.i32(i32, i32, i32)
7 declare i64 @llvm.fshl.i64(i64, i64, i64)
8 declare <4 x i32> @llvm.fshl.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
10 declare i8 @llvm.fshr.i8(i8, i8, i8)
11 declare i16 @llvm.fshr.i16(i16, i16, i16)
12 declare i32 @llvm.fshr.i32(i32, i32, i32)
13 declare i64 @llvm.fshr.i64(i64, i64, i64)
14 declare <4 x i32> @llvm.fshr.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
16 ; General case - all operands can be variables.
18 define i32 @fshl_i32(i32 %x, i32 %y, i32 %z) {
19 ; CHECK-LABEL: fshl_i32:
21 ; CHECK-NEXT: andi. 5, 5, 31
22 ; CHECK-NEXT: subfic 6, 5, 32
23 ; CHECK-NEXT: slw 5, 3, 5
24 ; CHECK-NEXT: srw 4, 4, 6
25 ; CHECK-NEXT: or 4, 5, 4
26 ; CHECK-NEXT: isel 3, 3, 4, 2
28 %f = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 %z)
32 ; Verify that weird types are minimally supported.
33 declare i37 @llvm.fshl.i37(i37, i37, i37)
34 define i37 @fshl_i37(i37 %x, i37 %y, i37 %z) {
35 ; CHECK-LABEL: fshl_i37:
37 ; CHECK-NEXT: lis 6, -8857
38 ; CHECK-NEXT: clrldi 5, 5, 27
39 ; CHECK-NEXT: ori 6, 6, 51366
40 ; CHECK-NEXT: clrldi 4, 4, 27
41 ; CHECK-NEXT: sldi 6, 6, 32
42 ; CHECK-NEXT: oris 6, 6, 3542
43 ; CHECK-NEXT: ori 6, 6, 31883
44 ; CHECK-NEXT: mulhdu 6, 5, 6
45 ; CHECK-NEXT: rldicl 6, 6, 59, 5
46 ; CHECK-NEXT: mulli 6, 6, 37
47 ; CHECK-NEXT: subf. 5, 6, 5
48 ; CHECK-NEXT: subfic 6, 5, 37
49 ; CHECK-NEXT: sld 5, 3, 5
50 ; CHECK-NEXT: srd 4, 4, 6
51 ; CHECK-NEXT: or 4, 5, 4
52 ; CHECK-NEXT: isel 3, 3, 4, 2
54 %f = call i37 @llvm.fshl.i37(i37 %x, i37 %y, i37 %z)
58 ; extract(concat(0b1110000, 0b1111111) << 2) = 0b1000011
60 declare i7 @llvm.fshl.i7(i7, i7, i7)
61 define i7 @fshl_i7_const_fold() {
62 ; CHECK-LABEL: fshl_i7_const_fold:
64 ; CHECK-NEXT: li 3, 67
66 %f = call i7 @llvm.fshl.i7(i7 112, i7 127, i7 2)
70 ; With constant shift amount, this is rotate + insert (missing extended mnemonics).
72 define i32 @fshl_i32_const_shift(i32 %x, i32 %y) {
73 ; CHECK-LABEL: fshl_i32_const_shift:
75 ; CHECK-NEXT: rlwinm 4, 4, 9, 0, 31
76 ; CHECK-NEXT: rlwimi 4, 3, 9, 0, 22
79 %f = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 9)
83 ; Check modulo math on shift amount.
85 define i32 @fshl_i32_const_overshift(i32 %x, i32 %y) {
86 ; CHECK-LABEL: fshl_i32_const_overshift:
88 ; CHECK-NEXT: rlwinm 4, 4, 9, 0, 31
89 ; CHECK-NEXT: rlwimi 4, 3, 9, 0, 22
92 %f = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 41)
96 ; 64-bit should also work.
98 define i64 @fshl_i64_const_overshift(i64 %x, i64 %y) {
99 ; CHECK-LABEL: fshl_i64_const_overshift:
101 ; CHECK-NEXT: rotldi 4, 4, 41
102 ; CHECK-NEXT: rldimi 4, 3, 41, 0
103 ; CHECK-NEXT: mr 3, 4
105 %f = call i64 @llvm.fshl.i64(i64 %x, i64 %y, i64 105)
109 ; This should work without any node-specific logic.
111 define i8 @fshl_i8_const_fold() {
112 ; CHECK-LABEL: fshl_i8_const_fold:
114 ; CHECK-NEXT: li 3, 128
116 %f = call i8 @llvm.fshl.i8(i8 255, i8 0, i8 7)
120 ; Repeat everything for funnel shift right.
122 ; General case - all operands can be variables.
124 define i32 @fshr_i32(i32 %x, i32 %y, i32 %z) {
125 ; CHECK-LABEL: fshr_i32:
127 ; CHECK-NEXT: andi. 5, 5, 31
128 ; CHECK-NEXT: subfic 6, 5, 32
129 ; CHECK-NEXT: srw 5, 4, 5
130 ; CHECK-NEXT: slw 3, 3, 6
131 ; CHECK-NEXT: or 3, 3, 5
132 ; CHECK-NEXT: isel 3, 4, 3, 2
134 %f = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 %z)
138 ; Verify that weird types are minimally supported.
139 declare i37 @llvm.fshr.i37(i37, i37, i37)
140 define i37 @fshr_i37(i37 %x, i37 %y, i37 %z) {
141 ; CHECK-LABEL: fshr_i37:
143 ; CHECK-NEXT: lis 6, -8857
144 ; CHECK-NEXT: clrldi 5, 5, 27
145 ; CHECK-NEXT: ori 6, 6, 51366
146 ; CHECK-NEXT: sldi 6, 6, 32
147 ; CHECK-NEXT: oris 6, 6, 3542
148 ; CHECK-NEXT: ori 6, 6, 31883
149 ; CHECK-NEXT: mulhdu 6, 5, 6
150 ; CHECK-NEXT: rldicl 6, 6, 59, 5
151 ; CHECK-NEXT: mulli 6, 6, 37
152 ; CHECK-NEXT: subf. 5, 6, 5
153 ; CHECK-NEXT: clrldi 6, 4, 27
154 ; CHECK-NEXT: subfic 7, 5, 37
155 ; CHECK-NEXT: srd 5, 6, 5
156 ; CHECK-NEXT: sld 3, 3, 7
157 ; CHECK-NEXT: or 3, 3, 5
158 ; CHECK-NEXT: isel 3, 4, 3, 2
160 %f = call i37 @llvm.fshr.i37(i37 %x, i37 %y, i37 %z)
164 ; extract(concat(0b1110000, 0b1111111) >> 2) = 0b0011111
166 declare i7 @llvm.fshr.i7(i7, i7, i7)
167 define i7 @fshr_i7_const_fold() {
168 ; CHECK-LABEL: fshr_i7_const_fold:
170 ; CHECK-NEXT: li 3, 31
172 %f = call i7 @llvm.fshr.i7(i7 112, i7 127, i7 2)
176 ; With constant shift amount, this is rotate + insert (missing extended mnemonics).
178 define i32 @fshr_i32_const_shift(i32 %x, i32 %y) {
179 ; CHECK-LABEL: fshr_i32_const_shift:
181 ; CHECK-NEXT: rlwinm 4, 4, 23, 0, 31
182 ; CHECK-NEXT: rlwimi 4, 3, 23, 0, 8
183 ; CHECK-NEXT: mr 3, 4
185 %f = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 9)
189 ; Check modulo math on shift amount. 41-32=9.
191 define i32 @fshr_i32_const_overshift(i32 %x, i32 %y) {
192 ; CHECK-LABEL: fshr_i32_const_overshift:
194 ; CHECK-NEXT: rlwinm 4, 4, 23, 0, 31
195 ; CHECK-NEXT: rlwimi 4, 3, 23, 0, 8
196 ; CHECK-NEXT: mr 3, 4
198 %f = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 41)
202 ; 64-bit should also work. 105-64 = 41.
204 define i64 @fshr_i64_const_overshift(i64 %x, i64 %y) {
205 ; CHECK-LABEL: fshr_i64_const_overshift:
207 ; CHECK-NEXT: rotldi 4, 4, 23
208 ; CHECK-NEXT: rldimi 4, 3, 23, 0
209 ; CHECK-NEXT: mr 3, 4
211 %f = call i64 @llvm.fshr.i64(i64 %x, i64 %y, i64 105)
215 ; This should work without any node-specific logic.
217 define i8 @fshr_i8_const_fold() {
218 ; CHECK-LABEL: fshr_i8_const_fold:
220 ; CHECK-NEXT: li 3, 254
222 %f = call i8 @llvm.fshr.i8(i8 255, i8 0, i8 7)
226 define i32 @fshl_i32_shift_by_bitwidth(i32 %x, i32 %y) {
227 ; CHECK-LABEL: fshl_i32_shift_by_bitwidth:
230 %f = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 32)
234 define i32 @fshr_i32_shift_by_bitwidth(i32 %x, i32 %y) {
235 ; CHECK-LABEL: fshr_i32_shift_by_bitwidth:
237 ; CHECK-NEXT: mr 3, 4
239 %f = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 32)
243 define <4 x i32> @fshl_v4i32_shift_by_bitwidth(<4 x i32> %x, <4 x i32> %y) {
244 ; CHECK-LABEL: fshl_v4i32_shift_by_bitwidth:
247 %f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 32, i32 32, i32 32, i32 32>)
251 define <4 x i32> @fshr_v4i32_shift_by_bitwidth(<4 x i32> %x, <4 x i32> %y) {
252 ; CHECK-LABEL: fshr_v4i32_shift_by_bitwidth:
254 ; CHECK-NEXT: vmr 2, 3
256 %f = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 32, i32 32, i32 32, i32 32>)