1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
3 ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names \
4 ; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s
5 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
6 ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names \
7 ; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE
9 ; Test reduce scalarization in fpext v2f32 to v2f64 from the extract_subvector v4f32 node.
11 define dso_local void @test(<4 x float>* nocapture readonly %a, <2 x double>* nocapture %b, <2 x double>* nocapture %c) {
13 ; CHECK: # %bb.0: # %entry
14 ; CHECK-NEXT: lxv vs0, 0(r3)
15 ; CHECK-NEXT: xxmrglw vs1, vs0, vs0
16 ; CHECK-NEXT: xxmrghw vs0, vs0, vs0
17 ; CHECK-NEXT: xvcvspdp vs1, vs1
18 ; CHECK-NEXT: xvcvspdp vs0, vs0
19 ; CHECK-NEXT: stxv vs1, 0(r4)
20 ; CHECK-NEXT: stxv vs0, 0(r5)
23 ; CHECK-BE-LABEL: test:
24 ; CHECK-BE: # %bb.0: # %entry
25 ; CHECK-BE-NEXT: lxv vs0, 0(r3)
26 ; CHECK-BE-NEXT: xxmrghw vs1, vs0, vs0
27 ; CHECK-BE-NEXT: xxmrglw vs0, vs0, vs0
28 ; CHECK-BE-NEXT: xvcvspdp vs1, vs1
29 ; CHECK-BE-NEXT: xvcvspdp vs0, vs0
30 ; CHECK-BE-NEXT: stxv vs1, 0(r4)
31 ; CHECK-BE-NEXT: stxv vs0, 0(r5)
34 %0 = load <4 x float>, <4 x float>* %a, align 16
35 %shuffle = shufflevector <4 x float> %0, <4 x float> undef, <2 x i32> <i32 0, i32 1>
36 %shuffle1 = shufflevector <4 x float> %0, <4 x float> undef, <2 x i32> <i32 2, i32 3>
37 %vecinit4 = fpext <2 x float> %shuffle to <2 x double>
38 %vecinit11 = fpext <2 x float> %shuffle1 to <2 x double>
39 store <2 x double> %vecinit4, <2 x double>* %b, align 16
40 store <2 x double> %vecinit11, <2 x double>* %c, align 16
44 ; Ensure we don't crash for wider types
46 define dso_local void @test2(<16 x float>* nocapture readonly %a, <2 x double>* nocapture %b, <2 x double>* nocapture %c) {
48 ; CHECK: # %bb.0: # %entry
49 ; CHECK-NEXT: lxv vs0, 0(r3)
50 ; CHECK-NEXT: xxsldwi vs1, vs0, vs0, 1
51 ; CHECK-NEXT: xscvspdpn f2, vs0
52 ; CHECK-NEXT: xxsldwi vs3, vs0, vs0, 3
53 ; CHECK-NEXT: xxswapd vs0, vs0
54 ; CHECK-NEXT: xscvspdpn f1, vs1
55 ; CHECK-NEXT: xscvspdpn f3, vs3
56 ; CHECK-NEXT: xscvspdpn f0, vs0
57 ; CHECK-NEXT: xxmrghd vs0, vs0, vs3
58 ; CHECK-NEXT: xxmrghd vs1, vs2, vs1
59 ; CHECK-NEXT: stxv vs0, 0(r4)
60 ; CHECK-NEXT: stxv vs1, 0(r5)
63 ; CHECK-BE-LABEL: test2:
64 ; CHECK-BE: # %bb.0: # %entry
65 ; CHECK-BE-NEXT: lxv vs0, 0(r3)
66 ; CHECK-BE-NEXT: xxswapd vs1, vs0
67 ; CHECK-BE-NEXT: xxsldwi vs2, vs0, vs0, 3
68 ; CHECK-BE-NEXT: xscvspdpn f3, vs0
69 ; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
70 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
71 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
72 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
73 ; CHECK-BE-NEXT: xxmrghd vs0, vs3, vs0
74 ; CHECK-BE-NEXT: xxmrghd vs1, vs1, vs2
75 ; CHECK-BE-NEXT: stxv vs0, 0(r4)
76 ; CHECK-BE-NEXT: stxv vs1, 0(r5)
79 %0 = load <16 x float>, <16 x float>* %a, align 16
80 %shuffle = shufflevector <16 x float> %0, <16 x float> undef, <2 x i32> <i32 0, i32 1>
81 %shuffle1 = shufflevector <16 x float> %0, <16 x float> undef, <2 x i32> <i32 2, i32 3>
82 %vecinit4 = fpext <2 x float> %shuffle to <2 x double>
83 %vecinit11 = fpext <2 x float> %shuffle1 to <2 x double>
84 store <2 x double> %vecinit4, <2 x double>* %b, align 16
85 store <2 x double> %vecinit11, <2 x double>* %c, align 16