| blob | 9e87876f81f15c0a778c562385cefae80fefc889 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
3 ; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
4 ; RUN: FileCheck %s --check-prefix=CHECK-P8
5 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
6 ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
7 ; RUN: FileCheck %s --check-prefix=CHECK-P9
8 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
9 ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
10 ; RUN: FileCheck %s --check-prefix=CHECK-BE
12 define i32 @test2elt(<2 x double> %a) local_unnamed_addr #0 {
13 ; CHECK-P8-LABEL: test2elt:
14 ; CHECK-P8: # %bb.0: # %entry
15 ; CHECK-P8-NEXT: xxswapd vs0, v2
16 ; CHECK-P8-NEXT: xscvdpsxws f1, v2
17 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
18 ; CHECK-P8-NEXT: mfvsrwz r3, f1
19 ; CHECK-P8-NEXT: mfvsrwz r4, f0
20 ; CHECK-P8-NEXT: mtvsrd f0, r3
21 ; CHECK-P8-NEXT: mtvsrd f1, r4
22 ; CHECK-P8-NEXT: xxswapd v2, vs0
23 ; CHECK-P8-NEXT: xxswapd v3, vs1
24 ; CHECK-P8-NEXT: vmrglh v2, v2, v3
25 ; CHECK-P8-NEXT: xxswapd vs0, v2
26 ; CHECK-P8-NEXT: mfvsrwz r3, f0
27 ; CHECK-P8-NEXT: blr
28 ;
29 ; CHECK-P9-LABEL: test2elt:
30 ; CHECK-P9: # %bb.0: # %entry
31 ; CHECK-P9-NEXT: xscvdpsxws f0, v2
32 ; CHECK-P9-NEXT: mfvsrwz r3, f0
33 ; CHECK-P9-NEXT: mtvsrd f0, r3
34 ; CHECK-P9-NEXT: xxswapd v3, vs0
35 ; CHECK-P9-NEXT: xxswapd vs0, v2
36 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
37 ; CHECK-P9-NEXT: mfvsrwz r3, f0
38 ; CHECK-P9-NEXT: mtvsrd f0, r3
39 ; CHECK-P9-NEXT: li r3, 0
40 ; CHECK-P9-NEXT: xxswapd v2, vs0
41 ; CHECK-P9-NEXT: vmrglh v2, v3, v2
42 ; CHECK-P9-NEXT: vextuwrx r3, r3, v2
43 ; CHECK-P9-NEXT: blr
44 ;
45 ; CHECK-BE-LABEL: test2elt:
46 ; CHECK-BE: # %bb.0: # %entry
47 ; CHECK-BE-NEXT: xscvdpsxws f0, v2
48 ; CHECK-BE-NEXT: mfvsrwz r3, f0
49 ; CHECK-BE-NEXT: xxswapd vs0, v2
50 ; CHECK-BE-NEXT: sldi r3, r3, 48
51 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
52 ; CHECK-BE-NEXT: mtvsrd v3, r3
53 ; CHECK-BE-NEXT: mfvsrwz r3, f0
54 ; CHECK-BE-NEXT: sldi r3, r3, 48
55 ; CHECK-BE-NEXT: mtvsrd v2, r3
56 ; CHECK-BE-NEXT: li r3, 0
57 ; CHECK-BE-NEXT: vmrghh v2, v3, v2
58 ; CHECK-BE-NEXT: vextuwlx r3, r3, v2
59 ; CHECK-BE-NEXT: blr
60 entry:
61 %0 = fptoui <2 x double> %a to <2 x i16>
62 %1 = bitcast <2 x i16> %0 to i32
63 ret i32 %1
64 }
66 define i64 @test4elt(<4 x double>* nocapture readonly) local_unnamed_addr #1 {
67 ; CHECK-P8-LABEL: test4elt:
68 ; CHECK-P8: # %bb.0: # %entry
69 ; CHECK-P8-NEXT: li r4, 16
70 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
71 ; CHECK-P8-NEXT: lxvd2x vs1, r3, r4
72 ; CHECK-P8-NEXT: xscvdpsxws f2, f0
73 ; CHECK-P8-NEXT: xxswapd vs0, vs0
74 ; CHECK-P8-NEXT: xscvdpsxws f3, f1
75 ; CHECK-P8-NEXT: xxswapd vs1, vs1
76 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
77 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
78 ; CHECK-P8-NEXT: mfvsrwz r3, f2
79 ; CHECK-P8-NEXT: mfvsrwz r4, f3
80 ; CHECK-P8-NEXT: mtvsrd f2, r3
81 ; CHECK-P8-NEXT: mtvsrd f3, r4
82 ; CHECK-P8-NEXT: mfvsrwz r3, f0
83 ; CHECK-P8-NEXT: xxswapd v2, vs2
84 ; CHECK-P8-NEXT: mfvsrwz r4, f1
85 ; CHECK-P8-NEXT: xxswapd v4, vs3
86 ; CHECK-P8-NEXT: mtvsrd f0, r3
87 ; CHECK-P8-NEXT: mtvsrd f1, r4
88 ; CHECK-P8-NEXT: xxswapd v3, vs0
89 ; CHECK-P8-NEXT: xxswapd v5, vs1
90 ; CHECK-P8-NEXT: vmrglh v2, v3, v2
91 ; CHECK-P8-NEXT: vmrglh v3, v5, v4
92 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
93 ; CHECK-P8-NEXT: xxswapd vs0, v2
94 ; CHECK-P8-NEXT: mfvsrd r3, f0
95 ; CHECK-P8-NEXT: blr
96 ;
97 ; CHECK-P9-LABEL: test4elt:
98 ; CHECK-P9: # %bb.0: # %entry
99 ; CHECK-P9-NEXT: lxv vs1, 0(r3)
100 ; CHECK-P9-NEXT: xscvdpsxws f2, f1
101 ; CHECK-P9-NEXT: xxswapd vs1, vs1
102 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
103 ; CHECK-P9-NEXT: lxv vs0, 16(r3)
104 ; CHECK-P9-NEXT: mfvsrwz r3, f2
105 ; CHECK-P9-NEXT: mtvsrd f2, r3
106 ; CHECK-P9-NEXT: mfvsrwz r3, f1
107 ; CHECK-P9-NEXT: xxswapd v2, vs2
108 ; CHECK-P9-NEXT: mtvsrd f1, r3
109 ; CHECK-P9-NEXT: xxswapd v3, vs1
110 ; CHECK-P9-NEXT: xscvdpsxws f1, f0
111 ; CHECK-P9-NEXT: xxswapd vs0, vs0
112 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
113 ; CHECK-P9-NEXT: mfvsrwz r3, f1
114 ; CHECK-P9-NEXT: mtvsrd f1, r3
115 ; CHECK-P9-NEXT: mfvsrwz r3, f0
116 ; CHECK-P9-NEXT: mtvsrd f0, r3
117 ; CHECK-P9-NEXT: vmrglh v2, v2, v3
118 ; CHECK-P9-NEXT: xxswapd v3, vs1
119 ; CHECK-P9-NEXT: xxswapd v4, vs0
120 ; CHECK-P9-NEXT: vmrglh v3, v3, v4
121 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
122 ; CHECK-P9-NEXT: mfvsrld r3, v2
123 ; CHECK-P9-NEXT: blr
124 ;
125 ; CHECK-BE-LABEL: test4elt:
126 ; CHECK-BE: # %bb.0: # %entry
127 ; CHECK-BE-NEXT: lxv vs1, 16(r3)
128 ; CHECK-BE-NEXT: xscvdpsxws f2, f1
129 ; CHECK-BE-NEXT: xxswapd vs1, vs1
130 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
131 ; CHECK-BE-NEXT: lxv vs0, 0(r3)
132 ; CHECK-BE-NEXT: mfvsrwz r3, f2
133 ; CHECK-BE-NEXT: sldi r3, r3, 48
134 ; CHECK-BE-NEXT: mtvsrd v2, r3
135 ; CHECK-BE-NEXT: mfvsrwz r3, f1
136 ; CHECK-BE-NEXT: xscvdpsxws f1, f0
137 ; CHECK-BE-NEXT: xxswapd vs0, vs0
138 ; CHECK-BE-NEXT: sldi r3, r3, 48
139 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
140 ; CHECK-BE-NEXT: mtvsrd v3, r3
141 ; CHECK-BE-NEXT: vmrghh v2, v2, v3
142 ; CHECK-BE-NEXT: mfvsrwz r3, f1
143 ; CHECK-BE-NEXT: sldi r3, r3, 48
144 ; CHECK-BE-NEXT: mtvsrd v3, r3
145 ; CHECK-BE-NEXT: mfvsrwz r3, f0
146 ; CHECK-BE-NEXT: sldi r3, r3, 48
147 ; CHECK-BE-NEXT: mtvsrd v4, r3
148 ; CHECK-BE-NEXT: vmrghh v3, v3, v4
149 ; CHECK-BE-NEXT: vmrghw v2, v3, v2
150 ; CHECK-BE-NEXT: mfvsrd r3, v2
151 ; CHECK-BE-NEXT: blr
152 entry:
153 %a = load <4 x double>, <4 x double>* %0, align 32
154 %1 = fptoui <4 x double> %a to <4 x i16>
155 %2 = bitcast <4 x i16> %1 to i64
156 ret i64 %2
157 }
159 define <8 x i16> @test8elt(<8 x double>* nocapture readonly) local_unnamed_addr #2 {
160 ; CHECK-P8-LABEL: test8elt:
161 ; CHECK-P8: # %bb.0: # %entry
162 ; CHECK-P8-NEXT: li r4, 16
163 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
164 ; CHECK-P8-NEXT: lxvd2x vs1, r3, r4
165 ; CHECK-P8-NEXT: li r4, 32
166 ; CHECK-P8-NEXT: lxvd2x vs2, r3, r4
167 ; CHECK-P8-NEXT: li r4, 48
168 ; CHECK-P8-NEXT: lxvd2x vs3, r3, r4
169 ; CHECK-P8-NEXT: xscvdpsxws f4, f0
170 ; CHECK-P8-NEXT: xxswapd vs0, vs0
171 ; CHECK-P8-NEXT: xscvdpsxws f5, f1
172 ; CHECK-P8-NEXT: xxswapd vs1, vs1
173 ; CHECK-P8-NEXT: xscvdpsxws f6, f2
174 ; CHECK-P8-NEXT: xxswapd vs2, vs2
175 ; CHECK-P8-NEXT: xscvdpsxws f7, f3
176 ; CHECK-P8-NEXT: xxswapd vs3, vs3
177 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
178 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
179 ; CHECK-P8-NEXT: mfvsrwz r3, f4
180 ; CHECK-P8-NEXT: xscvdpsxws f2, f2
181 ; CHECK-P8-NEXT: xscvdpsxws f3, f3
182 ; CHECK-P8-NEXT: mfvsrwz r4, f5
183 ; CHECK-P8-NEXT: mtvsrd f4, r3
184 ; CHECK-P8-NEXT: mfvsrwz r3, f6
185 ; CHECK-P8-NEXT: mtvsrd f5, r4
186 ; CHECK-P8-NEXT: xxswapd v2, vs4
187 ; CHECK-P8-NEXT: mfvsrwz r4, f7
188 ; CHECK-P8-NEXT: mtvsrd f6, r3
189 ; CHECK-P8-NEXT: xxswapd v3, vs5
190 ; CHECK-P8-NEXT: mfvsrwz r3, f0
191 ; CHECK-P8-NEXT: mtvsrd f7, r4
192 ; CHECK-P8-NEXT: xxswapd v4, vs6
193 ; CHECK-P8-NEXT: mfvsrwz r4, f1
194 ; CHECK-P8-NEXT: mtvsrd f0, r3
195 ; CHECK-P8-NEXT: xxswapd v1, vs7
196 ; CHECK-P8-NEXT: mfvsrwz r3, f2
197 ; CHECK-P8-NEXT: mtvsrd f1, r4
198 ; CHECK-P8-NEXT: xxswapd v5, vs0
199 ; CHECK-P8-NEXT: mfvsrwz r4, f3
200 ; CHECK-P8-NEXT: mtvsrd f2, r3
201 ; CHECK-P8-NEXT: xxswapd v0, vs1
202 ; CHECK-P8-NEXT: mtvsrd f0, r4
203 ; CHECK-P8-NEXT: xxswapd v6, vs2
204 ; CHECK-P8-NEXT: vmrglh v2, v5, v2
205 ; CHECK-P8-NEXT: xxswapd v5, vs0
206 ; CHECK-P8-NEXT: vmrglh v3, v0, v3
207 ; CHECK-P8-NEXT: vmrglh v4, v6, v4
208 ; CHECK-P8-NEXT: vmrglh v5, v5, v1
209 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
210 ; CHECK-P8-NEXT: vmrglw v3, v5, v4
211 ; CHECK-P8-NEXT: xxmrgld v2, v3, v2
212 ; CHECK-P8-NEXT: blr
213 ;
214 ; CHECK-P9-LABEL: test8elt:
215 ; CHECK-P9: # %bb.0: # %entry
216 ; CHECK-P9-NEXT: lxv vs3, 0(r3)
217 ; CHECK-P9-NEXT: xscvdpsxws f4, f3
218 ; CHECK-P9-NEXT: xxswapd vs3, vs3
219 ; CHECK-P9-NEXT: xscvdpsxws f3, f3
220 ; CHECK-P9-NEXT: lxv vs0, 48(r3)
221 ; CHECK-P9-NEXT: lxv vs1, 32(r3)
222 ; CHECK-P9-NEXT: lxv vs2, 16(r3)
223 ; CHECK-P9-NEXT: mfvsrwz r3, f4
224 ; CHECK-P9-NEXT: mtvsrd f4, r3
225 ; CHECK-P9-NEXT: mfvsrwz r3, f3
226 ; CHECK-P9-NEXT: xxswapd v2, vs4
227 ; CHECK-P9-NEXT: mtvsrd f3, r3
228 ; CHECK-P9-NEXT: xxswapd v3, vs3
229 ; CHECK-P9-NEXT: xscvdpsxws f3, f2
230 ; CHECK-P9-NEXT: xxswapd vs2, vs2
231 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
232 ; CHECK-P9-NEXT: mfvsrwz r3, f3
233 ; CHECK-P9-NEXT: mtvsrd f3, r3
234 ; CHECK-P9-NEXT: mfvsrwz r3, f2
235 ; CHECK-P9-NEXT: mtvsrd f2, r3
236 ; CHECK-P9-NEXT: xxswapd v4, vs2
237 ; CHECK-P9-NEXT: xscvdpsxws f2, f1
238 ; CHECK-P9-NEXT: xxswapd vs1, vs1
239 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
240 ; CHECK-P9-NEXT: mfvsrwz r3, f2
241 ; CHECK-P9-NEXT: mtvsrd f2, r3
242 ; CHECK-P9-NEXT: mfvsrwz r3, f1
243 ; CHECK-P9-NEXT: vmrglh v2, v2, v3
244 ; CHECK-P9-NEXT: xxswapd v3, vs3
245 ; CHECK-P9-NEXT: vmrglh v3, v3, v4
246 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
247 ; CHECK-P9-NEXT: xxswapd v3, vs2
248 ; CHECK-P9-NEXT: mtvsrd f1, r3
249 ; CHECK-P9-NEXT: xxswapd v4, vs1
250 ; CHECK-P9-NEXT: xscvdpsxws f1, f0
251 ; CHECK-P9-NEXT: xxswapd vs0, vs0
252 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
253 ; CHECK-P9-NEXT: mfvsrwz r3, f1
254 ; CHECK-P9-NEXT: mtvsrd f1, r3
255 ; CHECK-P9-NEXT: mfvsrwz r3, f0
256 ; CHECK-P9-NEXT: mtvsrd f0, r3
257 ; CHECK-P9-NEXT: vmrglh v3, v3, v4
258 ; CHECK-P9-NEXT: xxswapd v4, vs1
259 ; CHECK-P9-NEXT: xxswapd v5, vs0
260 ; CHECK-P9-NEXT: vmrglh v4, v4, v5
261 ; CHECK-P9-NEXT: vmrglw v3, v4, v3
262 ; CHECK-P9-NEXT: xxmrgld v2, v3, v2
263 ; CHECK-P9-NEXT: blr
264 ;
265 ; CHECK-BE-LABEL: test8elt:
266 ; CHECK-BE: # %bb.0: # %entry
267 ; CHECK-BE-NEXT: lxv vs3, 48(r3)
268 ; CHECK-BE-NEXT: xscvdpsxws f4, f3
269 ; CHECK-BE-NEXT: xxswapd vs3, vs3
270 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
271 ; CHECK-BE-NEXT: lxv vs2, 32(r3)
272 ; CHECK-BE-NEXT: lxv vs0, 0(r3)
273 ; CHECK-BE-NEXT: lxv vs1, 16(r3)
274 ; CHECK-BE-NEXT: mfvsrwz r3, f4
275 ; CHECK-BE-NEXT: sldi r3, r3, 48
276 ; CHECK-BE-NEXT: mtvsrd v2, r3
277 ; CHECK-BE-NEXT: mfvsrwz r3, f3
278 ; CHECK-BE-NEXT: xscvdpsxws f3, f2
279 ; CHECK-BE-NEXT: xxswapd vs2, vs2
280 ; CHECK-BE-NEXT: sldi r3, r3, 48
281 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
282 ; CHECK-BE-NEXT: mtvsrd v3, r3
283 ; CHECK-BE-NEXT: vmrghh v2, v2, v3
284 ; CHECK-BE-NEXT: mfvsrwz r3, f3
285 ; CHECK-BE-NEXT: sldi r3, r3, 48
286 ; CHECK-BE-NEXT: mtvsrd v3, r3
287 ; CHECK-BE-NEXT: mfvsrwz r3, f2
288 ; CHECK-BE-NEXT: xscvdpsxws f2, f1
289 ; CHECK-BE-NEXT: xxswapd vs1, vs1
290 ; CHECK-BE-NEXT: sldi r3, r3, 48
291 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
292 ; CHECK-BE-NEXT: mtvsrd v4, r3
293 ; CHECK-BE-NEXT: vmrghh v3, v3, v4
294 ; CHECK-BE-NEXT: mfvsrwz r3, f2
295 ; CHECK-BE-NEXT: sldi r3, r3, 48
296 ; CHECK-BE-NEXT: vmrghw v2, v3, v2
297 ; CHECK-BE-NEXT: mtvsrd v3, r3
298 ; CHECK-BE-NEXT: mfvsrwz r3, f1
299 ; CHECK-BE-NEXT: xscvdpsxws f1, f0
300 ; CHECK-BE-NEXT: xxswapd vs0, vs0
301 ; CHECK-BE-NEXT: sldi r3, r3, 48
302 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
303 ; CHECK-BE-NEXT: mtvsrd v4, r3
304 ; CHECK-BE-NEXT: vmrghh v3, v3, v4
305 ; CHECK-BE-NEXT: mfvsrwz r3, f1
306 ; CHECK-BE-NEXT: sldi r3, r3, 48
307 ; CHECK-BE-NEXT: mtvsrd v4, r3
308 ; CHECK-BE-NEXT: mfvsrwz r3, f0
309 ; CHECK-BE-NEXT: sldi r3, r3, 48
310 ; CHECK-BE-NEXT: mtvsrd v5, r3
311 ; CHECK-BE-NEXT: vmrghh v4, v4, v5
312 ; CHECK-BE-NEXT: vmrghw v3, v4, v3
313 ; CHECK-BE-NEXT: xxmrghd v2, v3, v2
314 ; CHECK-BE-NEXT: blr
315 entry:
316 %a = load <8 x double>, <8 x double>* %0, align 64
317 %1 = fptoui <8 x double> %a to <8 x i16>
318 ret <8 x i16> %1
319 }
321 define void @test16elt(<16 x i16>* noalias nocapture sret %agg.result, <16 x double>* nocapture readonly) local_unnamed_addr #3 {
322 ; CHECK-P8-LABEL: test16elt:
323 ; CHECK-P8: # %bb.0: # %entry
324 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
325 ; CHECK-P8-NEXT: li r5, 16
326 ; CHECK-P8-NEXT: li r6, 32
327 ; CHECK-P8-NEXT: lxvd2x vs1, r4, r5
328 ; CHECK-P8-NEXT: lxvd2x vs2, r4, r6
329 ; CHECK-P8-NEXT: li r6, 48
330 ; CHECK-P8-NEXT: lxvd2x vs3, r4, r6
331 ; CHECK-P8-NEXT: li r6, 64
332 ; CHECK-P8-NEXT: xscvdpsxws f4, f0
333 ; CHECK-P8-NEXT: lxvd2x vs5, r4, r6
334 ; CHECK-P8-NEXT: li r6, 80
335 ; CHECK-P8-NEXT: xxswapd vs0, vs0
336 ; CHECK-P8-NEXT: xscvdpsxws f6, f1
337 ; CHECK-P8-NEXT: lxvd2x vs7, r4, r6
338 ; CHECK-P8-NEXT: li r6, 96
339 ; CHECK-P8-NEXT: xxswapd vs1, vs1
340 ; CHECK-P8-NEXT: xscvdpsxws f8, f2
341 ; CHECK-P8-NEXT: lxvd2x vs9, r4, r6
342 ; CHECK-P8-NEXT: li r6, 112
343 ; CHECK-P8-NEXT: xxswapd vs2, vs2
344 ; CHECK-P8-NEXT: xscvdpsxws f10, f3
345 ; CHECK-P8-NEXT: lxvd2x vs11, r4, r6
346 ; CHECK-P8-NEXT: xxswapd vs3, vs3
347 ; CHECK-P8-NEXT: xscvdpsxws f12, f5
348 ; CHECK-P8-NEXT: xxswapd vs5, vs5
349 ; CHECK-P8-NEXT: xscvdpsxws f13, f7
350 ; CHECK-P8-NEXT: xxswapd vs7, vs7
351 ; CHECK-P8-NEXT: xscvdpsxws v2, f9
352 ; CHECK-P8-NEXT: xxswapd vs9, vs9
353 ; CHECK-P8-NEXT: mfvsrwz r4, f4
354 ; CHECK-P8-NEXT: xscvdpsxws v3, f11
355 ; CHECK-P8-NEXT: xxswapd vs11, vs11
356 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
357 ; CHECK-P8-NEXT: mfvsrwz r6, f6
358 ; CHECK-P8-NEXT: mtvsrd f4, r4
359 ; CHECK-P8-NEXT: mfvsrwz r4, f8
360 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
361 ; CHECK-P8-NEXT: xxswapd v4, vs4
362 ; CHECK-P8-NEXT: xscvdpsxws f2, f2
363 ; CHECK-P8-NEXT: mtvsrd f6, r6
364 ; CHECK-P8-NEXT: mfvsrwz r6, f10
365 ; CHECK-P8-NEXT: mtvsrd f8, r4
366 ; CHECK-P8-NEXT: xxswapd v5, vs6
367 ; CHECK-P8-NEXT: mfvsrwz r4, f12
368 ; CHECK-P8-NEXT: xscvdpsxws f5, f5
369 ; CHECK-P8-NEXT: xxswapd v0, vs8
370 ; CHECK-P8-NEXT: mtvsrd f10, r6
371 ; CHECK-P8-NEXT: mfvsrwz r6, f13
372 ; CHECK-P8-NEXT: mtvsrd f12, r4
373 ; CHECK-P8-NEXT: xxswapd v1, vs10
374 ; CHECK-P8-NEXT: mfvsrwz r4, v2
375 ; CHECK-P8-NEXT: xscvdpsxws f3, f3
376 ; CHECK-P8-NEXT: xxswapd v6, vs12
377 ; CHECK-P8-NEXT: xscvdpsxws f9, f9
378 ; CHECK-P8-NEXT: mtvsrd f13, r6
379 ; CHECK-P8-NEXT: mfvsrwz r6, v3
380 ; CHECK-P8-NEXT: mtvsrd v2, r4
381 ; CHECK-P8-NEXT: xxswapd v7, vs13
382 ; CHECK-P8-NEXT: mfvsrwz r4, f0
383 ; CHECK-P8-NEXT: xscvdpsxws f7, f7
384 ; CHECK-P8-NEXT: xxswapd v2, v2
385 ; CHECK-P8-NEXT: xscvdpsxws f11, f11
386 ; CHECK-P8-NEXT: mtvsrd v3, r6
387 ; CHECK-P8-NEXT: mfvsrwz r6, f1
388 ; CHECK-P8-NEXT: mtvsrd f0, r4
389 ; CHECK-P8-NEXT: xxswapd v3, v3
390 ; CHECK-P8-NEXT: mfvsrwz r4, f2
391 ; CHECK-P8-NEXT: mtvsrd f1, r6
392 ; CHECK-P8-NEXT: xxswapd v8, vs0
393 ; CHECK-P8-NEXT: mtvsrd f2, r4
394 ; CHECK-P8-NEXT: mfvsrwz r4, f5
395 ; CHECK-P8-NEXT: xxswapd v9, vs1
396 ; CHECK-P8-NEXT: mfvsrwz r6, f3
397 ; CHECK-P8-NEXT: xxswapd v10, vs2
398 ; CHECK-P8-NEXT: mtvsrd f5, r4
399 ; CHECK-P8-NEXT: mfvsrwz r4, f9
400 ; CHECK-P8-NEXT: mtvsrd f3, r6
401 ; CHECK-P8-NEXT: mfvsrwz r6, f7
402 ; CHECK-P8-NEXT: mtvsrd f9, r4
403 ; CHECK-P8-NEXT: mfvsrwz r4, f11
404 ; CHECK-P8-NEXT: vmrglh v4, v8, v4
405 ; CHECK-P8-NEXT: xxswapd v8, vs3
406 ; CHECK-P8-NEXT: vmrglh v5, v9, v5
407 ; CHECK-P8-NEXT: xxswapd v9, vs5
408 ; CHECK-P8-NEXT: mtvsrd f7, r6
409 ; CHECK-P8-NEXT: mtvsrd f0, r4
410 ; CHECK-P8-NEXT: vmrglh v0, v10, v0
411 ; CHECK-P8-NEXT: xxswapd v10, vs7
412 ; CHECK-P8-NEXT: vmrglh v1, v8, v1
413 ; CHECK-P8-NEXT: xxswapd v8, vs9
414 ; CHECK-P8-NEXT: vmrglh v6, v9, v6
415 ; CHECK-P8-NEXT: xxswapd v9, vs0
416 ; CHECK-P8-NEXT: vmrglh v7, v10, v7
417 ; CHECK-P8-NEXT: vmrglh v2, v8, v2
418 ; CHECK-P8-NEXT: vmrglh v3, v9, v3
419 ; CHECK-P8-NEXT: vmrglw v4, v5, v4
420 ; CHECK-P8-NEXT: vmrglw v5, v1, v0
421 ; CHECK-P8-NEXT: vmrglw v0, v7, v6
422 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
423 ; CHECK-P8-NEXT: xxmrgld v3, v5, v4
424 ; CHECK-P8-NEXT: stvx v3, 0, r3
425 ; CHECK-P8-NEXT: xxmrgld v2, v2, v0
426 ; CHECK-P8-NEXT: stvx v2, r3, r5
427 ; CHECK-P8-NEXT: blr
428 ;
429 ; CHECK-P9-LABEL: test16elt:
430 ; CHECK-P9: # %bb.0: # %entry
431 ; CHECK-P9-NEXT: lxv vs4, 0(r4)
432 ; CHECK-P9-NEXT: lxv vs3, 16(r4)
433 ; CHECK-P9-NEXT: lxv vs2, 32(r4)
434 ; CHECK-P9-NEXT: xscvdpsxws f5, f4
435 ; CHECK-P9-NEXT: lxv vs1, 48(r4)
436 ; CHECK-P9-NEXT: xscvdpsxws f6, f3
437 ; CHECK-P9-NEXT: lxv vs0, 64(r4)
438 ; CHECK-P9-NEXT: xscvdpsxws f7, f2
439 ; CHECK-P9-NEXT: xscvdpsxws f8, f1
440 ; CHECK-P9-NEXT: xxswapd vs4, vs4
441 ; CHECK-P9-NEXT: xscvdpsxws f4, f4
442 ; CHECK-P9-NEXT: mfvsrwz r5, f5
443 ; CHECK-P9-NEXT: xscvdpsxws f9, f0
444 ; CHECK-P9-NEXT: xxswapd vs3, vs3
445 ; CHECK-P9-NEXT: xscvdpsxws f3, f3
446 ; CHECK-P9-NEXT: mtvsrd f5, r5
447 ; CHECK-P9-NEXT: mfvsrwz r5, f6
448 ; CHECK-P9-NEXT: xxswapd vs2, vs2
449 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
450 ; CHECK-P9-NEXT: mtvsrd f6, r5
451 ; CHECK-P9-NEXT: mfvsrwz r5, f7
452 ; CHECK-P9-NEXT: mtvsrd f7, r5
453 ; CHECK-P9-NEXT: mfvsrwz r5, f8
454 ; CHECK-P9-NEXT: mtvsrd f8, r5
455 ; CHECK-P9-NEXT: mfvsrwz r5, f9
456 ; CHECK-P9-NEXT: mtvsrd f9, r5
457 ; CHECK-P9-NEXT: mfvsrwz r5, f4
458 ; CHECK-P9-NEXT: mtvsrd f4, r5
459 ; CHECK-P9-NEXT: mfvsrwz r5, f3
460 ; CHECK-P9-NEXT: xxswapd vs1, vs1
461 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
462 ; CHECK-P9-NEXT: xxswapd v2, vs5
463 ; CHECK-P9-NEXT: xxswapd v5, vs8
464 ; CHECK-P9-NEXT: xxswapd v0, vs9
465 ; CHECK-P9-NEXT: mtvsrd f3, r5
466 ; CHECK-P9-NEXT: mfvsrwz r5, f2
467 ; CHECK-P9-NEXT: mtvsrd f2, r5
468 ; CHECK-P9-NEXT: xxswapd vs0, vs0
469 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
470 ; CHECK-P9-NEXT: xxswapd v1, vs2
471 ; CHECK-P9-NEXT: lxv vs2, 80(r4)
472 ; CHECK-P9-NEXT: xxswapd v3, vs4
473 ; CHECK-P9-NEXT: vmrglh v2, v2, v3
474 ; CHECK-P9-NEXT: xxswapd v3, vs6
475 ; CHECK-P9-NEXT: xxswapd v4, vs3
476 ; CHECK-P9-NEXT: xscvdpsxws f3, f2
477 ; CHECK-P9-NEXT: xxswapd vs2, vs2
478 ; CHECK-P9-NEXT: mfvsrwz r5, f1
479 ; CHECK-P9-NEXT: vmrglh v3, v3, v4
480 ; CHECK-P9-NEXT: xxswapd v4, vs7
481 ; CHECK-P9-NEXT: mtvsrd f1, r5
482 ; CHECK-P9-NEXT: mfvsrwz r5, f0
483 ; CHECK-P9-NEXT: vmrglh v4, v4, v1
484 ; CHECK-P9-NEXT: xxswapd v1, vs1
485 ; CHECK-P9-NEXT: mtvsrd f0, r5
486 ; CHECK-P9-NEXT: vmrglh v5, v5, v1
487 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
488 ; CHECK-P9-NEXT: xxswapd v1, vs0
489 ; CHECK-P9-NEXT: lxv vs0, 112(r4)
490 ; CHECK-P9-NEXT: lxv vs1, 96(r4)
491 ; CHECK-P9-NEXT: mfvsrwz r4, f3
492 ; CHECK-P9-NEXT: mtvsrd f3, r4
493 ; CHECK-P9-NEXT: mfvsrwz r4, f2
494 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
495 ; CHECK-P9-NEXT: vmrglw v3, v5, v4
496 ; CHECK-P9-NEXT: xxmrgld vs4, v3, v2
497 ; CHECK-P9-NEXT: xxswapd v2, vs3
498 ; CHECK-P9-NEXT: vmrglh v0, v0, v1
499 ; CHECK-P9-NEXT: mtvsrd f2, r4
500 ; CHECK-P9-NEXT: xxswapd v3, vs2
501 ; CHECK-P9-NEXT: xscvdpsxws f2, f1
502 ; CHECK-P9-NEXT: xxswapd vs1, vs1
503 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
504 ; CHECK-P9-NEXT: mfvsrwz r4, f2
505 ; CHECK-P9-NEXT: mtvsrd f2, r4
506 ; CHECK-P9-NEXT: mfvsrwz r4, f1
507 ; CHECK-P9-NEXT: mtvsrd f1, r4
508 ; CHECK-P9-NEXT: xxswapd v4, vs1
509 ; CHECK-P9-NEXT: xscvdpsxws f1, f0
510 ; CHECK-P9-NEXT: xxswapd vs0, vs0
511 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
512 ; CHECK-P9-NEXT: mfvsrwz r4, f1
513 ; CHECK-P9-NEXT: mtvsrd f1, r4
514 ; CHECK-P9-NEXT: mfvsrwz r4, f0
515 ; CHECK-P9-NEXT: vmrglh v2, v2, v3
516 ; CHECK-P9-NEXT: xxswapd v3, vs2
517 ; CHECK-P9-NEXT: vmrglh v3, v3, v4
518 ; CHECK-P9-NEXT: xxswapd v4, vs1
519 ; CHECK-P9-NEXT: vmrglw v2, v2, v0
520 ; CHECK-P9-NEXT: mtvsrd f0, r4
521 ; CHECK-P9-NEXT: xxswapd v5, vs0
522 ; CHECK-P9-NEXT: vmrglh v4, v4, v5
523 ; CHECK-P9-NEXT: vmrglw v3, v4, v3
524 ; CHECK-P9-NEXT: xxmrgld vs0, v3, v2
525 ; CHECK-P9-NEXT: stxv vs0, 16(r3)
526 ; CHECK-P9-NEXT: stxv vs4, 0(r3)
527 ; CHECK-P9-NEXT: blr
528 ;
529 ; CHECK-BE-LABEL: test16elt:
530 ; CHECK-BE: # %bb.0: # %entry
531 ; CHECK-BE-NEXT: lxv vs4, 48(r4)
532 ; CHECK-BE-NEXT: xscvdpsxws f5, f4
533 ; CHECK-BE-NEXT: xxswapd vs4, vs4
534 ; CHECK-BE-NEXT: lxv vs3, 32(r4)
535 ; CHECK-BE-NEXT: xscvdpsxws f6, f3
536 ; CHECK-BE-NEXT: xxswapd vs3, vs3
537 ; CHECK-BE-NEXT: xscvdpsxws f4, f4
538 ; CHECK-BE-NEXT: mfvsrwz r5, f5
539 ; CHECK-BE-NEXT: sldi r5, r5, 48
540 ; CHECK-BE-NEXT: lxv vs2, 16(r4)
541 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
542 ; CHECK-BE-NEXT: xscvdpsxws f7, f2
543 ; CHECK-BE-NEXT: xxswapd vs2, vs2
544 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
545 ; CHECK-BE-NEXT: mtvsrd v2, r5
546 ; CHECK-BE-NEXT: mfvsrwz r5, f4
547 ; CHECK-BE-NEXT: sldi r5, r5, 48
548 ; CHECK-BE-NEXT: lxv vs1, 0(r4)
549 ; CHECK-BE-NEXT: xscvdpsxws f4, f1
550 ; CHECK-BE-NEXT: xxswapd vs1, vs1
551 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
552 ; CHECK-BE-NEXT: mtvsrd v3, r5
553 ; CHECK-BE-NEXT: mfvsrwz r5, f6
554 ; CHECK-BE-NEXT: sldi r5, r5, 48
555 ; CHECK-BE-NEXT: lxv vs0, 112(r4)
556 ; CHECK-BE-NEXT: vmrghh v2, v2, v3
557 ; CHECK-BE-NEXT: mtvsrd v3, r5
558 ; CHECK-BE-NEXT: mfvsrwz r5, f3
559 ; CHECK-BE-NEXT: xscvdpsxws f3, f0
560 ; CHECK-BE-NEXT: xxswapd vs0, vs0
561 ; CHECK-BE-NEXT: sldi r5, r5, 48
562 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
563 ; CHECK-BE-NEXT: mtvsrd v4, r5
564 ; CHECK-BE-NEXT: mfvsrwz r5, f7
565 ; CHECK-BE-NEXT: sldi r5, r5, 48
566 ; CHECK-BE-NEXT: vmrghh v3, v3, v4
567 ; CHECK-BE-NEXT: mtvsrd v4, r5
568 ; CHECK-BE-NEXT: mfvsrwz r5, f4
569 ; CHECK-BE-NEXT: vmrghw v2, v3, v2
570 ; CHECK-BE-NEXT: sldi r5, r5, 48
571 ; CHECK-BE-NEXT: mtvsrd v5, r5
572 ; CHECK-BE-NEXT: mfvsrwz r5, f3
573 ; CHECK-BE-NEXT: sldi r5, r5, 48
574 ; CHECK-BE-NEXT: mtvsrd v0, r5
575 ; CHECK-BE-NEXT: mfvsrwz r5, f2
576 ; CHECK-BE-NEXT: lxv vs2, 96(r4)
577 ; CHECK-BE-NEXT: sldi r5, r5, 48
578 ; CHECK-BE-NEXT: mtvsrd v1, r5
579 ; CHECK-BE-NEXT: mfvsrwz r5, f1
580 ; CHECK-BE-NEXT: lxv vs1, 80(r4)
581 ; CHECK-BE-NEXT: xscvdpsxws f3, f2
582 ; CHECK-BE-NEXT: xxswapd vs2, vs2
583 ; CHECK-BE-NEXT: sldi r5, r5, 48
584 ; CHECK-BE-NEXT: vmrghh v4, v4, v1
585 ; CHECK-BE-NEXT: mtvsrd v1, r5
586 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
587 ; CHECK-BE-NEXT: vmrghh v5, v5, v1
588 ; CHECK-BE-NEXT: mfvsrwz r5, f0
589 ; CHECK-BE-NEXT: lxv vs0, 64(r4)
590 ; CHECK-BE-NEXT: mfvsrwz r4, f3
591 ; CHECK-BE-NEXT: sldi r4, r4, 48
592 ; CHECK-BE-NEXT: vmrghw v3, v5, v4
593 ; CHECK-BE-NEXT: xxmrghd vs3, v3, v2
594 ; CHECK-BE-NEXT: mtvsrd v2, r4
595 ; CHECK-BE-NEXT: mfvsrwz r4, f2
596 ; CHECK-BE-NEXT: xscvdpsxws f2, f1
597 ; CHECK-BE-NEXT: xxswapd vs1, vs1
598 ; CHECK-BE-NEXT: sldi r4, r4, 48
599 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
600 ; CHECK-BE-NEXT: mtvsrd v3, r4
601 ; CHECK-BE-NEXT: vmrghh v2, v2, v3
602 ; CHECK-BE-NEXT: mfvsrwz r4, f2
603 ; CHECK-BE-NEXT: sldi r4, r4, 48
604 ; CHECK-BE-NEXT: mtvsrd v3, r4
605 ; CHECK-BE-NEXT: mfvsrwz r4, f1
606 ; CHECK-BE-NEXT: xscvdpsxws f1, f0
607 ; CHECK-BE-NEXT: xxswapd vs0, vs0
608 ; CHECK-BE-NEXT: sldi r4, r4, 48
609 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
610 ; CHECK-BE-NEXT: mtvsrd v4, r4
611 ; CHECK-BE-NEXT: vmrghh v3, v3, v4
612 ; CHECK-BE-NEXT: mfvsrwz r4, f1
613 ; CHECK-BE-NEXT: sldi r4, r4, 48
614 ; CHECK-BE-NEXT: mtvsrd v4, r4
615 ; CHECK-BE-NEXT: mfvsrwz r4, f0
616 ; CHECK-BE-NEXT: sldi r5, r5, 48
617 ; CHECK-BE-NEXT: mtvsrd v1, r5
618 ; CHECK-BE-NEXT: vmrghh v0, v0, v1
619 ; CHECK-BE-NEXT: vmrghw v2, v2, v0
620 ; CHECK-BE-NEXT: stxv vs3, 0(r3)
621 ; CHECK-BE-NEXT: sldi r4, r4, 48
622 ; CHECK-BE-NEXT: mtvsrd v5, r4
623 ; CHECK-BE-NEXT: vmrghh v4, v4, v5
624 ; CHECK-BE-NEXT: vmrghw v3, v4, v3
625 ; CHECK-BE-NEXT: xxmrghd vs0, v3, v2
626 ; CHECK-BE-NEXT: stxv vs0, 16(r3)
627 ; CHECK-BE-NEXT: blr
628 entry:
629 %a = load <16 x double>, <16 x double>* %0, align 128
630 %1 = fptoui <16 x double> %a to <16 x i16>
631 store <16 x i16> %1, <16 x i16>* %agg.result, align 32
632 ret void
633 }
635 define i32 @test2elt_signed(<2 x double> %a) local_unnamed_addr #0 {
636 ; CHECK-P8-LABEL: test2elt_signed:
637 ; CHECK-P8: # %bb.0: # %entry
638 ; CHECK-P8-NEXT: xxswapd vs0, v2
639 ; CHECK-P8-NEXT: xscvdpsxws f1, v2
640 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
641 ; CHECK-P8-NEXT: mfvsrwz r3, f1
642 ; CHECK-P8-NEXT: mfvsrwz r4, f0
643 ; CHECK-P8-NEXT: mtvsrd f0, r3
644 ; CHECK-P8-NEXT: mtvsrd f1, r4
645 ; CHECK-P8-NEXT: xxswapd v2, vs0
646 ; CHECK-P8-NEXT: xxswapd v3, vs1
647 ; CHECK-P8-NEXT: vmrglh v2, v2, v3
648 ; CHECK-P8-NEXT: xxswapd vs0, v2
649 ; CHECK-P8-NEXT: mfvsrwz r3, f0
650 ; CHECK-P8-NEXT: blr
651 ;
652 ; CHECK-P9-LABEL: test2elt_signed:
653 ; CHECK-P9: # %bb.0: # %entry
654 ; CHECK-P9-NEXT: xscvdpsxws f0, v2
655 ; CHECK-P9-NEXT: mfvsrwz r3, f0
656 ; CHECK-P9-NEXT: mtvsrd f0, r3
657 ; CHECK-P9-NEXT: xxswapd v3, vs0
658 ; CHECK-P9-NEXT: xxswapd vs0, v2
659 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
660 ; CHECK-P9-NEXT: mfvsrwz r3, f0
661 ; CHECK-P9-NEXT: mtvsrd f0, r3
662 ; CHECK-P9-NEXT: li r3, 0
663 ; CHECK-P9-NEXT: xxswapd v2, vs0
664 ; CHECK-P9-NEXT: vmrglh v2, v3, v2
665 ; CHECK-P9-NEXT: vextuwrx r3, r3, v2
666 ; CHECK-P9-NEXT: blr
667 ;
668 ; CHECK-BE-LABEL: test2elt_signed:
669 ; CHECK-BE: # %bb.0: # %entry
670 ; CHECK-BE-NEXT: xscvdpsxws f0, v2
671 ; CHECK-BE-NEXT: mfvsrwz r3, f0
672 ; CHECK-BE-NEXT: xxswapd vs0, v2
673 ; CHECK-BE-NEXT: sldi r3, r3, 48
674 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
675 ; CHECK-BE-NEXT: mtvsrd v3, r3
676 ; CHECK-BE-NEXT: mfvsrwz r3, f0
677 ; CHECK-BE-NEXT: sldi r3, r3, 48
678 ; CHECK-BE-NEXT: mtvsrd v2, r3
679 ; CHECK-BE-NEXT: li r3, 0
680 ; CHECK-BE-NEXT: vmrghh v2, v3, v2
681 ; CHECK-BE-NEXT: vextuwlx r3, r3, v2
682 ; CHECK-BE-NEXT: blr
683 entry:
684 %0 = fptosi <2 x double> %a to <2 x i16>
685 %1 = bitcast <2 x i16> %0 to i32
686 ret i32 %1
687 }
689 define i64 @test4elt_signed(<4 x double>* nocapture readonly) local_unnamed_addr #1 {
690 ; CHECK-P8-LABEL: test4elt_signed:
691 ; CHECK-P8: # %bb.0: # %entry
692 ; CHECK-P8-NEXT: li r4, 16
693 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
694 ; CHECK-P8-NEXT: lxvd2x vs1, r3, r4
695 ; CHECK-P8-NEXT: xscvdpsxws f2, f0
696 ; CHECK-P8-NEXT: xxswapd vs0, vs0
697 ; CHECK-P8-NEXT: xscvdpsxws f3, f1
698 ; CHECK-P8-NEXT: xxswapd vs1, vs1
699 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
700 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
701 ; CHECK-P8-NEXT: mfvsrwz r3, f2
702 ; CHECK-P8-NEXT: mfvsrwz r4, f3
703 ; CHECK-P8-NEXT: mtvsrd f2, r3
704 ; CHECK-P8-NEXT: mtvsrd f3, r4
705 ; CHECK-P8-NEXT: mfvsrwz r3, f0
706 ; CHECK-P8-NEXT: xxswapd v2, vs2
707 ; CHECK-P8-NEXT: mfvsrwz r4, f1
708 ; CHECK-P8-NEXT: xxswapd v4, vs3
709 ; CHECK-P8-NEXT: mtvsrd f0, r3
710 ; CHECK-P8-NEXT: mtvsrd f1, r4
711 ; CHECK-P8-NEXT: xxswapd v3, vs0
712 ; CHECK-P8-NEXT: xxswapd v5, vs1
713 ; CHECK-P8-NEXT: vmrglh v2, v3, v2
714 ; CHECK-P8-NEXT: vmrglh v3, v5, v4
715 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
716 ; CHECK-P8-NEXT: xxswapd vs0, v2
717 ; CHECK-P8-NEXT: mfvsrd r3, f0
718 ; CHECK-P8-NEXT: blr
719 ;
720 ; CHECK-P9-LABEL: test4elt_signed:
721 ; CHECK-P9: # %bb.0: # %entry
722 ; CHECK-P9-NEXT: lxv vs1, 0(r3)
723 ; CHECK-P9-NEXT: xscvdpsxws f2, f1
724 ; CHECK-P9-NEXT: xxswapd vs1, vs1
725 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
726 ; CHECK-P9-NEXT: lxv vs0, 16(r3)
727 ; CHECK-P9-NEXT: mfvsrwz r3, f2
728 ; CHECK-P9-NEXT: mtvsrd f2, r3
729 ; CHECK-P9-NEXT: mfvsrwz r3, f1
730 ; CHECK-P9-NEXT: xxswapd v2, vs2
731 ; CHECK-P9-NEXT: mtvsrd f1, r3
732 ; CHECK-P9-NEXT: xxswapd v3, vs1
733 ; CHECK-P9-NEXT: xscvdpsxws f1, f0
734 ; CHECK-P9-NEXT: xxswapd vs0, vs0
735 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
736 ; CHECK-P9-NEXT: mfvsrwz r3, f1
737 ; CHECK-P9-NEXT: mtvsrd f1, r3
738 ; CHECK-P9-NEXT: mfvsrwz r3, f0
739 ; CHECK-P9-NEXT: mtvsrd f0, r3
740 ; CHECK-P9-NEXT: vmrglh v2, v2, v3
741 ; CHECK-P9-NEXT: xxswapd v3, vs1
742 ; CHECK-P9-NEXT: xxswapd v4, vs0
743 ; CHECK-P9-NEXT: vmrglh v3, v3, v4
744 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
745 ; CHECK-P9-NEXT: mfvsrld r3, v2
746 ; CHECK-P9-NEXT: blr
747 ;
748 ; CHECK-BE-LABEL: test4elt_signed:
749 ; CHECK-BE: # %bb.0: # %entry
750 ; CHECK-BE-NEXT: lxv vs1, 16(r3)
751 ; CHECK-BE-NEXT: xscvdpsxws f2, f1
752 ; CHECK-BE-NEXT: xxswapd vs1, vs1
753 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
754 ; CHECK-BE-NEXT: lxv vs0, 0(r3)
755 ; CHECK-BE-NEXT: mfvsrwz r3, f2
756 ; CHECK-BE-NEXT: sldi r3, r3, 48
757 ; CHECK-BE-NEXT: mtvsrd v2, r3
758 ; CHECK-BE-NEXT: mfvsrwz r3, f1
759 ; CHECK-BE-NEXT: xscvdpsxws f1, f0
760 ; CHECK-BE-NEXT: xxswapd vs0, vs0
761 ; CHECK-BE-NEXT: sldi r3, r3, 48
762 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
763 ; CHECK-BE-NEXT: mtvsrd v3, r3
764 ; CHECK-BE-NEXT: vmrghh v2, v2, v3
765 ; CHECK-BE-NEXT: mfvsrwz r3, f1
766 ; CHECK-BE-NEXT: sldi r3, r3, 48
767 ; CHECK-BE-NEXT: mtvsrd v3, r3
768 ; CHECK-BE-NEXT: mfvsrwz r3, f0
769 ; CHECK-BE-NEXT: sldi r3, r3, 48
770 ; CHECK-BE-NEXT: mtvsrd v4, r3
771 ; CHECK-BE-NEXT: vmrghh v3, v3, v4
772 ; CHECK-BE-NEXT: vmrghw v2, v3, v2
773 ; CHECK-BE-NEXT: mfvsrd r3, v2
774 ; CHECK-BE-NEXT: blr
775 entry:
776 %a = load <4 x double>, <4 x double>* %0, align 32
777 %1 = fptosi <4 x double> %a to <4 x i16>
778 %2 = bitcast <4 x i16> %1 to i64
779 ret i64 %2
780 }
782 define <8 x i16> @test8elt_signed(<8 x double>* nocapture readonly) local_unnamed_addr #2 {
783 ; CHECK-P8-LABEL: test8elt_signed:
784 ; CHECK-P8: # %bb.0: # %entry
785 ; CHECK-P8-NEXT: li r4, 16
786 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
787 ; CHECK-P8-NEXT: lxvd2x vs1, r3, r4
788 ; CHECK-P8-NEXT: li r4, 32
789 ; CHECK-P8-NEXT: lxvd2x vs2, r3, r4
790 ; CHECK-P8-NEXT: li r4, 48
791 ; CHECK-P8-NEXT: lxvd2x vs3, r3, r4
792 ; CHECK-P8-NEXT: xscvdpsxws f4, f0
793 ; CHECK-P8-NEXT: xxswapd vs0, vs0
794 ; CHECK-P8-NEXT: xscvdpsxws f5, f1
795 ; CHECK-P8-NEXT: xxswapd vs1, vs1
796 ; CHECK-P8-NEXT: xscvdpsxws f6, f2
797 ; CHECK-P8-NEXT: xxswapd vs2, vs2
798 ; CHECK-P8-NEXT: xscvdpsxws f7, f3
799 ; CHECK-P8-NEXT: xxswapd vs3, vs3
800 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
801 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
802 ; CHECK-P8-NEXT: mfvsrwz r3, f4
803 ; CHECK-P8-NEXT: xscvdpsxws f2, f2
804 ; CHECK-P8-NEXT: xscvdpsxws f3, f3
805 ; CHECK-P8-NEXT: mfvsrwz r4, f5
806 ; CHECK-P8-NEXT: mtvsrd f4, r3
807 ; CHECK-P8-NEXT: mfvsrwz r3, f6
808 ; CHECK-P8-NEXT: mtvsrd f5, r4
809 ; CHECK-P8-NEXT: xxswapd v2, vs4
810 ; CHECK-P8-NEXT: mfvsrwz r4, f7
811 ; CHECK-P8-NEXT: mtvsrd f6, r3
812 ; CHECK-P8-NEXT: xxswapd v3, vs5
813 ; CHECK-P8-NEXT: mfvsrwz r3, f0
814 ; CHECK-P8-NEXT: mtvsrd f7, r4
815 ; CHECK-P8-NEXT: xxswapd v4, vs6
816 ; CHECK-P8-NEXT: mfvsrwz r4, f1
817 ; CHECK-P8-NEXT: mtvsrd f0, r3
818 ; CHECK-P8-NEXT: xxswapd v1, vs7
819 ; CHECK-P8-NEXT: mfvsrwz r3, f2
820 ; CHECK-P8-NEXT: mtvsrd f1, r4
821 ; CHECK-P8-NEXT: xxswapd v5, vs0
822 ; CHECK-P8-NEXT: mfvsrwz r4, f3
823 ; CHECK-P8-NEXT: mtvsrd f2, r3
824 ; CHECK-P8-NEXT: xxswapd v0, vs1
825 ; CHECK-P8-NEXT: mtvsrd f0, r4
826 ; CHECK-P8-NEXT: xxswapd v6, vs2
827 ; CHECK-P8-NEXT: vmrglh v2, v5, v2
828 ; CHECK-P8-NEXT: xxswapd v5, vs0
829 ; CHECK-P8-NEXT: vmrglh v3, v0, v3
830 ; CHECK-P8-NEXT: vmrglh v4, v6, v4
831 ; CHECK-P8-NEXT: vmrglh v5, v5, v1
832 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
833 ; CHECK-P8-NEXT: vmrglw v3, v5, v4
834 ; CHECK-P8-NEXT: xxmrgld v2, v3, v2
835 ; CHECK-P8-NEXT: blr
836 ;
837 ; CHECK-P9-LABEL: test8elt_signed:
838 ; CHECK-P9: # %bb.0: # %entry
839 ; CHECK-P9-NEXT: lxv vs3, 0(r3)
840 ; CHECK-P9-NEXT: xscvdpsxws f4, f3
841 ; CHECK-P9-NEXT: xxswapd vs3, vs3
842 ; CHECK-P9-NEXT: xscvdpsxws f3, f3
843 ; CHECK-P9-NEXT: lxv vs0, 48(r3)
844 ; CHECK-P9-NEXT: lxv vs1, 32(r3)
845 ; CHECK-P9-NEXT: lxv vs2, 16(r3)
846 ; CHECK-P9-NEXT: mfvsrwz r3, f4
847 ; CHECK-P9-NEXT: mtvsrd f4, r3
848 ; CHECK-P9-NEXT: mfvsrwz r3, f3
849 ; CHECK-P9-NEXT: xxswapd v2, vs4
850 ; CHECK-P9-NEXT: mtvsrd f3, r3
851 ; CHECK-P9-NEXT: xxswapd v3, vs3
852 ; CHECK-P9-NEXT: xscvdpsxws f3, f2
853 ; CHECK-P9-NEXT: xxswapd vs2, vs2
854 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
855 ; CHECK-P9-NEXT: mfvsrwz r3, f3
856 ; CHECK-P9-NEXT: mtvsrd f3, r3
857 ; CHECK-P9-NEXT: mfvsrwz r3, f2
858 ; CHECK-P9-NEXT: mtvsrd f2, r3
859 ; CHECK-P9-NEXT: xxswapd v4, vs2
860 ; CHECK-P9-NEXT: xscvdpsxws f2, f1
861 ; CHECK-P9-NEXT: xxswapd vs1, vs1
862 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
863 ; CHECK-P9-NEXT: mfvsrwz r3, f2
864 ; CHECK-P9-NEXT: mtvsrd f2, r3
865 ; CHECK-P9-NEXT: mfvsrwz r3, f1
866 ; CHECK-P9-NEXT: vmrglh v2, v2, v3
867 ; CHECK-P9-NEXT: xxswapd v3, vs3
868 ; CHECK-P9-NEXT: vmrglh v3, v3, v4
869 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
870 ; CHECK-P9-NEXT: xxswapd v3, vs2
871 ; CHECK-P9-NEXT: mtvsrd f1, r3
872 ; CHECK-P9-NEXT: xxswapd v4, vs1
873 ; CHECK-P9-NEXT: xscvdpsxws f1, f0
874 ; CHECK-P9-NEXT: xxswapd vs0, vs0
875 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
876 ; CHECK-P9-NEXT: mfvsrwz r3, f1
877 ; CHECK-P9-NEXT: mtvsrd f1, r3
878 ; CHECK-P9-NEXT: mfvsrwz r3, f0
879 ; CHECK-P9-NEXT: mtvsrd f0, r3
880 ; CHECK-P9-NEXT: vmrglh v3, v3, v4
881 ; CHECK-P9-NEXT: xxswapd v4, vs1
882 ; CHECK-P9-NEXT: xxswapd v5, vs0
883 ; CHECK-P9-NEXT: vmrglh v4, v4, v5
884 ; CHECK-P9-NEXT: vmrglw v3, v4, v3
885 ; CHECK-P9-NEXT: xxmrgld v2, v3, v2
886 ; CHECK-P9-NEXT: blr
887 ;
888 ; CHECK-BE-LABEL: test8elt_signed:
889 ; CHECK-BE: # %bb.0: # %entry
890 ; CHECK-BE-NEXT: lxv vs3, 48(r3)
891 ; CHECK-BE-NEXT: xscvdpsxws f4, f3
892 ; CHECK-BE-NEXT: xxswapd vs3, vs3
893 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
894 ; CHECK-BE-NEXT: lxv vs2, 32(r3)
895 ; CHECK-BE-NEXT: lxv vs0, 0(r3)
896 ; CHECK-BE-NEXT: lxv vs1, 16(r3)
897 ; CHECK-BE-NEXT: mfvsrwz r3, f4
898 ; CHECK-BE-NEXT: sldi r3, r3, 48
899 ; CHECK-BE-NEXT: mtvsrd v2, r3
900 ; CHECK-BE-NEXT: mfvsrwz r3, f3
901 ; CHECK-BE-NEXT: xscvdpsxws f3, f2
902 ; CHECK-BE-NEXT: xxswapd vs2, vs2
903 ; CHECK-BE-NEXT: sldi r3, r3, 48
904 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
905 ; CHECK-BE-NEXT: mtvsrd v3, r3
906 ; CHECK-BE-NEXT: vmrghh v2, v2, v3
907 ; CHECK-BE-NEXT: mfvsrwz r3, f3
908 ; CHECK-BE-NEXT: sldi r3, r3, 48
909 ; CHECK-BE-NEXT: mtvsrd v3, r3
910 ; CHECK-BE-NEXT: mfvsrwz r3, f2
911 ; CHECK-BE-NEXT: xscvdpsxws f2, f1
912 ; CHECK-BE-NEXT: xxswapd vs1, vs1
913 ; CHECK-BE-NEXT: sldi r3, r3, 48
914 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
915 ; CHECK-BE-NEXT: mtvsrd v4, r3
916 ; CHECK-BE-NEXT: vmrghh v3, v3, v4
917 ; CHECK-BE-NEXT: mfvsrwz r3, f2
918 ; CHECK-BE-NEXT: sldi r3, r3, 48
919 ; CHECK-BE-NEXT: vmrghw v2, v3, v2
920 ; CHECK-BE-NEXT: mtvsrd v3, r3
921 ; CHECK-BE-NEXT: mfvsrwz r3, f1
922 ; CHECK-BE-NEXT: xscvdpsxws f1, f0
923 ; CHECK-BE-NEXT: xxswapd vs0, vs0
924 ; CHECK-BE-NEXT: sldi r3, r3, 48
925 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
926 ; CHECK-BE-NEXT: mtvsrd v4, r3
927 ; CHECK-BE-NEXT: vmrghh v3, v3, v4
928 ; CHECK-BE-NEXT: mfvsrwz r3, f1
929 ; CHECK-BE-NEXT: sldi r3, r3, 48
930 ; CHECK-BE-NEXT: mtvsrd v4, r3
931 ; CHECK-BE-NEXT: mfvsrwz r3, f0
932 ; CHECK-BE-NEXT: sldi r3, r3, 48
933 ; CHECK-BE-NEXT: mtvsrd v5, r3
934 ; CHECK-BE-NEXT: vmrghh v4, v4, v5
935 ; CHECK-BE-NEXT: vmrghw v3, v4, v3
936 ; CHECK-BE-NEXT: xxmrghd v2, v3, v2
937 ; CHECK-BE-NEXT: blr
938 entry:
939 %a = load <8 x double>, <8 x double>* %0, align 64
940 %1 = fptosi <8 x double> %a to <8 x i16>
941 ret <8 x i16> %1
942 }
944 define void @test16elt_signed(<16 x i16>* noalias nocapture sret %agg.result, <16 x double>* nocapture readonly) local_unnamed_addr #3 {
945 ; CHECK-P8-LABEL: test16elt_signed:
946 ; CHECK-P8: # %bb.0: # %entry
947 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
948 ; CHECK-P8-NEXT: li r5, 16
949 ; CHECK-P8-NEXT: li r6, 32
950 ; CHECK-P8-NEXT: lxvd2x vs1, r4, r5
951 ; CHECK-P8-NEXT: lxvd2x vs2, r4, r6
952 ; CHECK-P8-NEXT: li r6, 48
953 ; CHECK-P8-NEXT: lxvd2x vs3, r4, r6
954 ; CHECK-P8-NEXT: li r6, 64
955 ; CHECK-P8-NEXT: xscvdpsxws f4, f0
956 ; CHECK-P8-NEXT: lxvd2x vs5, r4, r6
957 ; CHECK-P8-NEXT: li r6, 80
958 ; CHECK-P8-NEXT: xxswapd vs0, vs0
959 ; CHECK-P8-NEXT: xscvdpsxws f6, f1
960 ; CHECK-P8-NEXT: lxvd2x vs7, r4, r6
961 ; CHECK-P8-NEXT: li r6, 96
962 ; CHECK-P8-NEXT: xxswapd vs1, vs1
963 ; CHECK-P8-NEXT: xscvdpsxws f8, f2
964 ; CHECK-P8-NEXT: lxvd2x vs9, r4, r6
965 ; CHECK-P8-NEXT: li r6, 112
966 ; CHECK-P8-NEXT: xxswapd vs2, vs2
967 ; CHECK-P8-NEXT: xscvdpsxws f10, f3
968 ; CHECK-P8-NEXT: lxvd2x vs11, r4, r6
969 ; CHECK-P8-NEXT: xxswapd vs3, vs3
970 ; CHECK-P8-NEXT: xscvdpsxws f12, f5
971 ; CHECK-P8-NEXT: xxswapd vs5, vs5
972 ; CHECK-P8-NEXT: xscvdpsxws f13, f7
973 ; CHECK-P8-NEXT: xxswapd vs7, vs7
974 ; CHECK-P8-NEXT: xscvdpsxws v2, f9
975 ; CHECK-P8-NEXT: xxswapd vs9, vs9
976 ; CHECK-P8-NEXT: mfvsrwz r4, f4
977 ; CHECK-P8-NEXT: xscvdpsxws v3, f11
978 ; CHECK-P8-NEXT: xxswapd vs11, vs11
979 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
980 ; CHECK-P8-NEXT: mfvsrwz r6, f6
981 ; CHECK-P8-NEXT: mtvsrd f4, r4
982 ; CHECK-P8-NEXT: mfvsrwz r4, f8
983 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
984 ; CHECK-P8-NEXT: xxswapd v4, vs4
985 ; CHECK-P8-NEXT: xscvdpsxws f2, f2
986 ; CHECK-P8-NEXT: mtvsrd f6, r6
987 ; CHECK-P8-NEXT: mfvsrwz r6, f10
988 ; CHECK-P8-NEXT: mtvsrd f8, r4
989 ; CHECK-P8-NEXT: xxswapd v5, vs6
990 ; CHECK-P8-NEXT: mfvsrwz r4, f12
991 ; CHECK-P8-NEXT: xscvdpsxws f5, f5
992 ; CHECK-P8-NEXT: xxswapd v0, vs8
993 ; CHECK-P8-NEXT: mtvsrd f10, r6
994 ; CHECK-P8-NEXT: mfvsrwz r6, f13
995 ; CHECK-P8-NEXT: mtvsrd f12, r4
996 ; CHECK-P8-NEXT: xxswapd v1, vs10
997 ; CHECK-P8-NEXT: mfvsrwz r4, v2
998 ; CHECK-P8-NEXT: xscvdpsxws f3, f3
999 ; CHECK-P8-NEXT: xxswapd v6, vs12
1000 ; CHECK-P8-NEXT: xscvdpsxws f9, f9
1001 ; CHECK-P8-NEXT: mtvsrd f13, r6
1002 ; CHECK-P8-NEXT: mfvsrwz r6, v3
1003 ; CHECK-P8-NEXT: mtvsrd v2, r4
1004 ; CHECK-P8-NEXT: xxswapd v7, vs13
1005 ; CHECK-P8-NEXT: mfvsrwz r4, f0
1006 ; CHECK-P8-NEXT: xscvdpsxws f7, f7
1007 ; CHECK-P8-NEXT: xxswapd v2, v2
1008 ; CHECK-P8-NEXT: xscvdpsxws f11, f11
1009 ; CHECK-P8-NEXT: mtvsrd v3, r6
1010 ; CHECK-P8-NEXT: mfvsrwz r6, f1
1011 ; CHECK-P8-NEXT: mtvsrd f0, r4
1012 ; CHECK-P8-NEXT: xxswapd v3, v3
1013 ; CHECK-P8-NEXT: mfvsrwz r4, f2
1014 ; CHECK-P8-NEXT: mtvsrd f1, r6
1015 ; CHECK-P8-NEXT: xxswapd v8, vs0
1016 ; CHECK-P8-NEXT: mtvsrd f2, r4
1017 ; CHECK-P8-NEXT: mfvsrwz r4, f5
1018 ; CHECK-P8-NEXT: xxswapd v9, vs1
1019 ; CHECK-P8-NEXT: mfvsrwz r6, f3
1020 ; CHECK-P8-NEXT: xxswapd v10, vs2
1021 ; CHECK-P8-NEXT: mtvsrd f5, r4
1022 ; CHECK-P8-NEXT: mfvsrwz r4, f9
1023 ; CHECK-P8-NEXT: mtvsrd f3, r6
1024 ; CHECK-P8-NEXT: mfvsrwz r6, f7
1025 ; CHECK-P8-NEXT: mtvsrd f9, r4
1026 ; CHECK-P8-NEXT: mfvsrwz r4, f11
1027 ; CHECK-P8-NEXT: vmrglh v4, v8, v4
1028 ; CHECK-P8-NEXT: xxswapd v8, vs3
1029 ; CHECK-P8-NEXT: vmrglh v5, v9, v5
1030 ; CHECK-P8-NEXT: xxswapd v9, vs5
1031 ; CHECK-P8-NEXT: mtvsrd f7, r6
1032 ; CHECK-P8-NEXT: mtvsrd f0, r4
1033 ; CHECK-P8-NEXT: vmrglh v0, v10, v0
1034 ; CHECK-P8-NEXT: xxswapd v10, vs7
1035 ; CHECK-P8-NEXT: vmrglh v1, v8, v1
1036 ; CHECK-P8-NEXT: xxswapd v8, vs9
1037 ; CHECK-P8-NEXT: vmrglh v6, v9, v6
1038 ; CHECK-P8-NEXT: xxswapd v9, vs0
1039 ; CHECK-P8-NEXT: vmrglh v7, v10, v7
1040 ; CHECK-P8-NEXT: vmrglh v2, v8, v2
1041 ; CHECK-P8-NEXT: vmrglh v3, v9, v3
1042 ; CHECK-P8-NEXT: vmrglw v4, v5, v4
1043 ; CHECK-P8-NEXT: vmrglw v5, v1, v0
1044 ; CHECK-P8-NEXT: vmrglw v0, v7, v6
1045 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
1046 ; CHECK-P8-NEXT: xxmrgld v3, v5, v4
1047 ; CHECK-P8-NEXT: stvx v3, 0, r3
1048 ; CHECK-P8-NEXT: xxmrgld v2, v2, v0
1049 ; CHECK-P8-NEXT: stvx v2, r3, r5
1050 ; CHECK-P8-NEXT: blr
1051 ;
1052 ; CHECK-P9-LABEL: test16elt_signed:
1053 ; CHECK-P9: # %bb.0: # %entry
1054 ; CHECK-P9-NEXT: lxv vs4, 0(r4)
1055 ; CHECK-P9-NEXT: lxv vs3, 16(r4)
1056 ; CHECK-P9-NEXT: lxv vs2, 32(r4)
1057 ; CHECK-P9-NEXT: xscvdpsxws f5, f4
1058 ; CHECK-P9-NEXT: lxv vs1, 48(r4)
1059 ; CHECK-P9-NEXT: xscvdpsxws f6, f3
1060 ; CHECK-P9-NEXT: lxv vs0, 64(r4)
1061 ; CHECK-P9-NEXT: xscvdpsxws f7, f2
1062 ; CHECK-P9-NEXT: xscvdpsxws f8, f1
1063 ; CHECK-P9-NEXT: xxswapd vs4, vs4
1064 ; CHECK-P9-NEXT: xscvdpsxws f4, f4
1065 ; CHECK-P9-NEXT: mfvsrwz r5, f5
1066 ; CHECK-P9-NEXT: xscvdpsxws f9, f0
1067 ; CHECK-P9-NEXT: xxswapd vs3, vs3
1068 ; CHECK-P9-NEXT: xscvdpsxws f3, f3
1069 ; CHECK-P9-NEXT: mtvsrd f5, r5
1070 ; CHECK-P9-NEXT: mfvsrwz r5, f6
1071 ; CHECK-P9-NEXT: xxswapd vs2, vs2
1072 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
1073 ; CHECK-P9-NEXT: mtvsrd f6, r5
1074 ; CHECK-P9-NEXT: mfvsrwz r5, f7
1075 ; CHECK-P9-NEXT: mtvsrd f7, r5
1076 ; CHECK-P9-NEXT: mfvsrwz r5, f8
1077 ; CHECK-P9-NEXT: mtvsrd f8, r5
1078 ; CHECK-P9-NEXT: mfvsrwz r5, f9
1079 ; CHECK-P9-NEXT: mtvsrd f9, r5
1080 ; CHECK-P9-NEXT: mfvsrwz r5, f4
1081 ; CHECK-P9-NEXT: mtvsrd f4, r5
1082 ; CHECK-P9-NEXT: mfvsrwz r5, f3
1083 ; CHECK-P9-NEXT: xxswapd vs1, vs1
1084 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
1085 ; CHECK-P9-NEXT: xxswapd v2, vs5
1086 ; CHECK-P9-NEXT: xxswapd v5, vs8
1087 ; CHECK-P9-NEXT: xxswapd v0, vs9
1088 ; CHECK-P9-NEXT: mtvsrd f3, r5
1089 ; CHECK-P9-NEXT: mfvsrwz r5, f2
1090 ; CHECK-P9-NEXT: mtvsrd f2, r5
1091 ; CHECK-P9-NEXT: xxswapd vs0, vs0
1092 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
1093 ; CHECK-P9-NEXT: xxswapd v1, vs2
1094 ; CHECK-P9-NEXT: lxv vs2, 80(r4)
1095 ; CHECK-P9-NEXT: xxswapd v3, vs4
1096 ; CHECK-P9-NEXT: vmrglh v2, v2, v3
1097 ; CHECK-P9-NEXT: xxswapd v3, vs6
1098 ; CHECK-P9-NEXT: xxswapd v4, vs3
1099 ; CHECK-P9-NEXT: xscvdpsxws f3, f2
1100 ; CHECK-P9-NEXT: xxswapd vs2, vs2
1101 ; CHECK-P9-NEXT: mfvsrwz r5, f1
1102 ; CHECK-P9-NEXT: vmrglh v3, v3, v4
1103 ; CHECK-P9-NEXT: xxswapd v4, vs7
1104 ; CHECK-P9-NEXT: mtvsrd f1, r5
1105 ; CHECK-P9-NEXT: mfvsrwz r5, f0
1106 ; CHECK-P9-NEXT: vmrglh v4, v4, v1
1107 ; CHECK-P9-NEXT: xxswapd v1, vs1
1108 ; CHECK-P9-NEXT: mtvsrd f0, r5
1109 ; CHECK-P9-NEXT: vmrglh v5, v5, v1
1110 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
1111 ; CHECK-P9-NEXT: xxswapd v1, vs0
1112 ; CHECK-P9-NEXT: lxv vs0, 112(r4)
1113 ; CHECK-P9-NEXT: lxv vs1, 96(r4)
1114 ; CHECK-P9-NEXT: mfvsrwz r4, f3
1115 ; CHECK-P9-NEXT: mtvsrd f3, r4
1116 ; CHECK-P9-NEXT: mfvsrwz r4, f2
1117 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
1118 ; CHECK-P9-NEXT: vmrglw v3, v5, v4
1119 ; CHECK-P9-NEXT: xxmrgld vs4, v3, v2
1120 ; CHECK-P9-NEXT: xxswapd v2, vs3
1121 ; CHECK-P9-NEXT: vmrglh v0, v0, v1
1122 ; CHECK-P9-NEXT: mtvsrd f2, r4
1123 ; CHECK-P9-NEXT: xxswapd v3, vs2
1124 ; CHECK-P9-NEXT: xscvdpsxws f2, f1
1125 ; CHECK-P9-NEXT: xxswapd vs1, vs1
1126 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
1127 ; CHECK-P9-NEXT: mfvsrwz r4, f2
1128 ; CHECK-P9-NEXT: mtvsrd f2, r4
1129 ; CHECK-P9-NEXT: mfvsrwz r4, f1
1130 ; CHECK-P9-NEXT: mtvsrd f1, r4
1131 ; CHECK-P9-NEXT: xxswapd v4, vs1
1132 ; CHECK-P9-NEXT: xscvdpsxws f1, f0
1133 ; CHECK-P9-NEXT: xxswapd vs0, vs0
1134 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
1135 ; CHECK-P9-NEXT: mfvsrwz r4, f1
1136 ; CHECK-P9-NEXT: mtvsrd f1, r4
1137 ; CHECK-P9-NEXT: mfvsrwz r4, f0
1138 ; CHECK-P9-NEXT: vmrglh v2, v2, v3
1139 ; CHECK-P9-NEXT: xxswapd v3, vs2
1140 ; CHECK-P9-NEXT: vmrglh v3, v3, v4
1141 ; CHECK-P9-NEXT: xxswapd v4, vs1
1142 ; CHECK-P9-NEXT: vmrglw v2, v2, v0
1143 ; CHECK-P9-NEXT: mtvsrd f0, r4
1144 ; CHECK-P9-NEXT: xxswapd v5, vs0
1145 ; CHECK-P9-NEXT: vmrglh v4, v4, v5
1146 ; CHECK-P9-NEXT: vmrglw v3, v4, v3
1147 ; CHECK-P9-NEXT: xxmrgld vs0, v3, v2
1148 ; CHECK-P9-NEXT: stxv vs0, 16(r3)
1149 ; CHECK-P9-NEXT: stxv vs4, 0(r3)
1150 ; CHECK-P9-NEXT: blr
1151 ;
1152 ; CHECK-BE-LABEL: test16elt_signed:
1153 ; CHECK-BE: # %bb.0: # %entry
1154 ; CHECK-BE-NEXT: lxv vs4, 48(r4)
1155 ; CHECK-BE-NEXT: xscvdpsxws f5, f4
1156 ; CHECK-BE-NEXT: xxswapd vs4, vs4
1157 ; CHECK-BE-NEXT: lxv vs3, 32(r4)
1158 ; CHECK-BE-NEXT: xscvdpsxws f6, f3
1159 ; CHECK-BE-NEXT: xxswapd vs3, vs3
1160 ; CHECK-BE-NEXT: xscvdpsxws f4, f4
1161 ; CHECK-BE-NEXT: mfvsrwz r5, f5
1162 ; CHECK-BE-NEXT: sldi r5, r5, 48
1163 ; CHECK-BE-NEXT: lxv vs2, 16(r4)
1164 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
1165 ; CHECK-BE-NEXT: xscvdpsxws f7, f2
1166 ; CHECK-BE-NEXT: xxswapd vs2, vs2
1167 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
1168 ; CHECK-BE-NEXT: mtvsrd v2, r5
1169 ; CHECK-BE-NEXT: mfvsrwz r5, f4
1170 ; CHECK-BE-NEXT: sldi r5, r5, 48
1171 ; CHECK-BE-NEXT: lxv vs1, 0(r4)
1172 ; CHECK-BE-NEXT: xscvdpsxws f4, f1
1173 ; CHECK-BE-NEXT: xxswapd vs1, vs1
1174 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
1175 ; CHECK-BE-NEXT: mtvsrd v3, r5
1176 ; CHECK-BE-NEXT: mfvsrwz r5, f6
1177 ; CHECK-BE-NEXT: sldi r5, r5, 48
1178 ; CHECK-BE-NEXT: lxv vs0, 112(r4)
1179 ; CHECK-BE-NEXT: vmrghh v2, v2, v3
1180 ; CHECK-BE-NEXT: mtvsrd v3, r5
1181 ; CHECK-BE-NEXT: mfvsrwz r5, f3
1182 ; CHECK-BE-NEXT: xscvdpsxws f3, f0
1183 ; CHECK-BE-NEXT: xxswapd vs0, vs0
1184 ; CHECK-BE-NEXT: sldi r5, r5, 48
1185 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
1186 ; CHECK-BE-NEXT: mtvsrd v4, r5
1187 ; CHECK-BE-NEXT: mfvsrwz r5, f7
1188 ; CHECK-BE-NEXT: sldi r5, r5, 48
1189 ; CHECK-BE-NEXT: vmrghh v3, v3, v4
1190 ; CHECK-BE-NEXT: mtvsrd v4, r5
1191 ; CHECK-BE-NEXT: mfvsrwz r5, f4
1192 ; CHECK-BE-NEXT: vmrghw v2, v3, v2
1193 ; CHECK-BE-NEXT: sldi r5, r5, 48
1194 ; CHECK-BE-NEXT: mtvsrd v5, r5
1195 ; CHECK-BE-NEXT: mfvsrwz r5, f3
1196 ; CHECK-BE-NEXT: sldi r5, r5, 48
1197 ; CHECK-BE-NEXT: mtvsrd v0, r5
1198 ; CHECK-BE-NEXT: mfvsrwz r5, f2
1199 ; CHECK-BE-NEXT: lxv vs2, 96(r4)
1200 ; CHECK-BE-NEXT: sldi r5, r5, 48
1201 ; CHECK-BE-NEXT: mtvsrd v1, r5
1202 ; CHECK-BE-NEXT: mfvsrwz r5, f1
1203 ; CHECK-BE-NEXT: lxv vs1, 80(r4)
1204 ; CHECK-BE-NEXT: xscvdpsxws f3, f2
1205 ; CHECK-BE-NEXT: xxswapd vs2, vs2
1206 ; CHECK-BE-NEXT: sldi r5, r5, 48
1207 ; CHECK-BE-NEXT: vmrghh v4, v4, v1
1208 ; CHECK-BE-NEXT: mtvsrd v1, r5
1209 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
1210 ; CHECK-BE-NEXT: vmrghh v5, v5, v1
1211 ; CHECK-BE-NEXT: mfvsrwz r5, f0
1212 ; CHECK-BE-NEXT: lxv vs0, 64(r4)
1213 ; CHECK-BE-NEXT: mfvsrwz r4, f3
1214 ; CHECK-BE-NEXT: sldi r4, r4, 48
1215 ; CHECK-BE-NEXT: vmrghw v3, v5, v4
1216 ; CHECK-BE-NEXT: xxmrghd vs3, v3, v2
1217 ; CHECK-BE-NEXT: mtvsrd v2, r4
1218 ; CHECK-BE-NEXT: mfvsrwz r4, f2
1219 ; CHECK-BE-NEXT: xscvdpsxws f2, f1
1220 ; CHECK-BE-NEXT: xxswapd vs1, vs1
1221 ; CHECK-BE-NEXT: sldi r4, r4, 48
1222 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
1223 ; CHECK-BE-NEXT: mtvsrd v3, r4
1224 ; CHECK-BE-NEXT: vmrghh v2, v2, v3
1225 ; CHECK-BE-NEXT: mfvsrwz r4, f2
1226 ; CHECK-BE-NEXT: sldi r4, r4, 48
1227 ; CHECK-BE-NEXT: mtvsrd v3, r4
1228 ; CHECK-BE-NEXT: mfvsrwz r4, f1
1229 ; CHECK-BE-NEXT: xscvdpsxws f1, f0
1230 ; CHECK-BE-NEXT: xxswapd vs0, vs0
1231 ; CHECK-BE-NEXT: sldi r4, r4, 48
1232 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
1233 ; CHECK-BE-NEXT: mtvsrd v4, r4
1234 ; CHECK-BE-NEXT: vmrghh v3, v3, v4
1235 ; CHECK-BE-NEXT: mfvsrwz r4, f1
1236 ; CHECK-BE-NEXT: sldi r4, r4, 48
1237 ; CHECK-BE-NEXT: mtvsrd v4, r4
1238 ; CHECK-BE-NEXT: mfvsrwz r4, f0
1239 ; CHECK-BE-NEXT: sldi r5, r5, 48
1240 ; CHECK-BE-NEXT: mtvsrd v1, r5
1241 ; CHECK-BE-NEXT: vmrghh v0, v0, v1
1242 ; CHECK-BE-NEXT: vmrghw v2, v2, v0
1243 ; CHECK-BE-NEXT: stxv vs3, 0(r3)
1244 ; CHECK-BE-NEXT: sldi r4, r4, 48
1245 ; CHECK-BE-NEXT: mtvsrd v5, r4
1246 ; CHECK-BE-NEXT: vmrghh v4, v4, v5
1247 ; CHECK-BE-NEXT: vmrghw v3, v4, v3
1248 ; CHECK-BE-NEXT: xxmrghd vs0, v3, v2
1249 ; CHECK-BE-NEXT: stxv vs0, 16(r3)
1250 ; CHECK-BE-NEXT: blr
1251 entry:
1252 %a = load <16 x double>, <16 x double>* %0, align 128
1253 %1 = fptosi <16 x double> %a to <16 x i16>
1254 store <16 x i16> %1, <16 x i16>* %agg.result, align 32
1255 ret void
1256 }