| blob | 2179db537d4e2fe1b8c53c8a8be6db328984a769 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
3 ; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
4 ; RUN: FileCheck %s --check-prefix=CHECK-P8
5 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
6 ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
7 ; RUN: FileCheck %s --check-prefix=CHECK-P9
8 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
9 ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
10 ; RUN: FileCheck %s --check-prefix=CHECK-BE
12 define i64 @test2elt(i32 %a.coerce) local_unnamed_addr #0 {
13 ; CHECK-P8-LABEL: test2elt:
14 ; CHECK-P8: # %bb.0: # %entry
15 ; CHECK-P8-NEXT: mtvsrd f0, r3
16 ; CHECK-P8-NEXT: mfvsrd r3, f0
17 ; CHECK-P8-NEXT: clrldi r4, r3, 48
18 ; CHECK-P8-NEXT: rldicl r3, r3, 48, 48
19 ; CHECK-P8-NEXT: rlwinm r4, r4, 0, 16, 31
20 ; CHECK-P8-NEXT: rlwinm r3, r3, 0, 16, 31
21 ; CHECK-P8-NEXT: mtfprwz f0, r4
22 ; CHECK-P8-NEXT: mtfprwz f1, r3
23 ; CHECK-P8-NEXT: xscvuxdsp f0, f0
24 ; CHECK-P8-NEXT: xscvuxdsp f1, f1
25 ; CHECK-P8-NEXT: xscvdpspn vs0, f0
26 ; CHECK-P8-NEXT: xscvdpspn vs1, f1
27 ; CHECK-P8-NEXT: xxsldwi v2, vs0, vs0, 1
28 ; CHECK-P8-NEXT: xxsldwi v3, vs1, vs1, 1
29 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
30 ; CHECK-P8-NEXT: xxswapd vs0, v2
31 ; CHECK-P8-NEXT: mfvsrd r3, f0
32 ; CHECK-P8-NEXT: blr
33 ;
34 ; CHECK-P9-LABEL: test2elt:
35 ; CHECK-P9: # %bb.0: # %entry
36 ; CHECK-P9-NEXT: mtvsrws v2, r3
37 ; CHECK-P9-NEXT: li r3, 0
38 ; CHECK-P9-NEXT: vextuhrx r3, r3, v2
39 ; CHECK-P9-NEXT: rlwinm r3, r3, 0, 16, 31
40 ; CHECK-P9-NEXT: mtfprwz f0, r3
41 ; CHECK-P9-NEXT: li r3, 2
42 ; CHECK-P9-NEXT: xscvuxdsp f0, f0
43 ; CHECK-P9-NEXT: xscvdpspn vs0, f0
44 ; CHECK-P9-NEXT: vextuhrx r3, r3, v2
45 ; CHECK-P9-NEXT: rlwinm r3, r3, 0, 16, 31
46 ; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 1
47 ; CHECK-P9-NEXT: mtfprwz f0, r3
48 ; CHECK-P9-NEXT: xscvuxdsp f0, f0
49 ; CHECK-P9-NEXT: xscvdpspn vs0, f0
50 ; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 1
51 ; CHECK-P9-NEXT: vmrglw v2, v2, v3
52 ; CHECK-P9-NEXT: mfvsrld r3, v2
53 ; CHECK-P9-NEXT: blr
54 ;
55 ; CHECK-BE-LABEL: test2elt:
56 ; CHECK-BE: # %bb.0: # %entry
57 ; CHECK-BE-NEXT: mtvsrws v2, r3
58 ; CHECK-BE-NEXT: li r3, 2
59 ; CHECK-BE-NEXT: vextuhlx r3, r3, v2
60 ; CHECK-BE-NEXT: rlwinm r3, r3, 0, 16, 31
61 ; CHECK-BE-NEXT: mtfprwz f0, r3
62 ; CHECK-BE-NEXT: li r3, 0
63 ; CHECK-BE-NEXT: xscvuxdsp f0, f0
64 ; CHECK-BE-NEXT: vextuhlx r3, r3, v2
65 ; CHECK-BE-NEXT: rlwinm r3, r3, 0, 16, 31
66 ; CHECK-BE-NEXT: xscvdpspn v3, f0
67 ; CHECK-BE-NEXT: mtfprwz f0, r3
68 ; CHECK-BE-NEXT: xscvuxdsp f0, f0
69 ; CHECK-BE-NEXT: xscvdpspn v2, f0
70 ; CHECK-BE-NEXT: vmrghw v2, v2, v3
71 ; CHECK-BE-NEXT: mfvsrd r3, v2
72 ; CHECK-BE-NEXT: blr
73 entry:
74 %0 = bitcast i32 %a.coerce to <2 x i16>
75 %1 = uitofp <2 x i16> %0 to <2 x float>
76 %2 = bitcast <2 x float> %1 to i64
77 ret i64 %2
78 }
80 define <4 x float> @test4elt(i64 %a.coerce) local_unnamed_addr #1 {
81 ; CHECK-P8-LABEL: test4elt:
82 ; CHECK-P8: # %bb.0: # %entry
83 ; CHECK-P8-NEXT: addis r4, r2, .LCPI1_0@toc@ha
84 ; CHECK-P8-NEXT: mtvsrd f0, r3
85 ; CHECK-P8-NEXT: addi r3, r4, .LCPI1_0@toc@l
86 ; CHECK-P8-NEXT: xxlxor v4, v4, v4
87 ; CHECK-P8-NEXT: xxswapd v2, vs0
88 ; CHECK-P8-NEXT: lvx v3, 0, r3
89 ; CHECK-P8-NEXT: vperm v2, v4, v2, v3
90 ; CHECK-P8-NEXT: xvcvuxwsp v2, v2
91 ; CHECK-P8-NEXT: blr
92 ;
93 ; CHECK-P9-LABEL: test4elt:
94 ; CHECK-P9: # %bb.0: # %entry
95 ; CHECK-P9-NEXT: mtvsrd f0, r3
96 ; CHECK-P9-NEXT: addis r3, r2, .LCPI1_0@toc@ha
97 ; CHECK-P9-NEXT: addi r3, r3, .LCPI1_0@toc@l
98 ; CHECK-P9-NEXT: lxvx v3, 0, r3
99 ; CHECK-P9-NEXT: xxswapd v2, vs0
100 ; CHECK-P9-NEXT: xxlxor v4, v4, v4
101 ; CHECK-P9-NEXT: vperm v2, v4, v2, v3
102 ; CHECK-P9-NEXT: xvcvuxwsp v2, v2
103 ; CHECK-P9-NEXT: blr
104 ;
105 ; CHECK-BE-LABEL: test4elt:
106 ; CHECK-BE: # %bb.0: # %entry
107 ; CHECK-BE-NEXT: mtvsrd v2, r3
108 ; CHECK-BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha
109 ; CHECK-BE-NEXT: addi r3, r3, .LCPI1_0@toc@l
110 ; CHECK-BE-NEXT: lxvx v3, 0, r3
111 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
112 ; CHECK-BE-NEXT: vperm v2, v2, v4, v3
113 ; CHECK-BE-NEXT: xvcvuxwsp v2, v2
114 ; CHECK-BE-NEXT: blr
115 entry:
116 %0 = bitcast i64 %a.coerce to <4 x i16>
117 %1 = uitofp <4 x i16> %0 to <4 x float>
118 ret <4 x float> %1
119 }
121 define void @test8elt(<8 x float>* noalias nocapture sret %agg.result, <8 x i16> %a) local_unnamed_addr #2 {
122 ; CHECK-P8-LABEL: test8elt:
123 ; CHECK-P8: # %bb.0: # %entry
124 ; CHECK-P8-NEXT: addis r4, r2, .LCPI2_0@toc@ha
125 ; CHECK-P8-NEXT: addis r5, r2, .LCPI2_1@toc@ha
126 ; CHECK-P8-NEXT: xxlxor v4, v4, v4
127 ; CHECK-P8-NEXT: addi r4, r4, .LCPI2_0@toc@l
128 ; CHECK-P8-NEXT: lvx v3, 0, r4
129 ; CHECK-P8-NEXT: addi r4, r5, .LCPI2_1@toc@l
130 ; CHECK-P8-NEXT: lvx v5, 0, r4
131 ; CHECK-P8-NEXT: li r4, 16
132 ; CHECK-P8-NEXT: vperm v3, v4, v2, v3
133 ; CHECK-P8-NEXT: vperm v2, v4, v2, v5
134 ; CHECK-P8-NEXT: xvcvuxwsp v3, v3
135 ; CHECK-P8-NEXT: xvcvuxwsp v2, v2
136 ; CHECK-P8-NEXT: stvx v3, 0, r3
137 ; CHECK-P8-NEXT: stvx v2, r3, r4
138 ; CHECK-P8-NEXT: blr
139 ;
140 ; CHECK-P9-LABEL: test8elt:
141 ; CHECK-P9: # %bb.0: # %entry
142 ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha
143 ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l
144 ; CHECK-P9-NEXT: lxvx v3, 0, r4
145 ; CHECK-P9-NEXT: xxlxor v4, v4, v4
146 ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_1@toc@ha
147 ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_1@toc@l
148 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
149 ; CHECK-P9-NEXT: xvcvuxwsp vs0, v3
150 ; CHECK-P9-NEXT: lxvx v3, 0, r4
151 ; CHECK-P9-NEXT: vperm v2, v4, v2, v3
152 ; CHECK-P9-NEXT: stxv vs0, 0(r3)
153 ; CHECK-P9-NEXT: xvcvuxwsp vs1, v2
154 ; CHECK-P9-NEXT: stxv vs1, 16(r3)
155 ; CHECK-P9-NEXT: blr
156 ;
157 ; CHECK-BE-LABEL: test8elt:
158 ; CHECK-BE: # %bb.0: # %entry
159 ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha
160 ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_0@toc@l
161 ; CHECK-BE-NEXT: lxvx v3, 0, r4
162 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
163 ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_1@toc@ha
164 ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_1@toc@l
165 ; CHECK-BE-NEXT: vperm v3, v2, v4, v3
166 ; CHECK-BE-NEXT: xvcvuxwsp vs0, v3
167 ; CHECK-BE-NEXT: lxvx v3, 0, r4
168 ; CHECK-BE-NEXT: vperm v2, v4, v2, v3
169 ; CHECK-BE-NEXT: stxv vs0, 0(r3)
170 ; CHECK-BE-NEXT: xvcvuxwsp vs1, v2
171 ; CHECK-BE-NEXT: stxv vs1, 16(r3)
172 ; CHECK-BE-NEXT: blr
173 entry:
174 %0 = uitofp <8 x i16> %a to <8 x float>
175 store <8 x float> %0, <8 x float>* %agg.result, align 32
176 ret void
177 }
179 define void @test16elt(<16 x float>* noalias nocapture sret %agg.result, <16 x i16>* nocapture readonly) local_unnamed_addr #3 {
180 ; CHECK-P8-LABEL: test16elt:
181 ; CHECK-P8: # %bb.0: # %entry
182 ; CHECK-P8-NEXT: addis r5, r2, .LCPI3_0@toc@ha
183 ; CHECK-P8-NEXT: addis r6, r2, .LCPI3_1@toc@ha
184 ; CHECK-P8-NEXT: xxlxor v3, v3, v3
185 ; CHECK-P8-NEXT: lvx v4, 0, r4
186 ; CHECK-P8-NEXT: addi r5, r5, .LCPI3_0@toc@l
187 ; CHECK-P8-NEXT: addi r6, r6, .LCPI3_1@toc@l
188 ; CHECK-P8-NEXT: lvx v2, 0, r5
189 ; CHECK-P8-NEXT: li r5, 16
190 ; CHECK-P8-NEXT: lvx v0, 0, r6
191 ; CHECK-P8-NEXT: li r6, 32
192 ; CHECK-P8-NEXT: lvx v5, r4, r5
193 ; CHECK-P8-NEXT: li r4, 48
194 ; CHECK-P8-NEXT: vperm v1, v3, v4, v2
195 ; CHECK-P8-NEXT: vperm v2, v3, v5, v2
196 ; CHECK-P8-NEXT: vperm v5, v3, v5, v0
197 ; CHECK-P8-NEXT: vperm v3, v3, v4, v0
198 ; CHECK-P8-NEXT: xvcvuxwsp v4, v1
199 ; CHECK-P8-NEXT: xvcvuxwsp v2, v2
200 ; CHECK-P8-NEXT: xvcvuxwsp v5, v5
201 ; CHECK-P8-NEXT: xvcvuxwsp v3, v3
202 ; CHECK-P8-NEXT: stvx v4, 0, r3
203 ; CHECK-P8-NEXT: stvx v2, r3, r6
204 ; CHECK-P8-NEXT: stvx v5, r3, r4
205 ; CHECK-P8-NEXT: stvx v3, r3, r5
206 ; CHECK-P8-NEXT: blr
207 ;
208 ; CHECK-P9-LABEL: test16elt:
209 ; CHECK-P9: # %bb.0: # %entry
210 ; CHECK-P9-NEXT: lxv v2, 16(r4)
211 ; CHECK-P9-NEXT: lxv v3, 0(r4)
212 ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha
213 ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l
214 ; CHECK-P9-NEXT: lxvx v4, 0, r4
215 ; CHECK-P9-NEXT: xxlxor v5, v5, v5
216 ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_1@toc@ha
217 ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_1@toc@l
218 ; CHECK-P9-NEXT: vperm v0, v5, v3, v4
219 ; CHECK-P9-NEXT: xvcvuxwsp vs0, v0
220 ; CHECK-P9-NEXT: lxvx v0, 0, r4
221 ; CHECK-P9-NEXT: vperm v3, v5, v3, v0
222 ; CHECK-P9-NEXT: stxv vs0, 0(r3)
223 ; CHECK-P9-NEXT: xvcvuxwsp vs1, v3
224 ; CHECK-P9-NEXT: vperm v3, v5, v2, v4
225 ; CHECK-P9-NEXT: vperm v2, v5, v2, v0
226 ; CHECK-P9-NEXT: xvcvuxwsp vs2, v3
227 ; CHECK-P9-NEXT: xvcvuxwsp vs3, v2
228 ; CHECK-P9-NEXT: stxv vs1, 16(r3)
229 ; CHECK-P9-NEXT: stxv vs3, 48(r3)
230 ; CHECK-P9-NEXT: stxv vs2, 32(r3)
231 ; CHECK-P9-NEXT: blr
232 ;
233 ; CHECK-BE-LABEL: test16elt:
234 ; CHECK-BE: # %bb.0: # %entry
235 ; CHECK-BE-NEXT: lxv v2, 16(r4)
236 ; CHECK-BE-NEXT: lxv v3, 0(r4)
237 ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha
238 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l
239 ; CHECK-BE-NEXT: lxvx v4, 0, r4
240 ; CHECK-BE-NEXT: xxlxor v5, v5, v5
241 ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_1@toc@ha
242 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_1@toc@l
243 ; CHECK-BE-NEXT: vperm v0, v3, v5, v4
244 ; CHECK-BE-NEXT: xvcvuxwsp vs0, v0
245 ; CHECK-BE-NEXT: lxvx v0, 0, r4
246 ; CHECK-BE-NEXT: vperm v3, v5, v3, v0
247 ; CHECK-BE-NEXT: stxv vs0, 0(r3)
248 ; CHECK-BE-NEXT: xvcvuxwsp vs1, v3
249 ; CHECK-BE-NEXT: vperm v3, v2, v5, v4
250 ; CHECK-BE-NEXT: vperm v2, v5, v2, v0
251 ; CHECK-BE-NEXT: xvcvuxwsp vs2, v3
252 ; CHECK-BE-NEXT: xvcvuxwsp vs3, v2
253 ; CHECK-BE-NEXT: stxv vs1, 16(r3)
254 ; CHECK-BE-NEXT: stxv vs3, 48(r3)
255 ; CHECK-BE-NEXT: stxv vs2, 32(r3)
256 ; CHECK-BE-NEXT: blr
257 entry:
258 %a = load <16 x i16>, <16 x i16>* %0, align 32
259 %1 = uitofp <16 x i16> %a to <16 x float>
260 store <16 x float> %1, <16 x float>* %agg.result, align 64
261 ret void
262 }
264 define i64 @test2elt_signed(i32 %a.coerce) local_unnamed_addr #0 {
265 ; CHECK-P8-LABEL: test2elt_signed:
266 ; CHECK-P8: # %bb.0: # %entry
267 ; CHECK-P8-NEXT: mtvsrd f0, r3
268 ; CHECK-P8-NEXT: mfvsrd r3, f0
269 ; CHECK-P8-NEXT: clrldi r4, r3, 48
270 ; CHECK-P8-NEXT: rldicl r3, r3, 48, 48
271 ; CHECK-P8-NEXT: extsh r4, r4
272 ; CHECK-P8-NEXT: extsh r3, r3
273 ; CHECK-P8-NEXT: mtfprwa f0, r4
274 ; CHECK-P8-NEXT: mtfprwa f1, r3
275 ; CHECK-P8-NEXT: xscvsxdsp f0, f0
276 ; CHECK-P8-NEXT: xscvsxdsp f1, f1
277 ; CHECK-P8-NEXT: xscvdpspn vs0, f0
278 ; CHECK-P8-NEXT: xscvdpspn vs1, f1
279 ; CHECK-P8-NEXT: xxsldwi v2, vs0, vs0, 1
280 ; CHECK-P8-NEXT: xxsldwi v3, vs1, vs1, 1
281 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
282 ; CHECK-P8-NEXT: xxswapd vs0, v2
283 ; CHECK-P8-NEXT: mfvsrd r3, f0
284 ; CHECK-P8-NEXT: blr
285 ;
286 ; CHECK-P9-LABEL: test2elt_signed:
287 ; CHECK-P9: # %bb.0: # %entry
288 ; CHECK-P9-NEXT: mtvsrws v2, r3
289 ; CHECK-P9-NEXT: li r3, 0
290 ; CHECK-P9-NEXT: vextuhrx r3, r3, v2
291 ; CHECK-P9-NEXT: extsh r3, r3
292 ; CHECK-P9-NEXT: mtfprwa f0, r3
293 ; CHECK-P9-NEXT: li r3, 2
294 ; CHECK-P9-NEXT: xscvsxdsp f0, f0
295 ; CHECK-P9-NEXT: xscvdpspn vs0, f0
296 ; CHECK-P9-NEXT: vextuhrx r3, r3, v2
297 ; CHECK-P9-NEXT: extsh r3, r3
298 ; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 1
299 ; CHECK-P9-NEXT: mtfprwa f0, r3
300 ; CHECK-P9-NEXT: xscvsxdsp f0, f0
301 ; CHECK-P9-NEXT: xscvdpspn vs0, f0
302 ; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 1
303 ; CHECK-P9-NEXT: vmrglw v2, v2, v3
304 ; CHECK-P9-NEXT: mfvsrld r3, v2
305 ; CHECK-P9-NEXT: blr
306 ;
307 ; CHECK-BE-LABEL: test2elt_signed:
308 ; CHECK-BE: # %bb.0: # %entry
309 ; CHECK-BE-NEXT: mtvsrws v2, r3
310 ; CHECK-BE-NEXT: li r3, 2
311 ; CHECK-BE-NEXT: vextuhlx r3, r3, v2
312 ; CHECK-BE-NEXT: extsh r3, r3
313 ; CHECK-BE-NEXT: mtfprwa f0, r3
314 ; CHECK-BE-NEXT: li r3, 0
315 ; CHECK-BE-NEXT: xscvsxdsp f0, f0
316 ; CHECK-BE-NEXT: vextuhlx r3, r3, v2
317 ; CHECK-BE-NEXT: extsh r3, r3
318 ; CHECK-BE-NEXT: xscvdpspn v3, f0
319 ; CHECK-BE-NEXT: mtfprwa f0, r3
320 ; CHECK-BE-NEXT: xscvsxdsp f0, f0
321 ; CHECK-BE-NEXT: xscvdpspn v2, f0
322 ; CHECK-BE-NEXT: vmrghw v2, v2, v3
323 ; CHECK-BE-NEXT: mfvsrd r3, v2
324 ; CHECK-BE-NEXT: blr
325 entry:
326 %0 = bitcast i32 %a.coerce to <2 x i16>
327 %1 = sitofp <2 x i16> %0 to <2 x float>
328 %2 = bitcast <2 x float> %1 to i64
329 ret i64 %2
330 }
332 define <4 x float> @test4elt_signed(i64 %a.coerce) local_unnamed_addr #1 {
333 ; CHECK-P8-LABEL: test4elt_signed:
334 ; CHECK-P8: # %bb.0: # %entry
335 ; CHECK-P8-NEXT: mtvsrd f0, r3
336 ; CHECK-P8-NEXT: vspltisw v3, 8
337 ; CHECK-P8-NEXT: xxswapd v2, vs0
338 ; CHECK-P8-NEXT: vadduwm v3, v3, v3
339 ; CHECK-P8-NEXT: vmrglh v2, v2, v2
340 ; CHECK-P8-NEXT: vslw v2, v2, v3
341 ; CHECK-P8-NEXT: vsraw v2, v2, v3
342 ; CHECK-P8-NEXT: xvcvsxwsp v2, v2
343 ; CHECK-P8-NEXT: blr
344 ;
345 ; CHECK-P9-LABEL: test4elt_signed:
346 ; CHECK-P9: # %bb.0: # %entry
347 ; CHECK-P9-NEXT: mtvsrd f0, r3
348 ; CHECK-P9-NEXT: xxswapd v2, vs0
349 ; CHECK-P9-NEXT: vmrglh v2, v2, v2
350 ; CHECK-P9-NEXT: vextsh2w v2, v2
351 ; CHECK-P9-NEXT: xvcvsxwsp v2, v2
352 ; CHECK-P9-NEXT: blr
353 ;
354 ; CHECK-BE-LABEL: test4elt_signed:
355 ; CHECK-BE: # %bb.0: # %entry
356 ; CHECK-BE-NEXT: mtvsrd v2, r3
357 ; CHECK-BE-NEXT: vmrghh v2, v2, v2
358 ; CHECK-BE-NEXT: vextsh2w v2, v2
359 ; CHECK-BE-NEXT: xvcvsxwsp v2, v2
360 ; CHECK-BE-NEXT: blr
361 entry:
362 %0 = bitcast i64 %a.coerce to <4 x i16>
363 %1 = sitofp <4 x i16> %0 to <4 x float>
364 ret <4 x float> %1
365 }
367 define void @test8elt_signed(<8 x float>* noalias nocapture sret %agg.result, <8 x i16> %a) local_unnamed_addr #2 {
368 ; CHECK-P8-LABEL: test8elt_signed:
369 ; CHECK-P8: # %bb.0: # %entry
370 ; CHECK-P8-NEXT: vmrglh v4, v2, v2
371 ; CHECK-P8-NEXT: vspltisw v3, 8
372 ; CHECK-P8-NEXT: li r4, 16
373 ; CHECK-P8-NEXT: vmrghh v2, v2, v2
374 ; CHECK-P8-NEXT: vadduwm v3, v3, v3
375 ; CHECK-P8-NEXT: vslw v4, v4, v3
376 ; CHECK-P8-NEXT: vslw v2, v2, v3
377 ; CHECK-P8-NEXT: vsraw v4, v4, v3
378 ; CHECK-P8-NEXT: vsraw v2, v2, v3
379 ; CHECK-P8-NEXT: xvcvsxwsp v3, v4
380 ; CHECK-P8-NEXT: xvcvsxwsp v2, v2
381 ; CHECK-P8-NEXT: stvx v3, 0, r3
382 ; CHECK-P8-NEXT: stvx v2, r3, r4
383 ; CHECK-P8-NEXT: blr
384 ;
385 ; CHECK-P9-LABEL: test8elt_signed:
386 ; CHECK-P9: # %bb.0: # %entry
387 ; CHECK-P9-NEXT: vmrglh v3, v2, v2
388 ; CHECK-P9-NEXT: vmrghh v2, v2, v2
389 ; CHECK-P9-NEXT: vextsh2w v3, v3
390 ; CHECK-P9-NEXT: vextsh2w v2, v2
391 ; CHECK-P9-NEXT: xvcvsxwsp vs0, v3
392 ; CHECK-P9-NEXT: xvcvsxwsp vs1, v2
393 ; CHECK-P9-NEXT: stxv vs1, 16(r3)
394 ; CHECK-P9-NEXT: stxv vs0, 0(r3)
395 ; CHECK-P9-NEXT: blr
396 ;
397 ; CHECK-BE-LABEL: test8elt_signed:
398 ; CHECK-BE: # %bb.0: # %entry
399 ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_0@toc@ha
400 ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_0@toc@l
401 ; CHECK-BE-NEXT: lxvx v3, 0, r4
402 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
403 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
404 ; CHECK-BE-NEXT: vmrghh v2, v2, v2
405 ; CHECK-BE-NEXT: vextsh2w v3, v3
406 ; CHECK-BE-NEXT: vextsh2w v2, v2
407 ; CHECK-BE-NEXT: xvcvsxwsp vs0, v3
408 ; CHECK-BE-NEXT: xvcvsxwsp vs1, v2
409 ; CHECK-BE-NEXT: stxv vs1, 0(r3)
410 ; CHECK-BE-NEXT: stxv vs0, 16(r3)
411 ; CHECK-BE-NEXT: blr
412 entry:
413 %0 = sitofp <8 x i16> %a to <8 x float>
414 store <8 x float> %0, <8 x float>* %agg.result, align 32
415 ret void
416 }
418 define void @test16elt_signed(<16 x float>* noalias nocapture sret %agg.result, <16 x i16>* nocapture readonly) local_unnamed_addr #3 {
419 ; CHECK-P8-LABEL: test16elt_signed:
420 ; CHECK-P8: # %bb.0: # %entry
421 ; CHECK-P8-NEXT: li r5, 16
422 ; CHECK-P8-NEXT: lvx v2, 0, r4
423 ; CHECK-P8-NEXT: vspltisw v5, 8
424 ; CHECK-P8-NEXT: li r6, 32
425 ; CHECK-P8-NEXT: lvx v3, r4, r5
426 ; CHECK-P8-NEXT: li r4, 48
427 ; CHECK-P8-NEXT: vmrglh v4, v2, v2
428 ; CHECK-P8-NEXT: vmrglh v0, v3, v3
429 ; CHECK-P8-NEXT: vmrghh v3, v3, v3
430 ; CHECK-P8-NEXT: vmrghh v2, v2, v2
431 ; CHECK-P8-NEXT: vadduwm v5, v5, v5
432 ; CHECK-P8-NEXT: vslw v4, v4, v5
433 ; CHECK-P8-NEXT: vslw v0, v0, v5
434 ; CHECK-P8-NEXT: vslw v3, v3, v5
435 ; CHECK-P8-NEXT: vslw v2, v2, v5
436 ; CHECK-P8-NEXT: vsraw v4, v4, v5
437 ; CHECK-P8-NEXT: vsraw v0, v0, v5
438 ; CHECK-P8-NEXT: vsraw v3, v3, v5
439 ; CHECK-P8-NEXT: vsraw v2, v2, v5
440 ; CHECK-P8-NEXT: xvcvsxwsp v4, v4
441 ; CHECK-P8-NEXT: xvcvsxwsp v5, v0
442 ; CHECK-P8-NEXT: xvcvsxwsp v3, v3
443 ; CHECK-P8-NEXT: xvcvsxwsp v2, v2
444 ; CHECK-P8-NEXT: stvx v4, 0, r3
445 ; CHECK-P8-NEXT: stvx v5, r3, r6
446 ; CHECK-P8-NEXT: stvx v3, r3, r4
447 ; CHECK-P8-NEXT: stvx v2, r3, r5
448 ; CHECK-P8-NEXT: blr
449 ;
450 ; CHECK-P9-LABEL: test16elt_signed:
451 ; CHECK-P9: # %bb.0: # %entry
452 ; CHECK-P9-NEXT: lxv v3, 0(r4)
453 ; CHECK-P9-NEXT: lxv v2, 16(r4)
454 ; CHECK-P9-NEXT: vmrglh v4, v3, v3
455 ; CHECK-P9-NEXT: vmrghh v3, v3, v3
456 ; CHECK-P9-NEXT: vextsh2w v3, v3
457 ; CHECK-P9-NEXT: xvcvsxwsp vs1, v3
458 ; CHECK-P9-NEXT: vmrglh v3, v2, v2
459 ; CHECK-P9-NEXT: vmrghh v2, v2, v2
460 ; CHECK-P9-NEXT: vextsh2w v4, v4
461 ; CHECK-P9-NEXT: xvcvsxwsp vs0, v4
462 ; CHECK-P9-NEXT: vextsh2w v3, v3
463 ; CHECK-P9-NEXT: vextsh2w v2, v2
464 ; CHECK-P9-NEXT: xvcvsxwsp vs2, v3
465 ; CHECK-P9-NEXT: xvcvsxwsp vs3, v2
466 ; CHECK-P9-NEXT: stxv vs1, 16(r3)
467 ; CHECK-P9-NEXT: stxv vs0, 0(r3)
468 ; CHECK-P9-NEXT: stxv vs3, 48(r3)
469 ; CHECK-P9-NEXT: stxv vs2, 32(r3)
470 ; CHECK-P9-NEXT: blr
471 ;
472 ; CHECK-BE-LABEL: test16elt_signed:
473 ; CHECK-BE: # %bb.0: # %entry
474 ; CHECK-BE-NEXT: lxv v2, 16(r4)
475 ; CHECK-BE-NEXT: lxv v3, 0(r4)
476 ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_0@toc@ha
477 ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_0@toc@l
478 ; CHECK-BE-NEXT: lxvx v4, 0, r4
479 ; CHECK-BE-NEXT: xxlxor v5, v5, v5
480 ; CHECK-BE-NEXT: vperm v0, v5, v3, v4
481 ; CHECK-BE-NEXT: vperm v4, v5, v2, v4
482 ; CHECK-BE-NEXT: vmrghh v3, v3, v3
483 ; CHECK-BE-NEXT: vmrghh v2, v2, v2
484 ; CHECK-BE-NEXT: vextsh2w v0, v0
485 ; CHECK-BE-NEXT: vextsh2w v4, v4
486 ; CHECK-BE-NEXT: vextsh2w v3, v3
487 ; CHECK-BE-NEXT: vextsh2w v2, v2
488 ; CHECK-BE-NEXT: xvcvsxwsp vs0, v0
489 ; CHECK-BE-NEXT: xvcvsxwsp vs1, v4
490 ; CHECK-BE-NEXT: xvcvsxwsp vs2, v3
491 ; CHECK-BE-NEXT: xvcvsxwsp vs3, v2
492 ; CHECK-BE-NEXT: stxv vs3, 32(r3)
493 ; CHECK-BE-NEXT: stxv vs2, 0(r3)
494 ; CHECK-BE-NEXT: stxv vs1, 48(r3)
495 ; CHECK-BE-NEXT: stxv vs0, 16(r3)
496 ; CHECK-BE-NEXT: blr
497 entry:
498 %a = load <16 x i16>, <16 x i16>* %0, align 32
499 %1 = sitofp <16 x i16> %a to <16 x float>
500 store <16 x float> %1, <16 x float>* %agg.result, align 64
501 ret void
502 }