| blob | 95cf39e79d3ccbc878c3d7d0a37dbabf019fdea3 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
3 ; RUN: | FileCheck -check-prefix=RV64I %s
4 ; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f \
5 ; RUN: -verify-machineinstrs < %s \
6 ; RUN: | FileCheck -check-prefix=RV64I %s
7 ; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64d \
8 ; RUN: -verify-machineinstrs < %s \
9 ; RUN: | FileCheck -check-prefix=RV64I %s
11 ; This file contains tests that should have identical output for the lp64,
12 ; lp64f, and lp64d ABIs. i.e. where no arguments are passed according to
13 ; the floating point ABI. It doesn't check codegen when frame pointer
14 ; elimination is disabled, as there is sufficient coverage for this case in
15 ; other files.
17 ; Check that on RV64, i128 is passed in a pair of registers. Unlike
18 ; the convention for varargs, this need not be an aligned pair.
20 define i64 @callee_i128_in_regs(i64 %a, i128 %b) nounwind {
21 ; RV64I-LABEL: callee_i128_in_regs:
22 ; RV64I: # %bb.0:
23 ; RV64I-NEXT: add a0, a0, a1
24 ; RV64I-NEXT: ret
25 %b_trunc = trunc i128 %b to i64
26 %1 = add i64 %a, %b_trunc
27 ret i64 %1
28 }
30 define i64 @caller_i128_in_regs() nounwind {
31 ; RV64I-LABEL: caller_i128_in_regs:
32 ; RV64I: # %bb.0:
33 ; RV64I-NEXT: addi sp, sp, -16
34 ; RV64I-NEXT: sd ra, 8(sp)
35 ; RV64I-NEXT: addi a0, zero, 1
36 ; RV64I-NEXT: addi a1, zero, 2
37 ; RV64I-NEXT: mv a2, zero
38 ; RV64I-NEXT: call callee_i128_in_regs
39 ; RV64I-NEXT: ld ra, 8(sp)
40 ; RV64I-NEXT: addi sp, sp, 16
41 ; RV64I-NEXT: ret
42 %1 = call i64 @callee_i128_in_regs(i64 1, i128 2)
43 ret i64 %1
44 }
46 ; Check that the stack is used once the GPRs are exhausted
48 define i32 @callee_many_scalars(i8 %a, i16 %b, i32 %c, i128 %d, i32 %e, i32 %f, i128 %g, i32 %h) nounwind {
49 ; RV64I-LABEL: callee_many_scalars:
50 ; RV64I: # %bb.0:
51 ; RV64I-NEXT: lw t0, 8(sp)
52 ; RV64I-NEXT: ld t1, 0(sp)
53 ; RV64I-NEXT: andi t2, a0, 255
54 ; RV64I-NEXT: lui a0, 16
55 ; RV64I-NEXT: addiw a0, a0, -1
56 ; RV64I-NEXT: and a0, a1, a0
57 ; RV64I-NEXT: add a0, t2, a0
58 ; RV64I-NEXT: add a0, a0, a2
59 ; RV64I-NEXT: xor a1, a4, t1
60 ; RV64I-NEXT: xor a2, a3, a7
61 ; RV64I-NEXT: or a1, a2, a1
62 ; RV64I-NEXT: seqz a1, a1
63 ; RV64I-NEXT: add a0, a1, a0
64 ; RV64I-NEXT: add a0, a0, a5
65 ; RV64I-NEXT: add a0, a0, a6
66 ; RV64I-NEXT: addw a0, a0, t0
67 ; RV64I-NEXT: ret
68 %a_ext = zext i8 %a to i32
69 %b_ext = zext i16 %b to i32
70 %1 = add i32 %a_ext, %b_ext
71 %2 = add i32 %1, %c
72 %3 = icmp eq i128 %d, %g
73 %4 = zext i1 %3 to i32
74 %5 = add i32 %4, %2
75 %6 = add i32 %5, %e
76 %7 = add i32 %6, %f
77 %8 = add i32 %7, %h
78 ret i32 %8
79 }
81 define i32 @caller_many_scalars() nounwind {
82 ; RV64I-LABEL: caller_many_scalars:
83 ; RV64I: # %bb.0:
84 ; RV64I-NEXT: addi sp, sp, -32
85 ; RV64I-NEXT: sd ra, 24(sp)
86 ; RV64I-NEXT: addi a0, zero, 8
87 ; RV64I-NEXT: sd a0, 8(sp)
88 ; RV64I-NEXT: addi a0, zero, 1
89 ; RV64I-NEXT: addi a1, zero, 2
90 ; RV64I-NEXT: addi a2, zero, 3
91 ; RV64I-NEXT: addi a3, zero, 4
92 ; RV64I-NEXT: addi a5, zero, 5
93 ; RV64I-NEXT: addi a6, zero, 6
94 ; RV64I-NEXT: addi a7, zero, 7
95 ; RV64I-NEXT: sd zero, 0(sp)
96 ; RV64I-NEXT: mv a4, zero
97 ; RV64I-NEXT: call callee_many_scalars
98 ; RV64I-NEXT: ld ra, 24(sp)
99 ; RV64I-NEXT: addi sp, sp, 32
100 ; RV64I-NEXT: ret
101 %1 = call i32 @callee_many_scalars(i8 1, i16 2, i32 3, i128 4, i32 5, i32 6, i128 7, i32 8)
102 ret i32 %1
103 }
105 ; Check that i256 is passed indirectly.
107 define i64 @callee_large_scalars(i256 %a, i256 %b) nounwind {
108 ; RV64I-LABEL: callee_large_scalars:
109 ; RV64I: # %bb.0:
110 ; RV64I-NEXT: ld a6, 0(a1)
111 ; RV64I-NEXT: ld a7, 0(a0)
112 ; RV64I-NEXT: ld a4, 8(a1)
113 ; RV64I-NEXT: ld a5, 24(a1)
114 ; RV64I-NEXT: ld a2, 24(a0)
115 ; RV64I-NEXT: ld a3, 8(a0)
116 ; RV64I-NEXT: ld a1, 16(a1)
117 ; RV64I-NEXT: ld a0, 16(a0)
118 ; RV64I-NEXT: xor a2, a2, a5
119 ; RV64I-NEXT: xor a3, a3, a4
120 ; RV64I-NEXT: or a2, a3, a2
121 ; RV64I-NEXT: xor a0, a0, a1
122 ; RV64I-NEXT: xor a1, a7, a6
123 ; RV64I-NEXT: or a0, a1, a0
124 ; RV64I-NEXT: or a0, a0, a2
125 ; RV64I-NEXT: seqz a0, a0
126 ; RV64I-NEXT: ret
127 %1 = icmp eq i256 %a, %b
128 %2 = zext i1 %1 to i64
129 ret i64 %2
130 }
132 define i64 @caller_large_scalars() nounwind {
133 ; RV64I-LABEL: caller_large_scalars:
134 ; RV64I: # %bb.0:
135 ; RV64I-NEXT: addi sp, sp, -80
136 ; RV64I-NEXT: sd ra, 72(sp)
137 ; RV64I-NEXT: sd zero, 24(sp)
138 ; RV64I-NEXT: sd zero, 16(sp)
139 ; RV64I-NEXT: sd zero, 8(sp)
140 ; RV64I-NEXT: addi a0, zero, 2
141 ; RV64I-NEXT: sd a0, 0(sp)
142 ; RV64I-NEXT: sd zero, 56(sp)
143 ; RV64I-NEXT: sd zero, 48(sp)
144 ; RV64I-NEXT: sd zero, 40(sp)
145 ; RV64I-NEXT: addi a2, zero, 1
146 ; RV64I-NEXT: addi a0, sp, 32
147 ; RV64I-NEXT: mv a1, sp
148 ; RV64I-NEXT: sd a2, 32(sp)
149 ; RV64I-NEXT: call callee_large_scalars
150 ; RV64I-NEXT: ld ra, 72(sp)
151 ; RV64I-NEXT: addi sp, sp, 80
152 ; RV64I-NEXT: ret
153 %1 = call i64 @callee_large_scalars(i256 1, i256 2)
154 ret i64 %1
155 }
157 ; Check that arguments larger than 2*xlen are handled correctly when their
158 ; address is passed on the stack rather than in memory
160 ; Must keep define on a single line due to an update_llc_test_checks.py limitation
161 define i64 @callee_large_scalars_exhausted_regs(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f, i64 %g, i256 %h, i64 %i, i256 %j) nounwind {
162 ; RV64I-LABEL: callee_large_scalars_exhausted_regs:
163 ; RV64I: # %bb.0:
164 ; RV64I-NEXT: ld a0, 8(sp)
165 ; RV64I-NEXT: ld a6, 0(a0)
166 ; RV64I-NEXT: ld t0, 0(a7)
167 ; RV64I-NEXT: ld a3, 8(a0)
168 ; RV64I-NEXT: ld a4, 24(a0)
169 ; RV64I-NEXT: ld a5, 24(a7)
170 ; RV64I-NEXT: ld a1, 8(a7)
171 ; RV64I-NEXT: ld a0, 16(a0)
172 ; RV64I-NEXT: ld a2, 16(a7)
173 ; RV64I-NEXT: xor a4, a5, a4
174 ; RV64I-NEXT: xor a1, a1, a3
175 ; RV64I-NEXT: or a1, a1, a4
176 ; RV64I-NEXT: xor a0, a2, a0
177 ; RV64I-NEXT: xor a2, t0, a6
178 ; RV64I-NEXT: or a0, a2, a0
179 ; RV64I-NEXT: or a0, a0, a1
180 ; RV64I-NEXT: seqz a0, a0
181 ; RV64I-NEXT: ret
182 %1 = icmp eq i256 %h, %j
183 %2 = zext i1 %1 to i64
184 ret i64 %2
185 }
187 define i64 @caller_large_scalars_exhausted_regs() nounwind {
188 ; RV64I-LABEL: caller_large_scalars_exhausted_regs:
189 ; RV64I: # %bb.0:
190 ; RV64I-NEXT: addi sp, sp, -96
191 ; RV64I-NEXT: sd ra, 88(sp)
192 ; RV64I-NEXT: addi a0, sp, 16
193 ; RV64I-NEXT: sd a0, 8(sp)
194 ; RV64I-NEXT: addi a0, zero, 9
195 ; RV64I-NEXT: sd a0, 0(sp)
196 ; RV64I-NEXT: sd zero, 40(sp)
197 ; RV64I-NEXT: sd zero, 32(sp)
198 ; RV64I-NEXT: sd zero, 24(sp)
199 ; RV64I-NEXT: addi a0, zero, 10
200 ; RV64I-NEXT: sd a0, 16(sp)
201 ; RV64I-NEXT: sd zero, 72(sp)
202 ; RV64I-NEXT: sd zero, 64(sp)
203 ; RV64I-NEXT: sd zero, 56(sp)
204 ; RV64I-NEXT: addi t0, zero, 8
205 ; RV64I-NEXT: addi a7, sp, 48
206 ; RV64I-NEXT: addi a0, zero, 1
207 ; RV64I-NEXT: addi a1, zero, 2
208 ; RV64I-NEXT: addi a2, zero, 3
209 ; RV64I-NEXT: addi a3, zero, 4
210 ; RV64I-NEXT: addi a4, zero, 5
211 ; RV64I-NEXT: addi a5, zero, 6
212 ; RV64I-NEXT: addi a6, zero, 7
213 ; RV64I-NEXT: sd t0, 48(sp)
214 ; RV64I-NEXT: call callee_large_scalars_exhausted_regs
215 ; RV64I-NEXT: ld ra, 88(sp)
216 ; RV64I-NEXT: addi sp, sp, 96
217 ; RV64I-NEXT: ret
218 %1 = call i64 @callee_large_scalars_exhausted_regs(
219 i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7, i256 8, i64 9,
220 i256 10)
221 ret i64 %1
222 }
224 ; Ensure that libcalls generated in the middle-end obey the calling convention
226 define i64 @caller_mixed_scalar_libcalls(i64 %a) nounwind {
227 ; RV64I-LABEL: caller_mixed_scalar_libcalls:
228 ; RV64I: # %bb.0:
229 ; RV64I-NEXT: addi sp, sp, -16
230 ; RV64I-NEXT: sd ra, 8(sp)
231 ; RV64I-NEXT: call __floatditf
232 ; RV64I-NEXT: ld ra, 8(sp)
233 ; RV64I-NEXT: addi sp, sp, 16
234 ; RV64I-NEXT: ret
235 %1 = sitofp i64 %a to fp128
236 %2 = bitcast fp128 %1 to i128
237 %3 = trunc i128 %2 to i64
238 ret i64 %3
239 }
241 ; Check passing of coerced integer arrays
243 %struct.small = type { i64, i64* }
245 define i64 @callee_small_coerced_struct([2 x i64] %a.coerce) nounwind {
246 ; RV64I-LABEL: callee_small_coerced_struct:
247 ; RV64I: # %bb.0:
248 ; RV64I-NEXT: xor a0, a0, a1
249 ; RV64I-NEXT: seqz a0, a0
250 ; RV64I-NEXT: ret
251 %1 = extractvalue [2 x i64] %a.coerce, 0
252 %2 = extractvalue [2 x i64] %a.coerce, 1
253 %3 = icmp eq i64 %1, %2
254 %4 = zext i1 %3 to i64
255 ret i64 %4
256 }
258 define i64 @caller_small_coerced_struct() nounwind {
259 ; RV64I-LABEL: caller_small_coerced_struct:
260 ; RV64I: # %bb.0:
261 ; RV64I-NEXT: addi sp, sp, -16
262 ; RV64I-NEXT: sd ra, 8(sp)
263 ; RV64I-NEXT: addi a0, zero, 1
264 ; RV64I-NEXT: addi a1, zero, 2
265 ; RV64I-NEXT: call callee_small_coerced_struct
266 ; RV64I-NEXT: ld ra, 8(sp)
267 ; RV64I-NEXT: addi sp, sp, 16
268 ; RV64I-NEXT: ret
269 %1 = call i64 @callee_small_coerced_struct([2 x i64] [i64 1, i64 2])
270 ret i64 %1
271 }
273 ; Check large struct arguments, which are passed byval
275 %struct.large = type { i64, i64, i64, i64 }
277 define i64 @callee_large_struct(%struct.large* byval align 8 %a) nounwind {
278 ; RV64I-LABEL: callee_large_struct:
279 ; RV64I: # %bb.0:
280 ; RV64I-NEXT: ld a1, 0(a0)
281 ; RV64I-NEXT: ld a0, 24(a0)
282 ; RV64I-NEXT: add a0, a1, a0
283 ; RV64I-NEXT: ret
284 %1 = getelementptr inbounds %struct.large, %struct.large* %a, i64 0, i32 0
285 %2 = getelementptr inbounds %struct.large, %struct.large* %a, i64 0, i32 3
286 %3 = load i64, i64* %1
287 %4 = load i64, i64* %2
288 %5 = add i64 %3, %4
289 ret i64 %5
290 }
292 define i64 @caller_large_struct() nounwind {
293 ; RV64I-LABEL: caller_large_struct:
294 ; RV64I: # %bb.0:
295 ; RV64I-NEXT: addi sp, sp, -80
296 ; RV64I-NEXT: sd ra, 72(sp)
297 ; RV64I-NEXT: addi a0, zero, 1
298 ; RV64I-NEXT: sd a0, 40(sp)
299 ; RV64I-NEXT: addi a1, zero, 2
300 ; RV64I-NEXT: sd a1, 48(sp)
301 ; RV64I-NEXT: addi a2, zero, 3
302 ; RV64I-NEXT: sd a2, 56(sp)
303 ; RV64I-NEXT: addi a3, zero, 4
304 ; RV64I-NEXT: sd a3, 64(sp)
305 ; RV64I-NEXT: sd a0, 8(sp)
306 ; RV64I-NEXT: sd a1, 16(sp)
307 ; RV64I-NEXT: sd a2, 24(sp)
308 ; RV64I-NEXT: sd a3, 32(sp)
309 ; RV64I-NEXT: addi a0, sp, 8
310 ; RV64I-NEXT: call callee_large_struct
311 ; RV64I-NEXT: ld ra, 72(sp)
312 ; RV64I-NEXT: addi sp, sp, 80
313 ; RV64I-NEXT: ret
314 %ls = alloca %struct.large, align 8
315 %1 = bitcast %struct.large* %ls to i8*
316 %a = getelementptr inbounds %struct.large, %struct.large* %ls, i64 0, i32 0
317 store i64 1, i64* %a
318 %b = getelementptr inbounds %struct.large, %struct.large* %ls, i64 0, i32 1
319 store i64 2, i64* %b
320 %c = getelementptr inbounds %struct.large, %struct.large* %ls, i64 0, i32 2
321 store i64 3, i64* %c
322 %d = getelementptr inbounds %struct.large, %struct.large* %ls, i64 0, i32 3
323 store i64 4, i64* %d
324 %2 = call i64 @callee_large_struct(%struct.large* byval align 8 %ls)
325 ret i64 %2
326 }
328 ; Check 2x*xlen values are aligned appropriately when passed on the stack
329 ; Must keep define on a single line due to an update_llc_test_checks.py limitation
330 define i64 @callee_aligned_stack(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i128 %f, i64 %g, i64 %h, i128 %i, i64 %j, [2 x i64] %k) nounwind {
331 ; The i128 should be 16-byte aligned on the stack, but the two-element array
332 ; should only be 8-byte aligned
333 ; RV64I-LABEL: callee_aligned_stack:
334 ; RV64I: # %bb.0:
335 ; RV64I-NEXT: ld a0, 40(sp)
336 ; RV64I-NEXT: ld a1, 0(sp)
337 ; RV64I-NEXT: ld a2, 16(sp)
338 ; RV64I-NEXT: ld a3, 32(sp)
339 ; RV64I-NEXT: add a4, a5, a7
340 ; RV64I-NEXT: add a1, a4, a1
341 ; RV64I-NEXT: add a1, a1, a2
342 ; RV64I-NEXT: add a1, a1, a3
343 ; RV64I-NEXT: add a0, a1, a0
344 ; RV64I-NEXT: ret
345 %f_trunc = trunc i128 %f to i64
346 %1 = add i64 %f_trunc, %g
347 %2 = add i64 %1, %h
348 %3 = trunc i128 %i to i64
349 %4 = add i64 %2, %3
350 %5 = add i64 %4, %j
351 %6 = extractvalue [2 x i64] %k, 0
352 %7 = add i64 %5, %6
353 ret i64 %7
354 }
356 define void @caller_aligned_stack() nounwind {
357 ; The i128 should be 16-byte aligned on the stack, but the two-element array
358 ; should only be 8-byte aligned
359 ; RV64I-LABEL: caller_aligned_stack:
360 ; RV64I: # %bb.0:
361 ; RV64I-NEXT: addi sp, sp, -64
362 ; RV64I-NEXT: sd ra, 56(sp)
363 ; RV64I-NEXT: addi a0, zero, 12
364 ; RV64I-NEXT: sd a0, 48(sp)
365 ; RV64I-NEXT: addi a0, zero, 11
366 ; RV64I-NEXT: sd a0, 40(sp)
367 ; RV64I-NEXT: addi a0, zero, 10
368 ; RV64I-NEXT: sd a0, 32(sp)
369 ; RV64I-NEXT: sd zero, 24(sp)
370 ; RV64I-NEXT: addi a0, zero, 9
371 ; RV64I-NEXT: sd a0, 16(sp)
372 ; RV64I-NEXT: addi a6, zero, 8
373 ; RV64I-NEXT: addi a0, zero, 1
374 ; RV64I-NEXT: addi a1, zero, 2
375 ; RV64I-NEXT: addi a2, zero, 3
376 ; RV64I-NEXT: addi a3, zero, 4
377 ; RV64I-NEXT: addi a4, zero, 5
378 ; RV64I-NEXT: addi a5, zero, 6
379 ; RV64I-NEXT: addi a7, zero, 7
380 ; RV64I-NEXT: sd a6, 0(sp)
381 ; RV64I-NEXT: mv a6, zero
382 ; RV64I-NEXT: call callee_aligned_stack
383 ; RV64I-NEXT: ld ra, 56(sp)
384 ; RV64I-NEXT: addi sp, sp, 64
385 ; RV64I-NEXT: ret
386 %1 = call i64 @callee_aligned_stack(i64 1, i64 2, i64 3, i64 4, i64 5,
387 i128 6, i64 7, i64 8, i128 9, i64 10, [2 x i64] [i64 11, i64 12])
388 ret void
389 }
391 ; Check return of 2x xlen scalars
393 define i128 @callee_small_scalar_ret() nounwind {
394 ; RV64I-LABEL: callee_small_scalar_ret:
395 ; RV64I: # %bb.0:
396 ; RV64I-NEXT: addi a0, zero, -1
397 ; RV64I-NEXT: addi a1, zero, -1
398 ; RV64I-NEXT: ret
399 ret i128 -1
400 }
402 define i64 @caller_small_scalar_ret() nounwind {
403 ; RV64I-LABEL: caller_small_scalar_ret:
404 ; RV64I: # %bb.0:
405 ; RV64I-NEXT: addi sp, sp, -16
406 ; RV64I-NEXT: sd ra, 8(sp)
407 ; RV64I-NEXT: call callee_small_scalar_ret
408 ; RV64I-NEXT: not a1, a1
409 ; RV64I-NEXT: xori a0, a0, -2
410 ; RV64I-NEXT: or a0, a0, a1
411 ; RV64I-NEXT: seqz a0, a0
412 ; RV64I-NEXT: ld ra, 8(sp)
413 ; RV64I-NEXT: addi sp, sp, 16
414 ; RV64I-NEXT: ret
415 %1 = call i128 @callee_small_scalar_ret()
416 %2 = icmp eq i128 -2, %1
417 %3 = zext i1 %2 to i64
418 ret i64 %3
419 }
421 ; Check return of 2x xlen structs
423 define %struct.small @callee_small_struct_ret() nounwind {
424 ; RV64I-LABEL: callee_small_struct_ret:
425 ; RV64I: # %bb.0:
426 ; RV64I-NEXT: addi a0, zero, 1
427 ; RV64I-NEXT: mv a1, zero
428 ; RV64I-NEXT: ret
429 ret %struct.small { i64 1, i64* null }
430 }
432 define i64 @caller_small_struct_ret() nounwind {
433 ; RV64I-LABEL: caller_small_struct_ret:
434 ; RV64I: # %bb.0:
435 ; RV64I-NEXT: addi sp, sp, -16
436 ; RV64I-NEXT: sd ra, 8(sp)
437 ; RV64I-NEXT: call callee_small_struct_ret
438 ; RV64I-NEXT: add a0, a0, a1
439 ; RV64I-NEXT: ld ra, 8(sp)
440 ; RV64I-NEXT: addi sp, sp, 16
441 ; RV64I-NEXT: ret
442 %1 = call %struct.small @callee_small_struct_ret()
443 %2 = extractvalue %struct.small %1, 0
444 %3 = extractvalue %struct.small %1, 1
445 %4 = ptrtoint i64* %3 to i64
446 %5 = add i64 %2, %4
447 ret i64 %5
448 }
450 ; Check return of >2x xlen scalars
452 define i256 @callee_large_scalar_ret() nounwind {
453 ; RV64I-LABEL: callee_large_scalar_ret:
454 ; RV64I: # %bb.0:
455 ; RV64I-NEXT: addi a1, zero, -1
456 ; RV64I-NEXT: sd a1, 24(a0)
457 ; RV64I-NEXT: sd a1, 16(a0)
458 ; RV64I-NEXT: sd a1, 8(a0)
459 ; RV64I-NEXT: lui a1, 1018435
460 ; RV64I-NEXT: addiw a1, a1, 747
461 ; RV64I-NEXT: sd a1, 0(a0)
462 ; RV64I-NEXT: ret
463 ret i256 -123456789
464 }
466 define void @caller_large_scalar_ret() nounwind {
467 ; RV64I-LABEL: caller_large_scalar_ret:
468 ; RV64I: # %bb.0:
469 ; RV64I-NEXT: addi sp, sp, -48
470 ; RV64I-NEXT: sd ra, 40(sp)
471 ; RV64I-NEXT: mv a0, sp
472 ; RV64I-NEXT: call callee_large_scalar_ret
473 ; RV64I-NEXT: ld ra, 40(sp)
474 ; RV64I-NEXT: addi sp, sp, 48
475 ; RV64I-NEXT: ret
476 %1 = call i256 @callee_large_scalar_ret()
477 ret void
478 }
480 ; Check return of >2x xlen structs
482 define void @callee_large_struct_ret(%struct.large* noalias sret %agg.result) nounwind {
483 ; RV64I-LABEL: callee_large_struct_ret:
484 ; RV64I: # %bb.0:
485 ; RV64I-NEXT: sw zero, 4(a0)
486 ; RV64I-NEXT: addi a1, zero, 1
487 ; RV64I-NEXT: sw a1, 0(a0)
488 ; RV64I-NEXT: sw zero, 12(a0)
489 ; RV64I-NEXT: addi a1, zero, 2
490 ; RV64I-NEXT: sw a1, 8(a0)
491 ; RV64I-NEXT: sw zero, 20(a0)
492 ; RV64I-NEXT: addi a1, zero, 3
493 ; RV64I-NEXT: sw a1, 16(a0)
494 ; RV64I-NEXT: sw zero, 28(a0)
495 ; RV64I-NEXT: addi a1, zero, 4
496 ; RV64I-NEXT: sw a1, 24(a0)
497 ; RV64I-NEXT: ret
498 %a = getelementptr inbounds %struct.large, %struct.large* %agg.result, i64 0, i32 0
499 store i64 1, i64* %a, align 4
500 %b = getelementptr inbounds %struct.large, %struct.large* %agg.result, i64 0, i32 1
501 store i64 2, i64* %b, align 4
502 %c = getelementptr inbounds %struct.large, %struct.large* %agg.result, i64 0, i32 2
503 store i64 3, i64* %c, align 4
504 %d = getelementptr inbounds %struct.large, %struct.large* %agg.result, i64 0, i32 3
505 store i64 4, i64* %d, align 4
506 ret void
507 }
509 define i64 @caller_large_struct_ret() nounwind {
510 ; RV64I-LABEL: caller_large_struct_ret:
511 ; RV64I: # %bb.0:
512 ; RV64I-NEXT: addi sp, sp, -48
513 ; RV64I-NEXT: sd ra, 40(sp)
514 ; RV64I-NEXT: addi a0, sp, 8
515 ; RV64I-NEXT: call callee_large_struct_ret
516 ; RV64I-NEXT: ld a0, 8(sp)
517 ; RV64I-NEXT: ld a1, 32(sp)
518 ; RV64I-NEXT: add a0, a0, a1
519 ; RV64I-NEXT: ld ra, 40(sp)
520 ; RV64I-NEXT: addi sp, sp, 48
521 ; RV64I-NEXT: ret
522 %1 = alloca %struct.large
523 call void @callee_large_struct_ret(%struct.large* sret %1)
524 %2 = getelementptr inbounds %struct.large, %struct.large* %1, i64 0, i32 0
525 %3 = load i64, i64* %2
526 %4 = getelementptr inbounds %struct.large, %struct.large* %1, i64 0, i32 3
527 %5 = load i64, i64* %4
528 %6 = add i64 %3, %5
529 ret i64 %6
530 }