| blob | ca9326ad66a2629456d212b549985367d3244c3e |
1 ; RUN: llc < %s -mtriple=thumbv7-none-eabi -mcpu=cortex-m3 | FileCheck %s -check-prefix=CHECK -check-prefix=NONE
2 ; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m4 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=SP
3 ; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m7 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP
4 ; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a8 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP
8 define i1 @cmp_f_false(float %a, float %b) {
9 ; CHECK-LABEL: cmp_f_false:
10 ; NONE: movs r0, #0
11 ; HARD: movs r0, #0
12 %1 = fcmp false float %a, %b
13 ret i1 %1
14 }
15 define i1 @cmp_f_oeq(float %a, float %b) {
16 ; CHECK-LABEL: cmp_f_oeq:
17 ; NONE: bl __aeabi_fcmpeq
18 ; HARD: vcmp.f32
19 ; HARD: moveq r0, #1
20 %1 = fcmp oeq float %a, %b
21 ret i1 %1
22 }
23 define i1 @cmp_f_ogt(float %a, float %b) {
24 ; CHECK-LABEL: cmp_f_ogt:
25 ; NONE: bl __aeabi_fcmpgt
26 ; HARD: vcmp.f32
27 ; HARD: movgt r0, #1
28 %1 = fcmp ogt float %a, %b
29 ret i1 %1
30 }
31 define i1 @cmp_f_oge(float %a, float %b) {
32 ; CHECK-LABEL: cmp_f_oge:
33 ; NONE: bl __aeabi_fcmpge
34 ; HARD: vcmp.f32
35 ; HARD: movge r0, #1
36 %1 = fcmp oge float %a, %b
37 ret i1 %1
38 }
39 define i1 @cmp_f_olt(float %a, float %b) {
40 ; CHECK-LABEL: cmp_f_olt:
41 ; NONE: bl __aeabi_fcmplt
42 ; HARD: vcmp.f32
43 ; HARD: movmi r0, #1
44 %1 = fcmp olt float %a, %b
45 ret i1 %1
46 }
47 define i1 @cmp_f_ole(float %a, float %b) {
48 ; CHECK-LABEL: cmp_f_ole:
49 ; NONE: bl __aeabi_fcmple
50 ; HARD: vcmp.f32
51 ; HARD: movls r0, #1
52 %1 = fcmp ole float %a, %b
53 ret i1 %1
54 }
55 define i1 @cmp_f_one(float %a, float %b) {
56 ; CHECK-LABEL: cmp_f_one:
57 ; NONE: bl __aeabi_fcmpgt
58 ; NONE: bl __aeabi_fcmplt
59 ; HARD: vcmp.f32
60 ; HARD: movmi r0, #1
61 ; HARD: movgt r0, #1
62 %1 = fcmp one float %a, %b
63 ret i1 %1
64 }
65 define i1 @cmp_f_ord(float %a, float %b) {
66 ; CHECK-LABEL: cmp_f_ord:
67 ; NONE: bl __aeabi_fcmpun
68 ; HARD: vcmp.f32
69 ; HARD: movvc r0, #1
70 %1 = fcmp ord float %a, %b
71 ret i1 %1
72 }
73 define i1 @cmp_f_ueq(float %a, float %b) {
74 ; CHECK-LABEL: cmp_f_ueq:
75 ; NONE: bl __aeabi_fcmpeq
76 ; NONE: bl __aeabi_fcmpun
77 ; HARD: vcmp.f32
78 ; HARD: moveq r0, #1
79 ; HARD: movvs r0, #1
80 %1 = fcmp ueq float %a, %b
81 ret i1 %1
82 }
83 define i1 @cmp_f_ugt(float %a, float %b) {
84 ; CHECK-LABEL: cmp_f_ugt:
85 ; NONE: bl __aeabi_fcmple
86 ; NONE-NEXT: clz r0, r0
87 ; NONE-NEXT: lsrs r0, r0, #5
88 ; HARD: vcmp.f32
89 ; HARD: movhi r0, #1
90 %1 = fcmp ugt float %a, %b
91 ret i1 %1
92 }
93 define i1 @cmp_f_uge(float %a, float %b) {
94 ; CHECK-LABEL: cmp_f_uge:
95 ; NONE: bl __aeabi_fcmplt
96 ; NONE-NEXT: clz r0, r0
97 ; NONE-NEXT: lsrs r0, r0, #5
98 ; HARD: vcmp.f32
99 ; HARD: movpl r0, #1
100 %1 = fcmp uge float %a, %b
101 ret i1 %1
102 }
103 define i1 @cmp_f_ult(float %a, float %b) {
104 ; CHECK-LABEL: cmp_f_ult:
105 ; NONE: bl __aeabi_fcmpge
106 ; NONE-NEXT: clz r0, r0
107 ; NONE-NEXT: lsrs r0, r0, #5
108 ; HARD: vcmp.f32
109 ; HARD: movlt r0, #1
110 %1 = fcmp ult float %a, %b
111 ret i1 %1
112 }
113 define i1 @cmp_f_ule(float %a, float %b) {
114 ; CHECK-LABEL: cmp_f_ule:
115 ; NONE: bl __aeabi_fcmpgt
116 ; NONE-NEXT: clz r0, r0
117 ; NONE-NEXT: lsrs r0, r0, #5
118 ; HARD: vcmp.f32
119 ; HARD: movle r0, #1
120 %1 = fcmp ule float %a, %b
121 ret i1 %1
122 }
123 define i1 @cmp_f_une(float %a, float %b) {
124 ; CHECK-LABEL: cmp_f_une:
125 ; NONE: bl __aeabi_fcmpeq
126 ; HARD: vcmp.f32
127 ; HARD: movne r0, #1
128 %1 = fcmp une float %a, %b
129 ret i1 %1
130 }
131 define i1 @cmp_f_uno(float %a, float %b) {
132 ; CHECK-LABEL: cmp_f_uno:
133 ; NONE: bl __aeabi_fcmpun
134 ; HARD: vcmp.f32
135 ; HARD: movvs r0, #1
136 %1 = fcmp uno float %a, %b
137 ret i1 %1
138 }
139 define i1 @cmp_f_true(float %a, float %b) {
140 ; CHECK-LABEL: cmp_f_true:
141 ; NONE: movs r0, #1
142 ; HARD: movs r0, #1
143 %1 = fcmp true float %a, %b
144 ret i1 %1
145 }
147 define i1 @cmp_d_false(double %a, double %b) {
148 ; CHECK-LABEL: cmp_d_false:
149 ; NONE: movs r0, #0
150 ; HARD: movs r0, #0
151 %1 = fcmp false double %a, %b
152 ret i1 %1
153 }
154 define i1 @cmp_d_oeq(double %a, double %b) {
155 ; CHECK-LABEL: cmp_d_oeq:
156 ; NONE: bl __aeabi_dcmpeq
157 ; SP: bl __aeabi_dcmpeq
158 ; DP: vcmp.f64
159 ; DP: moveq r0, #1
160 %1 = fcmp oeq double %a, %b
161 ret i1 %1
162 }
163 define i1 @cmp_d_ogt(double %a, double %b) {
164 ; CHECK-LABEL: cmp_d_ogt:
165 ; NONE: bl __aeabi_dcmpgt
166 ; SP: bl __aeabi_dcmpgt
167 ; DP: vcmp.f64
168 ; DP: movgt r0, #1
169 %1 = fcmp ogt double %a, %b
170 ret i1 %1
171 }
172 define i1 @cmp_d_oge(double %a, double %b) {
173 ; CHECK-LABEL: cmp_d_oge:
174 ; NONE: bl __aeabi_dcmpge
175 ; SP: bl __aeabi_dcmpge
176 ; DP: vcmp.f64
177 ; DP: movge r0, #1
178 %1 = fcmp oge double %a, %b
179 ret i1 %1
180 }
181 define i1 @cmp_d_olt(double %a, double %b) {
182 ; CHECK-LABEL: cmp_d_olt:
183 ; NONE: bl __aeabi_dcmplt
184 ; SP: bl __aeabi_dcmplt
185 ; DP: vcmp.f64
186 ; DP: movmi r0, #1
187 %1 = fcmp olt double %a, %b
188 ret i1 %1
189 }
190 define i1 @cmp_d_ole(double %a, double %b) {
191 ; CHECK-LABEL: cmp_d_ole:
192 ; NONE: bl __aeabi_dcmple
193 ; SP: bl __aeabi_dcmple
194 ; DP: vcmp.f64
195 ; DP: movls r0, #1
196 %1 = fcmp ole double %a, %b
197 ret i1 %1
198 }
199 define i1 @cmp_d_one(double %a, double %b) {
200 ; CHECK-LABEL: cmp_d_one:
201 ; NONE: bl __aeabi_dcmpgt
202 ; NONE: bl __aeabi_dcmplt
203 ; SP: bl __aeabi_dcmpgt
204 ; SP: bl __aeabi_dcmplt
205 ; DP: vcmp.f64
206 ; DP: movmi r0, #1
207 ; DP: movgt r0, #1
208 %1 = fcmp one double %a, %b
209 ret i1 %1
210 }
211 define i1 @cmp_d_ord(double %a, double %b) {
212 ; CHECK-LABEL: cmp_d_ord:
213 ; NONE: bl __aeabi_dcmpun
214 ; SP: bl __aeabi_dcmpun
215 ; DP: vcmp.f64
216 ; DP: movvc r0, #1
217 %1 = fcmp ord double %a, %b
218 ret i1 %1
219 }
220 define i1 @cmp_d_ugt(double %a, double %b) {
221 ; CHECK-LABEL: cmp_d_ugt:
222 ; NONE: bl __aeabi_dcmple
223 ; SP: bl __aeabi_dcmple
224 ; DP: vcmp.f64
225 ; DP: movhi r0, #1
226 %1 = fcmp ugt double %a, %b
227 ret i1 %1
228 }
230 define i1 @cmp_d_ult(double %a, double %b) {
231 ; CHECK-LABEL: cmp_d_ult:
232 ; NONE: bl __aeabi_dcmpge
233 ; SP: bl __aeabi_dcmpge
234 ; DP: vcmp.f64
235 ; DP: movlt r0, #1
236 %1 = fcmp ult double %a, %b
237 ret i1 %1
238 }
241 define i1 @cmp_d_uno(double %a, double %b) {
242 ; CHECK-LABEL: cmp_d_uno:
243 ; NONE: bl __aeabi_dcmpun
244 ; SP: bl __aeabi_dcmpun
245 ; DP: vcmp.f64
246 ; DP: movvs r0, #1
247 %1 = fcmp uno double %a, %b
248 ret i1 %1
249 }
250 define i1 @cmp_d_true(double %a, double %b) {
251 ; CHECK-LABEL: cmp_d_true:
252 ; NONE: movs r0, #1
253 ; HARD: movs r0, #1
254 %1 = fcmp true double %a, %b
255 ret i1 %1
256 }
257 define i1 @cmp_d_ueq(double %a, double %b) {
258 ; CHECK-LABEL: cmp_d_ueq:
259 ; NONE: bl __aeabi_dcmpeq
260 ; NONE: bl __aeabi_dcmpun
261 ; SP: bl __aeabi_dcmpeq
262 ; SP: bl __aeabi_dcmpun
263 ; DP: vcmp.f64
264 ; DP: moveq r0, #1
265 ; DP: movvs r0, #1
266 %1 = fcmp ueq double %a, %b
267 ret i1 %1
268 }
270 define i1 @cmp_d_uge(double %a, double %b) {
271 ; CHECK-LABEL: cmp_d_uge:
272 ; NONE: bl __aeabi_dcmplt
273 ; SP: bl __aeabi_dcmplt
274 ; DP: vcmp.f64
275 ; DP: movpl r0, #1
276 %1 = fcmp uge double %a, %b
277 ret i1 %1
278 }
280 define i1 @cmp_d_ule(double %a, double %b) {
281 ; CHECK-LABEL: cmp_d_ule:
282 ; NONE: bl __aeabi_dcmpgt
283 ; SP: bl __aeabi_dcmpgt
284 ; DP: vcmp.f64
285 ; DP: movle r0, #1
286 %1 = fcmp ule double %a, %b
287 ret i1 %1
288 }
290 define i1 @cmp_d_une(double %a, double %b) {
291 ; CHECK-LABEL: cmp_d_une:
292 ; NONE: bl __aeabi_dcmpeq
293 ; SP: bl __aeabi_dcmpeq
294 ; DP: vcmp.f64
295 ; DP: movne r0, #1
296 %1 = fcmp une double %a, %b
297 ret i1 %1
298 }