| blob | 61a78eb722e0cd10b337177be8efd65b2e42bcc3 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE
3 ; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE
5 define arm_aapcs_vfpcc <4 x i32> @bitcast_to_v4i1(i4 %b, <4 x i32> %a) {
6 ; CHECK-LE-LABEL: bitcast_to_v4i1:
7 ; CHECK-LE: @ %bb.0: @ %entry
8 ; CHECK-LE-NEXT: .pad #4
9 ; CHECK-LE-NEXT: sub sp, #4
10 ; CHECK-LE-NEXT: and r0, r0, #15
11 ; CHECK-LE-NEXT: vmov.i8 q1, #0x0
12 ; CHECK-LE-NEXT: vmov.i8 q2, #0xff
13 ; CHECK-LE-NEXT: vmsr p0, r0
14 ; CHECK-LE-NEXT: vpsel q1, q2, q1
15 ; CHECK-LE-NEXT: vmov.u8 r0, q1[0]
16 ; CHECK-LE-NEXT: vmov.32 q2[0], r0
17 ; CHECK-LE-NEXT: vmov.u8 r0, q1[1]
18 ; CHECK-LE-NEXT: vmov.32 q2[1], r0
19 ; CHECK-LE-NEXT: vmov.u8 r0, q1[2]
20 ; CHECK-LE-NEXT: vmov.32 q2[2], r0
21 ; CHECK-LE-NEXT: vmov.u8 r0, q1[3]
22 ; CHECK-LE-NEXT: vmov.32 q2[3], r0
23 ; CHECK-LE-NEXT: vmov.i32 q1, #0x0
24 ; CHECK-LE-NEXT: vcmp.i32 ne, q2, zr
25 ; CHECK-LE-NEXT: vpsel q0, q0, q1
26 ; CHECK-LE-NEXT: add sp, #4
27 ; CHECK-LE-NEXT: bx lr
28 ;
29 ; CHECK-BE-LABEL: bitcast_to_v4i1:
30 ; CHECK-BE: @ %bb.0: @ %entry
31 ; CHECK-BE-NEXT: .pad #4
32 ; CHECK-BE-NEXT: sub sp, #4
33 ; CHECK-BE-NEXT: and r0, r0, #15
34 ; CHECK-BE-NEXT: vmov.i8 q1, #0x0
35 ; CHECK-BE-NEXT: vmov.i8 q2, #0xff
36 ; CHECK-BE-NEXT: vmsr p0, r0
37 ; CHECK-BE-NEXT: vpsel q1, q2, q1
38 ; CHECK-BE-NEXT: vmov.u8 r0, q1[0]
39 ; CHECK-BE-NEXT: vmov.32 q2[0], r0
40 ; CHECK-BE-NEXT: vmov.u8 r0, q1[1]
41 ; CHECK-BE-NEXT: vmov.32 q2[1], r0
42 ; CHECK-BE-NEXT: vmov.u8 r0, q1[2]
43 ; CHECK-BE-NEXT: vmov.32 q2[2], r0
44 ; CHECK-BE-NEXT: vmov.u8 r0, q1[3]
45 ; CHECK-BE-NEXT: vmov.32 q2[3], r0
46 ; CHECK-BE-NEXT: vrev64.32 q1, q0
47 ; CHECK-BE-NEXT: vcmp.i32 ne, q2, zr
48 ; CHECK-BE-NEXT: vmov.i32 q0, #0x0
49 ; CHECK-BE-NEXT: vpsel q1, q1, q0
50 ; CHECK-BE-NEXT: vrev64.32 q0, q1
51 ; CHECK-BE-NEXT: add sp, #4
52 ; CHECK-BE-NEXT: bx lr
53 entry:
54 %c = bitcast i4 %b to <4 x i1>
55 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> zeroinitializer
56 ret <4 x i32> %s
57 }
59 define arm_aapcs_vfpcc <8 x i16> @bitcast_to_v8i1(i8 %b, <8 x i16> %a) {
60 ; CHECK-LE-LABEL: bitcast_to_v8i1:
61 ; CHECK-LE: @ %bb.0: @ %entry
62 ; CHECK-LE-NEXT: .pad #8
63 ; CHECK-LE-NEXT: sub sp, #8
64 ; CHECK-LE-NEXT: uxtb r0, r0
65 ; CHECK-LE-NEXT: vmov.i8 q1, #0x0
66 ; CHECK-LE-NEXT: vmov.i8 q2, #0xff
67 ; CHECK-LE-NEXT: vmsr p0, r0
68 ; CHECK-LE-NEXT: vpsel q2, q2, q1
69 ; CHECK-LE-NEXT: vmov.u8 r0, q2[0]
70 ; CHECK-LE-NEXT: vmov.16 q1[0], r0
71 ; CHECK-LE-NEXT: vmov.u8 r0, q2[1]
72 ; CHECK-LE-NEXT: vmov.16 q1[1], r0
73 ; CHECK-LE-NEXT: vmov.u8 r0, q2[2]
74 ; CHECK-LE-NEXT: vmov.16 q1[2], r0
75 ; CHECK-LE-NEXT: vmov.u8 r0, q2[3]
76 ; CHECK-LE-NEXT: vmov.16 q1[3], r0
77 ; CHECK-LE-NEXT: vmov.u8 r0, q2[4]
78 ; CHECK-LE-NEXT: vmov.16 q1[4], r0
79 ; CHECK-LE-NEXT: vmov.u8 r0, q2[5]
80 ; CHECK-LE-NEXT: vmov.16 q1[5], r0
81 ; CHECK-LE-NEXT: vmov.u8 r0, q2[6]
82 ; CHECK-LE-NEXT: vmov.16 q1[6], r0
83 ; CHECK-LE-NEXT: vmov.u8 r0, q2[7]
84 ; CHECK-LE-NEXT: vmov.16 q1[7], r0
85 ; CHECK-LE-NEXT: vcmp.i16 ne, q1, zr
86 ; CHECK-LE-NEXT: vmov.i32 q1, #0x0
87 ; CHECK-LE-NEXT: vpsel q0, q0, q1
88 ; CHECK-LE-NEXT: add sp, #8
89 ; CHECK-LE-NEXT: bx lr
90 ;
91 ; CHECK-BE-LABEL: bitcast_to_v8i1:
92 ; CHECK-BE: @ %bb.0: @ %entry
93 ; CHECK-BE-NEXT: .pad #8
94 ; CHECK-BE-NEXT: sub sp, #8
95 ; CHECK-BE-NEXT: uxtb r0, r0
96 ; CHECK-BE-NEXT: vmov.i8 q1, #0x0
97 ; CHECK-BE-NEXT: vmov.i8 q2, #0xff
98 ; CHECK-BE-NEXT: vmsr p0, r0
99 ; CHECK-BE-NEXT: vpsel q2, q2, q1
100 ; CHECK-BE-NEXT: vmov.u8 r0, q2[0]
101 ; CHECK-BE-NEXT: vmov.16 q1[0], r0
102 ; CHECK-BE-NEXT: vmov.u8 r0, q2[1]
103 ; CHECK-BE-NEXT: vmov.16 q1[1], r0
104 ; CHECK-BE-NEXT: vmov.u8 r0, q2[2]
105 ; CHECK-BE-NEXT: vmov.16 q1[2], r0
106 ; CHECK-BE-NEXT: vmov.u8 r0, q2[3]
107 ; CHECK-BE-NEXT: vmov.16 q1[3], r0
108 ; CHECK-BE-NEXT: vmov.u8 r0, q2[4]
109 ; CHECK-BE-NEXT: vmov.16 q1[4], r0
110 ; CHECK-BE-NEXT: vmov.u8 r0, q2[5]
111 ; CHECK-BE-NEXT: vmov.16 q1[5], r0
112 ; CHECK-BE-NEXT: vmov.u8 r0, q2[6]
113 ; CHECK-BE-NEXT: vmov.16 q1[6], r0
114 ; CHECK-BE-NEXT: vmov.u8 r0, q2[7]
115 ; CHECK-BE-NEXT: vmov.16 q1[7], r0
116 ; CHECK-BE-NEXT: vcmp.i16 ne, q1, zr
117 ; CHECK-BE-NEXT: vrev64.16 q1, q0
118 ; CHECK-BE-NEXT: vmov.i32 q0, #0x0
119 ; CHECK-BE-NEXT: vrev32.16 q0, q0
120 ; CHECK-BE-NEXT: vpsel q1, q1, q0
121 ; CHECK-BE-NEXT: vrev64.16 q0, q1
122 ; CHECK-BE-NEXT: add sp, #8
123 ; CHECK-BE-NEXT: bx lr
124 entry:
125 %c = bitcast i8 %b to <8 x i1>
126 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> zeroinitializer
127 ret <8 x i16> %s
128 }
130 define arm_aapcs_vfpcc <16 x i8> @bitcast_to_v16i1(i16 %b, <16 x i8> %a) {
131 ; CHECK-LE-LABEL: bitcast_to_v16i1:
132 ; CHECK-LE: @ %bb.0: @ %entry
133 ; CHECK-LE-NEXT: .save {r4, r6, r7, lr}
134 ; CHECK-LE-NEXT: push {r4, r6, r7, lr}
135 ; CHECK-LE-NEXT: .setfp r7, sp, #8
136 ; CHECK-LE-NEXT: add r7, sp, #8
137 ; CHECK-LE-NEXT: .pad #16
138 ; CHECK-LE-NEXT: sub sp, #16
139 ; CHECK-LE-NEXT: mov r4, sp
140 ; CHECK-LE-NEXT: bfc r4, #0, #4
141 ; CHECK-LE-NEXT: mov sp, r4
142 ; CHECK-LE-NEXT: uxth r0, r0
143 ; CHECK-LE-NEXT: sub.w r4, r7, #8
144 ; CHECK-LE-NEXT: vmov.i32 q1, #0x0
145 ; CHECK-LE-NEXT: vmsr p0, r0
146 ; CHECK-LE-NEXT: vpsel q0, q0, q1
147 ; CHECK-LE-NEXT: mov sp, r4
148 ; CHECK-LE-NEXT: pop {r4, r6, r7, pc}
149 ;
150 ; CHECK-BE-LABEL: bitcast_to_v16i1:
151 ; CHECK-BE: @ %bb.0: @ %entry
152 ; CHECK-BE-NEXT: .save {r4, r6, r7, lr}
153 ; CHECK-BE-NEXT: push {r4, r6, r7, lr}
154 ; CHECK-BE-NEXT: .setfp r7, sp, #8
155 ; CHECK-BE-NEXT: add r7, sp, #8
156 ; CHECK-BE-NEXT: .pad #16
157 ; CHECK-BE-NEXT: sub sp, #16
158 ; CHECK-BE-NEXT: mov r4, sp
159 ; CHECK-BE-NEXT: bfc r4, #0, #4
160 ; CHECK-BE-NEXT: mov sp, r4
161 ; CHECK-BE-NEXT: vrev64.8 q1, q0
162 ; CHECK-BE-NEXT: vmov.i32 q0, #0x0
163 ; CHECK-BE-NEXT: uxth r0, r0
164 ; CHECK-BE-NEXT: sub.w r4, r7, #8
165 ; CHECK-BE-NEXT: vrev32.8 q0, q0
166 ; CHECK-BE-NEXT: vmsr p0, r0
167 ; CHECK-BE-NEXT: vpsel q1, q1, q0
168 ; CHECK-BE-NEXT: vrev64.8 q0, q1
169 ; CHECK-BE-NEXT: mov sp, r4
170 ; CHECK-BE-NEXT: pop {r4, r6, r7, pc}
171 entry:
172 %c = bitcast i16 %b to <16 x i1>
173 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> zeroinitializer
174 ret <16 x i8> %s
175 }
177 define arm_aapcs_vfpcc <2 x i64> @bitcast_to_v2i1(i2 %b, <2 x i64> %a) {
178 ; CHECK-LE-LABEL: bitcast_to_v2i1:
179 ; CHECK-LE: @ %bb.0: @ %entry
180 ; CHECK-LE-NEXT: .pad #4
181 ; CHECK-LE-NEXT: sub sp, #4
182 ; CHECK-LE-NEXT: and r0, r0, #3
183 ; CHECK-LE-NEXT: sbfx r1, r0, #0, #1
184 ; CHECK-LE-NEXT: sbfx r0, r0, #1, #1
185 ; CHECK-LE-NEXT: vmov.32 q1[0], r1
186 ; CHECK-LE-NEXT: vmov.32 q1[1], r1
187 ; CHECK-LE-NEXT: vmov.32 q1[2], r0
188 ; CHECK-LE-NEXT: vmov.32 q1[3], r0
189 ; CHECK-LE-NEXT: vand q0, q0, q1
190 ; CHECK-LE-NEXT: add sp, #4
191 ; CHECK-LE-NEXT: bx lr
192 ;
193 ; CHECK-BE-LABEL: bitcast_to_v2i1:
194 ; CHECK-BE: @ %bb.0: @ %entry
195 ; CHECK-BE-NEXT: .pad #4
196 ; CHECK-BE-NEXT: sub sp, #4
197 ; CHECK-BE-NEXT: and r0, r0, #3
198 ; CHECK-BE-NEXT: sbfx r1, r0, #0, #1
199 ; CHECK-BE-NEXT: sbfx r0, r0, #1, #1
200 ; CHECK-BE-NEXT: vmov.32 q1[0], r1
201 ; CHECK-BE-NEXT: vmov.32 q1[1], r1
202 ; CHECK-BE-NEXT: vmov.32 q1[2], r0
203 ; CHECK-BE-NEXT: vmov.32 q1[3], r0
204 ; CHECK-BE-NEXT: vrev64.32 q2, q1
205 ; CHECK-BE-NEXT: vand q0, q0, q2
206 ; CHECK-BE-NEXT: add sp, #4
207 ; CHECK-BE-NEXT: bx lr
208 entry:
209 %c = bitcast i2 %b to <2 x i1>
210 %s = select <2 x i1> %c, <2 x i64> %a, <2 x i64> zeroinitializer
211 ret <2 x i64> %s
212 }
215 define arm_aapcs_vfpcc i4 @bitcast_from_v4i1(<4 x i32> %a) {
216 ; CHECK-LE-LABEL: bitcast_from_v4i1:
217 ; CHECK-LE: @ %bb.0: @ %entry
218 ; CHECK-LE-NEXT: .pad #4
219 ; CHECK-LE-NEXT: sub sp, #4
220 ; CHECK-LE-NEXT: vcmp.i32 eq, q0, zr
221 ; CHECK-LE-NEXT: vmrs r1, p0
222 ; CHECK-LE-NEXT: and r0, r1, #1
223 ; CHECK-LE-NEXT: rsbs r2, r0, #0
224 ; CHECK-LE-NEXT: movs r0, #0
225 ; CHECK-LE-NEXT: bfi r0, r2, #0, #1
226 ; CHECK-LE-NEXT: ubfx r2, r1, #4, #1
227 ; CHECK-LE-NEXT: rsbs r2, r2, #0
228 ; CHECK-LE-NEXT: bfi r0, r2, #1, #1
229 ; CHECK-LE-NEXT: ubfx r2, r1, #8, #1
230 ; CHECK-LE-NEXT: ubfx r1, r1, #12, #1
231 ; CHECK-LE-NEXT: rsbs r2, r2, #0
232 ; CHECK-LE-NEXT: bfi r0, r2, #2, #1
233 ; CHECK-LE-NEXT: rsbs r1, r1, #0
234 ; CHECK-LE-NEXT: bfi r0, r1, #3, #1
235 ; CHECK-LE-NEXT: add sp, #4
236 ; CHECK-LE-NEXT: bx lr
237 ;
238 ; CHECK-BE-LABEL: bitcast_from_v4i1:
239 ; CHECK-BE: @ %bb.0: @ %entry
240 ; CHECK-BE-NEXT: .pad #4
241 ; CHECK-BE-NEXT: sub sp, #4
242 ; CHECK-BE-NEXT: vrev64.32 q1, q0
243 ; CHECK-BE-NEXT: vcmp.i32 eq, q1, zr
244 ; CHECK-BE-NEXT: vmrs r1, p0
245 ; CHECK-BE-NEXT: and r0, r1, #1
246 ; CHECK-BE-NEXT: rsbs r2, r0, #0
247 ; CHECK-BE-NEXT: movs r0, #0
248 ; CHECK-BE-NEXT: bfi r0, r2, #0, #1
249 ; CHECK-BE-NEXT: ubfx r2, r1, #4, #1
250 ; CHECK-BE-NEXT: rsbs r2, r2, #0
251 ; CHECK-BE-NEXT: bfi r0, r2, #1, #1
252 ; CHECK-BE-NEXT: ubfx r2, r1, #8, #1
253 ; CHECK-BE-NEXT: ubfx r1, r1, #12, #1
254 ; CHECK-BE-NEXT: rsbs r2, r2, #0
255 ; CHECK-BE-NEXT: bfi r0, r2, #2, #1
256 ; CHECK-BE-NEXT: rsbs r1, r1, #0
257 ; CHECK-BE-NEXT: bfi r0, r1, #3, #1
258 ; CHECK-BE-NEXT: add sp, #4
259 ; CHECK-BE-NEXT: bx lr
260 entry:
261 %c = icmp eq <4 x i32> %a, zeroinitializer
262 %b = bitcast <4 x i1> %c to i4
263 ret i4 %b
264 }
266 define arm_aapcs_vfpcc i8 @bitcast_from_v8i1(<8 x i16> %a) {
267 ; CHECK-LE-LABEL: bitcast_from_v8i1:
268 ; CHECK-LE: @ %bb.0: @ %entry
269 ; CHECK-LE-NEXT: .pad #8
270 ; CHECK-LE-NEXT: sub sp, #8
271 ; CHECK-LE-NEXT: vcmp.i16 eq, q0, zr
272 ; CHECK-LE-NEXT: vmrs r1, p0
273 ; CHECK-LE-NEXT: and r0, r1, #1
274 ; CHECK-LE-NEXT: rsbs r2, r0, #0
275 ; CHECK-LE-NEXT: movs r0, #0
276 ; CHECK-LE-NEXT: bfi r0, r2, #0, #1
277 ; CHECK-LE-NEXT: ubfx r2, r1, #2, #1
278 ; CHECK-LE-NEXT: rsbs r2, r2, #0
279 ; CHECK-LE-NEXT: bfi r0, r2, #1, #1
280 ; CHECK-LE-NEXT: ubfx r2, r1, #4, #1
281 ; CHECK-LE-NEXT: rsbs r2, r2, #0
282 ; CHECK-LE-NEXT: bfi r0, r2, #2, #1
283 ; CHECK-LE-NEXT: ubfx r2, r1, #6, #1
284 ; CHECK-LE-NEXT: rsbs r2, r2, #0
285 ; CHECK-LE-NEXT: bfi r0, r2, #3, #1
286 ; CHECK-LE-NEXT: ubfx r2, r1, #8, #1
287 ; CHECK-LE-NEXT: rsbs r2, r2, #0
288 ; CHECK-LE-NEXT: bfi r0, r2, #4, #1
289 ; CHECK-LE-NEXT: ubfx r2, r1, #10, #1
290 ; CHECK-LE-NEXT: rsbs r2, r2, #0
291 ; CHECK-LE-NEXT: bfi r0, r2, #5, #1
292 ; CHECK-LE-NEXT: ubfx r2, r1, #12, #1
293 ; CHECK-LE-NEXT: ubfx r1, r1, #14, #1
294 ; CHECK-LE-NEXT: rsbs r2, r2, #0
295 ; CHECK-LE-NEXT: bfi r0, r2, #6, #1
296 ; CHECK-LE-NEXT: rsbs r1, r1, #0
297 ; CHECK-LE-NEXT: bfi r0, r1, #7, #1
298 ; CHECK-LE-NEXT: uxtb r0, r0
299 ; CHECK-LE-NEXT: add sp, #8
300 ; CHECK-LE-NEXT: bx lr
301 ;
302 ; CHECK-BE-LABEL: bitcast_from_v8i1:
303 ; CHECK-BE: @ %bb.0: @ %entry
304 ; CHECK-BE-NEXT: .pad #8
305 ; CHECK-BE-NEXT: sub sp, #8
306 ; CHECK-BE-NEXT: vrev64.16 q1, q0
307 ; CHECK-BE-NEXT: vcmp.i16 eq, q1, zr
308 ; CHECK-BE-NEXT: vmrs r1, p0
309 ; CHECK-BE-NEXT: and r0, r1, #1
310 ; CHECK-BE-NEXT: rsbs r2, r0, #0
311 ; CHECK-BE-NEXT: movs r0, #0
312 ; CHECK-BE-NEXT: bfi r0, r2, #0, #1
313 ; CHECK-BE-NEXT: ubfx r2, r1, #2, #1
314 ; CHECK-BE-NEXT: rsbs r2, r2, #0
315 ; CHECK-BE-NEXT: bfi r0, r2, #1, #1
316 ; CHECK-BE-NEXT: ubfx r2, r1, #4, #1
317 ; CHECK-BE-NEXT: rsbs r2, r2, #0
318 ; CHECK-BE-NEXT: bfi r0, r2, #2, #1
319 ; CHECK-BE-NEXT: ubfx r2, r1, #6, #1
320 ; CHECK-BE-NEXT: rsbs r2, r2, #0
321 ; CHECK-BE-NEXT: bfi r0, r2, #3, #1
322 ; CHECK-BE-NEXT: ubfx r2, r1, #8, #1
323 ; CHECK-BE-NEXT: rsbs r2, r2, #0
324 ; CHECK-BE-NEXT: bfi r0, r2, #4, #1
325 ; CHECK-BE-NEXT: ubfx r2, r1, #10, #1
326 ; CHECK-BE-NEXT: rsbs r2, r2, #0
327 ; CHECK-BE-NEXT: bfi r0, r2, #5, #1
328 ; CHECK-BE-NEXT: ubfx r2, r1, #12, #1
329 ; CHECK-BE-NEXT: ubfx r1, r1, #14, #1
330 ; CHECK-BE-NEXT: rsbs r2, r2, #0
331 ; CHECK-BE-NEXT: bfi r0, r2, #6, #1
332 ; CHECK-BE-NEXT: rsbs r1, r1, #0
333 ; CHECK-BE-NEXT: bfi r0, r1, #7, #1
334 ; CHECK-BE-NEXT: uxtb r0, r0
335 ; CHECK-BE-NEXT: add sp, #8
336 ; CHECK-BE-NEXT: bx lr
337 entry:
338 %c = icmp eq <8 x i16> %a, zeroinitializer
339 %b = bitcast <8 x i1> %c to i8
340 ret i8 %b
341 }
343 define arm_aapcs_vfpcc i16 @bitcast_from_v16i1(<16 x i8> %a) {
344 ; CHECK-LE-LABEL: bitcast_from_v16i1:
345 ; CHECK-LE: @ %bb.0: @ %entry
346 ; CHECK-LE-NEXT: .save {r4, r6, r7, lr}
347 ; CHECK-LE-NEXT: push {r4, r6, r7, lr}
348 ; CHECK-LE-NEXT: .setfp r7, sp, #8
349 ; CHECK-LE-NEXT: add r7, sp, #8
350 ; CHECK-LE-NEXT: .pad #16
351 ; CHECK-LE-NEXT: sub sp, #16
352 ; CHECK-LE-NEXT: mov r4, sp
353 ; CHECK-LE-NEXT: bfc r4, #0, #4
354 ; CHECK-LE-NEXT: mov sp, r4
355 ; CHECK-LE-NEXT: vcmp.i8 eq, q0, zr
356 ; CHECK-LE-NEXT: sub.w r4, r7, #8
357 ; CHECK-LE-NEXT: vmrs r0, p0
358 ; CHECK-LE-NEXT: uxth r0, r0
359 ; CHECK-LE-NEXT: mov sp, r4
360 ; CHECK-LE-NEXT: pop {r4, r6, r7, pc}
361 ;
362 ; CHECK-BE-LABEL: bitcast_from_v16i1:
363 ; CHECK-BE: @ %bb.0: @ %entry
364 ; CHECK-BE-NEXT: .save {r4, r6, r7, lr}
365 ; CHECK-BE-NEXT: push {r4, r6, r7, lr}
366 ; CHECK-BE-NEXT: .setfp r7, sp, #8
367 ; CHECK-BE-NEXT: add r7, sp, #8
368 ; CHECK-BE-NEXT: .pad #16
369 ; CHECK-BE-NEXT: sub sp, #16
370 ; CHECK-BE-NEXT: mov r4, sp
371 ; CHECK-BE-NEXT: bfc r4, #0, #4
372 ; CHECK-BE-NEXT: mov sp, r4
373 ; CHECK-BE-NEXT: vrev64.8 q1, q0
374 ; CHECK-BE-NEXT: sub.w r4, r7, #8
375 ; CHECK-BE-NEXT: vcmp.i8 eq, q1, zr
376 ; CHECK-BE-NEXT: vmrs r0, p0
377 ; CHECK-BE-NEXT: uxth r0, r0
378 ; CHECK-BE-NEXT: mov sp, r4
379 ; CHECK-BE-NEXT: pop {r4, r6, r7, pc}
380 entry:
381 %c = icmp eq <16 x i8> %a, zeroinitializer
382 %b = bitcast <16 x i1> %c to i16
383 ret i16 %b
384 }
386 define arm_aapcs_vfpcc i2 @bitcast_from_v2i1(<2 x i64> %a) {
387 ; CHECK-LE-LABEL: bitcast_from_v2i1:
388 ; CHECK-LE: @ %bb.0: @ %entry
389 ; CHECK-LE-NEXT: .pad #4
390 ; CHECK-LE-NEXT: sub sp, #4
391 ; CHECK-LE-NEXT: vmov r0, s1
392 ; CHECK-LE-NEXT: vmov r1, s0
393 ; CHECK-LE-NEXT: vmov r2, s2
394 ; CHECK-LE-NEXT: orrs r0, r1
395 ; CHECK-LE-NEXT: vmov r1, s3
396 ; CHECK-LE-NEXT: cset r0, eq
397 ; CHECK-LE-NEXT: orrs r1, r2
398 ; CHECK-LE-NEXT: cset r1, eq
399 ; CHECK-LE-NEXT: ands r1, r1, #1
400 ; CHECK-LE-NEXT: it ne
401 ; CHECK-LE-NEXT: mvnne r1, #1
402 ; CHECK-LE-NEXT: bfi r1, r0, #0, #1
403 ; CHECK-LE-NEXT: and r0, r1, #3
404 ; CHECK-LE-NEXT: add sp, #4
405 ; CHECK-LE-NEXT: bx lr
406 ;
407 ; CHECK-BE-LABEL: bitcast_from_v2i1:
408 ; CHECK-BE: @ %bb.0: @ %entry
409 ; CHECK-BE-NEXT: .pad #4
410 ; CHECK-BE-NEXT: sub sp, #4
411 ; CHECK-BE-NEXT: vrev64.32 q1, q0
412 ; CHECK-BE-NEXT: vmov r0, s6
413 ; CHECK-BE-NEXT: vmov r1, s7
414 ; CHECK-BE-NEXT: vmov r2, s5
415 ; CHECK-BE-NEXT: orrs r0, r1
416 ; CHECK-BE-NEXT: vmov r1, s4
417 ; CHECK-BE-NEXT: cset r0, eq
418 ; CHECK-BE-NEXT: orrs r1, r2
419 ; CHECK-BE-NEXT: cset r1, eq
420 ; CHECK-BE-NEXT: ands r1, r1, #1
421 ; CHECK-BE-NEXT: it ne
422 ; CHECK-BE-NEXT: mvnne r1, #1
423 ; CHECK-BE-NEXT: bfi r1, r0, #0, #1
424 ; CHECK-BE-NEXT: and r0, r1, #3
425 ; CHECK-BE-NEXT: add sp, #4
426 ; CHECK-BE-NEXT: bx lr
427 entry:
428 %c = icmp eq <2 x i64> %a, zeroinitializer
429 %b = bitcast <2 x i1> %c to i2
430 ret i2 %b
431 }