[MIParser] Set RegClassOrRegBank during instruction parsing
[llvm-complete.git] / test / MC / Hexagon / bug20416.s
blob530a4e64778aa85c886513a177a32375936c0d87
1 # RUN: not llvm-mc -triple=hexagon -mv60 -mhvx -filetype=asm %s 2>%t; FileCheck %s --check-prefix=CHECK-V60-ERROR <%t
2 # RUN: llvm-mc -triple=hexagon -mv62 -mhvx -filetype=asm %s | FileCheck %s
4 // for this a v60+/hvx instruction sequence, make sure fails with v60
5 // but passes with v62. this is because this instruction uses different
6 // itinerary between v60 and v62
8 v0.h=vsat(v5.w,v9.w)
9 v16.h=vsat(v6.w,v26.w)
11 # CHECK-V60-ERROR: rror: invalid instruction packet: slot error
12 # CHECK: v0.h = vsat(v5.w,v9.w)
13 # CHECK: v16.h = vsat(v6.w,v26.w)