[MIParser] Set RegClassOrRegBank during instruction parsing
[llvm-complete.git] / test / MC / Hexagon / empty_asm.s
blob10b30ff558ed4ab9d8467d4fe7bdcfa9bf2882bf
1 # RUN: llvm-mc -triple=hexagon -filetype=asm %s -o - | FileCheck %s
3 # Verify empty packets aren't printed
4 barrier
5 {}
6 barrier
7 # CHECK: {
8 # CHECK-NEXT: barrier
9 # CHECK-NEXT: }
10 # CHECK-NOT: }
11 # CHECK: {
12 # CHECK-NEXT: barrier
13 # CHECK-NEXT: }