[MIParser] Set RegClassOrRegBank during instruction parsing
[llvm-complete.git] / test / MC / Hexagon / v60-shift.s
blob0002714cab4ab0c243fe1e32250864f10d0bfd5d
1 #RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj -mhvx %s | \
2 #RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -mhvx -d - | \
3 #RUN: FileCheck %s
5 #CHECK: 198fd829 { v9.uw = vlsr(v24.uw,{{ *}}r15) }
6 v9.uw=vlsr(v24.uw,r15)
8 #CHECK: 1999d645 { v5.uh = vlsr(v22.uh,{{ *}}r25) }
9 v5.uh=vlsr(v22.uh,r25)
11 #CHECK: 198cc303 { v3.h = vasl(v3.h,{{ *}}r12) }
12 v3.h=vasl(v3.h,r12)
14 #CHECK: 1965d7ac { v12.w = vasr(v23.w,{{ *}}r5) }
15 v12.w=vasr(v23.w,r5)
17 #CHECK: 197dddc3 { v3.h = vasr(v29.h,{{ *}}r29) }
18 v3.h=vasr(v29.h,r29)
20 #CHECK: 197adde8 { v8.w = vasl(v29.w,{{ *}}r26) }
21 v8.w=vasl(v29.w,r26)
23 #CHECK: 1977cc26 { v6 = vror(v12,{{ *}}r23) }
24 v6=vror(v12,r23)
26 #CHECK: 1e02cfad { v13.uw = vcl0(v15.uw) }
27 v13.uw=vcl0(v15.uw)
29 #CHECK: 1e02defb { v27.uh = vcl0(v30.uh) }
30 v27.uh=vcl0(v30.uh)
32 #CHECK: 1e03de90 { v16.w = vnormamt(v30.w) }
33 v16.w=vnormamt(v30.w)
35 #CHECK: 1e03d4a3 { v3.h = vnormamt(v20.h) }
36 v3.h=vnormamt(v20.h)
38 #CHECK: 1e02c2d8 { v24.h = vpopcount(v2.h) }
39 v24.h=vpopcount(v2.h)