[MIParser] Set RegClassOrRegBank during instruction parsing
[llvm-complete.git] / test / MC / Hexagon / v66.s
blob465345fb35e77165fc729c603f40e0b576ed64a9
1 # RUN: llvm-mc -arch=hexagon -mcpu=hexagonv66 -mhvx -filetype=obj %s | llvm-objdump -mcpu=hexagonv66 -mhvx -d - | FileCheck %s
3 # CHECK: 1d8362e4 { v4.w = vsatdw(v2.w,v3.w)
5 v4.w = vsatdw(v2.w, v3.w)
6 vmem(r16+#0) = v4.new
9 # CHECK: 1aaae5e0 { v1:0.w = vasrinto(v5.w,v10.w) }
10 v1:0.w = vasrinto(v5.w, v10.w)
12 # CHECK: 1aaae5e0 { v1:0.w = vasrinto(v5.w,v10.w) }
13 v1:0 = vasrinto(v5, v10)
15 # CHECK: 1d89ef14 { v20.w = vadd(v15.w,v9.w,q0):carry:sat }
16 v20.w = vadd(v15.w, v9.w, q0):carry:sat