test/TableGen/GlobalISelEmitter.td

   1 // RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common -optimize-match-table=false %s -o %T/non-optimized.cpp
   2 // RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common -optimize-match-table=true  %s -o %T/optimized.cpp
   3 // RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common %s -o %T/default.cpp
   4
   5 // RUN: FileCheck %s --check-prefixes=CHECK,R19C,R19N -input-file=%T/non-optimized.cpp
   6 // RUN: FileCheck %s --check-prefixes=CHECK,R19C,R19O -input-file=%T/optimized.cpp
   7
   8 // RUN: FileCheck %s --check-prefixes=CHECK,R21C,R21N -input-file=%T/non-optimized.cpp
   9 // RUN: FileCheck %s --check-prefixes=CHECK,R21C,R21O -input-file=%T/optimized.cpp
  10
  11 // RUN: FileCheck %s --check-prefixes=CHECK,R20C,R20N -input-file=%T/non-optimized.cpp
  12 // RUN: FileCheck %s --check-prefixes=CHECK,R20C,R20O -input-file=%T/optimized.cpp
  13
  14 // RUN: FileCheck %s --check-prefixes=CHECK,R00C,R00N -input-file=%T/non-optimized.cpp
  15 // RUN: FileCheck %s --check-prefixes=CHECK,R00C,R00O -input-file=%T/optimized.cpp
  16
  17 // RUN: FileCheck %s --check-prefixes=CHECK,R01C,R01N -input-file=%T/non-optimized.cpp
  18 // RUN: FileCheck %s --check-prefixes=CHECK,R01C,R01O -input-file=%T/optimized.cpp
  19
  20 // RUN: FileCheck %s --check-prefixes=CHECK,R02C,R02N,NOOPT -input-file=%T/non-optimized.cpp
  21 // RUN: FileCheck %s --check-prefixes=CHECK,R02C,R02O       -input-file=%T/optimized.cpp
  22
  23 // RUN: diff %T/default.cpp %T/optimized.cpp
  24
  25 include "llvm/Target/Target.td"
  26 include "GlobalISelEmitterCommon.td"
  27
  28 //===- Define the necessary boilerplate for our test target. --------------===//
  29
  30 let TargetPrefix = "mytarget" in {
  31 def int_mytarget_nop : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
  32 }
  33
  34 def complex : Operand<i32>, ComplexPattern<i32, 2, "SelectComplexPattern", []> {
  35   let MIOperandInfo = (ops i32imm, i32imm);
  36 }
  37 def gi_complex :
  38     GIComplexOperandMatcher<s32, "selectComplexPattern">,
  39     GIComplexPatternEquiv<complex>;
  40 def complex_rr : Operand<i32>, ComplexPattern<i32, 2, "SelectComplexPatternRR", []> {
  41   let MIOperandInfo = (ops GPR32, GPR32);
  42 }
  43 def gi_complex_rr :
  44     GIComplexOperandMatcher<s32, "selectComplexPatternRR">,
  45     GIComplexPatternEquiv<complex_rr>;
  46
  47 def cimm8_xform : SDNodeXForm<imm, [{
  48     uint64_t Val = N->getZExtValue() << 1;
  49     return CurDAG->getTargetConstant(Val, SDLoc(N), MVT::i64);
  50   }]>;
  51
  52 def cimm8 : Operand<i32>, ImmLeaf<i32, [{return isInt<8>(Imm);}], cimm8_xform>;
  53
  54 def gi_cimm8 : GICustomOperandRenderer<"renderImm8">,
  55                 GISDNodeXFormEquiv<cimm8_xform>;
  56
  57 def m1 : OperandWithDefaultOps <i32, (ops (i32 -1))>;
  58 def Z : OperandWithDefaultOps <i32, (ops R0)>;
  59 def m1Z : OperandWithDefaultOps <i32, (ops (i32 -1), R0)>;
  60
  61 def HasA : Predicate<"Subtarget->hasA()">;
  62 def HasB : Predicate<"Subtarget->hasB()">;
  63 def HasC : Predicate<"Subtarget->hasC()"> { let RecomputePerFunction = 1; }
  64
  65 //===- Test the function boilerplate. -------------------------------------===//
  66
  67 // CHECK: const unsigned MAX_SUBTARGET_PREDICATES = 3;
  68 // CHECK: using PredicateBitset = llvm::PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
  69
  70 // CHECK-LABEL: #ifdef GET_GLOBALISEL_TEMPORARIES_DECL
  71 // CHECK-NEXT:    mutable MatcherState State;
  72 // CHECK-NEXT:    typedef ComplexRendererFns(MyTargetInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
  73 // CHECK-NEXT:    typedef void(MyTargetInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr&) const;
  74 // CHECK-NEXT:    const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ISelInfo;
  75 // CHECK-NEXT:    static MyTargetInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
  76 // CHECK-NEXT:    static MyTargetInstructionSelector::CustomRendererFn CustomRenderers[];
  77 // CHECK-NEXT:    bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
  78 // CHECK-NEXT:    bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
  79 // CHECK-NEXT:    bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
  80 // CHECK-NEXT:    const int64_t *getMatchTable() const override;
  81 // CHECK-NEXT:    bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI) const override;
  82 // CHECK-NEXT:  #endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL
  83
  84 // CHECK-LABEL: #ifdef GET_GLOBALISEL_TEMPORARIES_INIT
  85 // CHECK-NEXT:    , State(2),
  86 // CHECK-NEXT:    ISelInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
  87 // CHECK-NEXT:  #endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT
  88
  89 // CHECK-LABEL: enum SubtargetFeatureBits : uint8_t {
  90 // CHECK-NEXT:    Feature_HasABit = 0,
  91 // CHECK-NEXT:    Feature_HasBBit = 1,
  92 // CHECK-NEXT:    Feature_HasCBit = 2,
  93 // CHECK-NEXT:  };
  94
  95 // CHECK-LABEL: PredicateBitset MyTargetInstructionSelector::
  96 // CHECK-NEXT:  computeAvailableModuleFeatures(const MyTargetSubtarget *Subtarget) const {
  97 // CHECK-NEXT:    PredicateBitset Features;
  98 // CHECK-NEXT:    if (Subtarget->hasA())
  99 // CHECK-NEXT:      Features.set(Feature_HasABit);
 100 // CHECK-NEXT:    if (Subtarget->hasB())
 101 // CHECK-NEXT:      Features.set(Feature_HasBBit);
 102 // CHECK-NEXT:    return Features;
 103 // CHECK-NEXT:  }
 104
 105 // CHECK-LABEL: PredicateBitset MyTargetInstructionSelector::
 106 // CHECK-NEXT:  computeAvailableFunctionFeatures(const MyTargetSubtarget *Subtarget, const MachineFunction *MF) const {
 107 // CHECK-NEXT:    PredicateBitset Features;
 108 // CHECK-NEXT:    if (Subtarget->hasC())
 109 // CHECK-NEXT:      Features.set(Feature_HasCBit);
 110 // CHECK-NEXT:    return Features;
 111 // CHECK-NEXT:  }
 112
 113 // CHECK-LABEL: // LLT Objects.
 114 // CHECK-NEXT:  enum {
 115 // CHECK-NEXT:    GILLT_p0s32
 116 // CHECK-NEXT:    GILLT_s32,
 117 // CHECK-NEXT:  }
 118 // CHECK-NEXT:  const static size_t NumTypeObjects = 2;
 119 // CHECK-NEXT:  const static LLT TypeObjects[] = {
 120 // CHECK-NEXT:    LLT::pointer(0, 32),
 121 // CHECK-NEXT:    LLT::scalar(32),
 122 // CHECK-NEXT:  };
 123
 124 // CHECK-LABEL: // Feature bitsets.
 125 // CHECK-NEXT:  enum {
 126 // CHECK-NEXT:    GIFBS_Invalid,
 127 // CHECK-NEXT:    GIFBS_HasA,
 128 // CHECK-NEXT:    GIFBS_HasA_HasB_HasC,
 129 // CHECK-NEXT:  }
 130 // CHECK-NEXT:  const static PredicateBitset FeatureBitsets[] {
 131 // CHECK-NEXT:    {}, // GIFBS_Invalid
 132 // CHECK-NEXT:    {Feature_HasABit, },
 133 // CHECK-NEXT:    {Feature_HasABit, Feature_HasBBit, Feature_HasCBit, },
 134 // CHECK-NEXT:  };
 135
 136 // CHECK-LABEL: // ComplexPattern predicates.
 137 // CHECK-NEXT:  enum {
 138 // CHECK-NEXT:    GICP_Invalid,
 139 // CHECK-NEXT:    GICP_gi_complex,
 140 // CHECK-NEXT:    GICP_gi_complex_rr,
 141 // CHECK-NEXT:  };
 142
 143 // CHECK-LABEL: // PatFrag predicates.
 144 // CHECK-NEXT:  enum {
 145 // CHECK-NEXT:    GIPFP_I64_Predicate_cimm8 = GIPFP_I64_Invalid + 1,
 146 // CHECK-NEXT:    GIPFP_I64_Predicate_simm8,
 147 // CHECK-NEXT:  };
 148
 149
 150 // CHECK-NEXT: bool MyTargetInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
 151 // CHECK-NEXT:   switch (PredicateID) {
 152 // CHECK-NEXT:   case GIPFP_I64_Predicate_cimm8: {
 153 // CHECK-NEXT:     return isInt<8>(Imm);
 154 // CHECK-NEXT:     llvm_unreachable("ImmediateCode should have returned");
 155 // CHECK-NEXT:     return false;
 156 // CHECK-NEXT:   }
 157 // CHECK-NEXT:   case GIPFP_I64_Predicate_simm8: {
 158 // CHECK-NEXT:      return isInt<8>(Imm);
 159 // CHECK-NEXT:     llvm_unreachable("ImmediateCode should have returned");
 160 // CHECK-NEXT:     return false;
 161 // CHECK-NEXT:   }
 162 // CHECK-NEXT:   }
 163 // CHECK-NEXT:   llvm_unreachable("Unknown predicate");
 164 // CHECK-NEXT:   return false;
 165 // CHECK-NEXT: }
 166
 167 // CHECK-LABEL: // PatFrag predicates.
 168 // CHECK-NEXT:  enum {
 169 // CHECK-NEXT:    GIPFP_APFloat_Predicate_fpimmz = GIPFP_APFloat_Invalid + 1,
 170 // CHECK-NEXT:  };
 171 // CHECK-NEXT:  bool MyTargetInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
 172 // CHECK-NEXT:    switch (PredicateID) {
 173 // CHECK-NEXT:    case GIPFP_APFloat_Predicate_fpimmz: {
 174 // CHECK-NEXT:      return Imm->isExactlyValue(0.0);
 175 // CHECK-NEXT:      llvm_unreachable("ImmediateCode should have returned");
 176 // CHECK-NEXT:      return false;
 177 // CHECK-NEXT:    }
 178 // CHECK-NEXT:    }
 179 // CHECK-NEXT:    llvm_unreachable("Unknown predicate");
 180 // CHECK-NEXT:    return false;
 181 // CHECK-NEXT:  }
 182
 183 // CHECK-LABEL: // PatFrag predicates.
 184 // CHECK-NEXT:  enum {
 185 // CHECK-NEXT:    GIPFP_APInt_Predicate_simm9 = GIPFP_APInt_Invalid + 1,
 186 // CHECK-NEXT:  };
 187 // CHECK-NEXT:  bool MyTargetInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
 188 // CHECK-NEXT:    switch (PredicateID) {
 189 // CHECK-NEXT:    case GIPFP_APInt_Predicate_simm9: {
 190 // CHECK-NEXT:      return isInt<9>(Imm->getSExtValue());
 191 // CHECK-NEXT:      llvm_unreachable("ImmediateCode should have returned");
 192 // CHECK-NEXT:      return false;
 193 // CHECK-NEXT:    }
 194 // CHECK-NEXT:    }
 195 // CHECK-NEXT:    llvm_unreachable("Unknown predicate");
 196 // CHECK-NEXT:    return false;
 197 // CHECK-NEXT:  }
 198
 199 // CHECK-LABEL: MyTargetInstructionSelector::ComplexMatcherMemFn
 200 // CHECK-NEXT:  MyTargetInstructionSelector::ComplexPredicateFns[] = {
 201 // CHECK-NEXT:    nullptr, // GICP_Invalid
 202 // CHECK-NEXT:    &MyTargetInstructionSelector::selectComplexPattern, // gi_complex
 203 // CHECK-NEXT:    &MyTargetInstructionSelector::selectComplexPatternRR, // gi_complex_rr
 204 // CHECK-NEXT:  }
 205
 206 // CHECK-LABEL: // Custom renderers.
 207 // CHECK-NEXT: enum {
 208 // CHECK-NEXT:   GICR_Invalid,
 209 // CHECK-NEXT:   GICR_renderImm8,
 210 // CHECK-NEXT: };
 211 // CHECK-NEXT: MyTargetInstructionSelector::CustomRendererFn
 212 // CHECK-NEXT: MyTargetInstructionSelector::CustomRenderers[] = {
 213 // CHECK-NEXT:   nullptr, // GICP_Invalid
 214 // CHECK-NEXT:   &MyTargetInstructionSelector::renderImm8, // gi_cimm8
 215 // CHECK-NEXT: };
 216
 217 // CHECK: bool MyTargetInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
 218 // CHECK-NEXT: MachineFunction &MF = *I.getParent()->getParent();
 219 // CHECK-NEXT: MachineRegisterInfo &MRI = MF.getRegInfo();
 220 // CHECK:      AvailableFunctionFeatures = computeAvailableFunctionFeatures(&STI, &MF);
 221 // CHECK-NEXT: const PredicateBitset AvailableFeatures = getAvailableFeatures();
 222 // CHECK-NEXT: NewMIVector OutMIs;
 223 // CHECK-NEXT: State.MIs.clear();
 224 // CHECK-NEXT: State.MIs.push_back(&I);
 225
 226 // CHECK:      if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) {
 227 // CHECK-NEXT:   return true;
 228 // CHECK-NEXT: }
 229
 230 // CHECK: const int64_t *
 231 // CHECK-LABEL: MyTargetInstructionSelector::getMatchTable() const {
 232 // CHECK-NEXT: MatchTable0[] = {
 233
 234 //===- Test a pattern with multiple ComplexPatterns in multiple instrs ----===//
 235 //
 236 // R19O-NEXT:  GIM_SwitchOpcode, /*MI*/0, /*[*/{{[0-9]+}}, {{[0-9]+}}, /*)*//*default:*//*Label [[DEFAULT_NUM:[0-9]+]]*/ [[DEFAULT:[0-9]+]],
 237 // R19O-NEXT:  /*TargetOpcode::G_ADD*//*Label [[CASE_ADD_NUM:[0-9]+]]*/ [[CASE_ADD:[0-9]+]],
 238 // R19O:       /*TargetOpcode::G_SELECT*//*Label [[CASE_SELECT_NUM:[0-9]+]]*/ [[CASE_SELECT:[0-9]+]],
 239 // R19O:       // Label [[CASE_ADD_NUM]]: @[[CASE_ADD]]
 240 // R19O:       // Label [[CASE_SELECT_NUM]]: @[[CASE_SELECT]]
 241 // R19O-NEXT:  GIM_Try, /*On fail goto*//*Label [[GROUP_NUM:[0-9]+]]*/ [[GROUP:[0-9]+]],
 242 // R19O-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 243 // R19O-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
 244 // R19O-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
 245 // R19O-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
 246 //
 247 // R19C-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
 248 //
 249 // R19O-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 250 // R19O-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 251 // R19N-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
 252 // R19N-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_SELECT,
 253 // R19N-NEXT:    // MIs[0] dst
 254 // R19N-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 255 // R19N-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 256 // R19N-NEXT:    // MIs[0] src1
 257 // R19N-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
 258 // R19N-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 259 // R19N-NEXT:    // MIs[0] Operand 2
 260 // R19N-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
 261 //
 262 // R19N-NEXT:    GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_complex_rr,
 263 // R19N-NEXT:    // MIs[0] Operand 3
 264 // R19N-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
 265 // R19C-NEXT:    GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
 266 // R19N-NEXT:    GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
 267 // R19C-NEXT:    GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SELECT,
 268 // R19N-NEXT:    // MIs[1] Operand 0
 269 // R19N-NEXT:    GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
 270 // R19N-NEXT:    // MIs[1] src3
 271 // R19C-NEXT:    GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
 272 // R19O-NEXT:    GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
 273 // R19O-NEXT:    GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
 274 // R19N-NEXT:    GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 275 // R19N-NEXT:    // MIs[1] src4
 276 // R19N-NEXT:    GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
 277 // R19N-NEXT:    GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/1, GICP_gi_complex,
 278 // R19N-NEXT:    // MIs[1] Operand 3
 279 // R19N-NEXT:    GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
 280 // R19N-NEXT:    GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/2, GICP_gi_complex,
 281 // R19O-NEXT:    GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 282 // R19C-NEXT:    GIM_CheckIsSafeToFold, /*InsnID*/1,
 283 // R19O-NEXT:    GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_complex_rr,
 284 // R19O-NEXT:    GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/1, GICP_gi_complex,
 285 // R19O-NEXT:    GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/2, GICP_gi_complex,
 286 // R19C-NEXT:    // (select:{ *:[i32] } GPR32:{ *:[i32] }:$src1, (complex_rr:{ *:[i32] } GPR32:{ *:[i32] }:$src2a, GPR32:{ *:[i32] }:$src2b), (select:{ *:[i32] } GPR32:{ *:[i32] }:$src3, complex:{ *:[i32] }:$src4, (complex:{ *:[i32] } i32imm:{ *:[i32] }:$src5a, i32imm:{ *:[i32] }:$src5b)))  =>  (INSN3:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2b, GPR32:{ *:[i32] }:$src2a, (INSN4:{ *:[i32] } GPR32:{ *:[i32] }:$src3, complex:{ *:[i32] }:$src4, i32imm:{ *:[i32] }:$src5a, i32imm:{ *:[i32] }:$src5b))
 287 // R19C-NEXT:    GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
 288 // R19C-NEXT:    GIR_BuildMI, /*InsnID*/1, /*Opcode*/MyTarget::INSN4,
 289 // R19C-NEXT:    GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
 290 // R19C-NEXT:    GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src3
 291 // R19C-NEXT:    GIR_ComplexRenderer, /*InsnID*/1, /*RendererID*/1,
 292 // R19C-NEXT:    GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/2, /*SubOperand*/0, // src5a
 293 // R19C-NEXT:    GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/2, /*SubOperand*/1, // src5b
 294 // R19C-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
 295 // R19C-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::INSN3,
 296 // R19C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
 297 // R19C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
 298 // R19C-NEXT:    GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src2b
 299 // R19C-NEXT:    GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src2a
 300 // R19C-NEXT:    GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
 301 // R19C-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
 302 // R19C-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
 303 // R19C-NEXT:    // GIR_Coverage, 19,
 304 // R19C-NEXT:    GIR_Done,
 305 // R19C-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
 306 //
 307 // R19O:       // Label [[GROUP_NUM]]: @[[GROUP]]
 308 // R19O-NEXT:  GIM_Reject,
 309 // R19O:       // Label [[DEFAULT_NUM]]: @[[DEFAULT]]
 310 // R19O-NEXT:  GIM_Reject,
 311 // R19O-NEXT:  };
 312
 313 def INSN3 : I<(outs GPR32:$dst),
 314               (ins GPR32Op:$src1, GPR32:$src2a, GPR32:$src2b, GPR32:$scr), []>;
 315 def INSN4 : I<(outs GPR32:$scr),
 316               (ins GPR32:$src3, complex:$src4, i32imm:$src5a, i32imm:$src5b), []>;
 317 def : Pat<(select GPR32:$src1, (complex_rr GPR32:$src2a, GPR32:$src2b),
 318                                (select GPR32:$src3,
 319                                        complex:$src4,
 320                                        (complex i32imm:$src5a, i32imm:$src5b))),
 321           (INSN3 GPR32:$src1, GPR32:$src2b, GPR32:$src2a,
 322                  (INSN4 GPR32:$src3, complex:$src4, i32imm:$src5a,
 323                         i32imm:$src5b))>;
 324
 325 // R21O-NEXT:  GIM_SwitchOpcode, /*MI*/0, /*[*/{{[0-9]+}}, {{[0-9]+}}, /*)*//*default:*//*Label [[DEFAULT_NUM:[0-9]+]]*/ [[DEFAULT:[0-9]+]],
 326 // R21O-NEXT:  /*TargetOpcode::G_ADD*//*Label [[CASE_ADD_NUM:[0-9]+]]*/ [[CASE_ADD:[0-9]+]],
 327 // R21O:       /*TargetOpcode::G_SELECT*//*Label [[CASE_SELECT_NUM:[0-9]+]]*/ [[CASE_SELECT:[0-9]+]],
 328 // R21O:       // Label [[CASE_ADD_NUM]]: @[[CASE_ADD]]
 329 // R21O:       // Label [[CASE_SELECT_NUM]]: @[[CASE_SELECT]]
 330 // R21O-NEXT:  GIM_Try, /*On fail goto*//*Label [[GROUP_NUM:[0-9]+]]*/ [[GROUP:[0-9]+]],
 331 // R21O-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 332 // R21O-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
 333 // R21O-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
 334 // R21O-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
 335 //
 336 // R21C-NEXT:  GIM_Try, /*On fail goto*//*Label [[PREV_NUM:[0-9]+]]*/ [[PREV:[0-9]+]], // Rule ID 19 //
 337 // R21C-NOT:     GIR_Done,
 338 // R21C:         // GIR_Coverage, 19,
 339 // R21C-NEXT:    GIR_Done,
 340 // R21C-NEXT:  // Label [[PREV_NUM]]: @[[PREV]]
 341 // R21C-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]], // Rule ID 21 //
 342 //
 343 // R21O-NEXT:    GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_frag,
 344 // R21O-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 345 // R21O-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 346 // R21N-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
 347 // R21N-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_SELECT,
 348 // R21N-NEXT:    GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_frag,
 349 // R21N-NEXT:    // MIs[0] dst
 350 // R21N-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 351 // R21N-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 352 // R21N-NEXT:    // MIs[0] src1
 353 // R21N-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
 354 // R21N-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 355 // R21N-NEXT:    // MIs[0] src2
 356 // R21N-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
 357 //
 358 // R21C-NEXT:    GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_complex,
 359 // R21N-NEXT:    // MIs[0] src3
 360 // R21N-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
 361 // R21C-NEXT:    GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_complex,
 362 // R21C-NEXT:    // (select:{ *:[i32] } GPR32:{ *:[i32] }:$src1, complex:{ *:[i32] }:$src2, complex:{ *:[i32] }:$src3)<<P:Predicate_frag>> => (INSN2:{ *:[i32] } GPR32:{ *:[i32] }:$src1, complex:{ *:[i32] }:$src3, complex:{ *:[i32] }:$src2)
 363
 364 // R21C-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::INSN2,
 365 // R21C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
 366 // R21C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
 367 // R21C-NEXT:    GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/1,
 368 // R21C-NEXT:    GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0,
 369 // R21C-NEXT:    GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
 370 // R21C-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
 371 // R21C-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
 372 // R21C-NEXT:    // GIR_Coverage, 21,
 373 // R21C-NEXT:    GIR_Done,
 374 // R21C-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
 375 //
 376 // R21O-NEXT:  GIM_Reject,
 377 // R21O-NEXT:  // Label [[GROUP_NUM]]: @[[GROUP]]
 378 // R21O-NEXT:  GIM_Reject,
 379 // R21O:       // Label [[DEFAULT_NUM]]: @[[DEFAULT]]
 380 // R21O-NEXT:  GIM_Reject,
 381 // R21O-NEXT:  };
 382
 383 //===- Test a pattern with ComplexPattern operands. -----------------------===//
 384 //
 385 // R20O-NEXT:  GIM_SwitchOpcode, /*MI*/0, /*[*/{{[0-9]+}}, {{[0-9]+}}, /*)*//*default:*//*Label [[DEFAULT_NUM:[0-9]+]]*/ [[DEFAULT:[0-9]+]],
 386 // R20O-NEXT:  /*TargetOpcode::G_ADD*//*Label [[CASE_ADD_NUM:[0-9]+]]*/ [[CASE_ADD:[0-9]+]],
 387 // R20O:       /*TargetOpcode::G_SUB*//*Label [[CASE_SUB_NUM:[0-9]+]]*/ [[CASE_SUB:[0-9]+]],
 388 // R20O:       // Label [[CASE_ADD_NUM]]: @[[CASE_ADD]]
 389 // R20O:       // Label [[CASE_SUB_NUM]]: @[[CASE_SUB]]
 390 // R20O-NEXT:  GIM_Try, /*On fail goto*//*Label [[GROUP_NUM:[0-9]+]]*/ [[GROUP:[0-9]+]],
 391 // R20O-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 392 // R20O-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
 393 // R20O-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
 394 // R20O-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 395 //
 396 // R20N:       GIM_Try, /*On fail goto*//*Label [[PREV_NUM:[0-9]+]]*/ [[PREV:[0-9]+]], // Rule ID 21 //
 397 // R20N:       // Label [[PREV_NUM]]: @[[PREV]]
 398 //
 399 // R20C-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]], // Rule ID 20 //
 400 //
 401 // R20N-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
 402 // R20N-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_SUB,
 403 // R20N-NEXT:    // MIs[0] dst
 404 // R20N-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 405 // R20N-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 406 // R20N-NEXT:    // MIs[0] src1
 407 // R20N-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
 408 //
 409 // R20N-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 410 // R20N-NEXT:    // MIs[0] src2
 411 // R20N-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
 412 // R20O-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 413 // R20C-NEXT:    GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_complex,
 414 // R20C-NEXT:    // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$src1, complex:{ *:[i32] }:$src2) => (INSN1:{ *:[i32] } GPR32:{ *:[i32] }:$src1, complex:{ *:[i32] }:$src2)
 415 // R20C-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::INSN1,
 416 // R20C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
 417 // R20C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
 418 // R20C-NEXT:    GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0,
 419 // R20C-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
 420 // R20C-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
 421 // R20C-NEXT:    // GIR_Coverage, 20,
 422 // R20C-NEXT:    GIR_Done,
 423 // R20C-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
 424 //
 425 // R20O:       // Label [[GROUP_NUM]]: @[[GROUP]]
 426 // R20O-NEXT:  GIM_Reject,
 427 // R20O:       // Label [[DEFAULT_NUM]]: @[[DEFAULT]]
 428 // R20O-NEXT:  GIM_Reject,
 429 // R20O-NEXT:  };
 430
 431 def INSN1 : I<(outs GPR32:$dst), (ins GPR32:$src1, complex:$src2), []>;
 432 def : Pat<(sub GPR32:$src1, complex:$src2), (INSN1 GPR32:$src1, complex:$src2)>;
 433
 434 //===- Test a pattern with multiple ComplexPattern operands. --------------===//
 435 //
 436 def : GINodeEquiv<G_SELECT, select>;
 437 let mayLoad = 1 in {
 438   def INSN2 : I<(outs GPR32:$dst), (ins GPR32Op:$src1, complex:$src2, complex:$src3), []>;
 439 }
 440 def frag : PatFrag<(ops node:$a, node:$b, node:$c),
 441                    (select node:$a, node:$b, node:$c),
 442                    [{ return true; // C++ code }]> {
 443   let GISelPredicateCode = [{ return true; // C++ code }];
 444 }
 445 def : Pat<(frag GPR32:$src1, complex:$src2, complex:$src3),
 446           (INSN2 GPR32:$src1, complex:$src3, complex:$src2)>;
 447
 448 //===- Test a more complex multi-instruction match. -----------------------===//
 449 //
 450 // R00O-NEXT:  GIM_SwitchOpcode, /*MI*/0, /*[*/{{[0-9]+}}, {{[0-9]+}}, /*)*//*default:*//*Label [[DEFAULT_NUM:[0-9]+]]*/ [[DEFAULT:[0-9]+]],
 451 // R00O-NEXT:  /*TargetOpcode::G_ADD*//*Label [[CASE_ADD_NUM:[0-9]+]]*/ [[CASE_ADD:[0-9]+]],
 452 // R00O:       /*TargetOpcode::G_SUB*//*Label [[CASE_SUB_NUM:[0-9]+]]*/ [[CASE_SUB:[0-9]+]],
 453 // R00O:       // Label [[CASE_ADD_NUM]]: @[[CASE_ADD]]
 454 // R00O:       // Label [[CASE_SUB_NUM]]: @[[CASE_SUB]]
 455 // R00O-NEXT:  GIM_Try, /*On fail goto*//*Label [[GROUP_NUM:[0-9]+]]*/ [[GROUP:[0-9]+]],
 456 // R00O-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 457 // R00O-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
 458 // R00O-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
 459 // R00O-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 460 //
 461 // R00C:       GIM_Try, /*On fail goto*//*Label [[PREV_NUM:[0-9]+]]*/ [[PREV:[0-9]+]], // Rule ID 20 //
 462 // R00C:       // Label [[PREV_NUM]]: @[[PREV]]
 463 //
 464 // R00C-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]], // Rule ID 0 //
 465 // R00C-NEXT:    GIM_CheckFeatures, GIFBS_HasA,
 466 // R00N-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
 467 // R00N-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_SUB,
 468 // R00N-NEXT:    // MIs[0] dst
 469 // R00N-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 470 // R00N-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 471 // R00N-NEXT:    // MIs[0] Operand 1
 472 // R00N-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
 473 // R00C-NEXT:    GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
 474 // R00N-NEXT:    GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
 475 // R00C-NEXT:    GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB,
 476 // R00N-NEXT:    // MIs[1] Operand 0
 477 // R00N-NEXT:    GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
 478 // R00N-NEXT:    // MIs[1] src1
 479 // R00C-NEXT:    GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
 480 // R00O-NEXT:    GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
 481 // R00N-NEXT:    GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 482 // R00N-NEXT:    // MIs[1] src2
 483 // R00N-NEXT:    GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
 484 // R00N-NEXT:    GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID,
 485 // R00N-NEXT:    // MIs[0] Operand 2
 486 // R00N-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
 487 // R00O-NEXT:    GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 488 // R00O-NEXT:    GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID,
 489 // R00C-NEXT:    GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
 490 // R00N-NEXT:    GIM_CheckNumOperands, /*MI*/2, /*Expected*/3,
 491 // R00C-NEXT:    GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SUB,
 492 // R00N-NEXT:    // MIs[2] Operand 0
 493 // R00N-NEXT:    GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s32,
 494 // R00N-NEXT:    // MIs[2] src3
 495 // R00C-NEXT:    GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
 496 // R00O-NEXT:    GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
 497 // R00N-NEXT:    GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 498 // R00N-NEXT:    // MIs[2] src4
 499 // R00N-NEXT:    GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
 500 // R00N-NEXT:    GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID,
 501 // R00O-NEXT:    GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 502 // R00O-NEXT:    GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID,
 503 // R00C-NEXT:    GIM_CheckIsSafeToFold, /*InsnID*/1,
 504 // R00C-NEXT:    GIM_CheckIsSafeToFold, /*InsnID*/2,
 505 // R00C-NEXT:    // (sub:{ *:[i32] } (sub:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2), (sub:{ *:[i32] } GPR32:{ *:[i32] }:$src3, GPR32:{ *:[i32] }:$src4)) => (INSNBOB:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2, GPR32:{ *:[i32] }:$src3, GPR32:{ *:[i32] }:$src4)
 506 // R00C-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::INSNBOB,
 507 // R00C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
 508 // R00C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
 509 // R00C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
 510 // R00C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src3
 511 // R00C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src4
 512 // R00C-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
 513 // R00C-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
 514 // R00C-NEXT:    // GIR_Coverage, 0,
 515 // R00C-NEXT:    GIR_Done,
 516 // R00C-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
 517 //
 518 // R00O-NEXT:  GIM_Reject,
 519 // R00O-NEXT:  // Label [[GROUP_NUM]]: @[[GROUP]]
 520 // R00O-NEXT:  GIM_Reject,
 521 // R00O:       // Label [[DEFAULT_NUM]]: @[[DEFAULT]]
 522 // R00O-NEXT:  GIM_Reject,
 523 // R00O-NEXT:  };
 524
 525 def INSNBOB : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2, GPR32:$src3, GPR32:$src4),
 526                  [(set GPR32:$dst,
 527                       (sub (sub GPR32:$src1, GPR32:$src2), (sub GPR32:$src3, GPR32:$src4)))]>,
 528                Requires<[HasA]>;
 529
 530 //===- Test a simple pattern with an intrinsic. ---------------------------===//
 531 //
 532 // R01O-NEXT:  GIM_SwitchOpcode, /*MI*/0, /*[*/{{[0-9]+}}, {{[0-9]+}}, /*)*//*default:*//*Label [[DEFAULT_NUM:[0-9]+]]*/ [[DEFAULT:[0-9]+]],
 533 // R01O-NEXT:  /*TargetOpcode::G_ADD*//*Label [[CASE_ADD_NUM:[0-9]+]]*/ [[CASE_ADD:[0-9]+]],
 534 // R01O:       /*TargetOpcode::G_INTRINSIC*//*Label [[CASE_INTRINSIC_NUM:[0-9]+]]*/ [[CASE_INTRINSIC:[0-9]+]],
 535 // R01O:       // Label [[CASE_ADD_NUM]]: @[[CASE_ADD]]
 536 // R01O:       // Label [[CASE_INTRINSIC_NUM]]: @[[CASE_INTRINSIC]]
 537 //
 538 // R01N:       GIM_Try, /*On fail goto*//*Label [[PREV_NUM:[0-9]+]]*/ [[PREV:[0-9]+]], // Rule ID 0 //
 539 // R01N:       // Label [[PREV_NUM]]: @[[PREV]]
 540 //
 541 // R01C-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]], // Rule ID 1 //
 542 // R01C-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
 543 //
 544 // R01O-NEXT:    GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mytarget_nop,
 545 // R01O-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 546 // R01O-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
 547 // R01O-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 548 //
 549 // R01N-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
 550 // R01N-NEXT:    // MIs[0] dst
 551 // R01N-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 552 // R01N-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 553 // R01N-NEXT:    // MIs[0] Operand 1
 554 // R01N-NEXT:    GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mytarget_nop,
 555 // R01N-NEXT:    // MIs[0] src1
 556 // R01N-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
 557 //
 558 // R01C-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID,
 559 // R01C-NEXT:    // (intrinsic_wo_chain:{ *:[i32] } [[ID:[0-9]+]]:{ *:[iPTR] }, GPR32:{ *:[i32] }:$src1) => (MOV:{ *:[i32] } GPR32:{ *:[i32] }:$src1)
 560 // R01C-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MOV,
 561 // R01C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
 562 // R01C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
 563 // R01C-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
 564 // R01C-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
 565 // R01C-NEXT:    // GIR_Coverage, 1,
 566 // R01C-NEXT:    GIR_Done,
 567 // R01C-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
 568 //
 569 // R01O-NEXT:  GIM_Reject,
 570 // R01O:       // Label [[DEFAULT_NUM]]: @[[DEFAULT]]
 571 // R01O-NEXT:  GIM_Reject,
 572
 573 def MOV : I<(outs GPR32:$dst), (ins GPR32:$src1),
 574             [(set GPR32:$dst, (int_mytarget_nop GPR32:$src1))]>;
 575
 576 //===- Test a simple pattern with a default operand. ----------------------===//
 577 //
 578 // R02O-NEXT:  GIM_SwitchOpcode, /*MI*/0, /*[*/{{[0-9]+}}, {{[0-9]+}}, /*)*//*default:*//*Label [[DEFAULT_NUM:[0-9]+]]*/ [[DEFAULT:[0-9]+]],
 579 // R02O-NEXT:  /*TargetOpcode::G_ADD*//*Label [[CASE_ADD_NUM:[0-9]+]]*/ [[CASE_ADD:[0-9]+]],
 580 // R02O:       /*TargetOpcode::G_XOR*//*Label [[CASE_XOR_NUM:[0-9]+]]*/ [[CASE_XOR:[0-9]+]],
 581 // R02O:       // Label [[CASE_ADD_NUM]]: @[[CASE_ADD]]
 582 // R02O:       // Label [[CASE_XOR_NUM]]: @[[CASE_XOR]]
 583 // R02O-NEXT:  GIM_Try, /*On fail goto*//*Label [[GROUP_NUM:[0-9]+]]*/ [[GROUP:[0-9]+]],
 584 // R02O-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 585 // R02O-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
 586 // R02O-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
 587 // R02O-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 588 // R02O-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 589 //
 590 // R02N:       GIM_Try, /*On fail goto*//*Label [[PREV_NUM:[0-9]+]]*/ [[PREV:[0-9]+]], // Rule ID 1 //
 591 // R02N:       // Label [[PREV_NUM]]: @[[PREV]]
 592 //
 593 // R02C-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]], // Rule ID 2 //
 594 //
 595 // R02N-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
 596 // R02N-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_XOR,
 597 // R02N-NEXT:    // MIs[0] dst
 598 // R02N-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 599 // R02N-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 600 // R02N-NEXT:    // MIs[0] src1
 601 // R02N-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
 602 // R02N-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 603 // R02N-NEXT:    // MIs[0] Operand 2
 604 // R02N-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
 605 //
 606 // R02C-NEXT:    GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -2
 607 // R02C-NEXT:    // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$src1, -2:{ *:[i32] }) => (XORI:{ *:[i32] } GPR32:{ *:[i32] }:$src1)
 608 // R02C-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::XORI,
 609 // R02C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
 610 // R02C-NEXT:    GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
 611 // R02C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
 612 // R02C-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
 613 // R02C-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
 614 // R02C-NEXT:    // GIR_Coverage, 2,
 615 // R02C-NEXT:    GIR_Done,
 616 // R02C-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
 617 //
 618 // R02O:       // Label [[DEFAULT_NUM]]: @[[DEFAULT]]
 619 // R02O-NEXT:  GIM_Reject,
 620
 621 // The -2 is just to distinguish it from the 'not' case below.
 622 def XORI : I<(outs GPR32:$dst), (ins m1:$src2, GPR32:$src1),
 623              [(set GPR32:$dst, (xor GPR32:$src1, -2))]>;
 624
 625 //===- Test a simple pattern with a default register operand. -------------===//
 626 //
 627 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
 628 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
 629 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_XOR,
 630 // NOOPT-NEXT:    // MIs[0] dst
 631 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 632 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 633 // NOOPT-NEXT:    // MIs[0] src1
 634 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
 635 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 636 // NOOPT-NEXT:    // MIs[0] Operand 2
 637 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
 638 // NOOPT-NEXT:    GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -3
 639 // NOOPT-NEXT:    // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$src1, -3:{ *:[i32] }) => (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$src1)
 640 // NOOPT-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::XOR,
 641 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
 642 // NOOPT-NEXT:    GIR_AddRegister, /*InsnID*/0, MyTarget::R0,
 643 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
 644 // NOOPT-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
 645 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
 646 // NOOPT-NEXT:    // GIR_Coverage, 3,
 647 // NOOPT-NEXT:    GIR_Done,
 648 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
 649
 650 // The -3 is just to distinguish it from the 'not' case below and the other default op case above.
 651 def XOR : I<(outs GPR32:$dst), (ins Z:$src2, GPR32:$src1),
 652             [(set GPR32:$dst, (xor GPR32:$src1, -3))]>;
 653
 654 //===- Test a simple pattern with a multiple default operands. ------------===//
 655 //
 656 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
 657 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
 658 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_XOR,
 659 // NOOPT-NEXT:    // MIs[0] dst
 660 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 661 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 662 // NOOPT-NEXT:    // MIs[0] src1
 663 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
 664 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 665 // NOOPT-NEXT:    // MIs[0] Operand 2
 666 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
 667 // NOOPT-NEXT:    GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -4
 668 // NOOPT-NEXT:    // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$src1, -4:{ *:[i32] }) => (XORlike:{ *:[i32] } GPR32:{ *:[i32] }:$src1)
 669 // NOOPT-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::XORlike,
 670 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
 671 // NOOPT-NEXT:    GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
 672 // NOOPT-NEXT:    GIR_AddRegister, /*InsnID*/0, MyTarget::R0,
 673 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
 674 // NOOPT-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
 675 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
 676 // NOOPT-NEXT:    // GIR_Coverage, 4,
 677 // NOOPT-NEXT:    GIR_Done,
 678 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
 679
 680 // The -4 is just to distinguish it from the other 'not' cases.
 681 def XORlike : I<(outs GPR32:$dst), (ins m1Z:$src2, GPR32:$src1),
 682                 [(set GPR32:$dst, (xor GPR32:$src1, -4))]>;
 683
 684 //===- Test a simple pattern with multiple operands with defaults. --------===//
 685 //
 686 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
 687 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
 688 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_XOR,
 689 // NOOPT-NEXT:    // MIs[0] dst
 690 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 691 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 692 // NOOPT-NEXT:    // MIs[0] src1
 693 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
 694 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 695 // NOOPT-NEXT:    // MIs[0] Operand 2
 696 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
 697 // NOOPT-NEXT:    GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -5,
 698 // NOOPT-NEXT:    // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$src1, -5:{ *:[i32] }) => (XORManyDefaults:{ *:[i32] } GPR32:{ *:[i32] }:$src1)
 699 // NOOPT-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::XORManyDefaults,
 700 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
 701 // NOOPT-NEXT:    GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
 702 // NOOPT-NEXT:    GIR_AddRegister, /*InsnID*/0, MyTarget::R0,
 703 // NOOPT-NEXT:    GIR_AddRegister, /*InsnID*/0, MyTarget::R0,
 704 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
 705 // NOOPT-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
 706 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
 707 // NOOPT-NEXT:    // GIR_Coverage, 5,
 708 // NOOPT-NEXT:    GIR_Done,
 709 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
 710
 711 // The -5 is just to distinguish it from the other cases.
 712 def XORManyDefaults : I<(outs GPR32:$dst), (ins m1Z:$src3, Z:$src2, GPR32:$src1),
 713                         [(set GPR32:$dst, (xor GPR32:$src1, -5))]>;
 714
 715 //===- Test a simple pattern with constant immediate operands. ------------===//
 716 //
 717 // This must precede the 3-register variants because constant immediates have
 718 // priority over register banks.
 719 //
 720 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
 721 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
 722 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_XOR,
 723 // NOOPT-NEXT:    // MIs[0] dst
 724 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 725 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 726 // NOOPT-NEXT:    // MIs[0] Wm
 727 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
 728 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 729 // NOOPT-NEXT:    // MIs[0] Operand 2
 730 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
 731 // NOOPT-NEXT:    GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
 732 // NOOPT-NEXT:    // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Wm, -1:{ *:[i32] }) => (ORN:{ *:[i32] } R0:{ *:[i32] }, GPR32:{ *:[i32] }:$Wm)
 733 // NOOPT-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::ORN,
 734 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
 735 // NOOPT-NEXT:    GIR_AddRegister, /*InsnID*/0, MyTarget::R0,
 736 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Wm
 737 // NOOPT-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
 738 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
 739 // NOOPT-NEXT:    // GIR_Coverage, 22,
 740 // NOOPT-NEXT:    GIR_Done,
 741 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
 742
 743 def ORN : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), []>;
 744 def : Pat<(not GPR32:$Wm), (ORN R0, GPR32:$Wm)>;
 745
 746 //===- Test a nested instruction match. -----------------------------------===//
 747 //
 748 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
 749 // NOOPT-NEXT:    GIM_CheckFeatures, GIFBS_HasA,
 750 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
 751 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_MUL,
 752 // NOOPT-NEXT:    // MIs[0] dst
 753 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 754 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 755 // NOOPT-NEXT:    // MIs[0] Operand 1
 756 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
 757 // NOOPT-NEXT:    GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
 758 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
 759 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
 760 // NOOPT-NEXT:    // MIs[1] Operand 0
 761 // NOOPT-NEXT:    GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
 762 // NOOPT-NEXT:    // MIs[1] src1
 763 // NOOPT-NEXT:    GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
 764 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 765 // NOOPT-NEXT:    // MIs[1] src2
 766 // NOOPT-NEXT:    GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
 767 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID,
 768 // NOOPT-NEXT:    // MIs[0] src3
 769 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
 770 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID,
 771 // NOOPT-NEXT:    GIM_CheckIsSafeToFold, /*InsnID*/1,
 772 // NOOPT-NEXT:    // (mul:{ *:[i32] } (add:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2), GPR32:{ *:[i32] }:$src3)  =>  (MULADD:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2, GPR32:{ *:[i32] }:$src3)
 773 // NOOPT-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MULADD,
 774 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
 775 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
 776 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
 777 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src3
 778 // NOOPT-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
 779 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
 780 // NOOPT-NEXT:    // GIR_Coverage, 6,
 781 // NOOPT-NEXT:    GIR_Done,
 782 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
 783
 784 // We also get a second rule by commutativity.
 785 //
 786 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
 787 // NOOPT-NEXT:    GIM_CheckFeatures, GIFBS_HasA,
 788 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
 789 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_MUL,
 790 // NOOPT-NEXT:    // MIs[0] dst
 791 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 792 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 793 // NOOPT-NEXT:    // MIs[0] src3
 794 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
 795 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 796 // NOOPT-NEXT:    // MIs[0] Operand 2
 797 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
 798 // NOOPT-NEXT:    GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2,
 799 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
 800 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
 801 // NOOPT-NEXT:    // MIs[1] Operand 0
 802 // NOOPT-NEXT:    GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
 803 // NOOPT-NEXT:    // MIs[1] src1
 804 // NOOPT-NEXT:    GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
 805 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 806 // NOOPT-NEXT:    // MIs[1] src2
 807 // NOOPT-NEXT:    GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
 808 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID,
 809 // NOOPT-NEXT:    GIM_CheckIsSafeToFold, /*InsnID*/1,
 810 // NOOPT-NEXT:    // (mul:{ *:[i32] } GPR32:{ *:[i32] }:$src3, (add:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2))  =>  (MULADD:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2, GPR32:{ *:[i32] }:$src3)
 811 // NOOPT-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MULADD,
 812 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
 813 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
 814 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
 815 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src3
 816 // NOOPT-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
 817 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
 818 // NOOPT-NEXT:    // GIR_Coverage, 26,
 819 // NOOPT-NEXT:    GIR_Done,
 820 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
 821
 822 def MULADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2, GPR32:$src3),
 823                [(set GPR32:$dst,
 824                      (mul (add GPR32:$src1, GPR32:$src2), GPR32:$src3))]>,
 825              Requires<[HasA]>;
 826
 827 //===- Test a simple pattern with just a specific leaf immediate. ---------===//
 828 //
 829 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
 830 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
 831 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_CONSTANT,
 832 // NOOPT-NEXT:    // MIs[0] dst
 833 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 834 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 835 // NOOPT-NEXT:    // MIs[0] Operand 1
 836 // NOOPT-NEXT:    GIM_CheckLiteralInt, /*MI*/0, /*Op*/1, 1,
 837 // NOOPT-NEXT:    // 1:{ *:[i32] }  =>  (MOV1:{ *:[i32] })
 838 // NOOPT-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MOV1,
 839 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
 840 // NOOPT-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
 841 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
 842 // NOOPT-NEXT:    // GIR_Coverage, 7,
 843 // NOOPT-NEXT:    GIR_Done,
 844 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
 845
 846 def MOV1 : I<(outs GPR32:$dst), (ins), [(set GPR32:$dst, 1)]>;
 847
 848 //===- Test a simple pattern with a leaf immediate and a predicate. -------===//
 849 //
 850 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
 851 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
 852 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_CONSTANT,
 853 // NOOPT-NEXT:    GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIPFP_I64_Predicate_simm8,
 854 // NOOPT-NEXT:    // MIs[0] dst
 855 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 856 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 857 // NOOPT-NEXT:    // MIs[0] Operand 1
 858 // NOOPT-NEXT:    // No operand predicates
 859 // NOOPT-NEXT:    // (imm:{ *:[i32] })<<P:Predicate_simm8>>:$imm => (MOVimm8:{ *:[i32] } (imm:{ *:[i32] }):$imm)
 860 // NOOPT-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MOVimm8,
 861 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
 862 // NOOPT-NEXT:    GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
 863 // NOOPT-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
 864 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
 865 // NOOPT-NEXT:    // GIR_Coverage, 8,
 866 // NOOPT-NEXT:    GIR_Done,
 867 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
 868
 869 def simm8 : ImmLeaf<i32, [{ return isInt<8>(Imm); }]>;
 870 def MOVimm8 : I<(outs GPR32:$dst), (ins i32imm:$imm), [(set GPR32:$dst, simm8:$imm)]>;
 871
 872 //===- Same again but use an IntImmLeaf. ----------------------------------===//
 873 //
 874 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
 875 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
 876 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_CONSTANT,
 877 // NOOPT-NEXT:    GIM_CheckAPIntImmPredicate, /*MI*/0, /*Predicate*/GIPFP_APInt_Predicate_simm9,
 878 // NOOPT-NEXT:    // MIs[0] dst
 879 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 880 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 881 // NOOPT-NEXT:    // MIs[0] Operand 1
 882 // NOOPT-NEXT:    // No operand predicates
 883 // NOOPT-NEXT:    // (imm:{ *:[i32] })<<P:Predicate_simm9>>:$imm =>  (MOVimm9:{ *:[i32] } (imm:{ *:[i32] }):$imm)
 884 // NOOPT-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MOVimm9,
 885 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
 886 // NOOPT-NEXT:    GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
 887 // NOOPT-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
 888 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
 889 // NOOPT-NEXT:    // GIR_Coverage, 9,
 890 // NOOPT-NEXT:    GIR_Done,
 891 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
 892
 893 def simm9 : IntImmLeaf<i32, [{ return isInt<9>(Imm->getSExtValue()); }]>;
 894 def MOVimm9 : I<(outs GPR32:$dst), (ins i32imm:$imm), [(set GPR32:$dst, simm9:$imm)]>;
 895
 896 //===- Test a pattern with a custom renderer. -----------------------------===//
 897 //
 898 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
 899 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
 900 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_CONSTANT,
 901 // NOOPT-NEXT:    GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIPFP_I64_Predicate_cimm8,
 902 // NOOPT-NEXT:    // MIs[0] dst
 903 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 904 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 905 // NOOPT-NEXT:    // MIs[0] Operand 1
 906 // NOOPT-NEXT:    // No operand predicates
 907 // NOOPT-NEXT:    // (imm:{ *:[i32] })<<P:Predicate_cimm8>><<X:cimm8_xform>>:$imm  =>  (MOVcimm8:{ *:[i32] } (cimm8_xform:{ *:[i32] } (imm:{ *:[i32] }):$imm))
 908 // NOOPT-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MOVcimm8,
 909 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
 910 // NOOPT-NEXT:    GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GICR_renderImm8, // imm
 911 // NOOPT-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
 912 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
 913 // NOOPT-NEXT:    // GIR_Coverage, 10,
 914 // NOOPT-NEXT:    GIR_Done,
 915 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
 916
 917 def MOVcimm8 : I<(outs GPR32:$dst), (ins i32imm:$imm), [(set GPR32:$dst, cimm8:$imm)]>;
 918
 919 //===- Test a simple pattern with a FP immediate and a predicate. ---------===//
 920 //
 921 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
 922 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
 923 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_FCONSTANT,
 924 // NOOPT-NEXT:    GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIPFP_APFloat_Predicate_fpimmz,
 925 // NOOPT-NEXT:    // MIs[0] dst
 926 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 927 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::FPR32RegClassID,
 928 // NOOPT-NEXT:    // MIs[0] Operand 1
 929 // NOOPT-NEXT:    // No operand predicates
 930 // NOOPT-NEXT:    // (fpimm:{ *:[f32] })<<P:Predicate_fpimmz>>:$imm =>  (MOVfpimmz:{ *:[f32] } (fpimm:{ *:[f32] }):$imm)
 931 // NOOPT-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MOVfpimmz,
 932 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
 933 // NOOPT-NEXT:    GIR_CopyFConstantAsFPImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
 934 // NOOPT-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
 935 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
 936 // NOOPT-NEXT:    // GIR_Coverage, 17,
 937 // NOOPT-NEXT:    GIR_Done,
 938 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
 939
 940 //===- Test a simple pattern with inferred pointer operands. ---------------===//
 941 //
 942 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
 943 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
 944 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_LOAD,
 945 // NOOPT-NEXT:    GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
 946 // NOOPT-NEXT:    GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
 947 // NOOPT-NEXT:    // MIs[0] dst
 948 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 949 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 950 // NOOPT-NEXT:    // MIs[0] src1
 951 // NOOPT-NEXT:    GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
 952 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 953 // NOOPT-NEXT:    // (ld:{ *:[i32] } GPR32:{ *:[i32] }:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LOAD:{ *:[i32] } GPR32:{ *:[i32] }:$src1)
 954 // NOOPT-NEXT:    GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::LOAD,
 955 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
 956 // NOOPT-NEXT:    // GIR_Coverage, 11,
 957 // NOOPT-NEXT:    GIR_Done,
 958 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
 959
 960 def LOAD : I<(outs GPR32:$dst), (ins GPR32:$src1),
 961             [(set GPR32:$dst, (load GPR32:$src1))]>;
 962
 963 //===- Test a simple pattern with explicit pointer operands. ---------------===//
 964
 965 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
 966 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
 967 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_LOAD,
 968 // NOOPT-NEXT:    GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
 969 // NOOPT-NEXT:    GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
 970 // NOOPT-NEXT:    // MIs[0] dst
 971 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_p0s32,
 972 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 973 // NOOPT-NEXT:    // MIs[0] src
 974 // NOOPT-NEXT:    GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
 975 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 976 // NOOPT-NEXT:    // (ld:{ *:[i32] } GPR32:{ *:[i32] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LOAD:{ *:[i32] } GPR32:{ *:[i32] }:$src)
 977 // NOOPT-NEXT:    GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::LOAD,
 978 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
 979 // NOOPT-NEXT:    // GIR_Coverage, 23,
 980 // NOOPT-NEXT:    GIR_Done,
 981 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
 982
 983 def : Pat<(load GPR32:$src),
 984           (p0 (LOAD GPR32:$src))>;
 985
 986 //===- Test a simple pattern with a sextload -------------------------------===//
 987 //
 988 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
 989 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
 990 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_SEXTLOAD,
 991 // NOOPT-NEXT:    GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2,
 992 // NOOPT-NEXT:    GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
 993 // NOOPT-NEXT:    // MIs[0] dst
 994 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 995 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 996 // NOOPT-NEXT:    // MIs[0] src1
 997 // NOOPT-NEXT:    GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
 998 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 999 // NOOPT-NEXT:    // (ld:{ *:[i32] } GPR32:{ *:[i32] }:$src1)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>  =>  (SEXTLOAD:{ *:[i32] } GPR32:{ *:[i32] }:$src1)
1000 // NOOPT-NEXT:    GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::SEXTLOAD,
1001 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1002 // NOOPT-NEXT:    // GIR_Coverage, 12,
1003 // NOOPT-NEXT:    GIR_Done,
1004 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
1005
1006 def SEXTLOAD : I<(outs GPR32:$dst), (ins GPR32:$src1),
1007                  [(set GPR32:$dst, (sextloadi16 GPR32:$src1))]>;
1008
1009 //===- Test a simple pattern with regclass operands. ----------------------===//
1010 //
1011 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
1012 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
1013 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ADD,
1014 // NOOPT-NEXT:    // MIs[0] dst
1015 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
1016 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
1017 // NOOPT-NEXT:    // MIs[0] src1
1018 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1019 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID
1020 // NOOPT-NEXT:    // MIs[0] src2
1021 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1022 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID,
1023 // NOOPT-NEXT:    // (add:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2) => (ADD:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2)
1024 // NOOPT-NEXT:    GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::ADD,
1025 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1026 // NOOPT-NEXT:    // GIR_Coverage, 13,
1027 // NOOPT-NEXT:    GIR_Done,
1028 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
1029
1030 def ADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2),
1031             [(set GPR32:$dst, (add GPR32:$src1, GPR32:$src2))]>;
1032
1033 //===- Test a pattern with a tied operand in the matcher ------------------===//
1034 //
1035 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
1036 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
1037 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ADD,
1038 // NOOPT-NEXT:    // MIs[0] dst
1039 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
1040 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
1041 // NOOPT-NEXT:    // MIs[0] src{{$}}
1042 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1043 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
1044 // NOOPT-NEXT:    // MIs[0] src{{$}}
1045 // NOOPT-NEXT:    GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
1046 // NOOPT-NEXT:    // (add:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src) => (DOUBLE:{ *:[i32] } GPR32:{ *:[i32] }:$src)
1047 // NOOPT-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::DOUBLE,
1048 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1049 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
1050 // NOOPT-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
1051 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1052 // NOOPT-NEXT:    // GIR_Coverage, 14,
1053 // NOOPT-NEXT:    GIR_Done,
1054 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
1055
1056 def DOUBLE : I<(outs GPR32:$dst), (ins GPR32:$src), [(set GPR32:$dst, (add GPR32:$src, GPR32:$src))]>;
1057
1058 //===- Test a simple pattern with ValueType operands. ----------------------===//
1059 //
1060 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
1061 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
1062 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ADD,
1063 // NOOPT-NEXT:    // MIs[0] dst
1064 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
1065 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
1066 // NOOPT-NEXT:    // MIs[0] src1
1067 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1068 // NOOPT-NEXT:    // MIs[0] src2
1069 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1070 // NOOPT-NEXT:    // (add:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2) => (ADD:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)
1071 // NOOPT-NEXT:    GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::ADD,
1072 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1073 // NOOPT-NEXT:    // GIR_Coverage, 24,
1074 // NOOPT-NEXT:    GIR_Done,
1075 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
1076
1077 def : Pat<(add i32:$src1, i32:$src2),
1078           (ADD i32:$src1, i32:$src2)>;
1079
1080 //===- Test another simple pattern with regclass operands. ----------------===//
1081 //
1082 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
1083 // NOOPT-NEXT:    GIM_CheckFeatures, GIFBS_HasA_HasB_HasC,
1084 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
1085 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_MUL,
1086 // NOOPT-NEXT:    // MIs[0] dst
1087 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
1088 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
1089 // NOOPT-NEXT:    // MIs[0] src1
1090 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1091 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
1092 // NOOPT-NEXT:    // MIs[0] src2
1093 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1094 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID,
1095 // NOOPT-NEXT:    // (mul:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2) => (MUL:{ *:[i32] } GPR32:{ *:[i32] }:$src2, GPR32:{ *:[i32] }:$src1)
1096 // NOOPT-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MUL,
1097 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1098 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2
1099 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1100 // NOOPT-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
1101 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1102 // NOOPT-NEXT:    // GIR_Coverage, 15,
1103 // NOOPT-NEXT:    GIR_Done,
1104 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
1105
1106 def MUL : I<(outs GPR32:$dst), (ins GPR32:$src2, GPR32:$src1),
1107              [(set GPR32:$dst, (mul GPR32:$src1, GPR32:$src2))]>,
1108           Requires<[HasA, HasB, HasC]>;
1109
1110 //===- Test a COPY_TO_REGCLASS --------------------------------------------===//
1111 //
1112 //
1113 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
1114 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
1115 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_BITCAST,
1116 // NOOPT-NEXT:    // MIs[0] dst
1117 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
1118 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
1119 // NOOPT-NEXT:    // MIs[0] src1
1120 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1121 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::FPR32RegClassID,
1122 // NOOPT-NEXT:    // (bitconvert:{ *:[i32] } FPR32:{ *:[f32] }:$src1) => (COPY_TO_REGCLASS:{ *:[i32] } FPR32:{ *:[f32] }:$src1, GPR32:{ *:[i32] })
1123 // NOOPT-NEXT:    GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
1124 // NOOPT-NEXT:    GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR32*/1,
1125 // NOOPT-NEXT:    // GIR_Coverage, 25,
1126 // NOOPT-NEXT:    GIR_Done,
1127 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
1128
1129 def : Pat<(i32 (bitconvert FPR32:$src1)),
1130           (COPY_TO_REGCLASS FPR32:$src1, GPR32)>;
1131
1132 //===- Test a simple pattern with just a leaf immediate. ------------------===//
1133 //
1134 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
1135 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
1136 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_CONSTANT,
1137 // NOOPT-NEXT:    // MIs[0] dst
1138 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
1139 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
1140 // NOOPT-NEXT:    // MIs[0] Operand 1
1141 // NOOPT-NEXT:    // No operand predicates
1142 // NOOPT-NEXT:    // (imm:{ *:[i32] }):$imm =>  (MOVimm:{ *:[i32] } (imm:{ *:[i32] }):$imm)
1143 // NOOPT-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MOVimm,
1144 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1145 // NOOPT-NEXT:    GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
1146 // NOOPT-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
1147 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1148 // NOOPT-NEXT:    // GIR_Coverage, 16,
1149 // NOOPT-NEXT:    GIR_Done,
1150 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
1151
1152 def MOVimm : I<(outs GPR32:$dst), (ins i32imm:$imm), [(set GPR32:$dst, imm:$imm)]>;
1153
1154 def fpimmz : FPImmLeaf<f32, [{ return Imm->isExactlyValue(0.0); }]>;
1155 def MOVfpimmz : I<(outs FPR32:$dst), (ins f32imm:$imm), [(set FPR32:$dst, fpimmz:$imm)]>;
1156
1157 //===- Test a pattern with an MBB operand. --------------------------------===//
1158 //
1159 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
1160 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/1,
1161 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_BR,
1162 // NOOPT-NEXT:    // MIs[0] target
1163 // NOOPT-NEXT:    GIM_CheckIsMBB, /*MI*/0, /*Op*/0,
1164 // NOOPT-NEXT:    // (br (bb:{ *:[Other] }):$target) => (BR (bb:{ *:[Other] }):$target)
1165 // NOOPT-NEXT:    GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::BR,
1166 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1167 // NOOPT-NEXT:    // GIR_Coverage, 18,
1168 // NOOPT-NEXT:    GIR_Done,
1169 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
1170
1171 def BR : I<(outs), (ins unknown:$target),
1172             [(br bb:$target)]>;
1173
1174 // NOOPT-NEXT:    GIM_Reject,
1175 // NOOPT-NEXT:  };
1176 // NOOPT-NEXT:  return MatchTable0;