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[MIParser] Set RegClassOrRegBank during instruction parsing
[llvm-complete.git]
/
test
/
TableGen
/
compare.td
blob
e54d853b9a607acf53209e681671fed9b2683359
1
// RUN: llvm-tblgen %s | FileCheck %s
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// XFAIL: vg_leak
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// CHECK: --- Defs ---
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// CHECK: def A0 {
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// CHECK: bit eq = 1;
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// CHECK: bit ne = 0;
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// CHECK: bit le = 1;
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// CHECK: bit lt = 0;
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// CHECK: bit ge = 1;
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// CHECK: bit gt = 0;
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// CHECK: }
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// CHECK: def A1 {
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// CHECK: bit eq = 0;
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// CHECK: bit ne = 1;
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// CHECK: bit le = 1;
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// CHECK: bit lt = 1;
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// CHECK: bit ge = 0;
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// CHECK: bit gt = 0;
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// CHECK: }
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// CHECK: def A2 {
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// CHECK: bit eq = 0;
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// CHECK: bit ne = 1;
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// CHECK: bit le = 0;
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// CHECK: bit lt = 0;
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// CHECK: bit ge = 1;
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// CHECK: bit gt = 1;
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// CHECK: }
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// CHECK: def A3 {
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// CHECK: bit eq = 0;
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// CHECK: bit ne = 1;
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// CHECK: bit le = 0;
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// CHECK: bit lt = 0;
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// CHECK: bit ge = 1;
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// CHECK: bit gt = 1;
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// CHECK: }
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class A<int x, int y> {
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bit eq = !eq(x, y);
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bit ne = !ne(x, y);
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bit le = !le(x, y);
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bit lt = !lt(x, y);
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bit ge = !ge(x, y);
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bit gt = !gt(x, y);
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}
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def A0 : A<-3, -3>;
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def A1 : A<-1, 4>;
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def A2 : A<3, -2>;
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def A3 : A<4, 2>;