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[MIParser] Set RegClassOrRegBank during instruction parsing
[llvm-complete.git]
/
test
/
TableGen
/
eqbit.td
blob
5749b27e26c7c864702bf4be50b3ec275f8be7cc
1
// RUN: llvm-tblgen %s | FileCheck %s
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// XFAIL: vg_leak
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// CHECK-LABEL: def X {
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// CHECK: int a = 6;
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// CHECK: int c = 5;
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// CHECK: }
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// CHECK-LABEL: def Y {
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// CHECK: int a = 5;
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// CHECK: int c = 6;
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// CHECK: }
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class A<bit b = 1> {
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int a = !if(!eq(b, 1), 5, 6);
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int c = !if(!ne(b, 1), 5, 6);
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}
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def X : A<0>;
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def Y : A;