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[MIParser] Set RegClassOrRegBank during instruction parsing
[llvm-complete.git]
/
test
/
TableGen
/
ifbit.td
blob
18797cac11075aef1c4ac35ef4d6ff4422f48b88
1
// RUN: llvm-tblgen %s | FileCheck %s
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// XFAIL: vg_leak
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// CHECK: a = 6
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// CHECK: a = 5
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class A<bit b = 1> {
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int a = !if(b, 5, 6);
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bit c = !if(b, 0, 1);
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bits<1> d = !if(b, 0, 1);
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}
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def X : A<0>;
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def Y : A;