[MIParser] Set RegClassOrRegBank during instruction parsing
[llvm-complete.git] / test / TableGen / intrinsic-varargs.td
blob6a2252215a830f256eb3e9fa02c91ef7c9182aa6
1 // RUN: llvm-tblgen -gen-intrinsic-impl -I %p/../../include %s | FileCheck %s
2 // XFAIL: vg_leak
4 include "llvm/CodeGen/ValueTypes.td"
6 class IntrinsicProperty;
7 class SDNodeProperty;
9 class LLVMType<ValueType vt> {
10   ValueType VT = vt;
13 class Intrinsic<string name, list<LLVMType> param_types = []> {
14   string LLVMName = name;
15   bit isTarget = 0;
16   string TargetPrefix = "";
17   list<LLVMType> RetTypes = [];
18   list<LLVMType> ParamTypes = param_types;
19   list<IntrinsicProperty> IntrProperties = [];
20   list<SDNodeProperty> Properties = [];
23 def llvm_vararg_ty : LLVMType<isVoid>;   // this means vararg here
25 // CHECK: /* 0 */ 0, 29, 0,
26 def int_foo : Intrinsic<"llvm.foo", [llvm_vararg_ty]>;