[MIParser] Set RegClassOrRegBank during instruction parsing
[llvm-complete.git] / test / Transforms / SimplifyCFG / ARM / lit.local.cfg
blob5a3b8565213de95cd8782a4daaea9661ddb54a7e
1 config.suffixes = ['.ll']
3 targets = set(config.root.targets_to_build.split())
4 if not 'ARM' in targets:
5     config.unsupported = True