[MIParser] Set RegClassOrRegBank during instruction parsing
[llvm-complete.git] / utils / gn / secondary / llvm / lib / Target / Hexagon / MCTargetDesc / BUILD.gn
blob4b7d2b7119c81c8c90f4941d6fcf3b0485bb7ea4
1 import("//llvm/utils/TableGen/tablegen.gni")
3 tablegen("HexagonGenAsmWriter") {
4   visibility = [ ":MCTargetDesc" ]
5   args = [ "-gen-asm-writer" ]
6   td_file = "../Hexagon.td"
9 tablegen("HexagonGenInstrInfo") {
10   visibility = [ ":MCTargetDesc" ]
11   args = [ "-gen-instr-info" ]
12   td_file = "../Hexagon.td"
15 tablegen("HexagonGenMCCodeEmitter") {
16   visibility = [ ":MCTargetDesc" ]
17   args = [ "-gen-emitter" ]
18   td_file = "../Hexagon.td"
21 tablegen("HexagonGenRegisterInfo") {
22   visibility = [ ":MCTargetDesc" ]
23   args = [ "-gen-register-info" ]
24   td_file = "../Hexagon.td"
27 tablegen("HexagonGenSubtargetInfo") {
28   visibility = [ ":MCTargetDesc" ]
29   args = [ "-gen-subtarget" ]
30   td_file = "../Hexagon.td"
33 static_library("MCTargetDesc") {
34   output_name = "LLVMHexagonDesc"
36   # This should contain tablegen targets generating .inc files included
37   # by other targets. .inc files only used by .cpp files in this directory
38   # should be in deps instead.
39   public_deps = [
40     ":HexagonGenInstrInfo",
41     ":HexagonGenRegisterInfo",
42     ":HexagonGenSubtargetInfo",
43   ]
44   deps = [
45     ":HexagonGenAsmWriter",
46     ":HexagonGenMCCodeEmitter",
47     "//llvm/lib/MC",
48     "//llvm/lib/Support",
49     "//llvm/lib/Target/Hexagon/TargetInfo",
50   ]
51   include_dirs = [ ".." ]
52   sources = [
53     "HexagonAsmBackend.cpp",
54     "HexagonELFObjectWriter.cpp",
55     "HexagonInstPrinter.cpp",
56     "HexagonMCAsmInfo.cpp",
57     "HexagonMCChecker.cpp",
58     "HexagonMCCodeEmitter.cpp",
59     "HexagonMCCompound.cpp",
60     "HexagonMCDuplexInfo.cpp",
61     "HexagonMCELFStreamer.cpp",
62     "HexagonMCExpr.cpp",
63     "HexagonMCInstrInfo.cpp",
64     "HexagonMCShuffler.cpp",
65     "HexagonMCTargetDesc.cpp",
66     "HexagonShuffler.cpp",
67   ]