[MIParser] Set RegClassOrRegBank during instruction parsing
[llvm-complete.git] / utils / gn / secondary / llvm / unittests / Transforms / Vectorize / BUILD.gn
blob33e1efdbb584caa25b8fbf85cec5d28f93a10aba
1 import("//llvm/utils/unittest/unittest.gni")
3 unittest("VectorizeTests") {
4   deps = [
5     "//llvm/lib/Analysis",
6     "//llvm/lib/AsmParser",
7     "//llvm/lib/IR",
8     "//llvm/lib/Transforms/Vectorize",
9   ]
10   sources = [
11     "VPlanDominatorTreeTest.cpp",
12     "VPlanHCFGTest.cpp",
13     "VPlanLoopInfoTest.cpp",
14     "VPlanPredicatorTest.cpp",
15     "VPlanSlpTest.cpp",
16     "VPlanTest.cpp",
17   ]