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[llvm-complete.git] / lib / Target / Hexagon / HexagonInstrInfo.h
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1 //===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Hexagon implementation of the TargetInstrInfo class.
11 //===----------------------------------------------------------------------===//
13 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
14 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
16 #include "MCTargetDesc/HexagonBaseInfo.h"
17 #include "llvm/ADT/ArrayRef.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/TargetInstrInfo.h"
21 #include "llvm/CodeGen/ValueTypes.h"
22 #include "llvm/Support/MachineValueType.h"
23 #include <cstdint>
24 #include <vector>
26 #define GET_INSTRINFO_HEADER
27 #include "HexagonGenInstrInfo.inc"
29 namespace llvm {
31 class HexagonSubtarget;
32 class MachineBranchProbabilityInfo;
33 class MachineFunction;
34 class MachineInstr;
35 class MachineOperand;
36 class TargetRegisterInfo;
38 class HexagonInstrInfo : public HexagonGenInstrInfo {
39 const HexagonSubtarget &Subtarget;
41 enum BundleAttribute {
42 memShufDisabledMask = 0x4
45 virtual void anchor();
47 public:
48 explicit HexagonInstrInfo(HexagonSubtarget &ST);
50 /// TargetInstrInfo overrides.
52 /// If the specified machine instruction is a direct
53 /// load from a stack slot, return the virtual or physical register number of
54 /// the destination along with the FrameIndex of the loaded stack slot. If
55 /// not, return 0. This predicate must return 0 if the instruction has
56 /// any side effects other than loading from the stack slot.
57 unsigned isLoadFromStackSlot(const MachineInstr &MI,
58 int &FrameIndex) const override;
60 /// If the specified machine instruction is a direct
61 /// store to a stack slot, return the virtual or physical register number of
62 /// the source reg along with the FrameIndex of the loaded stack slot. If
63 /// not, return 0. This predicate must return 0 if the instruction has
64 /// any side effects other than storing to the stack slot.
65 unsigned isStoreToStackSlot(const MachineInstr &MI,
66 int &FrameIndex) const override;
68 /// Check if the instruction or the bundle of instructions has
69 /// load from stack slots. Return the frameindex and machine memory operand
70 /// if true.
71 bool hasLoadFromStackSlot(
72 const MachineInstr &MI,
73 SmallVectorImpl<const MachineMemOperand *> &Accesses) const override;
75 /// Check if the instruction or the bundle of instructions has
76 /// store to stack slots. Return the frameindex and machine memory operand
77 /// if true.
78 bool hasStoreToStackSlot(
79 const MachineInstr &MI,
80 SmallVectorImpl<const MachineMemOperand *> &Accesses) const override;
82 /// Analyze the branching code at the end of MBB, returning
83 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
84 /// implemented for a target). Upon success, this returns false and returns
85 /// with the following information in various cases:
86 ///
87 /// 1. If this block ends with no branches (it just falls through to its succ)
88 /// just return false, leaving TBB/FBB null.
89 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
90 /// the destination block.
91 /// 3. If this block ends with a conditional branch and it falls through to a
92 /// successor block, it sets TBB to be the branch destination block and a
93 /// list of operands that evaluate the condition. These operands can be
94 /// passed to other TargetInstrInfo methods to create new branches.
95 /// 4. If this block ends with a conditional branch followed by an
96 /// unconditional branch, it returns the 'true' destination in TBB, the
97 /// 'false' destination in FBB, and a list of operands that evaluate the
98 /// condition. These operands can be passed to other TargetInstrInfo
99 /// methods to create new branches.
101 /// Note that removeBranch and insertBranch must be implemented to support
102 /// cases where this method returns success.
104 /// If AllowModify is true, then this routine is allowed to modify the basic
105 /// block (e.g. delete instructions after the unconditional branch).
106 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
107 MachineBasicBlock *&FBB,
108 SmallVectorImpl<MachineOperand> &Cond,
109 bool AllowModify) const override;
111 /// Remove the branching code at the end of the specific MBB.
112 /// This is only invoked in cases where AnalyzeBranch returns success. It
113 /// returns the number of instructions that were removed.
114 unsigned removeBranch(MachineBasicBlock &MBB,
115 int *BytesRemoved = nullptr) const override;
117 /// Insert branch code into the end of the specified MachineBasicBlock.
118 /// The operands to this method are the same as those
119 /// returned by AnalyzeBranch. This is only invoked in cases where
120 /// AnalyzeBranch returns success. It returns the number of instructions
121 /// inserted.
123 /// It is also invoked by tail merging to add unconditional branches in
124 /// cases where AnalyzeBranch doesn't apply because there was no original
125 /// branch to analyze. At least this much must be implemented, else tail
126 /// merging needs to be disabled.
127 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
128 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
129 const DebugLoc &DL,
130 int *BytesAdded = nullptr) const override;
132 /// Analyze loop L, which must be a single-basic-block loop, and if the
133 /// conditions can be understood enough produce a PipelinerLoopInfo object.
134 std::unique_ptr<PipelinerLoopInfo>
135 analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override;
137 /// Return true if it's profitable to predicate
138 /// instructions with accumulated instruction latency of "NumCycles"
139 /// of the specified basic block, where the probability of the instructions
140 /// being executed is given by Probability, and Confidence is a measure
141 /// of our confidence that it will be properly predicted.
142 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
143 unsigned ExtraPredCycles,
144 BranchProbability Probability) const override;
146 /// Second variant of isProfitableToIfCvt. This one
147 /// checks for the case where two basic blocks from true and false path
148 /// of a if-then-else (diamond) are predicated on mutally exclusive
149 /// predicates, where the probability of the true path being taken is given
150 /// by Probability, and Confidence is a measure of our confidence that it
151 /// will be properly predicted.
152 bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
153 unsigned NumTCycles, unsigned ExtraTCycles,
154 MachineBasicBlock &FMBB,
155 unsigned NumFCycles, unsigned ExtraFCycles,
156 BranchProbability Probability) const override;
158 /// Return true if it's profitable for if-converter to duplicate instructions
159 /// of specified accumulated instruction latencies in the specified MBB to
160 /// enable if-conversion.
161 /// The probability of the instructions being executed is given by
162 /// Probability, and Confidence is a measure of our confidence that it
163 /// will be properly predicted.
164 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
165 BranchProbability Probability) const override;
167 /// Emit instructions to copy a pair of physical registers.
169 /// This function should support copies within any legal register class as
170 /// well as any cross-class copies created during instruction selection.
172 /// The source and destination registers may overlap, which may require a
173 /// careful implementation when multiple copy instructions are required for
174 /// large registers. See for example the ARM target.
175 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
176 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
177 bool KillSrc) const override;
179 /// Store the specified register of the given register class to the specified
180 /// stack frame index. The store instruction is to be added to the given
181 /// machine basic block before the specified machine instruction. If isKill
182 /// is true, the register operand is the last use and must be marked kill.
183 void storeRegToStackSlot(MachineBasicBlock &MBB,
184 MachineBasicBlock::iterator MBBI,
185 unsigned SrcReg, bool isKill, int FrameIndex,
186 const TargetRegisterClass *RC,
187 const TargetRegisterInfo *TRI) const override;
189 /// Load the specified register of the given register class from the specified
190 /// stack frame index. The load instruction is to be added to the given
191 /// machine basic block before the specified machine instruction.
192 void loadRegFromStackSlot(MachineBasicBlock &MBB,
193 MachineBasicBlock::iterator MBBI,
194 unsigned DestReg, int FrameIndex,
195 const TargetRegisterClass *RC,
196 const TargetRegisterInfo *TRI) const override;
198 /// This function is called for all pseudo instructions
199 /// that remain after register allocation. Many pseudo instructions are
200 /// created to help register allocation. This is the place to convert them
201 /// into real instructions. The target can edit MI in place, or it can insert
202 /// new instructions and erase MI. The function should return true if
203 /// anything was changed.
204 bool expandPostRAPseudo(MachineInstr &MI) const override;
206 /// Get the base register and byte offset of a load/store instr.
207 bool getMemOperandWithOffset(const MachineInstr &LdSt,
208 const MachineOperand *&BaseOp,
209 int64_t &Offset,
210 const TargetRegisterInfo *TRI) const override;
212 /// Reverses the branch condition of the specified condition list,
213 /// returning false on success and true if it cannot be reversed.
214 bool reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)
215 const override;
217 /// Insert a noop into the instruction stream at the specified point.
218 void insertNoop(MachineBasicBlock &MBB,
219 MachineBasicBlock::iterator MI) const override;
221 /// Returns true if the instruction is already predicated.
222 bool isPredicated(const MachineInstr &MI) const override;
224 /// Return true for post-incremented instructions.
225 bool isPostIncrement(const MachineInstr &MI) const override;
227 /// Convert the instruction into a predicated instruction.
228 /// It returns true if the operation was successful.
229 bool PredicateInstruction(MachineInstr &MI,
230 ArrayRef<MachineOperand> Cond) const override;
232 /// Returns true if the first specified predicate
233 /// subsumes the second, e.g. GE subsumes GT.
234 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
235 ArrayRef<MachineOperand> Pred2) const override;
237 /// If the specified instruction defines any predicate
238 /// or condition code register(s) used for predication, returns true as well
239 /// as the definition predicate(s) by reference.
240 bool DefinesPredicate(MachineInstr &MI,
241 std::vector<MachineOperand> &Pred) const override;
243 /// Return true if the specified instruction can be predicated.
244 /// By default, this returns true for every instruction with a
245 /// PredicateOperand.
246 bool isPredicable(const MachineInstr &MI) const override;
248 /// Test if the given instruction should be considered a scheduling boundary.
249 /// This primarily includes labels and terminators.
250 bool isSchedulingBoundary(const MachineInstr &MI,
251 const MachineBasicBlock *MBB,
252 const MachineFunction &MF) const override;
254 /// Measure the specified inline asm to determine an approximation of its
255 /// length.
256 unsigned getInlineAsmLength(
257 const char *Str,
258 const MCAsmInfo &MAI,
259 const TargetSubtargetInfo *STI = nullptr) const override;
261 /// Allocate and return a hazard recognizer to use for this target when
262 /// scheduling the machine instructions after register allocation.
263 ScheduleHazardRecognizer*
264 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
265 const ScheduleDAG *DAG) const override;
267 /// For a comparison instruction, return the source registers
268 /// in SrcReg and SrcReg2 if having two register operands, and the value it
269 /// compares against in CmpValue. Return true if the comparison instruction
270 /// can be analyzed.
271 bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
272 unsigned &SrcReg2, int &Mask, int &Value) const override;
274 /// Compute the instruction latency of a given instruction.
275 /// If the instruction has higher cost when predicated, it's returned via
276 /// PredCost.
277 unsigned getInstrLatency(const InstrItineraryData *ItinData,
278 const MachineInstr &MI,
279 unsigned *PredCost = nullptr) const override;
281 /// Create machine specific model for scheduling.
282 DFAPacketizer *
283 CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override;
285 // Sometimes, it is possible for the target
286 // to tell, even without aliasing information, that two MIs access different
287 // memory addresses. This function returns true if two MIs access different
288 // memory addresses and false otherwise.
289 bool
290 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
291 const MachineInstr &MIb) const override;
293 /// For instructions with a base and offset, return the position of the
294 /// base register and offset operands.
295 bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos,
296 unsigned &OffsetPos) const override;
298 /// If the instruction is an increment of a constant value, return the amount.
299 bool getIncrementValue(const MachineInstr &MI, int &Value) const override;
301 /// getOperandLatency - Compute and return the use operand latency of a given
302 /// pair of def and use.
303 /// In most cases, the static scheduling itinerary was enough to determine the
304 /// operand latency. But it may not be possible for instructions with variable
305 /// number of defs / uses.
307 /// This is a raw interface to the itinerary that may be directly overriden by
308 /// a target. Use computeOperandLatency to get the best estimate of latency.
309 int getOperandLatency(const InstrItineraryData *ItinData,
310 const MachineInstr &DefMI, unsigned DefIdx,
311 const MachineInstr &UseMI,
312 unsigned UseIdx) const override;
314 /// Decompose the machine operand's target flags into two values - the direct
315 /// target flag value and any of bit flags that are applied.
316 std::pair<unsigned, unsigned>
317 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
319 /// Return an array that contains the direct target flag values and their
320 /// names.
322 /// MIR Serialization is able to serialize only the target flags that are
323 /// defined by this method.
324 ArrayRef<std::pair<unsigned, const char *>>
325 getSerializableDirectMachineOperandTargetFlags() const override;
327 /// Return an array that contains the bitmask target flag values and their
328 /// names.
330 /// MIR Serialization is able to serialize only the target flags that are
331 /// defined by this method.
332 ArrayRef<std::pair<unsigned, const char *>>
333 getSerializableBitmaskMachineOperandTargetFlags() const override;
335 bool isTailCall(const MachineInstr &MI) const override;
337 /// HexagonInstrInfo specifics.
339 unsigned createVR(MachineFunction *MF, MVT VT) const;
340 MachineInstr *findLoopInstr(MachineBasicBlock *BB, unsigned EndLoopOp,
341 MachineBasicBlock *TargetBB,
342 SmallPtrSet<MachineBasicBlock *, 8> &Visited) const;
344 bool isBaseImmOffset(const MachineInstr &MI) const;
345 bool isAbsoluteSet(const MachineInstr &MI) const;
346 bool isAccumulator(const MachineInstr &MI) const;
347 bool isAddrModeWithOffset(const MachineInstr &MI) const;
348 bool isComplex(const MachineInstr &MI) const;
349 bool isCompoundBranchInstr(const MachineInstr &MI) const;
350 bool isConstExtended(const MachineInstr &MI) const;
351 bool isDeallocRet(const MachineInstr &MI) const;
352 bool isDependent(const MachineInstr &ProdMI,
353 const MachineInstr &ConsMI) const;
354 bool isDotCurInst(const MachineInstr &MI) const;
355 bool isDotNewInst(const MachineInstr &MI) const;
356 bool isDuplexPair(const MachineInstr &MIa, const MachineInstr &MIb) const;
357 bool isEarlySourceInstr(const MachineInstr &MI) const;
358 bool isEndLoopN(unsigned Opcode) const;
359 bool isExpr(unsigned OpType) const;
360 bool isExtendable(const MachineInstr &MI) const;
361 bool isExtended(const MachineInstr &MI) const;
362 bool isFloat(const MachineInstr &MI) const;
363 bool isHVXMemWithAIndirect(const MachineInstr &I,
364 const MachineInstr &J) const;
365 bool isIndirectCall(const MachineInstr &MI) const;
366 bool isIndirectL4Return(const MachineInstr &MI) const;
367 bool isJumpR(const MachineInstr &MI) const;
368 bool isJumpWithinBranchRange(const MachineInstr &MI, unsigned offset) const;
369 bool isLateInstrFeedsEarlyInstr(const MachineInstr &LRMI,
370 const MachineInstr &ESMI) const;
371 bool isLateResultInstr(const MachineInstr &MI) const;
372 bool isLateSourceInstr(const MachineInstr &MI) const;
373 bool isLoopN(const MachineInstr &MI) const;
374 bool isMemOp(const MachineInstr &MI) const;
375 bool isNewValue(const MachineInstr &MI) const;
376 bool isNewValue(unsigned Opcode) const;
377 bool isNewValueInst(const MachineInstr &MI) const;
378 bool isNewValueJump(const MachineInstr &MI) const;
379 bool isNewValueJump(unsigned Opcode) const;
380 bool isNewValueStore(const MachineInstr &MI) const;
381 bool isNewValueStore(unsigned Opcode) const;
382 bool isOperandExtended(const MachineInstr &MI, unsigned OperandNum) const;
383 bool isPredicatedNew(const MachineInstr &MI) const;
384 bool isPredicatedNew(unsigned Opcode) const;
385 bool isPredicatedTrue(const MachineInstr &MI) const;
386 bool isPredicatedTrue(unsigned Opcode) const;
387 bool isPredicated(unsigned Opcode) const;
388 bool isPredicateLate(unsigned Opcode) const;
389 bool isPredictedTaken(unsigned Opcode) const;
390 bool isSaveCalleeSavedRegsCall(const MachineInstr &MI) const;
391 bool isSignExtendingLoad(const MachineInstr &MI) const;
392 bool isSolo(const MachineInstr &MI) const;
393 bool isSpillPredRegOp(const MachineInstr &MI) const;
394 bool isTC1(const MachineInstr &MI) const;
395 bool isTC2(const MachineInstr &MI) const;
396 bool isTC2Early(const MachineInstr &MI) const;
397 bool isTC4x(const MachineInstr &MI) const;
398 bool isToBeScheduledASAP(const MachineInstr &MI1,
399 const MachineInstr &MI2) const;
400 bool isHVXVec(const MachineInstr &MI) const;
401 bool isValidAutoIncImm(const EVT VT, const int Offset) const;
402 bool isValidOffset(unsigned Opcode, int Offset,
403 const TargetRegisterInfo *TRI, bool Extend = true) const;
404 bool isVecAcc(const MachineInstr &MI) const;
405 bool isVecALU(const MachineInstr &MI) const;
406 bool isVecUsableNextPacket(const MachineInstr &ProdMI,
407 const MachineInstr &ConsMI) const;
408 bool isZeroExtendingLoad(const MachineInstr &MI) const;
410 bool addLatencyToSchedule(const MachineInstr &MI1,
411 const MachineInstr &MI2) const;
412 bool canExecuteInBundle(const MachineInstr &First,
413 const MachineInstr &Second) const;
414 bool doesNotReturn(const MachineInstr &CallMI) const;
415 bool hasEHLabel(const MachineBasicBlock *B) const;
416 bool hasNonExtEquivalent(const MachineInstr &MI) const;
417 bool hasPseudoInstrPair(const MachineInstr &MI) const;
418 bool hasUncondBranch(const MachineBasicBlock *B) const;
419 bool mayBeCurLoad(const MachineInstr &MI) const;
420 bool mayBeNewStore(const MachineInstr &MI) const;
421 bool producesStall(const MachineInstr &ProdMI,
422 const MachineInstr &ConsMI) const;
423 bool producesStall(const MachineInstr &MI,
424 MachineBasicBlock::const_instr_iterator MII) const;
425 bool predCanBeUsedAsDotNew(const MachineInstr &MI, unsigned PredReg) const;
426 bool PredOpcodeHasJMP_c(unsigned Opcode) const;
427 bool predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const;
429 unsigned getAddrMode(const MachineInstr &MI) const;
430 MachineOperand *getBaseAndOffset(const MachineInstr &MI, int64_t &Offset,
431 unsigned &AccessSize) const;
432 SmallVector<MachineInstr*,2> getBranchingInstrs(MachineBasicBlock& MBB) const;
433 unsigned getCExtOpNum(const MachineInstr &MI) const;
434 HexagonII::CompoundGroup
435 getCompoundCandidateGroup(const MachineInstr &MI) const;
436 unsigned getCompoundOpcode(const MachineInstr &GA,
437 const MachineInstr &GB) const;
438 int getCondOpcode(int Opc, bool sense) const;
439 int getDotCurOp(const MachineInstr &MI) const;
440 int getNonDotCurOp(const MachineInstr &MI) const;
441 int getDotNewOp(const MachineInstr &MI) const;
442 int getDotNewPredJumpOp(const MachineInstr &MI,
443 const MachineBranchProbabilityInfo *MBPI) const;
444 int getDotNewPredOp(const MachineInstr &MI,
445 const MachineBranchProbabilityInfo *MBPI) const;
446 int getDotOldOp(const MachineInstr &MI) const;
447 HexagonII::SubInstructionGroup getDuplexCandidateGroup(const MachineInstr &MI)
448 const;
449 short getEquivalentHWInstr(const MachineInstr &MI) const;
450 unsigned getInstrTimingClassLatency(const InstrItineraryData *ItinData,
451 const MachineInstr &MI) const;
452 bool getInvertedPredSense(SmallVectorImpl<MachineOperand> &Cond) const;
453 unsigned getInvertedPredicatedOpcode(const int Opc) const;
454 int getMaxValue(const MachineInstr &MI) const;
455 unsigned getMemAccessSize(const MachineInstr &MI) const;
456 int getMinValue(const MachineInstr &MI) const;
457 short getNonExtOpcode(const MachineInstr &MI) const;
458 bool getPredReg(ArrayRef<MachineOperand> Cond, unsigned &PredReg,
459 unsigned &PredRegPos, unsigned &PredRegFlags) const;
460 short getPseudoInstrPair(const MachineInstr &MI) const;
461 short getRegForm(const MachineInstr &MI) const;
462 unsigned getSize(const MachineInstr &MI) const;
463 uint64_t getType(const MachineInstr &MI) const;
464 unsigned getUnits(const MachineInstr &MI) const;
466 MachineBasicBlock::instr_iterator expandVGatherPseudo(MachineInstr &MI) const;
468 /// getInstrTimingClassLatency - Compute the instruction latency of a given
469 /// instruction using Timing Class information, if available.
470 unsigned nonDbgBBSize(const MachineBasicBlock *BB) const;
471 unsigned nonDbgBundleSize(MachineBasicBlock::const_iterator BundleHead) const;
473 void immediateExtend(MachineInstr &MI) const;
474 bool invertAndChangeJumpTarget(MachineInstr &MI,
475 MachineBasicBlock *NewTarget) const;
476 void genAllInsnTimingClasses(MachineFunction &MF) const;
477 bool reversePredSense(MachineInstr &MI) const;
478 unsigned reversePrediction(unsigned Opcode) const;
479 bool validateBranchCond(const ArrayRef<MachineOperand> &Cond) const;
481 void setBundleNoShuf(MachineBasicBlock::instr_iterator MIB) const;
482 bool getBundleNoShuf(const MachineInstr &MIB) const;
483 // Addressing mode relations.
484 short changeAddrMode_abs_io(short Opc) const;
485 short changeAddrMode_io_abs(short Opc) const;
486 short changeAddrMode_io_pi(short Opc) const;
487 short changeAddrMode_io_rr(short Opc) const;
488 short changeAddrMode_pi_io(short Opc) const;
489 short changeAddrMode_rr_io(short Opc) const;
490 short changeAddrMode_rr_ur(short Opc) const;
491 short changeAddrMode_ur_rr(short Opc) const;
493 short changeAddrMode_abs_io(const MachineInstr &MI) const {
494 return changeAddrMode_abs_io(MI.getOpcode());
496 short changeAddrMode_io_abs(const MachineInstr &MI) const {
497 return changeAddrMode_io_abs(MI.getOpcode());
499 short changeAddrMode_io_rr(const MachineInstr &MI) const {
500 return changeAddrMode_io_rr(MI.getOpcode());
502 short changeAddrMode_rr_io(const MachineInstr &MI) const {
503 return changeAddrMode_rr_io(MI.getOpcode());
505 short changeAddrMode_rr_ur(const MachineInstr &MI) const {
506 return changeAddrMode_rr_ur(MI.getOpcode());
508 short changeAddrMode_ur_rr(const MachineInstr &MI) const {
509 return changeAddrMode_ur_rr(MI.getOpcode());
513 } // end namespace llvm
515 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H