1 # Instructions that are available for the current ISA but should be rejected by
2 # the assembler (e.g. invalid set of operands or operand's restrictions not met).
4 # RUN: not llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32r6 2>%t1
5 # RUN: FileCheck %s < %t1
11 align $
4, $
2, $
3, -1 # CHECK: :[[@LINE]]:29: error: expected 2-bit unsigned immediate
12 align $
4, $
2, $
3, 4 # CHECK: :[[@LINE]]:29: error: expected 2-bit unsigned immediate
13 aui $
4, $
4, 65536 # CHECK: :[[@LINE]]:25: error: expected 16-bit unsigned immediate
14 aui $
4, $
4, -1 # CHECK: :[[@LINE]]:25: error: expected 16-bit unsigned immediate
15 jalr.hb $
31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
16 jalr.hb $
31, $
31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
17 swc2 $
25,24880($s0
) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
18 break
-1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
19 break
1024 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
20 break
-1, 5 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
21 break
1024, 5 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
22 break
7, -1 # CHECK: :[[@LINE]]:18: error: expected 10-bit unsigned immediate
23 break
7, 1024 # CHECK: :[[@LINE]]:18: error: expected 10-bit unsigned immediate
24 break
1024, 1024 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
25 lh $
33, 8($
4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number
26 lhe $
34, 8($
2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number
27 lhu $
35, 8($
2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number
28 lhue $
36, 8($
2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number
29 lh $
2, 8($
34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number
30 lhe $
4, 8($
33) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number
31 lhu $
4, 8($
35) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number
32 lhue $
4, 8($
37) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number
33 lh $
2, -2147483649($
4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset
34 lh $
2, 2147483648($
4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset
35 lhe $
4, -512($
2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
36 lhe $
4, 512($
2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
37 lhu $
4, -2147483649($
2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset
38 lhu $
4, 2147483648($
2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset
39 lhue $
4, -512($
2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
40 lhue $
4, 512($
2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
41 // FIXME
: Following tests are temporarily disabled
, until
"PredicateControl not in hierarchy" problem is resolved
42 bltl $
7, $
8, local_label
# -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
43 bltul $
7, $
8, local_label
# -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
44 blel $
7, $
8, local_label
# -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
45 bleul $
7, $
8, local_label
# -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
46 bgel $
7, $
8, local_label
# -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
47 bgeul $
7, $
8, local_label
# -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
48 bgtl $
7, $
8, local_label
# -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
49 bgtul $
7, $
8, local_label
# -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
50 bgec $
0, $
2, local_label
# CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction
51 bltc $
0, $
2, local_label
# CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction
52 bgeuc $
0, $
2, local_label
# CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction
53 bltuc $
0, $
2, local_label
# CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction
54 beqc $
0, $
2, local_label
# CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction
55 bnec $
0, $
2, local_label
# CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction
56 bgec $
2, $
2, local_label
# CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different
57 bltc $
2, $
2, local_label
# CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different
58 bgeuc $
2, $
2, local_label
# CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different
59 bltuc $
2, $
2, local_label
# CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different
60 beqc $
2, $
2, local_label
# CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different
61 bnec $
2, $
2, local_label
# CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different
62 blezc $
0, local_label
# CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction
63 bgezc $
0, local_label
# CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction
64 bgtzc $
0, local_label
# CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction
65 bltzc $
0, local_label
# CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction
66 beqzc $
0, local_label
# CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction
67 bnezc $
0, local_label
# CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction
68 bgec $
2, $
4, -131076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
69 bgec $
2, $
4, -131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
70 bgec $
2, $
4, 131072 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
71 bgec $
2, $
4, 131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
72 bltc $
2, $
4, -131076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
73 bltc $
2, $
4, -131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
74 bltc $
2, $
4, 131072 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
75 bltc $
2, $
4, 131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
76 bgeuc $
2, $
4, -131076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
77 bgeuc $
2, $
4, -131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
78 bgeuc $
2, $
4, 131072 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
79 bgeuc $
2, $
4, 131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
80 bltuc $
2, $
4, -131076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
81 bltuc $
2, $
4, -131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
82 bltuc $
2, $
4, 131072 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
83 bltuc $
2, $
4, 131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
84 beqc $
2, $
4, -131076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
85 beqc $
2, $
4, -131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
86 beqc $
2, $
4, 131072 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
87 beqc $
2, $
4, 131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
88 bnec $
2, $
4, -131076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
89 bnec $
2, $
4, -131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
90 bnec $
2, $
4, 131072 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
91 bnec $
2, $
4, 131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
92 blezc $
2, -131076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
93 blezc $
2, -131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
94 blezc $
2, 131072 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
95 blezc $
2, 131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
96 bgezc $
2, -131076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
97 bgezc $
2, -131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
98 bgezc $
2, 131072 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
99 bgezc $
2, 131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
100 bgtzc $
2, -131076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
101 bgtzc $
2, -131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
102 bgtzc $
2, 131072 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
103 bgtzc $
2, 131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
104 bltzc $
2, -131076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
105 bltzc $
2, -131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
106 bltzc $
2, 131072 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
107 bltzc $
2, 131071 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
108 beqzc $
2, -4194308 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
109 beqzc $
2, -4194303 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
110 beqzc $
2, 4194304 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
111 beqzc $
2, 4194303 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
112 bnezc $
2, -4194308 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
113 bnezc $
2, -4194303 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
114 bnezc $
2, 4194304 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
115 bnezc $
2, 4194303 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
116 cache
-1, 255($
7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
117 cache
32, 255($
7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
118 dvp $
17, $
3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
119 dvp $
17, 3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
120 dvp
3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
121 evp $
16, $
3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
122 evp $
16, 3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
123 evp
3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
124 jalr.hb $
31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
125 jalr.hb $
31, $
31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
126 lapc $
7, 1048576 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 19-bit signed immediate and multiple of 4
127 lapc $
6, -1048580 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 19-bit signed immediate and multiple of 4
128 lapc $
3, 3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 19-bit signed immediate and multiple of 4
129 lapc $
3, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 19-bit signed immediate and multiple of 4
130 ldc2 $
20, -1025($s2
) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
131 ldc2 $
20, 1024($s2
) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
132 lsa $
2, $
3, $
4, 0 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 4
133 lsa $
2, $
3, $
4, 5 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 4
134 pref
-1, 255($
7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
135 pref
32, 255($
7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
136 mtc0 $
4, $
3, -1 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
137 mtc0 $
4, $
3, 8 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
138 mtc2 $
4, $
3, -1 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
139 mtc2 $
4, $
3, 8 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
140 mfc0 $
4, $
3, -1 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
141 mfc0 $
4, $
3, 8 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
142 mfc2 $
4, $
3, -1 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
143 mfc2 $
4, $
3, 8 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
144 sdc2 $
20, -1025($s2
) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
145 sdc2 $
20, 1024($s2
) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
146 sync -1 # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
147 sync 32 # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
148 lb $
32, 8($
5) # CHECK: :[[@LINE]]:12: error: invalid register number
149 lb $
4, -2147483649($
5) # CHECK: :[[@LINE]]:16: error: expected memory with 32-bit signed offset
150 lb $
4, 2147483648($
5) # CHECK: :[[@LINE]]:16: error: expected memory with 32-bit signed offset
151 lb $
4, 8($
32) # CHECK: :[[@LINE]]:18: error: invalid register number
152 lbu $
32, 8($
5) # CHECK: :[[@LINE]]:13: error: invalid register number
153 lbu $
4, -2147483649($
5) # CHECK: :[[@LINE]]:17: error: expected memory with 32-bit signed offset
154 lbu $
4, 2147483648($
5) # CHECK: :[[@LINE]]:17: error: expected memory with 32-bit signed offset
155 lbu $
4, 8($
32) # CHECK: :[[@LINE]]:19: error: invalid register number
156 ldc1 $f32
, 300($
10) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
157 ldc1 $
f7, -32769($
10) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
158 ldc1 $
f7, 32768($
10) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
159 ldc1 $
f7, 300($
32) # CHECK: :[[@LINE]]:23: error: invalid register number
160 sdc1 $f32
, 64($
10) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
161 sdc1 $
f7, -32769($
10) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
162 sdc1 $
f7, 32768($
10) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
163 sdc1 $
f7, 64($
32) # CHECK: :[[@LINE]]:22: error: invalid register number
164 lwc1 $f32
, 32($
5) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
165 lwc1 $
f2, -32769($
5) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
166 lwc1 $
f2, 32768($
5) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
167 lwc1 $
f2, 32($
32) # CHECK: :[[@LINE]]:22: error: invalid register number
168 swc1 $f32
, 369($
13) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
169 swc1 $
f6, -32769($
13) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
170 swc1 $
f6, 32768($
13) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
171 swc1 $
f6, 369($
32) # CHECK: :[[@LINE]]:23: error: invalid register number
172 ldc2 $
32, 1023($
12) # CHECK: :[[@LINE]]:14: error: invalid register number
173 ldc2 $
11, -1025($
12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
174 ldc2 $
11, 1024($
12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
175 sdc2 $
32, 8($
16) # CHECK: :[[@LINE]]:14: error: invalid register number
176 sdc2 $
11, -1025($
12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
177 sdc2 $
11, 1024($
12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
178 lwc2 $
32, 16($
4) # CHECK: :[[@LINE]]:14: error: invalid register number
179 lwc2 $
11, -1025($
12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
180 lwc2 $
11, 1024($
12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
181 swc2 $
32, 777($
17) # CHECK: :[[@LINE]]:14: error: invalid register number
182 swc2 $
11, -1025($
12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
183 swc2 $
11, 1024($
12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
