utils/TableGen/InstrInfoEmitter.cpp

   1 //===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. --*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This tablegen backend is responsible for emitting a description of the target
  10 // instruction set for the code generator.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "CodeGenDAGPatterns.h"
  15 #include "CodeGenInstruction.h"
  16 #include "CodeGenSchedule.h"
  17 #include "CodeGenTarget.h"
  18 #include "PredicateExpander.h"
  19 #include "SequenceToOffsetTable.h"
  20 #include "TableGenBackends.h"
  21 #include "llvm/ADT/ArrayRef.h"
  22 #include "llvm/ADT/StringExtras.h"
  23 #include "llvm/Support/Casting.h"
  24 #include "llvm/Support/raw_ostream.h"
  25 #include "llvm/TableGen/Error.h"
  26 #include "llvm/TableGen/Record.h"
  27 #include "llvm/TableGen/TableGenBackend.h"
  28 #include <cassert>
  29 #include <cstdint>
  30 #include <map>
  31 #include <string>
  32 #include <utility>
  33 #include <vector>
  34
  35 using namespace llvm;
  36
  37 namespace {
  38
  39 class InstrInfoEmitter {
  40   RecordKeeper &Records;
  41   CodeGenDAGPatterns CDP;
  42   const CodeGenSchedModels &SchedModels;
  43
  44 public:
  45   InstrInfoEmitter(RecordKeeper &R):
  46     Records(R), CDP(R), SchedModels(CDP.getTargetInfo().getSchedModels()) {}
  47
  48   // run - Output the instruction set description.
  49   void run(raw_ostream &OS);
  50
  51 private:
  52   void emitEnums(raw_ostream &OS);
  53
  54   typedef std::map<std::vector<std::string>, unsigned> OperandInfoMapTy;
  55
  56   /// The keys of this map are maps which have OpName enum values as their keys
  57   /// and instruction operand indices as their values.  The values of this map
  58   /// are lists of instruction names.
  59   typedef std::map<std::map<unsigned, unsigned>,
  60                    std::vector<std::string>> OpNameMapTy;
  61   typedef std::map<std::string, unsigned>::iterator StrUintMapIter;
  62
  63   /// Generate member functions in the target-specific GenInstrInfo class.
  64   ///
  65   /// This method is used to custom expand TIIPredicate definitions.
  66   /// See file llvm/Target/TargetInstPredicates.td for a description of what is
  67   /// a TIIPredicate and how to use it.
  68   void emitTIIHelperMethods(raw_ostream &OS, StringRef TargetName,
  69                             bool ExpandDefinition = true);
  70
  71   /// Expand TIIPredicate definitions to functions that accept a const MCInst
  72   /// reference.
  73   void emitMCIIHelperMethods(raw_ostream &OS, StringRef TargetName);
  74   void emitRecord(const CodeGenInstruction &Inst, unsigned Num,
  75                   Record *InstrInfo,
  76                   std::map<std::vector<Record*>, unsigned> &EL,
  77                   const OperandInfoMapTy &OpInfo,
  78                   raw_ostream &OS);
  79   void emitOperandTypeMappings(
  80       raw_ostream &OS, const CodeGenTarget &Target,
  81       ArrayRef<const CodeGenInstruction *> NumberedInstructions);
  82   void initOperandMapData(
  83             ArrayRef<const CodeGenInstruction *> NumberedInstructions,
  84             StringRef Namespace,
  85             std::map<std::string, unsigned> &Operands,
  86             OpNameMapTy &OperandMap);
  87   void emitOperandNameMappings(raw_ostream &OS, const CodeGenTarget &Target,
  88             ArrayRef<const CodeGenInstruction*> NumberedInstructions);
  89
  90   // Operand information.
  91   void EmitOperandInfo(raw_ostream &OS, OperandInfoMapTy &OperandInfoIDs);
  92   std::vector<std::string> GetOperandInfo(const CodeGenInstruction &Inst);
  93 };
  94
  95 } // end anonymous namespace
  96
  97 static void PrintDefList(const std::vector<Record*> &Uses,
  98                          unsigned Num, raw_ostream &OS) {
  99   OS << "static const MCPhysReg ImplicitList" << Num << "[] = { ";
 100   for (Record *U : Uses)
 101     OS << getQualifiedName(U) << ", ";
 102   OS << "0 };\n";
 103 }
 104
 105 //===----------------------------------------------------------------------===//
 106 // Operand Info Emission.
 107 //===----------------------------------------------------------------------===//
 108
 109 std::vector<std::string>
 110 InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
 111   std::vector<std::string> Result;
 112
 113   for (auto &Op : Inst.Operands) {
 114     // Handle aggregate operands and normal operands the same way by expanding
 115     // either case into a list of operands for this op.
 116     std::vector<CGIOperandList::OperandInfo> OperandList;
 117
 118     // This might be a multiple operand thing.  Targets like X86 have
 119     // registers in their multi-operand operands.  It may also be an anonymous
 120     // operand, which has a single operand, but no declared class for the
 121     // operand.
 122     DagInit *MIOI = Op.MIOperandInfo;
 123
 124     if (!MIOI || MIOI->getNumArgs() == 0) {
 125       // Single, anonymous, operand.
 126       OperandList.push_back(Op);
 127     } else {
 128       for (unsigned j = 0, e = Op.MINumOperands; j != e; ++j) {
 129         OperandList.push_back(Op);
 130
 131         auto *OpR = cast<DefInit>(MIOI->getArg(j))->getDef();
 132         OperandList.back().Rec = OpR;
 133       }
 134     }
 135
 136     for (unsigned j = 0, e = OperandList.size(); j != e; ++j) {
 137       Record *OpR = OperandList[j].Rec;
 138       std::string Res;
 139
 140       if (OpR->isSubClassOf("RegisterOperand"))
 141         OpR = OpR->getValueAsDef("RegClass");
 142       if (OpR->isSubClassOf("RegisterClass"))
 143         Res += getQualifiedName(OpR) + "RegClassID, ";
 144       else if (OpR->isSubClassOf("PointerLikeRegClass"))
 145         Res += utostr(OpR->getValueAsInt("RegClassKind")) + ", ";
 146       else
 147         // -1 means the operand does not have a fixed register class.
 148         Res += "-1, ";
 149
 150       // Fill in applicable flags.
 151       Res += "0";
 152
 153       // Ptr value whose register class is resolved via callback.
 154       if (OpR->isSubClassOf("PointerLikeRegClass"))
 155         Res += "|(1<<MCOI::LookupPtrRegClass)";
 156
 157       // Predicate operands.  Check to see if the original unexpanded operand
 158       // was of type PredicateOp.
 159       if (Op.Rec->isSubClassOf("PredicateOp"))
 160         Res += "|(1<<MCOI::Predicate)";
 161
 162       // Optional def operands.  Check to see if the original unexpanded operand
 163       // was of type OptionalDefOperand.
 164       if (Op.Rec->isSubClassOf("OptionalDefOperand"))
 165         Res += "|(1<<MCOI::OptionalDef)";
 166
 167       // Fill in operand type.
 168       Res += ", ";
 169       assert(!Op.OperandType.empty() && "Invalid operand type.");
 170       Res += Op.OperandType;
 171
 172       // Fill in constraint info.
 173       Res += ", ";
 174
 175       const CGIOperandList::ConstraintInfo &Constraint =
 176         Op.Constraints[j];
 177       if (Constraint.isNone())
 178         Res += "0";
 179       else if (Constraint.isEarlyClobber())
 180         Res += "(1 << MCOI::EARLY_CLOBBER)";
 181       else {
 182         assert(Constraint.isTied());
 183         Res += "((" + utostr(Constraint.getTiedOperand()) +
 184                     " << 16) | (1 << MCOI::TIED_TO))";
 185       }
 186
 187       Result.push_back(Res);
 188     }
 189   }
 190
 191   return Result;
 192 }
 193
 194 void InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS,
 195                                        OperandInfoMapTy &OperandInfoIDs) {
 196   // ID #0 is for no operand info.
 197   unsigned OperandListNum = 0;
 198   OperandInfoIDs[std::vector<std::string>()] = ++OperandListNum;
 199
 200   OS << "\n";
 201   const CodeGenTarget &Target = CDP.getTargetInfo();
 202   for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
 203     std::vector<std::string> OperandInfo = GetOperandInfo(*Inst);
 204     unsigned &N = OperandInfoIDs[OperandInfo];
 205     if (N != 0) continue;
 206
 207     N = ++OperandListNum;
 208     OS << "static const MCOperandInfo OperandInfo" << N << "[] = { ";
 209     for (const std::string &Info : OperandInfo)
 210       OS << "{ " << Info << " }, ";
 211     OS << "};\n";
 212   }
 213 }
 214
 215 /// Initialize data structures for generating operand name mappings.
 216 ///
 217 /// \param Operands [out] A map used to generate the OpName enum with operand
 218 ///        names as its keys and operand enum values as its values.
 219 /// \param OperandMap [out] A map for representing the operand name mappings for
 220 ///        each instructions.  This is used to generate the OperandMap table as
 221 ///        well as the getNamedOperandIdx() function.
 222 void InstrInfoEmitter::initOperandMapData(
 223         ArrayRef<const CodeGenInstruction *> NumberedInstructions,
 224         StringRef Namespace,
 225         std::map<std::string, unsigned> &Operands,
 226         OpNameMapTy &OperandMap) {
 227   unsigned NumOperands = 0;
 228   for (const CodeGenInstruction *Inst : NumberedInstructions) {
 229     if (!Inst->TheDef->getValueAsBit("UseNamedOperandTable"))
 230       continue;
 231     std::map<unsigned, unsigned> OpList;
 232     for (const auto &Info : Inst->Operands) {
 233       StrUintMapIter I = Operands.find(Info.Name);
 234
 235       if (I == Operands.end()) {
 236         I = Operands.insert(Operands.begin(),
 237                     std::pair<std::string, unsigned>(Info.Name, NumOperands++));
 238       }
 239       OpList[I->second] = Info.MIOperandNo;
 240     }
 241     OperandMap[OpList].push_back(Namespace.str() + "::" +
 242                                  Inst->TheDef->getName().str());
 243   }
 244 }
 245
 246 /// Generate a table and function for looking up the indices of operands by
 247 /// name.
 248 ///
 249 /// This code generates:
 250 /// - An enum in the llvm::TargetNamespace::OpName namespace, with one entry
 251 ///   for each operand name.
 252 /// - A 2-dimensional table called OperandMap for mapping OpName enum values to
 253 ///   operand indices.
 254 /// - A function called getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
 255 ///   for looking up the operand index for an instruction, given a value from
 256 ///   OpName enum
 257 void InstrInfoEmitter::emitOperandNameMappings(raw_ostream &OS,
 258            const CodeGenTarget &Target,
 259            ArrayRef<const CodeGenInstruction*> NumberedInstructions) {
 260   StringRef Namespace = Target.getInstNamespace();
 261   std::string OpNameNS = "OpName";
 262   // Map of operand names to their enumeration value.  This will be used to
 263   // generate the OpName enum.
 264   std::map<std::string, unsigned> Operands;
 265   OpNameMapTy OperandMap;
 266
 267   initOperandMapData(NumberedInstructions, Namespace, Operands, OperandMap);
 268
 269   OS << "#ifdef GET_INSTRINFO_OPERAND_ENUM\n";
 270   OS << "#undef GET_INSTRINFO_OPERAND_ENUM\n";
 271   OS << "namespace llvm {\n";
 272   OS << "namespace " << Namespace << " {\n";
 273   OS << "namespace " << OpNameNS << " {\n";
 274   OS << "enum {\n";
 275   for (const auto &Op : Operands)
 276     OS << "  " << Op.first << " = " << Op.second << ",\n";
 277
 278   OS << "OPERAND_LAST";
 279   OS << "\n};\n";
 280   OS << "} // end namespace OpName\n";
 281   OS << "} // end namespace " << Namespace << "\n";
 282   OS << "} // end namespace llvm\n";
 283   OS << "#endif //GET_INSTRINFO_OPERAND_ENUM\n\n";
 284
 285   OS << "#ifdef GET_INSTRINFO_NAMED_OPS\n";
 286   OS << "#undef GET_INSTRINFO_NAMED_OPS\n";
 287   OS << "namespace llvm {\n";
 288   OS << "namespace " << Namespace << " {\n";
 289   OS << "LLVM_READONLY\n";
 290   OS << "int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {\n";
 291   if (!Operands.empty()) {
 292     OS << "  static const int16_t OperandMap [][" << Operands.size()
 293        << "] = {\n";
 294     for (const auto &Entry : OperandMap) {
 295       const std::map<unsigned, unsigned> &OpList = Entry.first;
 296       OS << "{";
 297
 298       // Emit a row of the OperandMap table
 299       for (unsigned i = 0, e = Operands.size(); i != e; ++i)
 300         OS << (OpList.count(i) == 0 ? -1 : (int)OpList.find(i)->second) << ", ";
 301
 302       OS << "},\n";
 303     }
 304     OS << "};\n";
 305
 306     OS << "  switch(Opcode) {\n";
 307     unsigned TableIndex = 0;
 308     for (const auto &Entry : OperandMap) {
 309       for (const std::string &Name : Entry.second)
 310         OS << "  case " << Name << ":\n";
 311
 312       OS << "    return OperandMap[" << TableIndex++ << "][NamedIdx];\n";
 313     }
 314     OS << "    default: return -1;\n";
 315     OS << "  }\n";
 316   } else {
 317     // There are no operands, so no need to emit anything
 318     OS << "  return -1;\n";
 319   }
 320   OS << "}\n";
 321   OS << "} // end namespace " << Namespace << "\n";
 322   OS << "} // end namespace llvm\n";
 323   OS << "#endif //GET_INSTRINFO_NAMED_OPS\n\n";
 324 }
 325
 326 /// Generate an enum for all the operand types for this target, under the
 327 /// llvm::TargetNamespace::OpTypes namespace.
 328 /// Operand types are all definitions derived of the Operand Target.td class.
 329 void InstrInfoEmitter::emitOperandTypeMappings(
 330     raw_ostream &OS, const CodeGenTarget &Target,
 331     ArrayRef<const CodeGenInstruction *> NumberedInstructions) {
 332
 333   StringRef Namespace = Target.getInstNamespace();
 334   std::vector<Record *> Operands = Records.getAllDerivedDefinitions("Operand");
 335   std::vector<Record *> RegisterOperands =
 336       Records.getAllDerivedDefinitions("RegisterOperand");
 337   std::vector<Record *> RegisterClasses =
 338       Records.getAllDerivedDefinitions("RegisterClass");
 339
 340   OS << "#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM\n";
 341   OS << "#undef GET_INSTRINFO_OPERAND_TYPES_ENUM\n";
 342   OS << "namespace llvm {\n";
 343   OS << "namespace " << Namespace << " {\n";
 344   OS << "namespace OpTypes {\n";
 345   OS << "enum OperandType {\n";
 346
 347   unsigned EnumVal = 0;
 348   for (const std::vector<Record *> *RecordsToAdd :
 349        {&Operands, &RegisterOperands, &RegisterClasses}) {
 350     for (const Record *Op : *RecordsToAdd) {
 351       if (!Op->isAnonymous())
 352         OS << "  " << Op->getName() << " = " << EnumVal << ",\n";
 353       ++EnumVal;
 354     }
 355   }
 356
 357   OS << "  OPERAND_TYPE_LIST_END" << "\n};\n";
 358   OS << "} // end namespace OpTypes\n";
 359   OS << "} // end namespace " << Namespace << "\n";
 360   OS << "} // end namespace llvm\n";
 361   OS << "#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM\n\n";
 362
 363   OS << "#ifdef GET_INSTRINFO_OPERAND_TYPE\n";
 364   OS << "#undef GET_INSTRINFO_OPERAND_TYPE\n";
 365   OS << "namespace llvm {\n";
 366   OS << "namespace " << Namespace << " {\n";
 367   OS << "LLVM_READONLY\n";
 368   OS << "static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {\n";
 369   // TODO: Factor out instructions with same operands to compress the tables.
 370   if (!NumberedInstructions.empty()) {
 371     std::vector<int> OperandOffsets;
 372     std::vector<Record *> OperandRecords;
 373     int CurrentOffset = 0;
 374     for (const CodeGenInstruction *Inst : NumberedInstructions) {
 375       OperandOffsets.push_back(CurrentOffset);
 376       for (const auto &Op : Inst->Operands) {
 377         const DagInit *MIOI = Op.MIOperandInfo;
 378         if (!MIOI || MIOI->getNumArgs() == 0) {
 379           // Single, anonymous, operand.
 380           OperandRecords.push_back(Op.Rec);
 381           ++CurrentOffset;
 382         } else {
 383           for (Init *Arg : make_range(MIOI->arg_begin(), MIOI->arg_end())) {
 384             OperandRecords.push_back(cast<DefInit>(Arg)->getDef());
 385             ++CurrentOffset;
 386           }
 387         }
 388       }
 389     }
 390
 391     // Emit the table of offsets for the opcode lookup.
 392     OS << "  const int Offsets[] = {\n";
 393     for (int I = 0, E = OperandOffsets.size(); I != E; ++I)
 394       OS << "    " << OperandOffsets[I] << ",\n";
 395     OS << "  };\n";
 396
 397     // Add an entry for the end so that we don't need to special case it below.
 398     OperandOffsets.push_back(OperandRecords.size());
 399     // Emit the actual operand types in a flat table.
 400     OS << "  const int OpcodeOperandTypes[] = {\n    ";
 401     for (int I = 0, E = OperandRecords.size(), CurOffset = 1; I != E; ++I) {
 402       // We print each Opcode's operands in its own row.
 403       if (I == OperandOffsets[CurOffset]) {
 404         OS << "\n    ";
 405         // If there are empty rows, mark them with an empty comment.
 406         while (OperandOffsets[++CurOffset] == I)
 407           OS << "/**/\n    ";
 408       }
 409       Record *OpR = OperandRecords[I];
 410       if ((OpR->isSubClassOf("Operand") ||
 411            OpR->isSubClassOf("RegisterOperand") ||
 412            OpR->isSubClassOf("RegisterClass")) &&
 413           !OpR->isAnonymous())
 414         OS << "OpTypes::" << OpR->getName();
 415       else
 416         OS << -1;
 417       OS << ", ";
 418     }
 419     OS << "\n  };\n";
 420
 421     OS << "  return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];\n";
 422   } else {
 423     OS << "  llvm_unreachable(\"No instructions defined\");\n";
 424   }
 425   OS << "}\n";
 426   OS << "} // end namespace " << Namespace << "\n";
 427   OS << "} // end namespace llvm\n";
 428   OS << "#endif // GET_INSTRINFO_OPERAND_TYPE\n\n";
 429 }
 430
 431 void InstrInfoEmitter::emitMCIIHelperMethods(raw_ostream &OS,
 432                                              StringRef TargetName) {
 433   RecVec TIIPredicates = Records.getAllDerivedDefinitions("TIIPredicate");
 434   if (TIIPredicates.empty())
 435     return;
 436
 437   OS << "#ifdef GET_INSTRINFO_MC_HELPER_DECLS\n";
 438   OS << "#undef GET_INSTRINFO_MC_HELPER_DECLS\n\n";
 439
 440   OS << "namespace llvm {\n";
 441   OS << "class MCInst;\n\n";
 442
 443   OS << "namespace " << TargetName << "_MC {\n\n";
 444
 445   for (const Record *Rec : TIIPredicates) {
 446     OS << "bool " << Rec->getValueAsString("FunctionName")
 447         << "(const MCInst &MI);\n";
 448   }
 449
 450   OS << "\n} // end namespace " << TargetName << "_MC\n";
 451   OS << "} // end namespace llvm\n\n";
 452
 453   OS << "#endif // GET_INSTRINFO_MC_HELPER_DECLS\n\n";
 454
 455   OS << "#ifdef GET_INSTRINFO_MC_HELPERS\n";
 456   OS << "#undef GET_INSTRINFO_MC_HELPERS\n\n";
 457
 458   OS << "namespace llvm {\n";
 459   OS << "namespace " << TargetName << "_MC {\n\n";
 460
 461   PredicateExpander PE(TargetName);
 462   PE.setExpandForMC(true);
 463
 464   for (const Record *Rec : TIIPredicates) {
 465     OS << "bool " << Rec->getValueAsString("FunctionName");
 466     OS << "(const MCInst &MI) {\n";
 467
 468     OS.indent(PE.getIndentLevel() * 2);
 469     PE.expandStatement(OS, Rec->getValueAsDef("Body"));
 470     OS << "\n}\n\n";
 471   }
 472
 473   OS << "} // end namespace " << TargetName << "_MC\n";
 474   OS << "} // end namespace llvm\n\n";
 475
 476   OS << "#endif // GET_GENISTRINFO_MC_HELPERS\n";
 477 }
 478
 479 void InstrInfoEmitter::emitTIIHelperMethods(raw_ostream &OS,
 480                                             StringRef TargetName,
 481                                             bool ExpandDefinition) {
 482   RecVec TIIPredicates = Records.getAllDerivedDefinitions("TIIPredicate");
 483   if (TIIPredicates.empty())
 484     return;
 485
 486   PredicateExpander PE(TargetName);
 487   PE.setExpandForMC(false);
 488
 489   for (const Record *Rec : TIIPredicates) {
 490     OS << (ExpandDefinition ? "" : "static ") << "bool ";
 491     if (ExpandDefinition)
 492       OS << TargetName << "InstrInfo::";
 493     OS << Rec->getValueAsString("FunctionName");
 494     OS << "(const MachineInstr &MI)";
 495     if (!ExpandDefinition) {
 496       OS << ";\n";
 497       continue;
 498     }
 499
 500     OS << " {\n";
 501     OS.indent(PE.getIndentLevel() * 2);
 502     PE.expandStatement(OS, Rec->getValueAsDef("Body"));
 503     OS << "\n}\n\n";
 504   }
 505 }
 506
 507 //===----------------------------------------------------------------------===//
 508 // Main Output.
 509 //===----------------------------------------------------------------------===//
 510
 511 // run - Emit the main instruction description records for the target...
 512 void InstrInfoEmitter::run(raw_ostream &OS) {
 513   emitSourceFileHeader("Target Instruction Enum Values and Descriptors", OS);
 514   emitEnums(OS);
 515
 516   OS << "#ifdef GET_INSTRINFO_MC_DESC\n";
 517   OS << "#undef GET_INSTRINFO_MC_DESC\n";
 518
 519   OS << "namespace llvm {\n\n";
 520
 521   CodeGenTarget &Target = CDP.getTargetInfo();
 522   const std::string &TargetName = Target.getName();
 523   Record *InstrInfo = Target.getInstructionSet();
 524
 525   // Keep track of all of the def lists we have emitted already.
 526   std::map<std::vector<Record*>, unsigned> EmittedLists;
 527   unsigned ListNumber = 0;
 528
 529   // Emit all of the instruction's implicit uses and defs.
 530   for (const CodeGenInstruction *II : Target.getInstructionsByEnumValue()) {
 531     Record *Inst = II->TheDef;
 532     std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
 533     if (!Uses.empty()) {
 534       unsigned &IL = EmittedLists[Uses];
 535       if (!IL) PrintDefList(Uses, IL = ++ListNumber, OS);
 536     }
 537     std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
 538     if (!Defs.empty()) {
 539       unsigned &IL = EmittedLists[Defs];
 540       if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS);
 541     }
 542   }
 543
 544   OperandInfoMapTy OperandInfoIDs;
 545
 546   // Emit all of the operand info records.
 547   EmitOperandInfo(OS, OperandInfoIDs);
 548
 549   // Emit all of the MCInstrDesc records in their ENUM ordering.
 550   //
 551   OS << "\nextern const MCInstrDesc " << TargetName << "Insts[] = {\n";
 552   ArrayRef<const CodeGenInstruction*> NumberedInstructions =
 553     Target.getInstructionsByEnumValue();
 554
 555   SequenceToOffsetTable<std::string> InstrNames;
 556   unsigned Num = 0;
 557   for (const CodeGenInstruction *Inst : NumberedInstructions) {
 558     // Keep a list of the instruction names.
 559     InstrNames.add(Inst->TheDef->getName());
 560     // Emit the record into the table.
 561     emitRecord(*Inst, Num++, InstrInfo, EmittedLists, OperandInfoIDs, OS);
 562   }
 563   OS << "};\n\n";
 564
 565   // Emit the array of instruction names.
 566   InstrNames.layout();
 567   OS << "extern const char " << TargetName << "InstrNameData[] = {\n";
 568   InstrNames.emit(OS, printChar);
 569   OS << "};\n\n";
 570
 571   OS << "extern const unsigned " << TargetName <<"InstrNameIndices[] = {";
 572   Num = 0;
 573   for (const CodeGenInstruction *Inst : NumberedInstructions) {
 574     // Newline every eight entries.
 575     if (Num % 8 == 0)
 576       OS << "\n    ";
 577     OS << InstrNames.get(Inst->TheDef->getName()) << "U, ";
 578     ++Num;
 579   }
 580
 581   OS << "\n};\n\n";
 582
 583   // MCInstrInfo initialization routine.
 584   OS << "static inline void Init" << TargetName
 585      << "MCInstrInfo(MCInstrInfo *II) {\n";
 586   OS << "  II->InitMCInstrInfo(" << TargetName << "Insts, "
 587      << TargetName << "InstrNameIndices, " << TargetName << "InstrNameData, "
 588      << NumberedInstructions.size() << ");\n}\n\n";
 589
 590   OS << "} // end namespace llvm\n";
 591
 592   OS << "#endif // GET_INSTRINFO_MC_DESC\n\n";
 593
 594   // Create a TargetInstrInfo subclass to hide the MC layer initialization.
 595   OS << "#ifdef GET_INSTRINFO_HEADER\n";
 596   OS << "#undef GET_INSTRINFO_HEADER\n";
 597
 598   std::string ClassName = TargetName + "GenInstrInfo";
 599   OS << "namespace llvm {\n";
 600   OS << "struct " << ClassName << " : public TargetInstrInfo {\n"
 601      << "  explicit " << ClassName
 602      << "(int CFSetupOpcode = -1, int CFDestroyOpcode = -1, int CatchRetOpcode = -1, int ReturnOpcode = -1);\n"
 603      << "  ~" << ClassName << "() override = default;\n";
 604
 605
 606   OS << "\n};\n} // end namespace llvm\n";
 607
 608   OS << "#endif // GET_INSTRINFO_HEADER\n\n";
 609
 610   OS << "#ifdef GET_INSTRINFO_HELPER_DECLS\n";
 611   OS << "#undef GET_INSTRINFO_HELPER_DECLS\n\n";
 612   emitTIIHelperMethods(OS, TargetName, /* ExpandDefintion = */false);
 613   OS << "\n";
 614   OS << "#endif // GET_INSTRINFO_HELPER_DECLS\n\n";
 615
 616   OS << "#ifdef GET_INSTRINFO_HELPERS\n";
 617   OS << "#undef GET_INSTRINFO_HELPERS\n\n";
 618   emitTIIHelperMethods(OS, TargetName, /* ExpandDefintion = */true);
 619   OS << "#endif // GET_INSTRINFO_HELPERS\n\n";
 620
 621   OS << "#ifdef GET_INSTRINFO_CTOR_DTOR\n";
 622   OS << "#undef GET_INSTRINFO_CTOR_DTOR\n";
 623
 624   OS << "namespace llvm {\n";
 625   OS << "extern const MCInstrDesc " << TargetName << "Insts[];\n";
 626   OS << "extern const unsigned " << TargetName << "InstrNameIndices[];\n";
 627   OS << "extern const char " << TargetName << "InstrNameData[];\n";
 628   OS << ClassName << "::" << ClassName
 629      << "(int CFSetupOpcode, int CFDestroyOpcode, int CatchRetOpcode, int ReturnOpcode)\n"
 630      << "  : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {\n"
 631      << "  InitMCInstrInfo(" << TargetName << "Insts, " << TargetName
 632      << "InstrNameIndices, " << TargetName << "InstrNameData, "
 633      << NumberedInstructions.size() << ");\n}\n";
 634   OS << "} // end namespace llvm\n";
 635
 636   OS << "#endif // GET_INSTRINFO_CTOR_DTOR\n\n";
 637
 638   emitOperandNameMappings(OS, Target, NumberedInstructions);
 639
 640   emitOperandTypeMappings(OS, Target, NumberedInstructions);
 641
 642   emitMCIIHelperMethods(OS, TargetName);
 643 }
 644
 645 void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
 646                                   Record *InstrInfo,
 647                          std::map<std::vector<Record*>, unsigned> &EmittedLists,
 648                                   const OperandInfoMapTy &OpInfo,
 649                                   raw_ostream &OS) {
 650   int MinOperands = 0;
 651   if (!Inst.Operands.empty())
 652     // Each logical operand can be multiple MI operands.
 653     MinOperands = Inst.Operands.back().MIOperandNo +
 654                   Inst.Operands.back().MINumOperands;
 655
 656   OS << "  { ";
 657   OS << Num << ",\t" << MinOperands << ",\t"
 658      << Inst.Operands.NumDefs << ",\t"
 659      << Inst.TheDef->getValueAsInt("Size") << ",\t"
 660      << SchedModels.getSchedClassIdx(Inst) << ",\t0";
 661
 662   CodeGenTarget &Target = CDP.getTargetInfo();
 663
 664   // Emit all of the target independent flags...
 665   if (Inst.isPreISelOpcode)    OS << "|(1ULL<<MCID::PreISelOpcode)";
 666   if (Inst.isPseudo)           OS << "|(1ULL<<MCID::Pseudo)";
 667   if (Inst.isReturn)           OS << "|(1ULL<<MCID::Return)";
 668   if (Inst.isEHScopeReturn)    OS << "|(1ULL<<MCID::EHScopeReturn)";
 669   if (Inst.isBranch)           OS << "|(1ULL<<MCID::Branch)";
 670   if (Inst.isIndirectBranch)   OS << "|(1ULL<<MCID::IndirectBranch)";
 671   if (Inst.isCompare)          OS << "|(1ULL<<MCID::Compare)";
 672   if (Inst.isMoveImm)          OS << "|(1ULL<<MCID::MoveImm)";
 673   if (Inst.isMoveReg)          OS << "|(1ULL<<MCID::MoveReg)";
 674   if (Inst.isBitcast)          OS << "|(1ULL<<MCID::Bitcast)";
 675   if (Inst.isAdd)              OS << "|(1ULL<<MCID::Add)";
 676   if (Inst.isTrap)             OS << "|(1ULL<<MCID::Trap)";
 677   if (Inst.isSelect)           OS << "|(1ULL<<MCID::Select)";
 678   if (Inst.isBarrier)          OS << "|(1ULL<<MCID::Barrier)";
 679   if (Inst.hasDelaySlot)       OS << "|(1ULL<<MCID::DelaySlot)";
 680   if (Inst.isCall)             OS << "|(1ULL<<MCID::Call)";
 681   if (Inst.canFoldAsLoad)      OS << "|(1ULL<<MCID::FoldableAsLoad)";
 682   if (Inst.mayLoad)            OS << "|(1ULL<<MCID::MayLoad)";
 683   if (Inst.mayStore)           OS << "|(1ULL<<MCID::MayStore)";
 684   if (Inst.mayRaiseFPException) OS << "|(1ULL<<MCID::MayRaiseFPException)";
 685   if (Inst.isPredicable)       OS << "|(1ULL<<MCID::Predicable)";
 686   if (Inst.isConvertibleToThreeAddress) OS << "|(1ULL<<MCID::ConvertibleTo3Addr)";
 687   if (Inst.isCommutable)       OS << "|(1ULL<<MCID::Commutable)";
 688   if (Inst.isTerminator)       OS << "|(1ULL<<MCID::Terminator)";
 689   if (Inst.isReMaterializable) OS << "|(1ULL<<MCID::Rematerializable)";
 690   if (Inst.isNotDuplicable)    OS << "|(1ULL<<MCID::NotDuplicable)";
 691   if (Inst.Operands.hasOptionalDef) OS << "|(1ULL<<MCID::HasOptionalDef)";
 692   if (Inst.usesCustomInserter) OS << "|(1ULL<<MCID::UsesCustomInserter)";
 693   if (Inst.hasPostISelHook)    OS << "|(1ULL<<MCID::HasPostISelHook)";
 694   if (Inst.Operands.isVariadic)OS << "|(1ULL<<MCID::Variadic)";
 695   if (Inst.hasSideEffects)     OS << "|(1ULL<<MCID::UnmodeledSideEffects)";
 696   if (Inst.isAsCheapAsAMove)   OS << "|(1ULL<<MCID::CheapAsAMove)";
 697   if (!Target.getAllowRegisterRenaming() || Inst.hasExtraSrcRegAllocReq)
 698     OS << "|(1ULL<<MCID::ExtraSrcRegAllocReq)";
 699   if (!Target.getAllowRegisterRenaming() || Inst.hasExtraDefRegAllocReq)
 700     OS << "|(1ULL<<MCID::ExtraDefRegAllocReq)";
 701   if (Inst.isRegSequence) OS << "|(1ULL<<MCID::RegSequence)";
 702   if (Inst.isExtractSubreg) OS << "|(1ULL<<MCID::ExtractSubreg)";
 703   if (Inst.isInsertSubreg) OS << "|(1ULL<<MCID::InsertSubreg)";
 704   if (Inst.isConvergent) OS << "|(1ULL<<MCID::Convergent)";
 705   if (Inst.variadicOpsAreDefs) OS << "|(1ULL<<MCID::VariadicOpsAreDefs)";
 706
 707   // Emit all of the target-specific flags...
 708   BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags");
 709   if (!TSF)
 710     PrintFatalError(Inst.TheDef->getLoc(), "no TSFlags?");
 711   uint64_t Value = 0;
 712   for (unsigned i = 0, e = TSF->getNumBits(); i != e; ++i) {
 713     if (const auto *Bit = dyn_cast<BitInit>(TSF->getBit(i)))
 714       Value |= uint64_t(Bit->getValue()) << i;
 715     else
 716       PrintFatalError(Inst.TheDef->getLoc(),
 717                       "Invalid TSFlags bit in " + Inst.TheDef->getName());
 718   }
 719   OS << ", 0x";
 720   OS.write_hex(Value);
 721   OS << "ULL, ";
 722
 723   // Emit the implicit uses and defs lists...
 724   std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
 725   if (UseList.empty())
 726     OS << "nullptr, ";
 727   else
 728     OS << "ImplicitList" << EmittedLists[UseList] << ", ";
 729
 730   std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
 731   if (DefList.empty())
 732     OS << "nullptr, ";
 733   else
 734     OS << "ImplicitList" << EmittedLists[DefList] << ", ";
 735
 736   // Emit the operand info.
 737   std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
 738   if (OperandInfo.empty())
 739     OS << "nullptr";
 740   else
 741     OS << "OperandInfo" << OpInfo.find(OperandInfo)->second;
 742
 743   if (Inst.HasComplexDeprecationPredicate)
 744     // Emit a function pointer to the complex predicate method.
 745     OS << ", -1 "
 746        << ",&get" << Inst.DeprecatedReason << "DeprecationInfo";
 747   else if (!Inst.DeprecatedReason.empty())
 748     // Emit the Subtarget feature.
 749     OS << ", " << Target.getInstNamespace() << "::" << Inst.DeprecatedReason
 750        << " ,nullptr";
 751   else
 752     // Instruction isn't deprecated.
 753     OS << ", -1 ,nullptr";
 754
 755   OS << " },  // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
 756 }
 757
 758 // emitEnums - Print out enum values for all of the instructions.
 759 void InstrInfoEmitter::emitEnums(raw_ostream &OS) {
 760   OS << "#ifdef GET_INSTRINFO_ENUM\n";
 761   OS << "#undef GET_INSTRINFO_ENUM\n";
 762
 763   OS << "namespace llvm {\n\n";
 764
 765   CodeGenTarget Target(Records);
 766
 767   // We must emit the PHI opcode first...
 768   StringRef Namespace = Target.getInstNamespace();
 769
 770   if (Namespace.empty())
 771     PrintFatalError("No instructions defined!");
 772
 773   OS << "namespace " << Namespace << " {\n";
 774   OS << "  enum {\n";
 775   unsigned Num = 0;
 776   for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue())
 777     OS << "    " << Inst->TheDef->getName() << "\t= " << Num++ << ",\n";
 778   OS << "    INSTRUCTION_LIST_END = " << Num << "\n";
 779   OS << "  };\n\n";
 780   OS << "} // end namespace " << Namespace << "\n";
 781   OS << "} // end namespace llvm\n";
 782   OS << "#endif // GET_INSTRINFO_ENUM\n\n";
 783
 784   OS << "#ifdef GET_INSTRINFO_SCHED_ENUM\n";
 785   OS << "#undef GET_INSTRINFO_SCHED_ENUM\n";
 786   OS << "namespace llvm {\n\n";
 787   OS << "namespace " << Namespace << " {\n";
 788   OS << "namespace Sched {\n";
 789   OS << "  enum {\n";
 790   Num = 0;
 791   for (const auto &Class : SchedModels.explicit_classes())
 792     OS << "    " << Class.Name << "\t= " << Num++ << ",\n";
 793   OS << "    SCHED_LIST_END = " << Num << "\n";
 794   OS << "  };\n";
 795   OS << "} // end namespace Sched\n";
 796   OS << "} // end namespace " << Namespace << "\n";
 797   OS << "} // end namespace llvm\n";
 798
 799   OS << "#endif // GET_INSTRINFO_SCHED_ENUM\n\n";
 800 }
 801
 802 namespace llvm {
 803
 804 void EmitInstrInfo(RecordKeeper &RK, raw_ostream &OS) {
 805   InstrInfoEmitter(RK).run(OS);
 806   EmitMapTable(RK, OS);
 807 }
 808
 809 } // end namespace llvm