utils/TableGen/X86RecognizableInstr.h

   1 //===- X86RecognizableInstr.h - Disassembler instruction spec ----*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file is part of the X86 Disassembler Emitter.
  10 // It contains the interface of a single recognizable instruction.
  11 // Documentation for the disassembler emitter in general can be found in
  12 //  X86DisassemblerEmitter.h.
  13 //
  14 //===----------------------------------------------------------------------===//
  15
  16 #ifndef LLVM_UTILS_TABLEGEN_X86RECOGNIZABLEINSTR_H
  17 #define LLVM_UTILS_TABLEGEN_X86RECOGNIZABLEINSTR_H
  18
  19 #include "CodeGenTarget.h"
  20 #include "X86DisassemblerTables.h"
  21 #include "llvm/Support/DataTypes.h"
  22 #include "llvm/TableGen/Record.h"
  23
  24 namespace llvm {
  25
  26 #define X86_INSTR_MRM_MAPPING     \
  27   MAP(C0, 64)                     \
  28   MAP(C1, 65)                     \
  29   MAP(C2, 66)                     \
  30   MAP(C3, 67)                     \
  31   MAP(C4, 68)                     \
  32   MAP(C5, 69)                     \
  33   MAP(C6, 70)                     \
  34   MAP(C7, 71)                     \
  35   MAP(C8, 72)                     \
  36   MAP(C9, 73)                     \
  37   MAP(CA, 74)                     \
  38   MAP(CB, 75)                     \
  39   MAP(CC, 76)                     \
  40   MAP(CD, 77)                     \
  41   MAP(CE, 78)                     \
  42   MAP(CF, 79)                     \
  43   MAP(D0, 80)                     \
  44   MAP(D1, 81)                     \
  45   MAP(D2, 82)                     \
  46   MAP(D3, 83)                     \
  47   MAP(D4, 84)                     \
  48   MAP(D5, 85)                     \
  49   MAP(D6, 86)                     \
  50   MAP(D7, 87)                     \
  51   MAP(D8, 88)                     \
  52   MAP(D9, 89)                     \
  53   MAP(DA, 90)                     \
  54   MAP(DB, 91)                     \
  55   MAP(DC, 92)                     \
  56   MAP(DD, 93)                     \
  57   MAP(DE, 94)                     \
  58   MAP(DF, 95)                     \
  59   MAP(E0, 96)                     \
  60   MAP(E1, 97)                     \
  61   MAP(E2, 98)                     \
  62   MAP(E3, 99)                     \
  63   MAP(E4, 100)                    \
  64   MAP(E5, 101)                    \
  65   MAP(E6, 102)                    \
  66   MAP(E7, 103)                    \
  67   MAP(E8, 104)                    \
  68   MAP(E9, 105)                    \
  69   MAP(EA, 106)                    \
  70   MAP(EB, 107)                    \
  71   MAP(EC, 108)                    \
  72   MAP(ED, 109)                    \
  73   MAP(EE, 110)                    \
  74   MAP(EF, 111)                    \
  75   MAP(F0, 112)                    \
  76   MAP(F1, 113)                    \
  77   MAP(F2, 114)                    \
  78   MAP(F3, 115)                    \
  79   MAP(F4, 116)                    \
  80   MAP(F5, 117)                    \
  81   MAP(F6, 118)                    \
  82   MAP(F7, 119)                    \
  83   MAP(F8, 120)                    \
  84   MAP(F9, 121)                    \
  85   MAP(FA, 122)                    \
  86   MAP(FB, 123)                    \
  87   MAP(FC, 124)                    \
  88   MAP(FD, 125)                    \
  89   MAP(FE, 126)                    \
  90   MAP(FF, 127)
  91
  92 // A clone of X86 since we can't depend on something that is generated.
  93 namespace X86Local {
  94   enum {
  95     Pseudo        = 0,
  96     RawFrm        = 1,
  97     AddRegFrm     = 2,
  98     RawFrmMemOffs = 3,
  99     RawFrmSrc     = 4,
 100     RawFrmDst     = 5,
 101     RawFrmDstSrc  = 6,
 102     RawFrmImm8    = 7,
 103     RawFrmImm16   = 8,
 104     AddCCFrm      = 9,
 105     MRMDestMem     = 32,
 106     MRMSrcMem      = 33,
 107     MRMSrcMem4VOp3 = 34,
 108     MRMSrcMemOp4   = 35,
 109     MRMSrcMemCC    = 36,
 110     MRMXmCC = 38, MRMXm = 39,
 111     MRM0m = 40, MRM1m = 41, MRM2m = 42, MRM3m = 43,
 112     MRM4m = 44, MRM5m = 45, MRM6m = 46, MRM7m = 47,
 113     MRMDestReg     = 48,
 114     MRMSrcReg      = 49,
 115     MRMSrcReg4VOp3 = 50,
 116     MRMSrcRegOp4   = 51,
 117     MRMSrcRegCC    = 52,
 118     MRMXrCC = 54, MRMXr = 55,
 119     MRM0r = 56, MRM1r = 57, MRM2r = 58, MRM3r = 59,
 120     MRM4r = 60, MRM5r = 61, MRM6r = 62, MRM7r = 63,
 121 #define MAP(from, to) MRM_##from = to,
 122     X86_INSTR_MRM_MAPPING
 123 #undef MAP
 124   };
 125
 126   enum {
 127     OB = 0, TB = 1, T8 = 2, TA = 3, XOP8 = 4, XOP9 = 5, XOPA = 6, ThreeDNow = 7
 128   };
 129
 130   enum {
 131     PD = 1, XS = 2, XD = 3, PS = 4
 132   };
 133
 134   enum {
 135     VEX = 1, XOP = 2, EVEX = 3
 136   };
 137
 138   enum {
 139     OpSize16 = 1, OpSize32 = 2
 140   };
 141
 142   enum {
 143     AdSize16 = 1, AdSize32 = 2, AdSize64 = 3
 144   };
 145 }
 146
 147 namespace X86Disassembler {
 148
 149 /// RecognizableInstr - Encapsulates all information required to decode a single
 150 ///   instruction, as extracted from the LLVM instruction tables.  Has methods
 151 ///   to interpret the information available in the LLVM tables, and to emit the
 152 ///   instruction into DisassemblerTables.
 153 class RecognizableInstr {
 154 private:
 155   /// The opcode of the instruction, as used in an MCInst
 156   InstrUID UID;
 157   /// The record from the .td files corresponding to this instruction
 158   const Record* Rec;
 159   /// The OpPrefix field from the record
 160   uint8_t OpPrefix;
 161   /// The OpMap field from the record
 162   uint8_t OpMap;
 163   /// The opcode field from the record; this is the opcode used in the Intel
 164   /// encoding and therefore distinct from the UID
 165   uint8_t Opcode;
 166   /// The form field from the record
 167   uint8_t Form;
 168   // The encoding field from the record
 169   uint8_t Encoding;
 170   /// The OpSize field from the record
 171   uint8_t OpSize;
 172   /// The AdSize field from the record
 173   uint8_t AdSize;
 174   /// The hasREX_WPrefix field from the record
 175   bool HasREX_WPrefix;
 176   /// The hasVEX_4V field from the record
 177   bool HasVEX_4V;
 178   /// The HasVEX_WPrefix field from the record
 179   bool HasVEX_W;
 180   /// The IgnoresVEX_W field from the record
 181   bool IgnoresVEX_W;
 182   /// Inferred from the operands; indicates whether the L bit in the VEX prefix is set
 183   bool HasVEX_LPrefix;
 184   /// The ignoreVEX_L field from the record
 185   bool IgnoresVEX_L;
 186   /// The hasEVEX_L2Prefix field from the record
 187   bool HasEVEX_L2Prefix;
 188   /// The hasEVEX_K field from the record
 189   bool HasEVEX_K;
 190   /// The hasEVEX_KZ field from the record
 191   bool HasEVEX_KZ;
 192   /// The hasEVEX_B field from the record
 193   bool HasEVEX_B;
 194   /// Indicates that the instruction uses the L and L' fields for RC.
 195   bool EncodeRC;
 196   /// The isCodeGenOnly field from the record
 197   bool IsCodeGenOnly;
 198   /// The ForceDisassemble field from the record
 199   bool ForceDisassemble;
 200   // The CD8_Scale field from the record
 201   uint8_t CD8_Scale;
 202   // Whether the instruction has the predicate "In64BitMode"
 203   bool Is64Bit;
 204   // Whether the instruction has the predicate "In32BitMode"
 205   bool Is32Bit;
 206
 207   /// The instruction name as listed in the tables
 208   std::string Name;
 209
 210   /// Indicates whether the instruction should be emitted into the decode
 211   /// tables; regardless, it will be emitted into the instruction info table
 212   bool ShouldBeEmitted;
 213
 214   /// The operands of the instruction, as listed in the CodeGenInstruction.
 215   /// They are not one-to-one with operands listed in the MCInst; for example,
 216   /// memory operands expand to 5 operands in the MCInst
 217   const std::vector<CGIOperandList::OperandInfo>* Operands;
 218
 219   /// The description of the instruction that is emitted into the instruction
 220   /// info table
 221   InstructionSpecifier* Spec;
 222
 223   /// insnContext - Returns the primary context in which the instruction is
 224   ///   valid.
 225   ///
 226   /// @return - The context in which the instruction is valid.
 227   InstructionContext insnContext() const;
 228
 229   /// typeFromString - Translates an operand type from the string provided in
 230   ///   the LLVM tables to an OperandType for use in the operand specifier.
 231   ///
 232   /// @param s              - The string, as extracted by calling Rec->getName()
 233   ///                         on a CodeGenInstruction::OperandInfo.
 234   /// @param hasREX_WPrefix - Indicates whether the instruction has a REX.W
 235   ///                         prefix.  If it does, 32-bit register operands stay
 236   ///                         32-bit regardless of the operand size.
 237   /// @param OpSize           Indicates the operand size of the instruction.
 238   ///                         If register size does not match OpSize, then
 239   ///                         register sizes keep their size.
 240   /// @return               - The operand's type.
 241   static OperandType typeFromString(const std::string& s,
 242                                     bool hasREX_WPrefix, uint8_t OpSize);
 243
 244   /// immediateEncodingFromString - Translates an immediate encoding from the
 245   ///   string provided in the LLVM tables to an OperandEncoding for use in
 246   ///   the operand specifier.
 247   ///
 248   /// @param s       - See typeFromString().
 249   /// @param OpSize  - Indicates whether this is an OpSize16 instruction.
 250   ///                  If it is not, then 16-bit immediate operands stay 16-bit.
 251   /// @return        - The operand's encoding.
 252   static OperandEncoding immediateEncodingFromString(const std::string &s,
 253                                                      uint8_t OpSize);
 254
 255   /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but
 256   ///   handles operands that are in the REG field of the ModR/M byte.
 257   static OperandEncoding rmRegisterEncodingFromString(const std::string &s,
 258                                                       uint8_t OpSize);
 259
 260   /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but
 261   ///   handles operands that are in the REG field of the ModR/M byte.
 262   static OperandEncoding roRegisterEncodingFromString(const std::string &s,
 263                                                       uint8_t OpSize);
 264   static OperandEncoding memoryEncodingFromString(const std::string &s,
 265                                                   uint8_t OpSize);
 266   static OperandEncoding relocationEncodingFromString(const std::string &s,
 267                                                       uint8_t OpSize);
 268   static OperandEncoding opcodeModifierEncodingFromString(const std::string &s,
 269                                                           uint8_t OpSize);
 270   static OperandEncoding vvvvRegisterEncodingFromString(const std::string &s,
 271                                                         uint8_t OpSize);
 272   static OperandEncoding writemaskRegisterEncodingFromString(const std::string &s,
 273                                                              uint8_t OpSize);
 274
 275   /// Adjust the encoding type for an operand based on the instruction.
 276   void adjustOperandEncoding(OperandEncoding &encoding);
 277
 278   /// handleOperand - Converts a single operand from the LLVM table format to
 279   ///   the emitted table format, handling any duplicate operands it encounters
 280   ///   and then one non-duplicate.
 281   ///
 282   /// @param optional             - Determines whether to assert that the
 283   ///                               operand exists.
 284   /// @param operandIndex         - The index into the generated operand table.
 285   ///                               Incremented by this function one or more
 286   ///                               times to reflect possible duplicate
 287   ///                               operands).
 288   /// @param physicalOperandIndex - The index of the current operand into the
 289   ///                               set of non-duplicate ('physical') operands.
 290   ///                               Incremented by this function once.
 291   /// @param numPhysicalOperands  - The number of non-duplicate operands in the
 292   ///                               instructions.
 293   /// @param operandMapping       - The operand mapping, which has an entry for
 294   ///                               each operand that indicates whether it is a
 295   ///                               duplicate, and of what.
 296   void handleOperand(bool optional,
 297                      unsigned &operandIndex,
 298                      unsigned &physicalOperandIndex,
 299                      unsigned numPhysicalOperands,
 300                      const unsigned *operandMapping,
 301                      OperandEncoding (*encodingFromString)
 302                        (const std::string&,
 303                         uint8_t OpSize));
 304
 305   /// shouldBeEmitted - Returns the shouldBeEmitted field.  Although filter()
 306   ///   filters out many instructions, at various points in decoding we
 307   ///   determine that the instruction should not actually be decodable.  In
 308   ///   particular, MMX MOV instructions aren't emitted, but they're only
 309   ///   identified during operand parsing.
 310   ///
 311   /// @return - true if at this point we believe the instruction should be
 312   ///   emitted; false if not.  This will return false if filter() returns false
 313   ///   once emitInstructionSpecifier() has been called.
 314   bool shouldBeEmitted() const {
 315     return ShouldBeEmitted;
 316   }
 317
 318   /// emitInstructionSpecifier - Loads the instruction specifier for the current
 319   ///   instruction into a DisassemblerTables.
 320   ///
 321   void emitInstructionSpecifier();
 322
 323   /// emitDecodePath - Populates the proper fields in the decode tables
 324   ///   corresponding to the decode paths for this instruction.
 325   ///
 326   /// \param tables The DisassemblerTables to populate with the decode
 327   ///               decode information for the current instruction.
 328   void emitDecodePath(DisassemblerTables &tables) const;
 329
 330   /// Constructor - Initializes a RecognizableInstr with the appropriate fields
 331   ///   from a CodeGenInstruction.
 332   ///
 333   /// \param tables The DisassemblerTables that the specifier will be added to.
 334   /// \param insn   The CodeGenInstruction to extract information from.
 335   /// \param uid    The unique ID of the current instruction.
 336   RecognizableInstr(DisassemblerTables &tables,
 337                     const CodeGenInstruction &insn,
 338                     InstrUID uid);
 339 public:
 340   /// processInstr - Accepts a CodeGenInstruction and loads decode information
 341   ///   for it into a DisassemblerTables if appropriate.
 342   ///
 343   /// \param tables The DiassemblerTables to be populated with decode
 344   ///               information.
 345   /// \param insn   The CodeGenInstruction to be used as a source for this
 346   ///               information.
 347   /// \param uid    The unique ID of the instruction.
 348   static void processInstr(DisassemblerTables &tables,
 349                            const CodeGenInstruction &insn,
 350                            InstrUID uid);
 351 };
 352
 353 } // namespace X86Disassembler
 354
 355 } // namespace llvm
 356
 357 #endif