lib/Target/PowerPC/PPCInstrInfo.cpp

   1 //===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file was developed by the LLVM research group and is distributed under
   6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "PPCInstrInfo.h"
  15 #include "PPCPredicates.h"
  16 #include "PPCGenInstrInfo.inc"
  17 #include "PPCTargetMachine.h"
  18 #include "llvm/ADT/STLExtras.h"
  19 #include "llvm/CodeGen/MachineInstrBuilder.h"
  20 using namespace llvm;
  21
  22 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
  23   : TargetInstrInfo(PPCInsts, array_lengthof(PPCInsts)), TM(tm),
  24     RI(*TM.getSubtargetImpl(), *this) {}
  25
  26 /// getPointerRegClass - Return the register class to use to hold pointers.
  27 /// This is used for addressing modes.
  28 const TargetRegisterClass *PPCInstrInfo::getPointerRegClass() const {
  29   if (TM.getSubtargetImpl()->isPPC64())
  30     return &PPC::G8RCRegClass;
  31   else
  32     return &PPC::GPRCRegClass;
  33 }
  34
  35
  36 bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
  37                                unsigned& sourceReg,
  38                                unsigned& destReg) const {
  39   MachineOpCode oc = MI.getOpcode();
  40   if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR ||
  41       oc == PPC::OR4To8 || oc == PPC::OR8To4) {                // or r1, r2, r2
  42     assert(MI.getNumOperands() >= 3 &&
  43            MI.getOperand(0).isRegister() &&
  44            MI.getOperand(1).isRegister() &&
  45            MI.getOperand(2).isRegister() &&
  46            "invalid PPC OR instruction!");
  47     if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
  48       sourceReg = MI.getOperand(1).getReg();
  49       destReg = MI.getOperand(0).getReg();
  50       return true;
  51     }
  52   } else if (oc == PPC::ADDI) {             // addi r1, r2, 0
  53     assert(MI.getNumOperands() >= 3 &&
  54            MI.getOperand(0).isRegister() &&
  55            MI.getOperand(2).isImmediate() &&
  56            "invalid PPC ADDI instruction!");
  57     if (MI.getOperand(1).isRegister() && MI.getOperand(2).getImmedValue()==0) {
  58       sourceReg = MI.getOperand(1).getReg();
  59       destReg = MI.getOperand(0).getReg();
  60       return true;
  61     }
  62   } else if (oc == PPC::ORI) {             // ori r1, r2, 0
  63     assert(MI.getNumOperands() >= 3 &&
  64            MI.getOperand(0).isRegister() &&
  65            MI.getOperand(1).isRegister() &&
  66            MI.getOperand(2).isImmediate() &&
  67            "invalid PPC ORI instruction!");
  68     if (MI.getOperand(2).getImmedValue()==0) {
  69       sourceReg = MI.getOperand(1).getReg();
  70       destReg = MI.getOperand(0).getReg();
  71       return true;
  72     }
  73   } else if (oc == PPC::FMRS || oc == PPC::FMRD ||
  74              oc == PPC::FMRSD) {      // fmr r1, r2
  75     assert(MI.getNumOperands() >= 2 &&
  76            MI.getOperand(0).isRegister() &&
  77            MI.getOperand(1).isRegister() &&
  78            "invalid PPC FMR instruction");
  79     sourceReg = MI.getOperand(1).getReg();
  80     destReg = MI.getOperand(0).getReg();
  81     return true;
  82   } else if (oc == PPC::MCRF) {             // mcrf cr1, cr2
  83     assert(MI.getNumOperands() >= 2 &&
  84            MI.getOperand(0).isRegister() &&
  85            MI.getOperand(1).isRegister() &&
  86            "invalid PPC MCRF instruction");
  87     sourceReg = MI.getOperand(1).getReg();
  88     destReg = MI.getOperand(0).getReg();
  89     return true;
  90   }
  91   return false;
  92 }
  93
  94 unsigned PPCInstrInfo::isLoadFromStackSlot(MachineInstr *MI,
  95                                            int &FrameIndex) const {
  96   switch (MI->getOpcode()) {
  97   default: break;
  98   case PPC::LD:
  99   case PPC::LWZ:
 100   case PPC::LFS:
 101   case PPC::LFD:
 102     if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() &&
 103         MI->getOperand(2).isFrameIndex()) {
 104       FrameIndex = MI->getOperand(2).getFrameIndex();
 105       return MI->getOperand(0).getReg();
 106     }
 107     break;
 108   }
 109   return 0;
 110 }
 111
 112 unsigned PPCInstrInfo::isStoreToStackSlot(MachineInstr *MI,
 113                                           int &FrameIndex) const {
 114   switch (MI->getOpcode()) {
 115   default: break;
 116   case PPC::STD:
 117   case PPC::STW:
 118   case PPC::STFS:
 119   case PPC::STFD:
 120     if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() &&
 121         MI->getOperand(2).isFrameIndex()) {
 122       FrameIndex = MI->getOperand(2).getFrameIndex();
 123       return MI->getOperand(0).getReg();
 124     }
 125     break;
 126   }
 127   return 0;
 128 }
 129
 130 // commuteInstruction - We can commute rlwimi instructions, but only if the
 131 // rotate amt is zero.  We also have to munge the immediates a bit.
 132 MachineInstr *PPCInstrInfo::commuteInstruction(MachineInstr *MI) const {
 133   // Normal instructions can be commuted the obvious way.
 134   if (MI->getOpcode() != PPC::RLWIMI)
 135     return TargetInstrInfo::commuteInstruction(MI);
 136
 137   // Cannot commute if it has a non-zero rotate count.
 138   if (MI->getOperand(3).getImmedValue() != 0)
 139     return 0;
 140
 141   // If we have a zero rotate count, we have:
 142   //   M = mask(MB,ME)
 143   //   Op0 = (Op1 & ~M) | (Op2 & M)
 144   // Change this to:
 145   //   M = mask((ME+1)&31, (MB-1)&31)
 146   //   Op0 = (Op2 & ~M) | (Op1 & M)
 147
 148   // Swap op1/op2
 149   unsigned Reg1 = MI->getOperand(1).getReg();
 150   unsigned Reg2 = MI->getOperand(2).getReg();
 151   bool Reg1IsKill = MI->getOperand(1).isKill();
 152   bool Reg2IsKill = MI->getOperand(2).isKill();
 153   MI->getOperand(2).setReg(Reg1);
 154   MI->getOperand(1).setReg(Reg2);
 155   if (Reg1IsKill)
 156     MI->getOperand(2).setIsKill();
 157   else
 158     MI->getOperand(2).unsetIsKill();
 159   if (Reg2IsKill)
 160     MI->getOperand(1).setIsKill();
 161   else
 162     MI->getOperand(1).unsetIsKill();
 163
 164   // Swap the mask around.
 165   unsigned MB = MI->getOperand(4).getImmedValue();
 166   unsigned ME = MI->getOperand(5).getImmedValue();
 167   MI->getOperand(4).setImmedValue((ME+1) & 31);
 168   MI->getOperand(5).setImmedValue((MB-1) & 31);
 169   return MI;
 170 }
 171
 172 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
 173                               MachineBasicBlock::iterator MI) const {
 174   BuildMI(MBB, MI, get(PPC::NOP));
 175 }
 176
 177
 178 // Branch analysis.
 179 bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
 180                                  MachineBasicBlock *&FBB,
 181                                  std::vector<MachineOperand> &Cond) const {
 182   // If the block has no terminators, it just falls into the block after it.
 183   MachineBasicBlock::iterator I = MBB.end();
 184   if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
 185     return false;
 186
 187   // Get the last instruction in the block.
 188   MachineInstr *LastInst = I;
 189
 190   // If there is only one terminator instruction, process it.
 191   if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
 192     if (LastInst->getOpcode() == PPC::B) {
 193       TBB = LastInst->getOperand(0).getMachineBasicBlock();
 194       return false;
 195     } else if (LastInst->getOpcode() == PPC::BCC) {
 196       // Block ends with fall-through condbranch.
 197       TBB = LastInst->getOperand(2).getMachineBasicBlock();
 198       Cond.push_back(LastInst->getOperand(0));
 199       Cond.push_back(LastInst->getOperand(1));
 200       return false;
 201     }
 202     // Otherwise, don't know what this is.
 203     return true;
 204   }
 205
 206   // Get the instruction before it if it's a terminator.
 207   MachineInstr *SecondLastInst = I;
 208
 209   // If there are three terminators, we don't know what sort of block this is.
 210   if (SecondLastInst && I != MBB.begin() &&
 211       isUnpredicatedTerminator(--I))
 212     return true;
 213
 214   // If the block ends with PPC::B and PPC:BCC, handle it.
 215   if (SecondLastInst->getOpcode() == PPC::BCC &&
 216       LastInst->getOpcode() == PPC::B) {
 217     TBB =  SecondLastInst->getOperand(2).getMachineBasicBlock();
 218     Cond.push_back(SecondLastInst->getOperand(0));
 219     Cond.push_back(SecondLastInst->getOperand(1));
 220     FBB = LastInst->getOperand(0).getMachineBasicBlock();
 221     return false;
 222   }
 223
 224   // If the block ends with two PPC:Bs, handle it.  The second one is not
 225   // executed, so remove it.
 226   if (SecondLastInst->getOpcode() == PPC::B &&
 227       LastInst->getOpcode() == PPC::B) {
 228     TBB = SecondLastInst->getOperand(0).getMachineBasicBlock();
 229     I = LastInst;
 230     I->eraseFromParent();
 231     return false;
 232   }
 233
 234   // Otherwise, can't handle this.
 235   return true;
 236 }
 237
 238 unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
 239   MachineBasicBlock::iterator I = MBB.end();
 240   if (I == MBB.begin()) return 0;
 241   --I;
 242   if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC)
 243     return 0;
 244
 245   // Remove the branch.
 246   I->eraseFromParent();
 247
 248   I = MBB.end();
 249
 250   if (I == MBB.begin()) return 1;
 251   --I;
 252   if (I->getOpcode() != PPC::BCC)
 253     return 1;
 254
 255   // Remove the branch.
 256   I->eraseFromParent();
 257   return 2;
 258 }
 259
 260 unsigned
 261 PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
 262                            MachineBasicBlock *FBB,
 263                            const std::vector<MachineOperand> &Cond) const {
 264   // Shouldn't be a fall through.
 265   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
 266   assert((Cond.size() == 2 || Cond.size() == 0) &&
 267          "PPC branch conditions have two components!");
 268
 269   // One-way branch.
 270   if (FBB == 0) {
 271     if (Cond.empty())   // Unconditional branch
 272       BuildMI(&MBB, get(PPC::B)).addMBB(TBB);
 273     else                // Conditional branch
 274       BuildMI(&MBB, get(PPC::BCC))
 275         .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
 276     return 1;
 277   }
 278
 279   // Two-way Conditional Branch.
 280   BuildMI(&MBB, get(PPC::BCC))
 281     .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
 282   BuildMI(&MBB, get(PPC::B)).addMBB(FBB);
 283   return 2;
 284 }
 285
 286 bool PPCInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
 287   if (MBB.empty()) return false;
 288
 289   switch (MBB.back().getOpcode()) {
 290   case PPC::BLR:   // Return.
 291   case PPC::B:     // Uncond branch.
 292   case PPC::BCTR:  // Indirect branch.
 293     return true;
 294   default: return false;
 295   }
 296 }
 297
 298 bool PPCInstrInfo::
 299 ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
 300   assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
 301   // Leave the CR# the same, but invert the condition.
 302   Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
 303   return false;
 304 }