lib/Target/AMDGPU/AMDGPU.h

   1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 /// \file
   9 //===----------------------------------------------------------------------===//
  10
  11 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
  12 #define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
  13
  14 #include "llvm/Target/TargetMachine.h"
  15
  16 namespace llvm {
  17
  18 class AMDGPUTargetMachine;
  19 class FunctionPass;
  20 class GCNTargetMachine;
  21 class ModulePass;
  22 class Pass;
  23 class Target;
  24 class TargetMachine;
  25 class TargetOptions;
  26 class PassRegistry;
  27 class Module;
  28
  29 // R600 Passes
  30 FunctionPass *createR600VectorRegMerger();
  31 FunctionPass *createR600ExpandSpecialInstrsPass();
  32 FunctionPass *createR600EmitClauseMarkers();
  33 FunctionPass *createR600ClauseMergePass();
  34 FunctionPass *createR600Packetizer();
  35 FunctionPass *createR600ControlFlowFinalizer();
  36 FunctionPass *createAMDGPUCFGStructurizerPass();
  37 FunctionPass *createR600ISelDag(TargetMachine *TM, CodeGenOpt::Level OptLevel);
  38
  39 // SI Passes
  40 FunctionPass *createSIAnnotateControlFlowPass();
  41 FunctionPass *createSIFoldOperandsPass();
  42 FunctionPass *createSIPeepholeSDWAPass();
  43 FunctionPass *createSILowerI1CopiesPass();
  44 FunctionPass *createSIShrinkInstructionsPass();
  45 FunctionPass *createSILoadStoreOptimizerPass();
  46 FunctionPass *createSIWholeQuadModePass();
  47 FunctionPass *createSIFixControlFlowLiveIntervalsPass();
  48 FunctionPass *createSIOptimizeExecMaskingPreRAPass();
  49 FunctionPass *createSIFixSGPRCopiesPass();
  50 FunctionPass *createSIMemoryLegalizerPass();
  51 FunctionPass *createSIDebuggerInsertNopsPass();
  52 FunctionPass *createSIInsertWaitcntsPass();
  53 FunctionPass *createSIFixWWMLivenessPass();
  54 FunctionPass *createSIFormMemoryClausesPass();
  55 FunctionPass *createAMDGPUSimplifyLibCallsPass(const TargetOptions &);
  56 FunctionPass *createAMDGPUUseNativeCallsPass();
  57 FunctionPass *createAMDGPUCodeGenPreparePass();
  58 FunctionPass *createAMDGPUMachineCFGStructurizerPass();
  59 FunctionPass *createAMDGPURewriteOutArgumentsPass();
  60
  61 void initializeAMDGPUDAGToDAGISelPass(PassRegistry&);
  62
  63 void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry&);
  64 extern char &AMDGPUMachineCFGStructurizerID;
  65
  66 void initializeAMDGPUAlwaysInlinePass(PassRegistry&);
  67
  68 Pass *createAMDGPUAnnotateKernelFeaturesPass();
  69 void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &);
  70 extern char &AMDGPUAnnotateKernelFeaturesID;
  71
  72 FunctionPass *createAMDGPUAtomicOptimizerPass();
  73 void initializeAMDGPUAtomicOptimizerPass(PassRegistry &);
  74 extern char &AMDGPUAtomicOptimizerID;
  75
  76 ModulePass *createAMDGPULowerIntrinsicsPass();
  77 void initializeAMDGPULowerIntrinsicsPass(PassRegistry &);
  78 extern char &AMDGPULowerIntrinsicsID;
  79
  80 FunctionPass *createAMDGPULowerKernelArgumentsPass();
  81 void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &);
  82 extern char &AMDGPULowerKernelArgumentsID;
  83
  84 ModulePass *createAMDGPULowerKernelAttributesPass();
  85 void initializeAMDGPULowerKernelAttributesPass(PassRegistry &);
  86 extern char &AMDGPULowerKernelAttributesID;
  87
  88 void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &);
  89 extern char &AMDGPURewriteOutArgumentsID;
  90
  91 void initializeR600ClauseMergePassPass(PassRegistry &);
  92 extern char &R600ClauseMergePassID;
  93
  94 void initializeR600ControlFlowFinalizerPass(PassRegistry &);
  95 extern char &R600ControlFlowFinalizerID;
  96
  97 void initializeR600ExpandSpecialInstrsPassPass(PassRegistry &);
  98 extern char &R600ExpandSpecialInstrsPassID;
  99
 100 void initializeR600VectorRegMergerPass(PassRegistry &);
 101 extern char &R600VectorRegMergerID;
 102
 103 void initializeR600PacketizerPass(PassRegistry &);
 104 extern char &R600PacketizerID;
 105
 106 void initializeSIFoldOperandsPass(PassRegistry &);
 107 extern char &SIFoldOperandsID;
 108
 109 void initializeSIPeepholeSDWAPass(PassRegistry &);
 110 extern char &SIPeepholeSDWAID;
 111
 112 void initializeSIShrinkInstructionsPass(PassRegistry&);
 113 extern char &SIShrinkInstructionsID;
 114
 115 void initializeSIFixSGPRCopiesPass(PassRegistry &);
 116 extern char &SIFixSGPRCopiesID;
 117
 118 void initializeSIFixVGPRCopiesPass(PassRegistry &);
 119 extern char &SIFixVGPRCopiesID;
 120
 121 void initializeSILowerI1CopiesPass(PassRegistry &);
 122 extern char &SILowerI1CopiesID;
 123
 124 void initializeSILoadStoreOptimizerPass(PassRegistry &);
 125 extern char &SILoadStoreOptimizerID;
 126
 127 void initializeSIWholeQuadModePass(PassRegistry &);
 128 extern char &SIWholeQuadModeID;
 129
 130 void initializeSILowerControlFlowPass(PassRegistry &);
 131 extern char &SILowerControlFlowID;
 132
 133 void initializeSIInsertSkipsPass(PassRegistry &);
 134 extern char &SIInsertSkipsPassID;
 135
 136 void initializeSIOptimizeExecMaskingPass(PassRegistry &);
 137 extern char &SIOptimizeExecMaskingID;
 138
 139 void initializeSIFixWWMLivenessPass(PassRegistry &);
 140 extern char &SIFixWWMLivenessID;
 141
 142 void initializeAMDGPUSimplifyLibCallsPass(PassRegistry &);
 143 extern char &AMDGPUSimplifyLibCallsID;
 144
 145 void initializeAMDGPUUseNativeCallsPass(PassRegistry &);
 146 extern char &AMDGPUUseNativeCallsID;
 147
 148 void initializeAMDGPUPerfHintAnalysisPass(PassRegistry &);
 149 extern char &AMDGPUPerfHintAnalysisID;
 150
 151 // Passes common to R600 and SI
 152 FunctionPass *createAMDGPUPromoteAlloca();
 153 void initializeAMDGPUPromoteAllocaPass(PassRegistry&);
 154 extern char &AMDGPUPromoteAllocaID;
 155
 156 Pass *createAMDGPUStructurizeCFGPass();
 157 FunctionPass *createAMDGPUISelDag(
 158   TargetMachine *TM = nullptr,
 159   CodeGenOpt::Level OptLevel = CodeGenOpt::Default);
 160 ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true);
 161 ModulePass *createR600OpenCLImageTypeLoweringPass();
 162 FunctionPass *createAMDGPUAnnotateUniformValues();
 163
 164 ModulePass* createAMDGPUUnifyMetadataPass();
 165 void initializeAMDGPUUnifyMetadataPass(PassRegistry&);
 166 extern char &AMDGPUUnifyMetadataID;
 167
 168 void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry&);
 169 extern char &SIOptimizeExecMaskingPreRAID;
 170
 171 void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry&);
 172 extern char &AMDGPUAnnotateUniformValuesPassID;
 173
 174 void initializeAMDGPUCodeGenPreparePass(PassRegistry&);
 175 extern char &AMDGPUCodeGenPrepareID;
 176
 177 void initializeSIAnnotateControlFlowPass(PassRegistry&);
 178 extern char &SIAnnotateControlFlowPassID;
 179
 180 void initializeSIMemoryLegalizerPass(PassRegistry&);
 181 extern char &SIMemoryLegalizerID;
 182
 183 void initializeSIDebuggerInsertNopsPass(PassRegistry&);
 184 extern char &SIDebuggerInsertNopsID;
 185
 186 void initializeSIInsertWaitcntsPass(PassRegistry&);
 187 extern char &SIInsertWaitcntsID;
 188
 189 void initializeSIFormMemoryClausesPass(PassRegistry&);
 190 extern char &SIFormMemoryClausesID;
 191
 192 void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry&);
 193 extern char &AMDGPUUnifyDivergentExitNodesID;
 194
 195 ImmutablePass *createAMDGPUAAWrapperPass();
 196 void initializeAMDGPUAAWrapperPassPass(PassRegistry&);
 197
 198 void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &);
 199
 200 Pass *createAMDGPUFunctionInliningPass();
 201 void initializeAMDGPUInlinerPass(PassRegistry&);
 202
 203 ModulePass *createAMDGPUOpenCLEnqueuedBlockLoweringPass();
 204 void initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(PassRegistry &);
 205 extern char &AMDGPUOpenCLEnqueuedBlockLoweringID;
 206
 207 Target &getTheAMDGPUTarget();
 208 Target &getTheGCNTarget();
 209
 210 namespace AMDGPU {
 211 enum TargetIndex {
 212   TI_CONSTDATA_START,
 213   TI_SCRATCH_RSRC_DWORD0,
 214   TI_SCRATCH_RSRC_DWORD1,
 215   TI_SCRATCH_RSRC_DWORD2,
 216   TI_SCRATCH_RSRC_DWORD3
 217 };
 218 }
 219
 220 } // End namespace llvm
 221
 222 /// OpenCL uses address spaces to differentiate between
 223 /// various memory regions on the hardware. On the CPU
 224 /// all of the address spaces point to the same memory,
 225 /// however on the GPU, each address space points to
 226 /// a separate piece of memory that is unique from other
 227 /// memory locations.
 228 namespace AMDGPUAS {
 229   enum : unsigned {
 230     // The maximum value for flat, generic, local, private, constant and region.
 231     MAX_AMDGPU_ADDRESS = 6,
 232
 233     FLAT_ADDRESS = 0,     ///< Address space for flat memory.
 234     GLOBAL_ADDRESS = 1,   ///< Address space for global memory (RAT0, VTX0).
 235     REGION_ADDRESS = 2,   ///< Address space for region memory.
 236
 237     CONSTANT_ADDRESS = 4, ///< Address space for constant memory (VTX2)
 238     LOCAL_ADDRESS = 3,    ///< Address space for local memory.
 239     PRIVATE_ADDRESS = 5,  ///< Address space for private memory.
 240
 241     CONSTANT_ADDRESS_32BIT = 6, ///< Address space for 32-bit constant memory
 242
 243     /// Address space for direct addressible parameter memory (CONST0)
 244     PARAM_D_ADDRESS = 6,
 245     /// Address space for indirect addressible parameter memory (VTX1)
 246     PARAM_I_ADDRESS = 7,
 247
 248     // Do not re-order the CONSTANT_BUFFER_* enums.  Several places depend on
 249     // this order to be able to dynamically index a constant buffer, for
 250     // example:
 251     //
 252     // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx
 253
 254     CONSTANT_BUFFER_0 = 8,
 255     CONSTANT_BUFFER_1 = 9,
 256     CONSTANT_BUFFER_2 = 10,
 257     CONSTANT_BUFFER_3 = 11,
 258     CONSTANT_BUFFER_4 = 12,
 259     CONSTANT_BUFFER_5 = 13,
 260     CONSTANT_BUFFER_6 = 14,
 261     CONSTANT_BUFFER_7 = 15,
 262     CONSTANT_BUFFER_8 = 16,
 263     CONSTANT_BUFFER_9 = 17,
 264     CONSTANT_BUFFER_10 = 18,
 265     CONSTANT_BUFFER_11 = 19,
 266     CONSTANT_BUFFER_12 = 20,
 267     CONSTANT_BUFFER_13 = 21,
 268     CONSTANT_BUFFER_14 = 22,
 269     CONSTANT_BUFFER_15 = 23,
 270
 271     // Some places use this if the address space can't be determined.
 272     UNKNOWN_ADDRESS_SPACE = ~0u,
 273   };
 274 }
 275
 276 #endif