[llvm-exegesis][NFC] Pass Instruction instead of bare Opcode
[llvm-core.git] / lib / Target / AMDGPU / R600FrameLowering.cpp
blob37787b3c5f7292cbc2a76cb94cb84e4256e4a7e9
1 //===----------------------- R600FrameLowering.cpp ------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //==-----------------------------------------------------------------------===//
10 #include "R600FrameLowering.h"
11 #include "AMDGPUSubtarget.h"
12 #include "R600RegisterInfo.h"
13 #include "llvm/CodeGen/MachineFrameInfo.h"
14 #include "llvm/CodeGen/MachineFunction.h"
15 #include "llvm/Support/MathExtras.h"
17 using namespace llvm;
19 R600FrameLowering::~R600FrameLowering() = default;
21 /// \returns The number of registers allocated for \p FI.
22 int R600FrameLowering::getFrameIndexReference(const MachineFunction &MF,
23 int FI,
24 unsigned &FrameReg) const {
25 const MachineFrameInfo &MFI = MF.getFrameInfo();
26 const R600RegisterInfo *RI
27 = MF.getSubtarget<R600Subtarget>().getRegisterInfo();
29 // Fill in FrameReg output argument.
30 FrameReg = RI->getFrameRegister(MF);
32 // Start the offset at 2 so we don't overwrite work group information.
33 // FIXME: We should only do this when the shader actually uses this
34 // information.
35 unsigned OffsetBytes = 2 * (getStackWidth(MF) * 4);
36 int UpperBound = FI == -1 ? MFI.getNumObjects() : FI;
38 for (int i = MFI.getObjectIndexBegin(); i < UpperBound; ++i) {
39 OffsetBytes = alignTo(OffsetBytes, MFI.getObjectAlignment(i));
40 OffsetBytes += MFI.getObjectSize(i);
41 // Each register holds 4 bytes, so we must always align the offset to at
42 // least 4 bytes, so that 2 frame objects won't share the same register.
43 OffsetBytes = alignTo(OffsetBytes, 4);
46 if (FI != -1)
47 OffsetBytes = alignTo(OffsetBytes, MFI.getObjectAlignment(FI));
49 return OffsetBytes / (getStackWidth(MF) * 4);