lib/Target/AMDGPU/SIISelLowering.h

   1 //===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 /// \file
  11 /// SI DAG Lowering interface definition
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #ifndef LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
  16 #define LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
  17
  18 #include "AMDGPUISelLowering.h"
  19 #include "AMDGPUArgumentUsageInfo.h"
  20 #include "SIInstrInfo.h"
  21
  22 namespace llvm {
  23
  24 class SITargetLowering final : public AMDGPUTargetLowering {
  25 private:
  26   const GCNSubtarget *Subtarget;
  27
  28 public:
  29   MVT getRegisterTypeForCallingConv(LLVMContext &Context,
  30                                     CallingConv::ID CC,
  31                                     EVT VT) const override;
  32   unsigned getNumRegistersForCallingConv(LLVMContext &Context,
  33                                          CallingConv::ID CC,
  34                                          EVT VT) const override;
  35
  36   unsigned getVectorTypeBreakdownForCallingConv(
  37     LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
  38     unsigned &NumIntermediates, MVT &RegisterVT) const override;
  39
  40 private:
  41   SDValue lowerKernArgParameterPtr(SelectionDAG &DAG, const SDLoc &SL,
  42                                    SDValue Chain, uint64_t Offset) const;
  43   SDValue getImplicitArgPtr(SelectionDAG &DAG, const SDLoc &SL) const;
  44   SDValue lowerKernargMemParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
  45                                    const SDLoc &SL, SDValue Chain,
  46                                    uint64_t Offset, unsigned Align, bool Signed,
  47                                    const ISD::InputArg *Arg = nullptr) const;
  48
  49   SDValue lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA,
  50                               const SDLoc &SL, SDValue Chain,
  51                               const ISD::InputArg &Arg) const;
  52   SDValue getPreloadedValue(SelectionDAG &DAG,
  53                             const SIMachineFunctionInfo &MFI,
  54                             EVT VT,
  55                             AMDGPUFunctionArgInfo::PreloadedValue) const;
  56
  57   SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
  58                              SelectionDAG &DAG) const override;
  59   SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op,
  60                                  MVT VT, unsigned Offset) const;
  61   SDValue lowerImage(SDValue Op, const AMDGPU::ImageDimIntrinsicInfo *Intr,
  62                      SelectionDAG &DAG) const;
  63
  64   SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
  65   SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
  66   SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
  67
  68   // The raw.tbuffer and struct.tbuffer intrinsics have two offset args: offset
  69   // (the offset that is included in bounds checking and swizzling, to be split
  70   // between the instruction's voffset and immoffset fields) and soffset (the
  71   // offset that is excluded from bounds checking and swizzling, to go in the
  72   // instruction's soffset field).  This function takes the first kind of
  73   // offset and figures out how to split it between voffset and immoffset.
  74   std::pair<SDValue, SDValue> splitBufferOffsets(SDValue Offset,
  75                                                  SelectionDAG &DAG) const;
  76
  77   SDValue widenLoad(LoadSDNode *Ld, DAGCombinerInfo &DCI) const;
  78   SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
  79   SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
  80   SDValue lowerFastUnsafeFDIV(SDValue Op, SelectionDAG &DAG) const;
  81   SDValue lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const;
  82   SDValue LowerFDIV16(SDValue Op, SelectionDAG &DAG) const;
  83   SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const;
  84   SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const;
  85   SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const;
  86   SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG, bool Signed) const;
  87   SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
  88   SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
  89   SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
  90   SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
  91
  92   SDValue adjustLoadValueType(unsigned Opcode, MemSDNode *M,
  93                               SelectionDAG &DAG, ArrayRef<SDValue> Ops,
  94                               bool IsIntrinsic = false) const;
  95
  96   SDValue handleD16VData(SDValue VData, SelectionDAG &DAG) const;
  97
  98   /// Converts \p Op, which must be of floating point type, to the
  99   /// floating point type \p VT, by either extending or truncating it.
 100   SDValue getFPExtOrFPTrunc(SelectionDAG &DAG,
 101                             SDValue Op,
 102                             const SDLoc &DL,
 103                             EVT VT) const;
 104
 105   SDValue convertArgType(
 106     SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Val,
 107     bool Signed, const ISD::InputArg *Arg = nullptr) const;
 108
 109   /// Custom lowering for ISD::FP_ROUND for MVT::f16.
 110   SDValue lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
 111
 112   SDValue getSegmentAperture(unsigned AS, const SDLoc &DL,
 113                              SelectionDAG &DAG) const;
 114
 115   SDValue lowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) const;
 116   SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
 117   SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
 118   SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
 119   SDValue lowerTRAP(SDValue Op, SelectionDAG &DAG) const;
 120   SDValue lowerDEBUGTRAP(SDValue Op, SelectionDAG &DAG) const;
 121
 122   SDNode *adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;
 123
 124   SDValue performUCharToFloatCombine(SDNode *N,
 125                                      DAGCombinerInfo &DCI) const;
 126   SDValue performSHLPtrCombine(SDNode *N,
 127                                unsigned AS,
 128                                EVT MemVT,
 129                                DAGCombinerInfo &DCI) const;
 130
 131   SDValue performMemSDNodeCombine(MemSDNode *N, DAGCombinerInfo &DCI) const;
 132
 133   SDValue splitBinaryBitConstantOp(DAGCombinerInfo &DCI, const SDLoc &SL,
 134                                    unsigned Opc, SDValue LHS,
 135                                    const ConstantSDNode *CRHS) const;
 136
 137   SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 138   SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 139   SDValue performXorCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 140   SDValue performZeroExtendCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 141   SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 142   SDValue getCanonicalConstantFP(SelectionDAG &DAG, const SDLoc &SL, EVT VT,
 143                                  const APFloat &C) const;
 144   SDValue performFCanonicalizeCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 145
 146   SDValue performFPMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
 147                                   SDValue Op0, SDValue Op1) const;
 148   SDValue performIntMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
 149                                    SDValue Op0, SDValue Op1, bool Signed) const;
 150   SDValue performMinMaxCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 151   SDValue performFMed3Combine(SDNode *N, DAGCombinerInfo &DCI) const;
 152   SDValue performCvtPkRTZCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 153   SDValue performExtractVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 154   SDValue performBuildVectorCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 155
 156   unsigned getFusedOpcode(const SelectionDAG &DAG,
 157                           const SDNode *N0, const SDNode *N1) const;
 158   SDValue performAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 159   SDValue performAddCarrySubCarryCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 160   SDValue performSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 161   SDValue performFAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 162   SDValue performFSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 163   SDValue performFMACombine(SDNode *N, DAGCombinerInfo &DCI) const;
 164   SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 165   SDValue performCvtF32UByteNCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 166   SDValue performClampCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 167   SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 168
 169   bool isLegalFlatAddressingMode(const AddrMode &AM) const;
 170   bool isLegalGlobalAddressingMode(const AddrMode &AM) const;
 171   bool isLegalMUBUFAddressingMode(const AddrMode &AM) const;
 172
 173   unsigned isCFIntrinsic(const SDNode *Intr) const;
 174
 175   void createDebuggerPrologueStackObjects(MachineFunction &MF) const;
 176
 177   /// \returns True if fixup needs to be emitted for given global value \p GV,
 178   /// false otherwise.
 179   bool shouldEmitFixup(const GlobalValue *GV) const;
 180
 181   /// \returns True if GOT relocation needs to be emitted for given global value
 182   /// \p GV, false otherwise.
 183   bool shouldEmitGOTReloc(const GlobalValue *GV) const;
 184
 185   /// \returns True if PC-relative relocation needs to be emitted for given
 186   /// global value \p GV, false otherwise.
 187   bool shouldEmitPCReloc(const GlobalValue *GV) const;
 188
 189   // Analyze a combined offset from an amdgcn_buffer_ intrinsic and store the
 190   // three offsets (voffset, soffset and instoffset) into the SDValue[3] array
 191   // pointed to by Offsets.
 192   void setBufferOffsets(SDValue CombinedOffset, SelectionDAG &DAG,
 193                         SDValue *Offsets) const;
 194
 195 public:
 196   SITargetLowering(const TargetMachine &tm, const GCNSubtarget &STI);
 197
 198   const GCNSubtarget *getSubtarget() const;
 199
 200   bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const override;
 201
 202   bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const override;
 203
 204   bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
 205                           MachineFunction &MF,
 206                           unsigned IntrinsicID) const override;
 207
 208   bool getAddrModeArguments(IntrinsicInst * /*I*/,
 209                             SmallVectorImpl<Value*> &/*Ops*/,
 210                             Type *&/*AccessTy*/) const override;
 211
 212   bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
 213                              unsigned AS,
 214                              Instruction *I = nullptr) const override;
 215
 216   bool canMergeStoresTo(unsigned AS, EVT MemVT,
 217                         const SelectionDAG &DAG) const override;
 218
 219   bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS,
 220                                       unsigned Align,
 221                                       bool *IsFast) const override;
 222
 223   EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
 224                           unsigned SrcAlign, bool IsMemset,
 225                           bool ZeroMemset,
 226                           bool MemcpyStrSrc,
 227                           MachineFunction &MF) const override;
 228
 229   bool isMemOpUniform(const SDNode *N) const;
 230   bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const;
 231   bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
 232   bool isCheapAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
 233
 234   TargetLoweringBase::LegalizeTypeAction
 235   getPreferredVectorAction(EVT VT) const override;
 236
 237   bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
 238                                         Type *Ty) const override;
 239
 240   bool isTypeDesirableForOp(unsigned Op, EVT VT) const override;
 241
 242   bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
 243
 244   bool supportSplitCSR(MachineFunction *MF) const override;
 245   void initializeSplitCSR(MachineBasicBlock *Entry) const override;
 246   void insertCopiesSplitCSR(
 247     MachineBasicBlock *Entry,
 248     const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
 249
 250   SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
 251                                bool isVarArg,
 252                                const SmallVectorImpl<ISD::InputArg> &Ins,
 253                                const SDLoc &DL, SelectionDAG &DAG,
 254                                SmallVectorImpl<SDValue> &InVals) const override;
 255
 256   bool CanLowerReturn(CallingConv::ID CallConv,
 257                       MachineFunction &MF, bool isVarArg,
 258                       const SmallVectorImpl<ISD::OutputArg> &Outs,
 259                       LLVMContext &Context) const override;
 260
 261   SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
 262                       const SmallVectorImpl<ISD::OutputArg> &Outs,
 263                       const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
 264                       SelectionDAG &DAG) const override;
 265
 266   void passSpecialInputs(
 267     CallLoweringInfo &CLI,
 268     CCState &CCInfo,
 269     const SIMachineFunctionInfo &Info,
 270     SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass,
 271     SmallVectorImpl<SDValue> &MemOpChains,
 272     SDValue Chain) const;
 273
 274   SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
 275                           CallingConv::ID CallConv, bool isVarArg,
 276                           const SmallVectorImpl<ISD::InputArg> &Ins,
 277                           const SDLoc &DL, SelectionDAG &DAG,
 278                           SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
 279                           SDValue ThisVal) const;
 280
 281   bool mayBeEmittedAsTailCall(const CallInst *) const override;
 282
 283   bool isEligibleForTailCallOptimization(
 284     SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
 285     const SmallVectorImpl<ISD::OutputArg> &Outs,
 286     const SmallVectorImpl<SDValue> &OutVals,
 287     const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
 288
 289   SDValue LowerCall(CallLoweringInfo &CLI,
 290                     SmallVectorImpl<SDValue> &InVals) const override;
 291
 292   unsigned getRegisterByName(const char* RegName, EVT VT,
 293                              SelectionDAG &DAG) const override;
 294
 295   MachineBasicBlock *splitKillBlock(MachineInstr &MI,
 296                                     MachineBasicBlock *BB) const;
 297
 298   MachineBasicBlock *
 299   EmitInstrWithCustomInserter(MachineInstr &MI,
 300                               MachineBasicBlock *BB) const override;
 301
 302   bool hasBitPreservingFPLogic(EVT VT) const override;
 303   bool enableAggressiveFMAFusion(EVT VT) const override;
 304   EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
 305                          EVT VT) const override;
 306   MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override;
 307   bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
 308   SDValue splitUnaryVectorOp(SDValue Op, SelectionDAG &DAG) const;
 309   SDValue splitBinaryVectorOp(SDValue Op, SelectionDAG &DAG) const;
 310   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
 311
 312   void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
 313                           SelectionDAG &DAG) const override;
 314
 315   SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
 316   SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
 317   void AdjustInstrPostInstrSelection(MachineInstr &MI,
 318                                      SDNode *Node) const override;
 319
 320   SDNode *legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const;
 321
 322   MachineSDNode *wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL,
 323                                 SDValue Ptr) const;
 324   MachineSDNode *buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr,
 325                            uint32_t RsrcDword1, uint64_t RsrcDword2And3) const;
 326   std::pair<unsigned, const TargetRegisterClass *>
 327   getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
 328                                StringRef Constraint, MVT VT) const override;
 329   ConstraintType getConstraintType(StringRef Constraint) const override;
 330   SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL,
 331                    SDValue V) const;
 332
 333   void finalizeLowering(MachineFunction &MF) const override;
 334
 335   void computeKnownBitsForFrameIndex(const SDValue Op,
 336                                      KnownBits &Known,
 337                                      const APInt &DemandedElts,
 338                                      const SelectionDAG &DAG,
 339                                      unsigned Depth = 0) const override;
 340
 341   bool isSDNodeSourceOfDivergence(const SDNode *N,
 342     FunctionLoweringInfo *FLI, LegacyDivergenceAnalysis *DA) const override;
 343
 344   bool isCanonicalized(SelectionDAG &DAG, SDValue Op,
 345                        unsigned MaxDepth = 5) const;
 346   bool denormalsEnabledForType(EVT VT) const;
 347 };
 348
 349 } // End namespace llvm
 350
 351 #endif