lib/Target/Mips/Mips16InstrInfo.h

   1 //===- Mips16InstrInfo.h - Mips16 Instruction Information -------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the Mips16 implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_LIB_TARGET_MIPS_MIPS16INSTRINFO_H
  15 #define LLVM_LIB_TARGET_MIPS_MIPS16INSTRINFO_H
  16
  17 #include "Mips16RegisterInfo.h"
  18 #include "MipsInstrInfo.h"
  19 #include "llvm/CodeGen/MachineBasicBlock.h"
  20 #include "llvm/Support/MathExtras.h"
  21 #include <cstdint>
  22
  23 namespace llvm {
  24
  25 class MCInstrDesc;
  26 class MipsSubtarget;
  27
  28 class Mips16InstrInfo : public MipsInstrInfo {
  29   const Mips16RegisterInfo RI;
  30
  31 public:
  32   explicit Mips16InstrInfo(const MipsSubtarget &STI);
  33
  34   const MipsRegisterInfo &getRegisterInfo() const override;
  35
  36   /// isLoadFromStackSlot - If the specified machine instruction is a direct
  37   /// load from a stack slot, return the virtual or physical register number of
  38   /// the destination along with the FrameIndex of the loaded stack slot.  If
  39   /// not, return 0.  This predicate must return 0 if the instruction has
  40   /// any side effects other than loading from the stack slot.
  41   unsigned isLoadFromStackSlot(const MachineInstr &MI,
  42                                int &FrameIndex) const override;
  43
  44   /// isStoreToStackSlot - If the specified machine instruction is a direct
  45   /// store to a stack slot, return the virtual or physical register number of
  46   /// the source reg along with the FrameIndex of the loaded stack slot.  If
  47   /// not, return 0.  This predicate must return 0 if the instruction has
  48   /// any side effects other than storing to the stack slot.
  49   unsigned isStoreToStackSlot(const MachineInstr &MI,
  50                               int &FrameIndex) const override;
  51
  52   void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
  53                    const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
  54                    bool KillSrc) const override;
  55
  56   void storeRegToStack(MachineBasicBlock &MBB,
  57                        MachineBasicBlock::iterator MBBI,
  58                        unsigned SrcReg, bool isKill, int FrameIndex,
  59                        const TargetRegisterClass *RC,
  60                        const TargetRegisterInfo *TRI,
  61                        int64_t Offset) const override;
  62
  63   void loadRegFromStack(MachineBasicBlock &MBB,
  64                         MachineBasicBlock::iterator MBBI,
  65                         unsigned DestReg, int FrameIndex,
  66                         const TargetRegisterClass *RC,
  67                         const TargetRegisterInfo *TRI,
  68                         int64_t Offset) const override;
  69
  70   bool expandPostRAPseudo(MachineInstr &MI) const override;
  71
  72   unsigned getOppositeBranchOpc(unsigned Opc) const override;
  73
  74   // Adjust SP by FrameSize bytes. Save RA, S0, S1
  75   void makeFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB,
  76                  MachineBasicBlock::iterator I) const;
  77
  78   // Adjust SP by FrameSize bytes. Restore RA, S0, S1
  79   void restoreFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB,
  80                       MachineBasicBlock::iterator I) const;
  81
  82   /// Adjust SP by Amount bytes.
  83   void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
  84                       MachineBasicBlock::iterator I) const override;
  85
  86   /// Emit a series of instructions to load an immediate.
  87   // This is to adjust some FrameReg. We return the new register to be used
  88   // in place of FrameReg and the adjusted immediate field (&NewImm)
  89   unsigned loadImmediate(unsigned FrameReg, int64_t Imm, MachineBasicBlock &MBB,
  90                          MachineBasicBlock::iterator II, const DebugLoc &DL,
  91                          unsigned &NewImm) const;
  92
  93   static bool validImmediate(unsigned Opcode, unsigned Reg, int64_t Amount);
  94
  95   static bool validSpImm8(int offset) {
  96     return ((offset & 7) == 0) && isInt<11>(offset);
  97   }
  98
  99   // build the proper one based on the Imm field
 100
 101   const MCInstrDesc& AddiuSpImm(int64_t Imm) const;
 102
 103   void BuildAddiuSpImm
 104     (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const;
 105
 106 protected:
 107   /// If the specific machine instruction is a instruction that moves/copies
 108   /// value from one register to another register return true along with
 109   /// @Source machine operand and @Destination machine operand.
 110   bool isCopyInstrImpl(const MachineInstr &MI, const MachineOperand *&Source,
 111                        const MachineOperand *&Destination) const override;
 112
 113 private:
 114   unsigned getAnalyzableBrOpc(unsigned Opc) const override;
 115
 116   void ExpandRetRA16(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
 117                    unsigned Opc) const;
 118
 119   // Adjust SP by Amount bytes where bytes can be up to 32bit number.
 120   void adjustStackPtrBig(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
 121                          MachineBasicBlock::iterator I,
 122                          unsigned Reg1, unsigned Reg2) const;
 123
 124   // Adjust SP by Amount bytes where bytes can be up to 32bit number.
 125   void adjustStackPtrBigUnrestricted(unsigned SP, int64_t Amount,
 126                                      MachineBasicBlock &MBB,
 127                                      MachineBasicBlock::iterator I) const;
 128 };
 129
 130 } // end namespace llvm
 131
 132 #endif // LLVM_LIB_TARGET_MIPS_MIPS16INSTRINFO_H