lib/Target/X86/X86PfmCounters.td

   1 //===-- X86PfmCounters.td - X86 Hardware Counters ----------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This describes the available hardware counters for various subtargets.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 let SchedModel = SandyBridgeModel in {
  15 def SBCycleCounter : PfmCycleCounter<"unhalted_core_cycles">;
  16 def SBPort0Counter : PfmIssueCounter<SBPort0, ["uops_dispatched_port:port_0"]>;
  17 def SBPort1Counter : PfmIssueCounter<SBPort1, ["uops_dispatched_port:port_1"]>;
  18 def SBPort23Counter : PfmIssueCounter<SBPort23,
  19                                       ["uops_dispatched_port:port_2",
  20                                        "uops_dispatched_port:port_3"]>;
  21 def SBPort4Counter : PfmIssueCounter<SBPort4, ["uops_dispatched_port:port_4"]>;
  22 def SBPort5Counter : PfmIssueCounter<SBPort5, ["uops_dispatched_port:port_5"]>;
  23 def SBUopsCounter  : PfmUopsCounter<"uops_issued:any">;
  24 }
  25
  26 let SchedModel = HaswellModel in {
  27 def HWCycleCounter : PfmCycleCounter<"unhalted_core_cycles">;
  28 def HWPort0Counter : PfmIssueCounter<HWPort0, ["uops_dispatched_port:port_0"]>;
  29 def HWPort1Counter : PfmIssueCounter<HWPort1, ["uops_dispatched_port:port_1"]>;
  30 def HWPort2Counter : PfmIssueCounter<HWPort2, ["uops_dispatched_port:port_2"]>;
  31 def HWPort3Counter : PfmIssueCounter<HWPort3, ["uops_dispatched_port:port_3"]>;
  32 def HWPort4Counter : PfmIssueCounter<HWPort4, ["uops_dispatched_port:port_4"]>;
  33 def HWPort5Counter : PfmIssueCounter<HWPort5, ["uops_dispatched_port:port_5"]>;
  34 def HWPort6Counter : PfmIssueCounter<HWPort6, ["uops_dispatched_port:port_6"]>;
  35 def HWPort7Counter : PfmIssueCounter<HWPort7, ["uops_dispatched_port:port_7"]>;
  36 def HWUopsCounter  : PfmUopsCounter<"uops_issued:any">;
  37 }
  38
  39 let SchedModel = BroadwellModel in {
  40 def BWCycleCounter : PfmCycleCounter<"unhalted_core_cycles">;
  41 def BWPort0Counter : PfmIssueCounter<BWPort0, ["uops_executed_port:port_0"]>;
  42 def BWPort1Counter : PfmIssueCounter<BWPort1, ["uops_executed_port:port_1"]>;
  43 def BWPort2Counter : PfmIssueCounter<BWPort2, ["uops_executed_port:port_2"]>;
  44 def BWPort3Counter : PfmIssueCounter<BWPort3, ["uops_executed_port:port_3"]>;
  45 def BWPort4Counter : PfmIssueCounter<BWPort4, ["uops_executed_port:port_4"]>;
  46 def BWPort5Counter : PfmIssueCounter<BWPort5, ["uops_executed_port:port_5"]>;
  47 def BWPort6Counter : PfmIssueCounter<BWPort6, ["uops_executed_port:port_6"]>;
  48 def BWPort7Counter : PfmIssueCounter<BWPort7, ["uops_executed_port:port_7"]>;
  49 def BWUopsCounter  : PfmUopsCounter<"uops_issued:any">;
  50 }
  51
  52 let SchedModel = SkylakeClientModel in {
  53 def SKLCycleCounter : PfmCycleCounter<"unhalted_core_cycles">;
  54 def SKLPort0Counter : PfmIssueCounter<SKLPort0, ["uops_dispatched_port:port_0"]>;
  55 def SKLPort1Counter : PfmIssueCounter<SKLPort1, ["uops_dispatched_port:port_1"]>;
  56 def SKLPort2Counter : PfmIssueCounter<SKLPort2, ["uops_dispatched_port:port_2"]>;
  57 def SKLPort3Counter : PfmIssueCounter<SKLPort3, ["uops_dispatched_port:port_3"]>;
  58 def SKLPort4Counter : PfmIssueCounter<SKLPort4, ["uops_dispatched_port:port_4"]>;
  59 def SKLPort5Counter : PfmIssueCounter<SKLPort5, ["uops_dispatched_port:port_5"]>;
  60 def SKLPort6Counter : PfmIssueCounter<SKLPort6, ["uops_dispatched_port:port_6"]>;
  61 def SKLPort7Counter : PfmIssueCounter<SKLPort7, ["uops_dispatched_port:port_7"]>;
  62 def SKLUopsCounter  : PfmUopsCounter<"uops_issued:any">;
  63 }
  64
  65 let SchedModel = SkylakeServerModel in {
  66 def SKXCycleCounter : PfmCycleCounter<"unhalted_core_cycles">;
  67 def SKXPort0Counter : PfmIssueCounter<SKXPort0, ["uops_dispatched_port:port_0"]>;
  68 def SKXPort1Counter : PfmIssueCounter<SKXPort1, ["uops_dispatched_port:port_1"]>;
  69 def SKXPort2Counter : PfmIssueCounter<SKXPort2, ["uops_dispatched_port:port_2"]>;
  70 def SKXPort3Counter : PfmIssueCounter<SKXPort3, ["uops_dispatched_port:port_3"]>;
  71 def SKXPort4Counter : PfmIssueCounter<SKXPort4, ["uops_dispatched_port:port_4"]>;
  72 def SKXPort5Counter : PfmIssueCounter<SKXPort5, ["uops_dispatched_port:port_5"]>;
  73 def SKXPort6Counter : PfmIssueCounter<SKXPort6, ["uops_dispatched_port:port_6"]>;
  74 def SKXPort7Counter : PfmIssueCounter<SKXPort7, ["uops_dispatched_port:port_7"]>;
  75 def SKXUopsCounter  : PfmUopsCounter<"uops_issued:any">;
  76 }
  77
  78 let SchedModel = BtVer2Model in {
  79 def JCycleCounter : PfmCycleCounter<"cpu_clk_unhalted">;
  80 def JUopsCounter  : PfmUopsCounter<"retired_uops">;
  81 def JFPU0Counter  : PfmIssueCounter<JFPU0, ["dispatched_fpu:pipe0"]>;
  82 def JFPU1Counter  : PfmIssueCounter<JFPU1, ["dispatched_fpu:pipe1"]>;
  83 }