lib/Target/X86/X86TargetMachine.cpp

   1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the X86 specific subclass of TargetMachine.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "X86TargetMachine.h"
  15 #include "MCTargetDesc/X86MCTargetDesc.h"
  16 #include "X86.h"
  17 #include "X86CallLowering.h"
  18 #include "X86LegalizerInfo.h"
  19 #include "X86MacroFusion.h"
  20 #include "X86Subtarget.h"
  21 #include "X86TargetObjectFile.h"
  22 #include "X86TargetTransformInfo.h"
  23 #include "llvm/ADT/Optional.h"
  24 #include "llvm/ADT/STLExtras.h"
  25 #include "llvm/ADT/SmallString.h"
  26 #include "llvm/ADT/StringRef.h"
  27 #include "llvm/ADT/Triple.h"
  28 #include "llvm/Analysis/TargetTransformInfo.h"
  29 #include "llvm/CodeGen/ExecutionDomainFix.h"
  30 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
  31 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
  32 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
  33 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
  34 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
  35 #include "llvm/CodeGen/MachineScheduler.h"
  36 #include "llvm/CodeGen/Passes.h"
  37 #include "llvm/CodeGen/TargetPassConfig.h"
  38 #include "llvm/IR/Attributes.h"
  39 #include "llvm/IR/DataLayout.h"
  40 #include "llvm/IR/Function.h"
  41 #include "llvm/Pass.h"
  42 #include "llvm/Support/CodeGen.h"
  43 #include "llvm/Support/CommandLine.h"
  44 #include "llvm/Support/ErrorHandling.h"
  45 #include "llvm/Support/TargetRegistry.h"
  46 #include "llvm/Target/TargetLoweringObjectFile.h"
  47 #include "llvm/Target/TargetOptions.h"
  48 #include <memory>
  49 #include <string>
  50
  51 using namespace llvm;
  52
  53 static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
  54                                cl::desc("Enable the machine combiner pass"),
  55                                cl::init(true), cl::Hidden);
  56
  57 static cl::opt<bool> EnableCondBrFoldingPass("x86-condbr-folding",
  58                                cl::desc("Enable the conditional branch "
  59                                         "folding pass"),
  60                                cl::init(true), cl::Hidden);
  61
  62 namespace llvm {
  63
  64 void initializeWinEHStatePassPass(PassRegistry &);
  65 void initializeFixupLEAPassPass(PassRegistry &);
  66 void initializeShadowCallStackPass(PassRegistry &);
  67 void initializeX86CallFrameOptimizationPass(PassRegistry &);
  68 void initializeX86CmovConverterPassPass(PassRegistry &);
  69 void initializeX86ExecutionDomainFixPass(PassRegistry &);
  70 void initializeX86DomainReassignmentPass(PassRegistry &);
  71 void initializeX86AvoidSFBPassPass(PassRegistry &);
  72 void initializeX86SpeculativeLoadHardeningPassPass(PassRegistry &);
  73 void initializeX86FlagsCopyLoweringPassPass(PassRegistry &);
  74
  75 } // end namespace llvm
  76
  77 extern "C" void LLVMInitializeX86Target() {
  78   // Register the target.
  79   RegisterTargetMachine<X86TargetMachine> X(getTheX86_32Target());
  80   RegisterTargetMachine<X86TargetMachine> Y(getTheX86_64Target());
  81
  82   PassRegistry &PR = *PassRegistry::getPassRegistry();
  83   initializeGlobalISel(PR);
  84   initializeWinEHStatePassPass(PR);
  85   initializeFixupBWInstPassPass(PR);
  86   initializeEvexToVexInstPassPass(PR);
  87   initializeFixupLEAPassPass(PR);
  88   initializeShadowCallStackPass(PR);
  89   initializeX86CallFrameOptimizationPass(PR);
  90   initializeX86CmovConverterPassPass(PR);
  91   initializeX86ExecutionDomainFixPass(PR);
  92   initializeX86DomainReassignmentPass(PR);
  93   initializeX86AvoidSFBPassPass(PR);
  94   initializeX86SpeculativeLoadHardeningPassPass(PR);
  95   initializeX86FlagsCopyLoweringPassPass(PR);
  96 }
  97
  98 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
  99   if (TT.isOSBinFormatMachO()) {
 100     if (TT.getArch() == Triple::x86_64)
 101       return llvm::make_unique<X86_64MachoTargetObjectFile>();
 102     return llvm::make_unique<TargetLoweringObjectFileMachO>();
 103   }
 104
 105   if (TT.isOSFreeBSD())
 106     return llvm::make_unique<X86FreeBSDTargetObjectFile>();
 107   if (TT.isOSLinux() || TT.isOSNaCl() || TT.isOSIAMCU())
 108     return llvm::make_unique<X86LinuxNaClTargetObjectFile>();
 109   if (TT.isOSSolaris())
 110     return llvm::make_unique<X86SolarisTargetObjectFile>();
 111   if (TT.isOSFuchsia())
 112     return llvm::make_unique<X86FuchsiaTargetObjectFile>();
 113   if (TT.isOSBinFormatELF())
 114     return llvm::make_unique<X86ELFTargetObjectFile>();
 115   if (TT.isOSBinFormatCOFF())
 116     return llvm::make_unique<TargetLoweringObjectFileCOFF>();
 117   llvm_unreachable("unknown subtarget type");
 118 }
 119
 120 static std::string computeDataLayout(const Triple &TT) {
 121   // X86 is little endian
 122   std::string Ret = "e";
 123
 124   Ret += DataLayout::getManglingComponent(TT);
 125   // X86 and x32 have 32 bit pointers.
 126   if ((TT.isArch64Bit() &&
 127        (TT.getEnvironment() == Triple::GNUX32 || TT.isOSNaCl())) ||
 128       !TT.isArch64Bit())
 129     Ret += "-p:32:32";
 130
 131   // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
 132   if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
 133     Ret += "-i64:64";
 134   else if (TT.isOSIAMCU())
 135     Ret += "-i64:32-f64:32";
 136   else
 137     Ret += "-f64:32:64";
 138
 139   // Some ABIs align long double to 128 bits, others to 32.
 140   if (TT.isOSNaCl() || TT.isOSIAMCU())
 141     ; // No f80
 142   else if (TT.isArch64Bit() || TT.isOSDarwin())
 143     Ret += "-f80:128";
 144   else
 145     Ret += "-f80:32";
 146
 147   if (TT.isOSIAMCU())
 148     Ret += "-f128:32";
 149
 150   // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
 151   if (TT.isArch64Bit())
 152     Ret += "-n8:16:32:64";
 153   else
 154     Ret += "-n8:16:32";
 155
 156   // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
 157   if ((!TT.isArch64Bit() && TT.isOSWindows()) || TT.isOSIAMCU())
 158     Ret += "-a:0:32-S32";
 159   else
 160     Ret += "-S128";
 161
 162   return Ret;
 163 }
 164
 165 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
 166                                            bool JIT,
 167                                            Optional<Reloc::Model> RM) {
 168   bool is64Bit = TT.getArch() == Triple::x86_64;
 169   if (!RM.hasValue()) {
 170     // JIT codegen should use static relocations by default, since it's
 171     // typically executed in process and not relocatable.
 172     if (JIT)
 173       return Reloc::Static;
 174
 175     // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
 176     // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
 177     // use static relocation model by default.
 178     if (TT.isOSDarwin()) {
 179       if (is64Bit)
 180         return Reloc::PIC_;
 181       return Reloc::DynamicNoPIC;
 182     }
 183     if (TT.isOSWindows() && is64Bit)
 184       return Reloc::PIC_;
 185     return Reloc::Static;
 186   }
 187
 188   // ELF and X86-64 don't have a distinct DynamicNoPIC model.  DynamicNoPIC
 189   // is defined as a model for code which may be used in static or dynamic
 190   // executables but not necessarily a shared library. On X86-32 we just
 191   // compile in -static mode, in x86-64 we use PIC.
 192   if (*RM == Reloc::DynamicNoPIC) {
 193     if (is64Bit)
 194       return Reloc::PIC_;
 195     if (!TT.isOSDarwin())
 196       return Reloc::Static;
 197   }
 198
 199   // If we are on Darwin, disallow static relocation model in X86-64 mode, since
 200   // the Mach-O file format doesn't support it.
 201   if (*RM == Reloc::Static && TT.isOSDarwin() && is64Bit)
 202     return Reloc::PIC_;
 203
 204   return *RM;
 205 }
 206
 207 static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM,
 208                                               bool JIT, bool Is64Bit) {
 209   if (CM)
 210     return *CM;
 211   if (JIT)
 212     return Is64Bit ? CodeModel::Large : CodeModel::Small;
 213   return CodeModel::Small;
 214 }
 215
 216 /// Create an X86 target.
 217 ///
 218 X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT,
 219                                    StringRef CPU, StringRef FS,
 220                                    const TargetOptions &Options,
 221                                    Optional<Reloc::Model> RM,
 222                                    Optional<CodeModel::Model> CM,
 223                                    CodeGenOpt::Level OL, bool JIT)
 224     : LLVMTargetMachine(
 225           T, computeDataLayout(TT), TT, CPU, FS, Options,
 226           getEffectiveRelocModel(TT, JIT, RM),
 227           getEffectiveCodeModel(CM, JIT, TT.getArch() == Triple::x86_64), OL),
 228       TLOF(createTLOF(getTargetTriple())) {
 229   // Windows stack unwinder gets confused when execution flow "falls through"
 230   // after a call to 'noreturn' function.
 231   // To prevent that, we emit a trap for 'unreachable' IR instructions.
 232   // (which on X86, happens to be the 'ud2' instruction)
 233   // On PS4, the "return address" of a 'noreturn' call must still be within
 234   // the calling function, and TrapUnreachable is an easy way to get that.
 235   // The check here for 64-bit windows is a bit icky, but as we're unlikely
 236   // to ever want to mix 32 and 64-bit windows code in a single module
 237   // this should be fine.
 238   if ((TT.isOSWindows() && TT.getArch() == Triple::x86_64) || TT.isPS4() ||
 239       TT.isOSBinFormatMachO()) {
 240     this->Options.TrapUnreachable = true;
 241     this->Options.NoTrapAfterNoreturn = TT.isOSBinFormatMachO();
 242   }
 243
 244   // Outlining is available for x86-64.
 245   if (TT.getArch() == Triple::x86_64)
 246     setMachineOutliner(true);
 247
 248   initAsmInfo();
 249 }
 250
 251 X86TargetMachine::~X86TargetMachine() = default;
 252
 253 const X86Subtarget *
 254 X86TargetMachine::getSubtargetImpl(const Function &F) const {
 255   Attribute CPUAttr = F.getFnAttribute("target-cpu");
 256   Attribute FSAttr = F.getFnAttribute("target-features");
 257
 258   StringRef CPU = !CPUAttr.hasAttribute(Attribute::None)
 259                       ? CPUAttr.getValueAsString()
 260                       : (StringRef)TargetCPU;
 261   StringRef FS = !FSAttr.hasAttribute(Attribute::None)
 262                      ? FSAttr.getValueAsString()
 263                      : (StringRef)TargetFS;
 264
 265   SmallString<512> Key;
 266   Key.reserve(CPU.size() + FS.size());
 267   Key += CPU;
 268   Key += FS;
 269
 270   // FIXME: This is related to the code below to reset the target options,
 271   // we need to know whether or not the soft float flag is set on the
 272   // function before we can generate a subtarget. We also need to use
 273   // it as a key for the subtarget since that can be the only difference
 274   // between two functions.
 275   bool SoftFloat =
 276       F.getFnAttribute("use-soft-float").getValueAsString() == "true";
 277   // If the soft float attribute is set on the function turn on the soft float
 278   // subtarget feature.
 279   if (SoftFloat)
 280     Key += FS.empty() ? "+soft-float" : ",+soft-float";
 281
 282   // Keep track of the key width after all features are added so we can extract
 283   // the feature string out later.
 284   unsigned CPUFSWidth = Key.size();
 285
 286   // Extract prefer-vector-width attribute.
 287   unsigned PreferVectorWidthOverride = 0;
 288   if (F.hasFnAttribute("prefer-vector-width")) {
 289     StringRef Val = F.getFnAttribute("prefer-vector-width").getValueAsString();
 290     unsigned Width;
 291     if (!Val.getAsInteger(0, Width)) {
 292       Key += ",prefer-vector-width=";
 293       Key += Val;
 294       PreferVectorWidthOverride = Width;
 295     }
 296   }
 297
 298   // Extract required-vector-width attribute.
 299   unsigned RequiredVectorWidth = UINT32_MAX;
 300   if (F.hasFnAttribute("required-vector-width")) {
 301     StringRef Val = F.getFnAttribute("required-vector-width").getValueAsString();
 302     unsigned Width;
 303     if (!Val.getAsInteger(0, Width)) {
 304       Key += ",required-vector-width=";
 305       Key += Val;
 306       RequiredVectorWidth = Width;
 307     }
 308   }
 309
 310   // Extracted here so that we make sure there is backing for the StringRef. If
 311   // we assigned earlier, its possible the SmallString reallocated leaving a
 312   // dangling StringRef.
 313   FS = Key.slice(CPU.size(), CPUFSWidth);
 314
 315   auto &I = SubtargetMap[Key];
 316   if (!I) {
 317     // This needs to be done before we create a new subtarget since any
 318     // creation will depend on the TM and the code generation flags on the
 319     // function that reside in TargetOptions.
 320     resetTargetOptions(F);
 321     I = llvm::make_unique<X86Subtarget>(TargetTriple, CPU, FS, *this,
 322                                         Options.StackAlignmentOverride,
 323                                         PreferVectorWidthOverride,
 324                                         RequiredVectorWidth);
 325   }
 326   return I.get();
 327 }
 328
 329 //===----------------------------------------------------------------------===//
 330 // Command line options for x86
 331 //===----------------------------------------------------------------------===//
 332 static cl::opt<bool>
 333 UseVZeroUpper("x86-use-vzeroupper", cl::Hidden,
 334   cl::desc("Minimize AVX to SSE transition penalty"),
 335   cl::init(true));
 336
 337 //===----------------------------------------------------------------------===//
 338 // X86 TTI query.
 339 //===----------------------------------------------------------------------===//
 340
 341 TargetTransformInfo
 342 X86TargetMachine::getTargetTransformInfo(const Function &F) {
 343   return TargetTransformInfo(X86TTIImpl(this, F));
 344 }
 345
 346 //===----------------------------------------------------------------------===//
 347 // Pass Pipeline Configuration
 348 //===----------------------------------------------------------------------===//
 349
 350 namespace {
 351
 352 /// X86 Code Generator Pass Configuration Options.
 353 class X86PassConfig : public TargetPassConfig {
 354 public:
 355   X86PassConfig(X86TargetMachine &TM, PassManagerBase &PM)
 356     : TargetPassConfig(TM, PM) {}
 357
 358   X86TargetMachine &getX86TargetMachine() const {
 359     return getTM<X86TargetMachine>();
 360   }
 361
 362   ScheduleDAGInstrs *
 363   createMachineScheduler(MachineSchedContext *C) const override {
 364     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
 365     DAG->addMutation(createX86MacroFusionDAGMutation());
 366     return DAG;
 367   }
 368
 369   void addIRPasses() override;
 370   bool addInstSelector() override;
 371   bool addIRTranslator() override;
 372   bool addLegalizeMachineIR() override;
 373   bool addRegBankSelect() override;
 374   bool addGlobalInstructionSelect() override;
 375   bool addILPOpts() override;
 376   bool addPreISel() override;
 377   void addMachineSSAOptimization() override;
 378   void addPreRegAlloc() override;
 379   void addPostRegAlloc() override;
 380   void addPreEmitPass() override;
 381   void addPreEmitPass2() override;
 382   void addPreSched2() override;
 383 };
 384
 385 class X86ExecutionDomainFix : public ExecutionDomainFix {
 386 public:
 387   static char ID;
 388   X86ExecutionDomainFix() : ExecutionDomainFix(ID, X86::VR128XRegClass) {}
 389   StringRef getPassName() const override {
 390     return "X86 Execution Dependency Fix";
 391   }
 392 };
 393 char X86ExecutionDomainFix::ID;
 394
 395 } // end anonymous namespace
 396
 397 INITIALIZE_PASS_BEGIN(X86ExecutionDomainFix, "x86-execution-domain-fix",
 398   "X86 Execution Domain Fix", false, false)
 399 INITIALIZE_PASS_DEPENDENCY(ReachingDefAnalysis)
 400 INITIALIZE_PASS_END(X86ExecutionDomainFix, "x86-execution-domain-fix",
 401   "X86 Execution Domain Fix", false, false)
 402
 403 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
 404   return new X86PassConfig(*this, PM);
 405 }
 406
 407 void X86PassConfig::addIRPasses() {
 408   addPass(createAtomicExpandPass());
 409
 410   TargetPassConfig::addIRPasses();
 411
 412   if (TM->getOptLevel() != CodeGenOpt::None)
 413     addPass(createInterleavedAccessPass());
 414
 415   // Add passes that handle indirect branch removal and insertion of a retpoline
 416   // thunk. These will be a no-op unless a function subtarget has the retpoline
 417   // feature enabled.
 418   addPass(createIndirectBrExpandPass());
 419 }
 420
 421 bool X86PassConfig::addInstSelector() {
 422   // Install an instruction selector.
 423   addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
 424
 425   // For ELF, cleanup any local-dynamic TLS accesses.
 426   if (TM->getTargetTriple().isOSBinFormatELF() &&
 427       getOptLevel() != CodeGenOpt::None)
 428     addPass(createCleanupLocalDynamicTLSPass());
 429
 430   addPass(createX86GlobalBaseRegPass());
 431   return false;
 432 }
 433
 434 bool X86PassConfig::addIRTranslator() {
 435   addPass(new IRTranslator());
 436   return false;
 437 }
 438
 439 bool X86PassConfig::addLegalizeMachineIR() {
 440   addPass(new Legalizer());
 441   return false;
 442 }
 443
 444 bool X86PassConfig::addRegBankSelect() {
 445   addPass(new RegBankSelect());
 446   return false;
 447 }
 448
 449 bool X86PassConfig::addGlobalInstructionSelect() {
 450   addPass(new InstructionSelect());
 451   return false;
 452 }
 453
 454 bool X86PassConfig::addILPOpts() {
 455   if (EnableCondBrFoldingPass)
 456     addPass(createX86CondBrFolding());
 457   addPass(&EarlyIfConverterID);
 458   if (EnableMachineCombinerPass)
 459     addPass(&MachineCombinerID);
 460   addPass(createX86CmovConverterPass());
 461   return true;
 462 }
 463
 464 bool X86PassConfig::addPreISel() {
 465   // Only add this pass for 32-bit x86 Windows.
 466   const Triple &TT = TM->getTargetTriple();
 467   if (TT.isOSWindows() && TT.getArch() == Triple::x86)
 468     addPass(createX86WinEHStatePass());
 469   return true;
 470 }
 471
 472 void X86PassConfig::addPreRegAlloc() {
 473   if (getOptLevel() != CodeGenOpt::None) {
 474     addPass(&LiveRangeShrinkID);
 475     addPass(createX86FixupSetCC());
 476     addPass(createX86OptimizeLEAs());
 477     addPass(createX86CallFrameOptimization());
 478     addPass(createX86AvoidStoreForwardingBlocks());
 479   }
 480
 481   addPass(createX86SpeculativeLoadHardeningPass());
 482   addPass(createX86FlagsCopyLoweringPass());
 483   addPass(createX86WinAllocaExpander());
 484 }
 485 void X86PassConfig::addMachineSSAOptimization() {
 486   addPass(createX86DomainReassignmentPass());
 487   TargetPassConfig::addMachineSSAOptimization();
 488 }
 489
 490 void X86PassConfig::addPostRegAlloc() {
 491   addPass(createX86FloatingPointStackifierPass());
 492 }
 493
 494 void X86PassConfig::addPreSched2() { addPass(createX86ExpandPseudoPass()); }
 495
 496 void X86PassConfig::addPreEmitPass() {
 497   if (getOptLevel() != CodeGenOpt::None) {
 498     addPass(new X86ExecutionDomainFix());
 499     addPass(createBreakFalseDeps());
 500   }
 501
 502   addPass(createShadowCallStackPass());
 503   addPass(createX86IndirectBranchTrackingPass());
 504
 505   if (UseVZeroUpper)
 506     addPass(createX86IssueVZeroUpperPass());
 507
 508   if (getOptLevel() != CodeGenOpt::None) {
 509     addPass(createX86FixupBWInsts());
 510     addPass(createX86PadShortFunctions());
 511     addPass(createX86FixupLEAs());
 512     addPass(createX86EvexToVexInsts());
 513   }
 514 }
 515
 516 void X86PassConfig::addPreEmitPass2() {
 517   addPass(createX86RetpolineThunksPass());
 518   // Verify basic block incoming and outgoing cfa offset and register values and
 519   // correct CFA calculation rule where needed by inserting appropriate CFI
 520   // instructions.
 521   const Triple &TT = TM->getTargetTriple();
 522   if (!TT.isOSDarwin() && !TT.isOSWindows())
 523     addPass(createCFIInstrInserter());
 524 }