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[AMDGPU] Check for immediate SrcC in mfma in AsmParser
[llvm-core.git] / lib / Target / AMDGPU / AMDGPUISelLowering.cpp
blobfcf17407b9e97acbbfc965040118fb00f7c95322
1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This is the parent TargetLowering class for hardware code gen
11 /// targets.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #define AMDGPU_LOG2E_F 1.44269504088896340735992468100189214f
16 #define AMDGPU_LN2_F 0.693147180559945309417232121458176568f
17 #define AMDGPU_LN10_F 2.30258509299404568401799145468436421f
18
19 #include "AMDGPUISelLowering.h"
20 #include "AMDGPU.h"
21 #include "AMDGPUCallLowering.h"
22 #include "AMDGPUFrameLowering.h"
23 #include "AMDGPURegisterInfo.h"
24 #include "AMDGPUSubtarget.h"
25 #include "AMDGPUTargetMachine.h"
26 #include "Utils/AMDGPUBaseInfo.h"
27 #include "R600MachineFunctionInfo.h"
28 #include "SIInstrInfo.h"
29 #include "SIMachineFunctionInfo.h"
30 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
31 #include "llvm/CodeGen/Analysis.h"
32 #include "llvm/CodeGen/CallingConvLower.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
37 #include "llvm/IR/DataLayout.h"
38 #include "llvm/IR/DiagnosticInfo.h"
39 #include "llvm/Support/KnownBits.h"
40 using namespace llvm;
41
42 #include "AMDGPUGenCallingConv.inc"
43
44 // Find a larger type to do a load / store of a vector with.
45 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {
46 unsigned StoreSize = VT.getStoreSizeInBits();
47 if (StoreSize <= 32)
48 return EVT::getIntegerVT(Ctx, StoreSize);
49
50 assert(StoreSize % 32 == 0 && "Store size not a multiple of 32");
51 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
52 }
53
54 unsigned AMDGPUTargetLowering::numBitsUnsigned(SDValue Op, SelectionDAG &DAG) {
55 EVT VT = Op.getValueType();
56 KnownBits Known = DAG.computeKnownBits(Op);
57 return VT.getSizeInBits() - Known.countMinLeadingZeros();
58 }
59
60 unsigned AMDGPUTargetLowering::numBitsSigned(SDValue Op, SelectionDAG &DAG) {
61 EVT VT = Op.getValueType();
62
63 // In order for this to be a signed 24-bit value, bit 23, must
64 // be a sign bit.
65 return VT.getSizeInBits() - DAG.ComputeNumSignBits(Op);
66 }
67
68 AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
69 const AMDGPUSubtarget &STI)
70 : TargetLowering(TM), Subtarget(&STI) {
71 // Lower floating point store/load to integer store/load to reduce the number
72 // of patterns in tablegen.
73 setOperationAction(ISD::LOAD, MVT::f32, Promote);
74 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
75
76 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
77 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
78
79 setOperationAction(ISD::LOAD, MVT::v3f32, Promote);
80 AddPromotedToType(ISD::LOAD, MVT::v3f32, MVT::v3i32);
81
82 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
83 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
84
85 setOperationAction(ISD::LOAD, MVT::v5f32, Promote);
86 AddPromotedToType(ISD::LOAD, MVT::v5f32, MVT::v5i32);
87
88 setOperationAction(ISD::LOAD, MVT::v8f32, Promote);
89 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32);
90
91 setOperationAction(ISD::LOAD, MVT::v16f32, Promote);
92 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32);
93
94 setOperationAction(ISD::LOAD, MVT::v32f32, Promote);
95 AddPromotedToType(ISD::LOAD, MVT::v32f32, MVT::v32i32);
96
97 setOperationAction(ISD::LOAD, MVT::i64, Promote);
98 AddPromotedToType(ISD::LOAD, MVT::i64, MVT::v2i32);
99
100 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
101 AddPromotedToType(ISD::LOAD, MVT::v2i64, MVT::v4i32);
102
103 setOperationAction(ISD::LOAD, MVT::f64, Promote);
104 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::v2i32);
105
106 setOperationAction(ISD::LOAD, MVT::v2f64, Promote);
107 AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v4i32);
108
109 // There are no 64-bit extloads. These should be done as a 32-bit extload and
110 // an extension to 64-bit.
111 for (MVT VT : MVT::integer_valuetypes()) {
112 setLoadExtAction(ISD::EXTLOAD, MVT::i64, VT, Expand);
113 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, VT, Expand);
114 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, VT, Expand);
115 }
116
117 for (MVT VT : MVT::integer_valuetypes()) {
118 if (VT == MVT::i64)
119 continue;
120
121 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
122 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Legal);
123 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Legal);
124 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand);
125
126 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
127 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Legal);
128 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Legal);
129 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand);
130
131 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
132 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i8, Legal);
133 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i16, Legal);
134 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand);
135 }
136
137 for (MVT VT : MVT::integer_vector_valuetypes()) {
138 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Expand);
139 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Expand);
140 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i8, Expand);
141 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Expand);
142 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Expand);
143 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i8, Expand);
144 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Expand);
145 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Expand);
146 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i16, Expand);
147 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v3i16, Expand);
148 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v3i16, Expand);
149 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v3i16, Expand);
150 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Expand);
151 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Expand);
152 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i16, Expand);
153 }
154
155 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
156 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, MVT::v2f16, Expand);
157 setLoadExtAction(ISD::EXTLOAD, MVT::v3f32, MVT::v3f16, Expand);
158 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4f16, Expand);
159 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, MVT::v8f16, Expand);
160 setLoadExtAction(ISD::EXTLOAD, MVT::v16f32, MVT::v16f16, Expand);
161 setLoadExtAction(ISD::EXTLOAD, MVT::v32f32, MVT::v32f16, Expand);
162
163 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
164 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f32, Expand);
165 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Expand);
166 setLoadExtAction(ISD::EXTLOAD, MVT::v8f64, MVT::v8f32, Expand);
167
168 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
169 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f16, Expand);
170 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f16, Expand);
171 setLoadExtAction(ISD::EXTLOAD, MVT::v8f64, MVT::v8f16, Expand);
172
173 setOperationAction(ISD::STORE, MVT::f32, Promote);
174 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
175
176 setOperationAction(ISD::STORE, MVT::v2f32, Promote);
177 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
178
179 setOperationAction(ISD::STORE, MVT::v3f32, Promote);
180 AddPromotedToType(ISD::STORE, MVT::v3f32, MVT::v3i32);
181
182 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
183 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
184
185 setOperationAction(ISD::STORE, MVT::v5f32, Promote);
186 AddPromotedToType(ISD::STORE, MVT::v5f32, MVT::v5i32);
187
188 setOperationAction(ISD::STORE, MVT::v8f32, Promote);
189 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32);
190
191 setOperationAction(ISD::STORE, MVT::v16f32, Promote);
192 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32);
193
194 setOperationAction(ISD::STORE, MVT::v32f32, Promote);
195 AddPromotedToType(ISD::STORE, MVT::v32f32, MVT::v32i32);
196
197 setOperationAction(ISD::STORE, MVT::i64, Promote);
198 AddPromotedToType(ISD::STORE, MVT::i64, MVT::v2i32);
199
200 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
201 AddPromotedToType(ISD::STORE, MVT::v2i64, MVT::v4i32);
202
203 setOperationAction(ISD::STORE, MVT::f64, Promote);
204 AddPromotedToType(ISD::STORE, MVT::f64, MVT::v2i32);
205
206 setOperationAction(ISD::STORE, MVT::v2f64, Promote);
207 AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v4i32);
208
209 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
210 setTruncStoreAction(MVT::i64, MVT::i8, Expand);
211 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
212 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
213
214 setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand);
215 setTruncStoreAction(MVT::v2i64, MVT::v2i8, Expand);
216 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Expand);
217 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Expand);
218
219 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
220 setTruncStoreAction(MVT::v2f32, MVT::v2f16, Expand);
221 setTruncStoreAction(MVT::v3f32, MVT::v3f16, Expand);
222 setTruncStoreAction(MVT::v4f32, MVT::v4f16, Expand);
223 setTruncStoreAction(MVT::v8f32, MVT::v8f16, Expand);
224 setTruncStoreAction(MVT::v16f32, MVT::v16f16, Expand);
225 setTruncStoreAction(MVT::v32f32, MVT::v32f16, Expand);
226
227 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
228 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
229
230 setTruncStoreAction(MVT::v2f64, MVT::v2f32, Expand);
231 setTruncStoreAction(MVT::v2f64, MVT::v2f16, Expand);
232
233 setTruncStoreAction(MVT::v4f64, MVT::v4f32, Expand);
234 setTruncStoreAction(MVT::v4f64, MVT::v4f16, Expand);
235
236 setTruncStoreAction(MVT::v8f64, MVT::v8f32, Expand);
237 setTruncStoreAction(MVT::v8f64, MVT::v8f16, Expand);
238
239
240 setOperationAction(ISD::Constant, MVT::i32, Legal);
241 setOperationAction(ISD::Constant, MVT::i64, Legal);
242 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
243 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
244
245 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
246 setOperationAction(ISD::BRIND, MVT::Other, Expand);
247
248 // This is totally unsupported, just custom lower to produce an error.
249 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
250
251 // Library functions. These default to Expand, but we have instructions
252 // for them.
253 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
254 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
255 setOperationAction(ISD::FPOW, MVT::f32, Legal);
256 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
257 setOperationAction(ISD::FABS, MVT::f32, Legal);
258 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
259 setOperationAction(ISD::FRINT, MVT::f32, Legal);
260 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
261 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
262 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
263
264 setOperationAction(ISD::FROUND, MVT::f32, Custom);
265 setOperationAction(ISD::FROUND, MVT::f64, Custom);
266
267 setOperationAction(ISD::FLOG, MVT::f32, Custom);
268 setOperationAction(ISD::FLOG10, MVT::f32, Custom);
269 setOperationAction(ISD::FEXP, MVT::f32, Custom);
270
271
272 setOperationAction(ISD::FNEARBYINT, MVT::f32, Custom);
273 setOperationAction(ISD::FNEARBYINT, MVT::f64, Custom);
274
275 setOperationAction(ISD::FREM, MVT::f32, Custom);
276 setOperationAction(ISD::FREM, MVT::f64, Custom);
277
278 // Expand to fneg + fadd.
279 setOperationAction(ISD::FSUB, MVT::f64, Expand);
280
281 setOperationAction(ISD::CONCAT_VECTORS, MVT::v3i32, Custom);
282 setOperationAction(ISD::CONCAT_VECTORS, MVT::v3f32, Custom);
283 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
284 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
285 setOperationAction(ISD::CONCAT_VECTORS, MVT::v5i32, Custom);
286 setOperationAction(ISD::CONCAT_VECTORS, MVT::v5f32, Custom);
287 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
288 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
289 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
290 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
291 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v3f32, Custom);
292 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v3i32, Custom);
293 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom);
294 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
295 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v5f32, Custom);
296 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v5i32, Custom);
297 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom);
298 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom);
299 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v16f32, Custom);
300 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v16i32, Custom);
301 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v32f32, Custom);
302 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v32i32, Custom);
303
304 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
305 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Custom);
306 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Custom);
307
308 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
309 for (MVT VT : ScalarIntVTs) {
310 // These should use [SU]DIVREM, so set them to expand
311 setOperationAction(ISD::SDIV, VT, Expand);
312 setOperationAction(ISD::UDIV, VT, Expand);
313 setOperationAction(ISD::SREM, VT, Expand);
314 setOperationAction(ISD::UREM, VT, Expand);
315
316 // GPU does not have divrem function for signed or unsigned.
317 setOperationAction(ISD::SDIVREM, VT, Custom);
318 setOperationAction(ISD::UDIVREM, VT, Custom);
319
320 // GPU does not have [S|U]MUL_LOHI functions as a single instruction.
321 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
322 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
323
324 setOperationAction(ISD::BSWAP, VT, Expand);
325 setOperationAction(ISD::CTTZ, VT, Expand);
326 setOperationAction(ISD::CTLZ, VT, Expand);
327
328 // AMDGPU uses ADDC/SUBC/ADDE/SUBE
329 setOperationAction(ISD::ADDC, VT, Legal);
330 setOperationAction(ISD::SUBC, VT, Legal);
331 setOperationAction(ISD::ADDE, VT, Legal);
332 setOperationAction(ISD::SUBE, VT, Legal);
333 }
334
335 // The hardware supports 32-bit ROTR, but not ROTL.
336 setOperationAction(ISD::ROTL, MVT::i32, Expand);
337 setOperationAction(ISD::ROTL, MVT::i64, Expand);
338 setOperationAction(ISD::ROTR, MVT::i64, Expand);
339
340 setOperationAction(ISD::MUL, MVT::i64, Expand);
341 setOperationAction(ISD::MULHU, MVT::i64, Expand);
342 setOperationAction(ISD::MULHS, MVT::i64, Expand);
343 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
344 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
345 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
346 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
347 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
348
349 setOperationAction(ISD::SMIN, MVT::i32, Legal);
350 setOperationAction(ISD::UMIN, MVT::i32, Legal);
351 setOperationAction(ISD::SMAX, MVT::i32, Legal);
352 setOperationAction(ISD::UMAX, MVT::i32, Legal);
353
354 setOperationAction(ISD::CTTZ, MVT::i64, Custom);
355 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Custom);
356 setOperationAction(ISD::CTLZ, MVT::i64, Custom);
357 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
358
359 static const MVT::SimpleValueType VectorIntTypes[] = {
360 MVT::v2i32, MVT::v3i32, MVT::v4i32, MVT::v5i32
361 };
362
363 for (MVT VT : VectorIntTypes) {
364 // Expand the following operations for the current type by default.
365 setOperationAction(ISD::ADD, VT, Expand);
366 setOperationAction(ISD::AND, VT, Expand);
367 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
368 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
369 setOperationAction(ISD::MUL, VT, Expand);
370 setOperationAction(ISD::MULHU, VT, Expand);
371 setOperationAction(ISD::MULHS, VT, Expand);
372 setOperationAction(ISD::OR, VT, Expand);
373 setOperationAction(ISD::SHL, VT, Expand);
374 setOperationAction(ISD::SRA, VT, Expand);
375 setOperationAction(ISD::SRL, VT, Expand);
376 setOperationAction(ISD::ROTL, VT, Expand);
377 setOperationAction(ISD::ROTR, VT, Expand);
378 setOperationAction(ISD::SUB, VT, Expand);
379 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
380 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
381 setOperationAction(ISD::SDIV, VT, Expand);
382 setOperationAction(ISD::UDIV, VT, Expand);
383 setOperationAction(ISD::SREM, VT, Expand);
384 setOperationAction(ISD::UREM, VT, Expand);
385 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
386 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
387 setOperationAction(ISD::SDIVREM, VT, Custom);
388 setOperationAction(ISD::UDIVREM, VT, Expand);
389 setOperationAction(ISD::SELECT, VT, Expand);
390 setOperationAction(ISD::VSELECT, VT, Expand);
391 setOperationAction(ISD::SELECT_CC, VT, Expand);
392 setOperationAction(ISD::XOR, VT, Expand);
393 setOperationAction(ISD::BSWAP, VT, Expand);
394 setOperationAction(ISD::CTPOP, VT, Expand);
395 setOperationAction(ISD::CTTZ, VT, Expand);
396 setOperationAction(ISD::CTLZ, VT, Expand);
397 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
398 setOperationAction(ISD::SETCC, VT, Expand);
399 }
400
401 static const MVT::SimpleValueType FloatVectorTypes[] = {
402 MVT::v2f32, MVT::v3f32, MVT::v4f32, MVT::v5f32
403 };
404
405 for (MVT VT : FloatVectorTypes) {
406 setOperationAction(ISD::FABS, VT, Expand);
407 setOperationAction(ISD::FMINNUM, VT, Expand);
408 setOperationAction(ISD::FMAXNUM, VT, Expand);
409 setOperationAction(ISD::FADD, VT, Expand);
410 setOperationAction(ISD::FCEIL, VT, Expand);
411 setOperationAction(ISD::FCOS, VT, Expand);
412 setOperationAction(ISD::FDIV, VT, Expand);
413 setOperationAction(ISD::FEXP2, VT, Expand);
414 setOperationAction(ISD::FEXP, VT, Expand);
415 setOperationAction(ISD::FLOG2, VT, Expand);
416 setOperationAction(ISD::FREM, VT, Expand);
417 setOperationAction(ISD::FLOG, VT, Expand);
418 setOperationAction(ISD::FLOG10, VT, Expand);
419 setOperationAction(ISD::FPOW, VT, Expand);
420 setOperationAction(ISD::FFLOOR, VT, Expand);
421 setOperationAction(ISD::FTRUNC, VT, Expand);
422 setOperationAction(ISD::FMUL, VT, Expand);
423 setOperationAction(ISD::FMA, VT, Expand);
424 setOperationAction(ISD::FRINT, VT, Expand);
425 setOperationAction(ISD::FNEARBYINT, VT, Expand);
426 setOperationAction(ISD::FSQRT, VT, Expand);
427 setOperationAction(ISD::FSIN, VT, Expand);
428 setOperationAction(ISD::FSUB, VT, Expand);
429 setOperationAction(ISD::FNEG, VT, Expand);
430 setOperationAction(ISD::VSELECT, VT, Expand);
431 setOperationAction(ISD::SELECT_CC, VT, Expand);
432 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
433 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
434 setOperationAction(ISD::SETCC, VT, Expand);
435 setOperationAction(ISD::FCANONICALIZE, VT, Expand);
436 }
437
438 // This causes using an unrolled select operation rather than expansion with
439 // bit operations. This is in general better, but the alternative using BFI
440 // instructions may be better if the select sources are SGPRs.
441 setOperationAction(ISD::SELECT, MVT::v2f32, Promote);
442 AddPromotedToType(ISD::SELECT, MVT::v2f32, MVT::v2i32);
443
444 setOperationAction(ISD::SELECT, MVT::v3f32, Promote);
445 AddPromotedToType(ISD::SELECT, MVT::v3f32, MVT::v3i32);
446
447 setOperationAction(ISD::SELECT, MVT::v4f32, Promote);
448 AddPromotedToType(ISD::SELECT, MVT::v4f32, MVT::v4i32);
449
450 setOperationAction(ISD::SELECT, MVT::v5f32, Promote);
451 AddPromotedToType(ISD::SELECT, MVT::v5f32, MVT::v5i32);
452
453 // There are no libcalls of any kind.
454 for (int I = 0; I < RTLIB::UNKNOWN_LIBCALL; ++I)
455 setLibcallName(static_cast<RTLIB::Libcall>(I), nullptr);
456
457 setBooleanContents(ZeroOrNegativeOneBooleanContent);
458 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
459
460 setSchedulingPreference(Sched::RegPressure);
461 setJumpIsExpensive(true);
462
463 // FIXME: This is only partially true. If we have to do vector compares, any
464 // SGPR pair can be a condition register. If we have a uniform condition, we
465 // are better off doing SALU operations, where there is only one SCC. For now,
466 // we don't have a way of knowing during instruction selection if a condition
467 // will be uniform and we always use vector compares. Assume we are using
468 // vector compares until that is fixed.
469 setHasMultipleConditionRegisters(true);
470
471 setMinCmpXchgSizeInBits(32);
472 setSupportsUnalignedAtomics(false);
473
474 PredictableSelectIsExpensive = false;
475
476 // We want to find all load dependencies for long chains of stores to enable
477 // merging into very wide vectors. The problem is with vectors with > 4
478 // elements. MergeConsecutiveStores will attempt to merge these because x8/x16
479 // vectors are a legal type, even though we have to split the loads
480 // usually. When we can more precisely specify load legality per address
481 // space, we should be able to make FindBetterChain/MergeConsecutiveStores
482 // smarter so that they can figure out what to do in 2 iterations without all
483 // N > 4 stores on the same chain.
484 GatherAllAliasesMaxDepth = 16;
485
486 // memcpy/memmove/memset are expanded in the IR, so we shouldn't need to worry
487 // about these during lowering.
488 MaxStoresPerMemcpy = 0xffffffff;
489 MaxStoresPerMemmove = 0xffffffff;
490 MaxStoresPerMemset = 0xffffffff;
491
492 setTargetDAGCombine(ISD::BITCAST);
493 setTargetDAGCombine(ISD::SHL);
494 setTargetDAGCombine(ISD::SRA);
495 setTargetDAGCombine(ISD::SRL);
496 setTargetDAGCombine(ISD::TRUNCATE);
497 setTargetDAGCombine(ISD::MUL);
498 setTargetDAGCombine(ISD::MULHU);
499 setTargetDAGCombine(ISD::MULHS);
500 setTargetDAGCombine(ISD::SELECT);
501 setTargetDAGCombine(ISD::SELECT_CC);
502 setTargetDAGCombine(ISD::STORE);
503 setTargetDAGCombine(ISD::FADD);
504 setTargetDAGCombine(ISD::FSUB);
505 setTargetDAGCombine(ISD::FNEG);
506 setTargetDAGCombine(ISD::FABS);
507 setTargetDAGCombine(ISD::AssertZext);
508 setTargetDAGCombine(ISD::AssertSext);
509 }
510
511 //===----------------------------------------------------------------------===//
512 // Target Information
513 //===----------------------------------------------------------------------===//
514
515 LLVM_READNONE
516 static bool fnegFoldsIntoOp(unsigned Opc) {
517 switch (Opc) {
518 case ISD::FADD:
519 case ISD::FSUB:
520 case ISD::FMUL:
521 case ISD::FMA:
522 case ISD::FMAD:
523 case ISD::FMINNUM:
524 case ISD::FMAXNUM:
525 case ISD::FMINNUM_IEEE:
526 case ISD::FMAXNUM_IEEE:
527 case ISD::FSIN:
528 case ISD::FTRUNC:
529 case ISD::FRINT:
530 case ISD::FNEARBYINT:
531 case ISD::FCANONICALIZE:
532 case AMDGPUISD::RCP:
533 case AMDGPUISD::RCP_LEGACY:
534 case AMDGPUISD::RCP_IFLAG:
535 case AMDGPUISD::SIN_HW:
536 case AMDGPUISD::FMUL_LEGACY:
537 case AMDGPUISD::FMIN_LEGACY:
538 case AMDGPUISD::FMAX_LEGACY:
539 case AMDGPUISD::FMED3:
540 return true;
541 default:
542 return false;
543 }
544 }
545
546 /// \p returns true if the operation will definitely need to use a 64-bit
547 /// encoding, and thus will use a VOP3 encoding regardless of the source
548 /// modifiers.
549 LLVM_READONLY
550 static bool opMustUseVOP3Encoding(const SDNode *N, MVT VT) {
551 return N->getNumOperands() > 2 || VT == MVT::f64;
552 }
553
554 // Most FP instructions support source modifiers, but this could be refined
555 // slightly.
556 LLVM_READONLY
557 static bool hasSourceMods(const SDNode *N) {
558 if (isa<MemSDNode>(N))
559 return false;
560
561 switch (N->getOpcode()) {
562 case ISD::CopyToReg:
563 case ISD::SELECT:
564 case ISD::FDIV:
565 case ISD::FREM:
566 case ISD::INLINEASM:
567 case ISD::INLINEASM_BR:
568 case AMDGPUISD::INTERP_P1:
569 case AMDGPUISD::INTERP_P2:
570 case AMDGPUISD::DIV_SCALE:
571
572 // TODO: Should really be looking at the users of the bitcast. These are
573 // problematic because bitcasts are used to legalize all stores to integer
574 // types.
575 case ISD::BITCAST:
576 return false;
577 default:
578 return true;
579 }
580 }
581
582 bool AMDGPUTargetLowering::allUsesHaveSourceMods(const SDNode *N,
583 unsigned CostThreshold) {
584 // Some users (such as 3-operand FMA/MAD) must use a VOP3 encoding, and thus
585 // it is truly free to use a source modifier in all cases. If there are
586 // multiple users but for each one will necessitate using VOP3, there will be
587 // a code size increase. Try to avoid increasing code size unless we know it
588 // will save on the instruction count.
589 unsigned NumMayIncreaseSize = 0;
590 MVT VT = N->getValueType(0).getScalarType().getSimpleVT();
591
592 // XXX - Should this limit number of uses to check?
593 for (const SDNode *U : N->uses()) {
594 if (!hasSourceMods(U))
595 return false;
596
597 if (!opMustUseVOP3Encoding(U, VT)) {
598 if (++NumMayIncreaseSize > CostThreshold)
599 return false;
600 }
601 }
602
603 return true;
604 }
605
606 MVT AMDGPUTargetLowering::getVectorIdxTy(const DataLayout &) const {
607 return MVT::i32;
608 }
609
610 bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const {
611 return true;
612 }
613
614 // The backend supports 32 and 64 bit floating point immediates.
615 // FIXME: Why are we reporting vectors of FP immediates as legal?
616 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
617 bool ForCodeSize) const {
618 EVT ScalarVT = VT.getScalarType();
619 return (ScalarVT == MVT::f32 || ScalarVT == MVT::f64 ||
620 (ScalarVT == MVT::f16 && Subtarget->has16BitInsts()));
621 }
622
623 // We don't want to shrink f64 / f32 constants.
624 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {
625 EVT ScalarVT = VT.getScalarType();
626 return (ScalarVT != MVT::f32 && ScalarVT != MVT::f64);
627 }
628
629 bool AMDGPUTargetLowering::shouldReduceLoadWidth(SDNode *N,
630 ISD::LoadExtType ExtTy,
631 EVT NewVT) const {
632 // TODO: This may be worth removing. Check regression tests for diffs.
633 if (!TargetLoweringBase::shouldReduceLoadWidth(N, ExtTy, NewVT))
634 return false;
635
636 unsigned NewSize = NewVT.getStoreSizeInBits();
637
638 // If we are reducing to a 32-bit load, this is always better.
639 if (NewSize == 32)
640 return true;
641
642 EVT OldVT = N->getValueType(0);
643 unsigned OldSize = OldVT.getStoreSizeInBits();
644
645 MemSDNode *MN = cast<MemSDNode>(N);
646 unsigned AS = MN->getAddressSpace();
647 // Do not shrink an aligned scalar load to sub-dword.
648 // Scalar engine cannot do sub-dword loads.
649 if (OldSize >= 32 && NewSize < 32 && MN->getAlignment() >= 4 &&
650 (AS == AMDGPUAS::CONSTANT_ADDRESS ||
651 AS == AMDGPUAS::CONSTANT_ADDRESS_32BIT ||
652 (isa<LoadSDNode>(N) &&
653 AS == AMDGPUAS::GLOBAL_ADDRESS && MN->isInvariant())) &&
654 AMDGPUInstrInfo::isUniformMMO(MN->getMemOperand()))
655 return false;
656
657 // Don't produce extloads from sub 32-bit types. SI doesn't have scalar
658 // extloads, so doing one requires using a buffer_load. In cases where we
659 // still couldn't use a scalar load, using the wider load shouldn't really
660 // hurt anything.
661
662 // If the old size already had to be an extload, there's no harm in continuing
663 // to reduce the width.
664 return (OldSize < 32);
665 }
666
667 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy, EVT CastTy,
668 const SelectionDAG &DAG,
669 const MachineMemOperand &MMO) const {
670
671 assert(LoadTy.getSizeInBits() == CastTy.getSizeInBits());
672
673 if (LoadTy.getScalarType() == MVT::i32)
674 return false;
675
676 unsigned LScalarSize = LoadTy.getScalarSizeInBits();
677 unsigned CastScalarSize = CastTy.getScalarSizeInBits();
678
679 if ((LScalarSize >= CastScalarSize) && (CastScalarSize < 32))
680 return false;
681
682 bool Fast = false;
683 return allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), CastTy,
684 MMO, &Fast) && Fast;
685 }
686
687 // SI+ has instructions for cttz / ctlz for 32-bit values. This is probably also
688 // profitable with the expansion for 64-bit since it's generally good to
689 // speculate things.
690 // FIXME: These should really have the size as a parameter.
691 bool AMDGPUTargetLowering::isCheapToSpeculateCttz() const {
692 return true;
693 }
694
695 bool AMDGPUTargetLowering::isCheapToSpeculateCtlz() const {
696 return true;
697 }
698
699 bool AMDGPUTargetLowering::isSDNodeAlwaysUniform(const SDNode * N) const {
700 switch (N->getOpcode()) {
701 default:
702 return false;
703 case ISD::EntryToken:
704 case ISD::TokenFactor:
705 return true;
706 case ISD::INTRINSIC_WO_CHAIN:
707 {
708 unsigned IntrID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
709 switch (IntrID) {
710 default:
711 return false;
712 case Intrinsic::amdgcn_readfirstlane:
713 case Intrinsic::amdgcn_readlane:
714 return true;
715 }
716 }
717 break;
718 case ISD::LOAD:
719 {
720 const LoadSDNode * L = dyn_cast<LoadSDNode>(N);
721 if (L->getMemOperand()->getAddrSpace()
722 == AMDGPUAS::CONSTANT_ADDRESS_32BIT)
723 return true;
724 return false;
725 }
726 break;
727 }
728 }
729
730 //===---------------------------------------------------------------------===//
731 // Target Properties
732 //===---------------------------------------------------------------------===//
733
734 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
735 assert(VT.isFloatingPoint());
736
737 // Packed operations do not have a fabs modifier.
738 return VT == MVT::f32 || VT == MVT::f64 ||
739 (Subtarget->has16BitInsts() && VT == MVT::f16);
740 }
741
742 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
743 assert(VT.isFloatingPoint());
744 return VT == MVT::f32 || VT == MVT::f64 ||
745 (Subtarget->has16BitInsts() && VT == MVT::f16) ||
746 (Subtarget->hasVOP3PInsts() && VT == MVT::v2f16);
747 }
748
749 bool AMDGPUTargetLowering:: storeOfVectorConstantIsCheap(EVT MemVT,
750 unsigned NumElem,
751 unsigned AS) const {
752 return true;
753 }
754
755 bool AMDGPUTargetLowering::aggressivelyPreferBuildVectorSources(EVT VecVT) const {
756 // There are few operations which truly have vector input operands. Any vector
757 // operation is going to involve operations on each component, and a
758 // build_vector will be a copy per element, so it always makes sense to use a
759 // build_vector input in place of the extracted element to avoid a copy into a
760 // super register.
761 //
762 // We should probably only do this if all users are extracts only, but this
763 // should be the common case.
764 return true;
765 }
766
767 bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {
768 // Truncate is just accessing a subregister.
769
770 unsigned SrcSize = Source.getSizeInBits();
771 unsigned DestSize = Dest.getSizeInBits();
772
773 return DestSize < SrcSize && DestSize % 32 == 0 ;
774 }
775
776 bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {
777 // Truncate is just accessing a subregister.
778
779 unsigned SrcSize = Source->getScalarSizeInBits();
780 unsigned DestSize = Dest->getScalarSizeInBits();
781
782 if (DestSize== 16 && Subtarget->has16BitInsts())
783 return SrcSize >= 32;
784
785 return DestSize < SrcSize && DestSize % 32 == 0;
786 }
787
788 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
789 unsigned SrcSize = Src->getScalarSizeInBits();
790 unsigned DestSize = Dest->getScalarSizeInBits();
791
792 if (SrcSize == 16 && Subtarget->has16BitInsts())
793 return DestSize >= 32;
794
795 return SrcSize == 32 && DestSize == 64;
796 }
797
798 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
799 // Any register load of a 64-bit value really requires 2 32-bit moves. For all
800 // practical purposes, the extra mov 0 to load a 64-bit is free. As used,
801 // this will enable reducing 64-bit operations the 32-bit, which is always
802 // good.
803
804 if (Src == MVT::i16)
805 return Dest == MVT::i32 ||Dest == MVT::i64 ;
806
807 return Src == MVT::i32 && Dest == MVT::i64;
808 }
809
810 bool AMDGPUTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
811 return isZExtFree(Val.getValueType(), VT2);
812 }
813
814 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
815 // There aren't really 64-bit registers, but pairs of 32-bit ones and only a
816 // limited number of native 64-bit operations. Shrinking an operation to fit
817 // in a single 32-bit register should always be helpful. As currently used,
818 // this is much less general than the name suggests, and is only used in
819 // places trying to reduce the sizes of loads. Shrinking loads to < 32-bits is
820 // not profitable, and may actually be harmful.
821 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
822 }
823
824 //===---------------------------------------------------------------------===//
825 // TargetLowering Callbacks
826 //===---------------------------------------------------------------------===//
827
828 CCAssignFn *AMDGPUCallLowering::CCAssignFnForCall(CallingConv::ID CC,
829 bool IsVarArg) {
830 switch (CC) {
831 case CallingConv::AMDGPU_VS:
832 case CallingConv::AMDGPU_GS:
833 case CallingConv::AMDGPU_PS:
834 case CallingConv::AMDGPU_CS:
835 case CallingConv::AMDGPU_HS:
836 case CallingConv::AMDGPU_ES:
837 case CallingConv::AMDGPU_LS:
838 return CC_AMDGPU;
839 case CallingConv::C:
840 case CallingConv::Fast:
841 case CallingConv::Cold:
842 return CC_AMDGPU_Func;
843 case CallingConv::AMDGPU_KERNEL:
844 case CallingConv::SPIR_KERNEL:
845 default:
846 report_fatal_error("Unsupported calling convention for call");
847 }
848 }
849
850 CCAssignFn *AMDGPUCallLowering::CCAssignFnForReturn(CallingConv::ID CC,
851 bool IsVarArg) {
852 switch (CC) {
853 case CallingConv::AMDGPU_KERNEL:
854 case CallingConv::SPIR_KERNEL:
855 llvm_unreachable("kernels should not be handled here");
856 case CallingConv::AMDGPU_VS:
857 case CallingConv::AMDGPU_GS:
858 case CallingConv::AMDGPU_PS:
859 case CallingConv::AMDGPU_CS:
860 case CallingConv::AMDGPU_HS:
861 case CallingConv::AMDGPU_ES:
862 case CallingConv::AMDGPU_LS:
863 return RetCC_SI_Shader;
864 case CallingConv::C:
865 case CallingConv::Fast:
866 case CallingConv::Cold:
867 return RetCC_AMDGPU_Func;
868 default:
869 report_fatal_error("Unsupported calling convention.");
870 }
871 }
872
873 /// The SelectionDAGBuilder will automatically promote function arguments
874 /// with illegal types. However, this does not work for the AMDGPU targets
875 /// since the function arguments are stored in memory as these illegal types.
876 /// In order to handle this properly we need to get the original types sizes
877 /// from the LLVM IR Function and fixup the ISD:InputArg values before
878 /// passing them to AnalyzeFormalArguments()
879
880 /// When the SelectionDAGBuilder computes the Ins, it takes care of splitting
881 /// input values across multiple registers. Each item in the Ins array
882 /// represents a single value that will be stored in registers. Ins[x].VT is
883 /// the value type of the value that will be stored in the register, so
884 /// whatever SDNode we lower the argument to needs to be this type.
885 ///
886 /// In order to correctly lower the arguments we need to know the size of each
887 /// argument. Since Ins[x].VT gives us the size of the register that will
888 /// hold the value, we need to look at Ins[x].ArgVT to see the 'real' type
889 /// for the orignal function argument so that we can deduce the correct memory
890 /// type to use for Ins[x]. In most cases the correct memory type will be
891 /// Ins[x].ArgVT. However, this will not always be the case. If, for example,
892 /// we have a kernel argument of type v8i8, this argument will be split into
893 /// 8 parts and each part will be represented by its own item in the Ins array.
894 /// For each part the Ins[x].ArgVT will be the v8i8, which is the full type of
895 /// the argument before it was split. From this, we deduce that the memory type
896 /// for each individual part is i8. We pass the memory type as LocVT to the
897 /// calling convention analysis function and the register type (Ins[x].VT) as
898 /// the ValVT.
899 void AMDGPUTargetLowering::analyzeFormalArgumentsCompute(
900 CCState &State,
901 const SmallVectorImpl<ISD::InputArg> &Ins) const {
902 const MachineFunction &MF = State.getMachineFunction();
903 const Function &Fn = MF.getFunction();
904 LLVMContext &Ctx = Fn.getParent()->getContext();
905 const AMDGPUSubtarget &ST = AMDGPUSubtarget::get(MF);
906 const unsigned ExplicitOffset = ST.getExplicitKernelArgOffset(Fn);
907 CallingConv::ID CC = Fn.getCallingConv();
908
909 unsigned MaxAlign = 1;
910 uint64_t ExplicitArgOffset = 0;
911 const DataLayout &DL = Fn.getParent()->getDataLayout();
912
913 unsigned InIndex = 0;
914
915 for (const Argument &Arg : Fn.args()) {
916 Type *BaseArgTy = Arg.getType();
917 unsigned Align = DL.getABITypeAlignment(BaseArgTy);
918 MaxAlign = std::max(Align, MaxAlign);
919 unsigned AllocSize = DL.getTypeAllocSize(BaseArgTy);
920
921 uint64_t ArgOffset = alignTo(ExplicitArgOffset, Align) + ExplicitOffset;
922 ExplicitArgOffset = alignTo(ExplicitArgOffset, Align) + AllocSize;
923
924 // We're basically throwing away everything passed into us and starting over
925 // to get accurate in-memory offsets. The "PartOffset" is completely useless
926 // to us as computed in Ins.
927 //
928 // We also need to figure out what type legalization is trying to do to get
929 // the correct memory offsets.
930
931 SmallVector<EVT, 16> ValueVTs;
932 SmallVector<uint64_t, 16> Offsets;
933 ComputeValueVTs(*this, DL, BaseArgTy, ValueVTs, &Offsets, ArgOffset);
934
935 for (unsigned Value = 0, NumValues = ValueVTs.size();
936 Value != NumValues; ++Value) {
937 uint64_t BasePartOffset = Offsets[Value];
938
939 EVT ArgVT = ValueVTs[Value];
940 EVT MemVT = ArgVT;
941 MVT RegisterVT = getRegisterTypeForCallingConv(Ctx, CC, ArgVT);
942 unsigned NumRegs = getNumRegistersForCallingConv(Ctx, CC, ArgVT);
943
944 if (NumRegs == 1) {
945 // This argument is not split, so the IR type is the memory type.
946 if (ArgVT.isExtended()) {
947 // We have an extended type, like i24, so we should just use the
948 // register type.
949 MemVT = RegisterVT;
950 } else {
951 MemVT = ArgVT;
952 }
953 } else if (ArgVT.isVector() && RegisterVT.isVector() &&
954 ArgVT.getScalarType() == RegisterVT.getScalarType()) {
955 assert(ArgVT.getVectorNumElements() > RegisterVT.getVectorNumElements());
956 // We have a vector value which has been split into a vector with
957 // the same scalar type, but fewer elements. This should handle
958 // all the floating-point vector types.
959 MemVT = RegisterVT;
960 } else if (ArgVT.isVector() &&
961 ArgVT.getVectorNumElements() == NumRegs) {
962 // This arg has been split so that each element is stored in a separate
963 // register.
964 MemVT = ArgVT.getScalarType();
965 } else if (ArgVT.isExtended()) {
966 // We have an extended type, like i65.
967 MemVT = RegisterVT;
968 } else {
969 unsigned MemoryBits = ArgVT.getStoreSizeInBits() / NumRegs;
970 assert(ArgVT.getStoreSizeInBits() % NumRegs == 0);
971 if (RegisterVT.isInteger()) {
972 MemVT = EVT::getIntegerVT(State.getContext(), MemoryBits);
973 } else if (RegisterVT.isVector()) {
974 assert(!RegisterVT.getScalarType().isFloatingPoint());
975 unsigned NumElements = RegisterVT.getVectorNumElements();
976 assert(MemoryBits % NumElements == 0);
977 // This vector type has been split into another vector type with
978 // a different elements size.
979 EVT ScalarVT = EVT::getIntegerVT(State.getContext(),
980 MemoryBits / NumElements);
981 MemVT = EVT::getVectorVT(State.getContext(), ScalarVT, NumElements);
982 } else {
983 llvm_unreachable("cannot deduce memory type.");
984 }
985 }
986
987 // Convert one element vectors to scalar.
988 if (MemVT.isVector() && MemVT.getVectorNumElements() == 1)
989 MemVT = MemVT.getScalarType();
990
991 // Round up vec3/vec5 argument.
992 if (MemVT.isVector() && !MemVT.isPow2VectorType()) {
993 assert(MemVT.getVectorNumElements() == 3 ||
994 MemVT.getVectorNumElements() == 5);
995 MemVT = MemVT.getPow2VectorType(State.getContext());
996 }
997
998 unsigned PartOffset = 0;
999 for (unsigned i = 0; i != NumRegs; ++i) {
1000 State.addLoc(CCValAssign::getCustomMem(InIndex++, RegisterVT,
1001 BasePartOffset + PartOffset,
1002 MemVT.getSimpleVT(),
1003 CCValAssign::Full));
1004 PartOffset += MemVT.getStoreSize();
1005 }
1006 }
1007 }
1008 }
1009
1010 SDValue AMDGPUTargetLowering::LowerReturn(
1011 SDValue Chain, CallingConv::ID CallConv,
1012 bool isVarArg,
1013 const SmallVectorImpl<ISD::OutputArg> &Outs,
1014 const SmallVectorImpl<SDValue> &OutVals,
1015 const SDLoc &DL, SelectionDAG &DAG) const {
1016 // FIXME: Fails for r600 tests
1017 //assert(!isVarArg && Outs.empty() && OutVals.empty() &&
1018 // "wave terminate should not have return values");
1019 return DAG.getNode(AMDGPUISD::ENDPGM, DL, MVT::Other, Chain);
1020 }
1021
1022 //===---------------------------------------------------------------------===//
1023 // Target specific lowering
1024 //===---------------------------------------------------------------------===//
1025
1026 /// Selects the correct CCAssignFn for a given CallingConvention value.
1027 CCAssignFn *AMDGPUTargetLowering::CCAssignFnForCall(CallingConv::ID CC,
1028 bool IsVarArg) {
1029 return AMDGPUCallLowering::CCAssignFnForCall(CC, IsVarArg);
1030 }
1031
1032 CCAssignFn *AMDGPUTargetLowering::CCAssignFnForReturn(CallingConv::ID CC,
1033 bool IsVarArg) {
1034 return AMDGPUCallLowering::CCAssignFnForReturn(CC, IsVarArg);
1035 }
1036
1037 SDValue AMDGPUTargetLowering::addTokenForArgument(SDValue Chain,
1038 SelectionDAG &DAG,
1039 MachineFrameInfo &MFI,
1040 int ClobberedFI) const {
1041 SmallVector<SDValue, 8> ArgChains;
1042 int64_t FirstByte = MFI.getObjectOffset(ClobberedFI);
1043 int64_t LastByte = FirstByte + MFI.getObjectSize(ClobberedFI) - 1;
1044
1045 // Include the original chain at the beginning of the list. When this is
1046 // used by target LowerCall hooks, this helps legalize find the
1047 // CALLSEQ_BEGIN node.
1048 ArgChains.push_back(Chain);
1049
1050 // Add a chain value for each stack argument corresponding
1051 for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(),
1052 UE = DAG.getEntryNode().getNode()->use_end();
1053 U != UE; ++U) {
1054 if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U)) {
1055 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr())) {
1056 if (FI->getIndex() < 0) {
1057 int64_t InFirstByte = MFI.getObjectOffset(FI->getIndex());
1058 int64_t InLastByte = InFirstByte;
1059 InLastByte += MFI.getObjectSize(FI->getIndex()) - 1;
1060
1061 if ((InFirstByte <= FirstByte && FirstByte <= InLastByte) ||
1062 (FirstByte <= InFirstByte && InFirstByte <= LastByte))
1063 ArgChains.push_back(SDValue(L, 1));
1064 }
1065 }
1066 }
1067 }
1068
1069 // Build a tokenfactor for all the chains.
1070 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains);
1071 }
1072
1073 SDValue AMDGPUTargetLowering::lowerUnhandledCall(CallLoweringInfo &CLI,
1074 SmallVectorImpl<SDValue> &InVals,
1075 StringRef Reason) const {
1076 SDValue Callee = CLI.Callee;
1077 SelectionDAG &DAG = CLI.DAG;
1078
1079 const Function &Fn = DAG.getMachineFunction().getFunction();
1080
1081 StringRef FuncName("<unknown>");
1082
1083 if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee))
1084 FuncName = G->getSymbol();
1085 else if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1086 FuncName = G->getGlobal()->getName();
1087
1088 DiagnosticInfoUnsupported NoCalls(
1089 Fn, Reason + FuncName, CLI.DL.getDebugLoc());
1090 DAG.getContext()->diagnose(NoCalls);
1091
1092 if (!CLI.IsTailCall) {
1093 for (unsigned I = 0, E = CLI.Ins.size(); I != E; ++I)
1094 InVals.push_back(DAG.getUNDEF(CLI.Ins[I].VT));
1095 }
1096
1097 return DAG.getEntryNode();
1098 }
1099
1100 SDValue AMDGPUTargetLowering::LowerCall(CallLoweringInfo &CLI,
1101 SmallVectorImpl<SDValue> &InVals) const {
1102 return lowerUnhandledCall(CLI, InVals, "unsupported call to function ");
1103 }
1104
1105 SDValue AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
1106 SelectionDAG &DAG) const {
1107 const Function &Fn = DAG.getMachineFunction().getFunction();
1108
1109 DiagnosticInfoUnsupported NoDynamicAlloca(Fn, "unsupported dynamic alloca",
1110 SDLoc(Op).getDebugLoc());
1111 DAG.getContext()->diagnose(NoDynamicAlloca);
1112 auto Ops = {DAG.getConstant(0, SDLoc(), Op.getValueType()), Op.getOperand(0)};
1113 return DAG.getMergeValues(Ops, SDLoc());
1114 }
1115
1116 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
1117 SelectionDAG &DAG) const {
1118 switch (Op.getOpcode()) {
1119 default:
1120 Op->print(errs(), &DAG);
1121 llvm_unreachable("Custom lowering code for this"
1122 "instruction is not implemented yet!");
1123 break;
1124 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
1125 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
1126 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
1127 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
1128 case ISD::SDIVREM: return LowerSDIVREM(Op, DAG);
1129 case ISD::FREM: return LowerFREM(Op, DAG);
1130 case ISD::FCEIL: return LowerFCEIL(Op, DAG);
1131 case ISD::FTRUNC: return LowerFTRUNC(Op, DAG);
1132 case ISD::FRINT: return LowerFRINT(Op, DAG);
1133 case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG);
1134 case ISD::FROUND: return LowerFROUND(Op, DAG);
1135 case ISD::FFLOOR: return LowerFFLOOR(Op, DAG);
1136 case ISD::FLOG:
1137 return LowerFLOG(Op, DAG, 1 / AMDGPU_LOG2E_F);
1138 case ISD::FLOG10:
1139 return LowerFLOG(Op, DAG, AMDGPU_LN2_F / AMDGPU_LN10_F);
1140 case ISD::FEXP:
1141 return lowerFEXP(Op, DAG);
1142 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
1143 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
1144 case ISD::FP_TO_FP16: return LowerFP_TO_FP16(Op, DAG);
1145 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
1146 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
1147 case ISD::CTTZ:
1148 case ISD::CTTZ_ZERO_UNDEF:
1149 case ISD::CTLZ:
1150 case ISD::CTLZ_ZERO_UNDEF:
1151 return LowerCTLZ_CTTZ(Op, DAG);
1152 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
1153 }
1154 return Op;
1155 }
1156
1157 void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
1158 SmallVectorImpl<SDValue> &Results,
1159 SelectionDAG &DAG) const {
1160 switch (N->getOpcode()) {
1161 case ISD::SIGN_EXTEND_INREG:
1162 // Different parts of legalization seem to interpret which type of
1163 // sign_extend_inreg is the one to check for custom lowering. The extended
1164 // from type is what really matters, but some places check for custom
1165 // lowering of the result type. This results in trying to use
1166 // ReplaceNodeResults to sext_in_reg to an illegal type, so we'll just do
1167 // nothing here and let the illegal result integer be handled normally.
1168 return;
1169 default:
1170 return;
1171 }
1172 }
1173
1174 static bool hasDefinedInitializer(const GlobalValue *GV) {
1175 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
1176 if (!GVar || !GVar->hasInitializer())
1177 return false;
1178
1179 return !isa<UndefValue>(GVar->getInitializer());
1180 }
1181
1182 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
1183 SDValue Op,
1184 SelectionDAG &DAG) const {
1185
1186 const DataLayout &DL = DAG.getDataLayout();
1187 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
1188 const GlobalValue *GV = G->getGlobal();
1189
1190 if (G->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
1191 G->getAddressSpace() == AMDGPUAS::REGION_ADDRESS) {
1192 if (!MFI->isEntryFunction()) {
1193 const Function &Fn = DAG.getMachineFunction().getFunction();
1194 DiagnosticInfoUnsupported BadLDSDecl(
1195 Fn, "local memory global used by non-kernel function", SDLoc(Op).getDebugLoc());
1196 DAG.getContext()->diagnose(BadLDSDecl);
1197 }
1198
1199 // XXX: What does the value of G->getOffset() mean?
1200 assert(G->getOffset() == 0 &&
1201 "Do not know what to do with an non-zero offset");
1202
1203 // TODO: We could emit code to handle the initialization somewhere.
1204 if (!hasDefinedInitializer(GV)) {
1205 unsigned Offset = MFI->allocateLDSGlobal(DL, *GV);
1206 return DAG.getConstant(Offset, SDLoc(Op), Op.getValueType());
1207 }
1208 }
1209
1210 const Function &Fn = DAG.getMachineFunction().getFunction();
1211 DiagnosticInfoUnsupported BadInit(
1212 Fn, "unsupported initializer for address space", SDLoc(Op).getDebugLoc());
1213 DAG.getContext()->diagnose(BadInit);
1214 return SDValue();
1215 }
1216
1217 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
1218 SelectionDAG &DAG) const {
1219 SmallVector<SDValue, 8> Args;
1220
1221 EVT VT = Op.getValueType();
1222 if (VT == MVT::v4i16 || VT == MVT::v4f16) {
1223 SDLoc SL(Op);
1224 SDValue Lo = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Op.getOperand(0));
1225 SDValue Hi = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Op.getOperand(1));
1226
1227 SDValue BV = DAG.getBuildVector(MVT::v2i32, SL, { Lo, Hi });
1228 return DAG.getNode(ISD::BITCAST, SL, VT, BV);
1229 }
1230
1231 for (const SDUse &U : Op->ops())
1232 DAG.ExtractVectorElements(U.get(), Args);
1233
1234 return DAG.getBuildVector(Op.getValueType(), SDLoc(Op), Args);
1235 }
1236
1237 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
1238 SelectionDAG &DAG) const {
1239
1240 SmallVector<SDValue, 8> Args;
1241 unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1242 EVT VT = Op.getValueType();
1243 DAG.ExtractVectorElements(Op.getOperand(0), Args, Start,
1244 VT.getVectorNumElements());
1245
1246 return DAG.getBuildVector(Op.getValueType(), SDLoc(Op), Args);
1247 }
1248
1249 /// Generate Min/Max node
1250 SDValue AMDGPUTargetLowering::combineFMinMaxLegacy(const SDLoc &DL, EVT VT,
1251 SDValue LHS, SDValue RHS,
1252 SDValue True, SDValue False,
1253 SDValue CC,
1254 DAGCombinerInfo &DCI) const {
1255 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
1256 return SDValue();
1257
1258 SelectionDAG &DAG = DCI.DAG;
1259 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1260 switch (CCOpcode) {
1261 case ISD::SETOEQ:
1262 case ISD::SETONE:
1263 case ISD::SETUNE:
1264 case ISD::SETNE:
1265 case ISD::SETUEQ:
1266 case ISD::SETEQ:
1267 case ISD::SETFALSE:
1268 case ISD::SETFALSE2:
1269 case ISD::SETTRUE:
1270 case ISD::SETTRUE2:
1271 case ISD::SETUO:
1272 case ISD::SETO:
1273 break;
1274 case ISD::SETULE:
1275 case ISD::SETULT: {
1276 if (LHS == True)
1277 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
1278 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
1279 }
1280 case ISD::SETOLE:
1281 case ISD::SETOLT:
1282 case ISD::SETLE:
1283 case ISD::SETLT: {
1284 // Ordered. Assume ordered for undefined.
1285
1286 // Only do this after legalization to avoid interfering with other combines
1287 // which might occur.
1288 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1289 !DCI.isCalledByLegalizer())
1290 return SDValue();
1291
1292 // We need to permute the operands to get the correct NaN behavior. The
1293 // selected operand is the second one based on the failing compare with NaN,
1294 // so permute it based on the compare type the hardware uses.
1295 if (LHS == True)
1296 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
1297 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
1298 }
1299 case ISD::SETUGE:
1300 case ISD::SETUGT: {
1301 if (LHS == True)
1302 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
1303 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
1304 }
1305 case ISD::SETGT:
1306 case ISD::SETGE:
1307 case ISD::SETOGE:
1308 case ISD::SETOGT: {
1309 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1310 !DCI.isCalledByLegalizer())
1311 return SDValue();
1312
1313 if (LHS == True)
1314 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
1315 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
1316 }
1317 case ISD::SETCC_INVALID:
1318 llvm_unreachable("Invalid setcc condcode!");
1319 }
1320 return SDValue();
1321 }
1322
1323 std::pair<SDValue, SDValue>
1324 AMDGPUTargetLowering::split64BitValue(SDValue Op, SelectionDAG &DAG) const {
1325 SDLoc SL(Op);
1326
1327 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op);
1328
1329 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
1330 const SDValue One = DAG.getConstant(1, SL, MVT::i32);
1331
1332 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero);
1333 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One);
1334
1335 return std::make_pair(Lo, Hi);
1336 }
1337
1338 SDValue AMDGPUTargetLowering::getLoHalf64(SDValue Op, SelectionDAG &DAG) const {
1339 SDLoc SL(Op);
1340
1341 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op);
1342 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
1343 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero);
1344 }
1345
1346 SDValue AMDGPUTargetLowering::getHiHalf64(SDValue Op, SelectionDAG &DAG) const {
1347 SDLoc SL(Op);
1348
1349 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op);
1350 const SDValue One = DAG.getConstant(1, SL, MVT::i32);
1351 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One);
1352 }
1353
1354 // Split a vector type into two parts. The first part is a power of two vector.
1355 // The second part is whatever is left over, and is a scalar if it would
1356 // otherwise be a 1-vector.
1357 std::pair<EVT, EVT>
1358 AMDGPUTargetLowering::getSplitDestVTs(const EVT &VT, SelectionDAG &DAG) const {
1359 EVT LoVT, HiVT;
1360 EVT EltVT = VT.getVectorElementType();
1361 unsigned NumElts = VT.getVectorNumElements();
1362 unsigned LoNumElts = PowerOf2Ceil((NumElts + 1) / 2);
1363 LoVT = EVT::getVectorVT(*DAG.getContext(), EltVT, LoNumElts);
1364 HiVT = NumElts - LoNumElts == 1
1365 ? EltVT
1366 : EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts - LoNumElts);
1367 return std::make_pair(LoVT, HiVT);
1368 }
1369
1370 // Split a vector value into two parts of types LoVT and HiVT. HiVT could be
1371 // scalar.
1372 std::pair<SDValue, SDValue>
1373 AMDGPUTargetLowering::splitVector(const SDValue &N, const SDLoc &DL,
1374 const EVT &LoVT, const EVT &HiVT,
1375 SelectionDAG &DAG) const {
1376 assert(LoVT.getVectorNumElements() +
1377 (HiVT.isVector() ? HiVT.getVectorNumElements() : 1) <=
1378 N.getValueType().getVectorNumElements() &&
1379 "More vector elements requested than available!");
1380 auto IdxTy = getVectorIdxTy(DAG.getDataLayout());
1381 SDValue Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, LoVT, N,
1382 DAG.getConstant(0, DL, IdxTy));
1383 SDValue Hi = DAG.getNode(
1384 HiVT.isVector() ? ISD::EXTRACT_SUBVECTOR : ISD::EXTRACT_VECTOR_ELT, DL,
1385 HiVT, N, DAG.getConstant(LoVT.getVectorNumElements(), DL, IdxTy));
1386 return std::make_pair(Lo, Hi);
1387 }
1388
1389 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue Op,
1390 SelectionDAG &DAG) const {
1391 LoadSDNode *Load = cast<LoadSDNode>(Op);
1392 EVT VT = Op.getValueType();
1393
1394
1395 // If this is a 2 element vector, we really want to scalarize and not create
1396 // weird 1 element vectors.
1397 if (VT.getVectorNumElements() == 2)
1398 return scalarizeVectorLoad(Load, DAG);
1399
1400 SDValue BasePtr = Load->getBasePtr();
1401 EVT MemVT = Load->getMemoryVT();
1402 SDLoc SL(Op);
1403
1404 const MachinePointerInfo &SrcValue = Load->getMemOperand()->getPointerInfo();
1405
1406 EVT LoVT, HiVT;
1407 EVT LoMemVT, HiMemVT;
1408 SDValue Lo, Hi;
1409
1410 std::tie(LoVT, HiVT) = getSplitDestVTs(VT, DAG);
1411 std::tie(LoMemVT, HiMemVT) = getSplitDestVTs(MemVT, DAG);
1412 std::tie(Lo, Hi) = splitVector(Op, SL, LoVT, HiVT, DAG);
1413
1414 unsigned Size = LoMemVT.getStoreSize();
1415 unsigned BaseAlign = Load->getAlignment();
1416 unsigned HiAlign = MinAlign(BaseAlign, Size);
1417
1418 SDValue LoLoad = DAG.getExtLoad(Load->getExtensionType(), SL, LoVT,
1419 Load->getChain(), BasePtr, SrcValue, LoMemVT,
1420 BaseAlign, Load->getMemOperand()->getFlags());
1421 SDValue HiPtr = DAG.getObjectPtrOffset(SL, BasePtr, Size);
1422 SDValue HiLoad =
1423 DAG.getExtLoad(Load->getExtensionType(), SL, HiVT, Load->getChain(),
1424 HiPtr, SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1425 HiMemVT, HiAlign, Load->getMemOperand()->getFlags());
1426
1427 auto IdxTy = getVectorIdxTy(DAG.getDataLayout());
1428 SDValue Join;
1429 if (LoVT == HiVT) {
1430 // This is the case that the vector is power of two so was evenly split.
1431 Join = DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad);
1432 } else {
1433 Join = DAG.getNode(ISD::INSERT_SUBVECTOR, SL, VT, DAG.getUNDEF(VT), LoLoad,
1434 DAG.getConstant(0, SL, IdxTy));
1435 Join = DAG.getNode(HiVT.isVector() ? ISD::INSERT_SUBVECTOR
1436 : ISD::INSERT_VECTOR_ELT,
1437 SL, VT, Join, HiLoad,
1438 DAG.getConstant(LoVT.getVectorNumElements(), SL, IdxTy));
1439 }
1440
1441 SDValue Ops[] = {Join, DAG.getNode(ISD::TokenFactor, SL, MVT::Other,
1442 LoLoad.getValue(1), HiLoad.getValue(1))};
1443
1444 return DAG.getMergeValues(Ops, SL);
1445 }
1446
1447 // Widen a vector load from vec3 to vec4.
1448 SDValue AMDGPUTargetLowering::WidenVectorLoad(SDValue Op,
1449 SelectionDAG &DAG) const {
1450 LoadSDNode *Load = cast<LoadSDNode>(Op);
1451 EVT VT = Op.getValueType();
1452 assert(VT.getVectorNumElements() == 3);
1453 SDValue BasePtr = Load->getBasePtr();
1454 EVT MemVT = Load->getMemoryVT();
1455 SDLoc SL(Op);
1456 const MachinePointerInfo &SrcValue = Load->getMemOperand()->getPointerInfo();
1457 unsigned BaseAlign = Load->getAlignment();
1458
1459 EVT WideVT =
1460 EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), 4);
1461 EVT WideMemVT =
1462 EVT::getVectorVT(*DAG.getContext(), MemVT.getVectorElementType(), 4);
1463 SDValue WideLoad = DAG.getExtLoad(
1464 Load->getExtensionType(), SL, WideVT, Load->getChain(), BasePtr, SrcValue,
1465 WideMemVT, BaseAlign, Load->getMemOperand()->getFlags());
1466 return DAG.getMergeValues(
1467 {DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, VT, WideLoad,
1468 DAG.getConstant(0, SL, getVectorIdxTy(DAG.getDataLayout()))),
1469 WideLoad.getValue(1)},
1470 SL);
1471 }
1472
1473 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
1474 SelectionDAG &DAG) const {
1475 StoreSDNode *Store = cast<StoreSDNode>(Op);
1476 SDValue Val = Store->getValue();
1477 EVT VT = Val.getValueType();
1478
1479 // If this is a 2 element vector, we really want to scalarize and not create
1480 // weird 1 element vectors.
1481 if (VT.getVectorNumElements() == 2)
1482 return scalarizeVectorStore(Store, DAG);
1483
1484 EVT MemVT = Store->getMemoryVT();
1485 SDValue Chain = Store->getChain();
1486 SDValue BasePtr = Store->getBasePtr();
1487 SDLoc SL(Op);
1488
1489 EVT LoVT, HiVT;
1490 EVT LoMemVT, HiMemVT;
1491 SDValue Lo, Hi;
1492
1493 std::tie(LoVT, HiVT) = getSplitDestVTs(VT, DAG);
1494 std::tie(LoMemVT, HiMemVT) = getSplitDestVTs(MemVT, DAG);
1495 std::tie(Lo, Hi) = splitVector(Val, SL, LoVT, HiVT, DAG);
1496
1497 SDValue HiPtr = DAG.getObjectPtrOffset(SL, BasePtr, LoMemVT.getStoreSize());
1498
1499 const MachinePointerInfo &SrcValue = Store->getMemOperand()->getPointerInfo();
1500 unsigned BaseAlign = Store->getAlignment();
1501 unsigned Size = LoMemVT.getStoreSize();
1502 unsigned HiAlign = MinAlign(BaseAlign, Size);
1503
1504 SDValue LoStore =
1505 DAG.getTruncStore(Chain, SL, Lo, BasePtr, SrcValue, LoMemVT, BaseAlign,
1506 Store->getMemOperand()->getFlags());
1507 SDValue HiStore =
1508 DAG.getTruncStore(Chain, SL, Hi, HiPtr, SrcValue.getWithOffset(Size),
1509 HiMemVT, HiAlign, Store->getMemOperand()->getFlags());
1510
1511 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, LoStore, HiStore);
1512 }
1513
1514 // This is a shortcut for integer division because we have fast i32<->f32
1515 // conversions, and fast f32 reciprocal instructions. The fractional part of a
1516 // float is enough to accurately represent up to a 24-bit signed integer.
1517 SDValue AMDGPUTargetLowering::LowerDIVREM24(SDValue Op, SelectionDAG &DAG,
1518 bool Sign) const {
1519 SDLoc DL(Op);
1520 EVT VT = Op.getValueType();
1521 SDValue LHS = Op.getOperand(0);
1522 SDValue RHS = Op.getOperand(1);
1523 MVT IntVT = MVT::i32;
1524 MVT FltVT = MVT::f32;
1525
1526 unsigned LHSSignBits = DAG.ComputeNumSignBits(LHS);
1527 if (LHSSignBits < 9)
1528 return SDValue();
1529
1530 unsigned RHSSignBits = DAG.ComputeNumSignBits(RHS);
1531 if (RHSSignBits < 9)
1532 return SDValue();
1533
1534 unsigned BitSize = VT.getSizeInBits();
1535 unsigned SignBits = std::min(LHSSignBits, RHSSignBits);
1536 unsigned DivBits = BitSize - SignBits;
1537 if (Sign)
1538 ++DivBits;
1539
1540 ISD::NodeType ToFp = Sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP;
1541 ISD::NodeType ToInt = Sign ? ISD::FP_TO_SINT : ISD::FP_TO_UINT;
1542
1543 SDValue jq = DAG.getConstant(1, DL, IntVT);
1544
1545 if (Sign) {
1546 // char|short jq = ia ^ ib;
1547 jq = DAG.getNode(ISD::XOR, DL, VT, LHS, RHS);
1548
1549 // jq = jq >> (bitsize - 2)
1550 jq = DAG.getNode(ISD::SRA, DL, VT, jq,
1551 DAG.getConstant(BitSize - 2, DL, VT));
1552
1553 // jq = jq | 0x1
1554 jq = DAG.getNode(ISD::OR, DL, VT, jq, DAG.getConstant(1, DL, VT));
1555 }
1556
1557 // int ia = (int)LHS;
1558 SDValue ia = LHS;
1559
1560 // int ib, (int)RHS;
1561 SDValue ib = RHS;
1562
1563 // float fa = (float)ia;
1564 SDValue fa = DAG.getNode(ToFp, DL, FltVT, ia);
1565
1566 // float fb = (float)ib;
1567 SDValue fb = DAG.getNode(ToFp, DL, FltVT, ib);
1568
1569 SDValue fq = DAG.getNode(ISD::FMUL, DL, FltVT,
1570 fa, DAG.getNode(AMDGPUISD::RCP, DL, FltVT, fb));
1571
1572 // fq = trunc(fq);
1573 fq = DAG.getNode(ISD::FTRUNC, DL, FltVT, fq);
1574
1575 // float fqneg = -fq;
1576 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq);
1577
1578 // float fr = mad(fqneg, fb, fa);
1579 unsigned OpCode = Subtarget->hasFP32Denormals() ?
1580 (unsigned)AMDGPUISD::FMAD_FTZ :
1581 (unsigned)ISD::FMAD;
1582 SDValue fr = DAG.getNode(OpCode, DL, FltVT, fqneg, fb, fa);
1583
1584 // int iq = (int)fq;
1585 SDValue iq = DAG.getNode(ToInt, DL, IntVT, fq);
1586
1587 // fr = fabs(fr);
1588 fr = DAG.getNode(ISD::FABS, DL, FltVT, fr);
1589
1590 // fb = fabs(fb);
1591 fb = DAG.getNode(ISD::FABS, DL, FltVT, fb);
1592
1593 EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
1594
1595 // int cv = fr >= fb;
1596 SDValue cv = DAG.getSetCC(DL, SetCCVT, fr, fb, ISD::SETOGE);
1597
1598 // jq = (cv ? jq : 0);
1599 jq = DAG.getNode(ISD::SELECT, DL, VT, cv, jq, DAG.getConstant(0, DL, VT));
1600
1601 // dst = iq + jq;
1602 SDValue Div = DAG.getNode(ISD::ADD, DL, VT, iq, jq);
1603
1604 // Rem needs compensation, it's easier to recompute it
1605 SDValue Rem = DAG.getNode(ISD::MUL, DL, VT, Div, RHS);
1606 Rem = DAG.getNode(ISD::SUB, DL, VT, LHS, Rem);
1607
1608 // Truncate to number of bits this divide really is.
1609 if (Sign) {
1610 SDValue InRegSize
1611 = DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), DivBits));
1612 Div = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Div, InRegSize);
1613 Rem = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Rem, InRegSize);
1614 } else {
1615 SDValue TruncMask = DAG.getConstant((UINT64_C(1) << DivBits) - 1, DL, VT);
1616 Div = DAG.getNode(ISD::AND, DL, VT, Div, TruncMask);
1617 Rem = DAG.getNode(ISD::AND, DL, VT, Rem, TruncMask);
1618 }
1619
1620 return DAG.getMergeValues({ Div, Rem }, DL);
1621 }
1622
1623 void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op,
1624 SelectionDAG &DAG,
1625 SmallVectorImpl<SDValue> &Results) const {
1626 SDLoc DL(Op);
1627 EVT VT = Op.getValueType();
1628
1629 assert(VT == MVT::i64 && "LowerUDIVREM64 expects an i64");
1630
1631 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
1632
1633 SDValue One = DAG.getConstant(1, DL, HalfVT);
1634 SDValue Zero = DAG.getConstant(0, DL, HalfVT);
1635
1636 //HiLo split
1637 SDValue LHS = Op.getOperand(0);
1638 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, Zero);
1639 SDValue LHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, One);
1640
1641 SDValue RHS = Op.getOperand(1);
1642 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, Zero);
1643 SDValue RHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, One);
1644
1645 if (DAG.MaskedValueIsZero(RHS, APInt::getHighBitsSet(64, 32)) &&
1646 DAG.MaskedValueIsZero(LHS, APInt::getHighBitsSet(64, 32))) {
1647
1648 SDValue Res = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
1649 LHS_Lo, RHS_Lo);
1650
1651 SDValue DIV = DAG.getBuildVector(MVT::v2i32, DL, {Res.getValue(0), Zero});
1652 SDValue REM = DAG.getBuildVector(MVT::v2i32, DL, {Res.getValue(1), Zero});
1653
1654 Results.push_back(DAG.getNode(ISD::BITCAST, DL, MVT::i64, DIV));
1655 Results.push_back(DAG.getNode(ISD::BITCAST, DL, MVT::i64, REM));
1656 return;
1657 }
1658
1659 if (isTypeLegal(MVT::i64)) {
1660 // Compute denominator reciprocal.
1661 unsigned FMAD = Subtarget->hasFP32Denormals() ?
1662 (unsigned)AMDGPUISD::FMAD_FTZ :
1663 (unsigned)ISD::FMAD;
1664
1665 SDValue Cvt_Lo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, RHS_Lo);
1666 SDValue Cvt_Hi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, RHS_Hi);
1667 SDValue Mad1 = DAG.getNode(FMAD, DL, MVT::f32, Cvt_Hi,
1668 DAG.getConstantFP(APInt(32, 0x4f800000).bitsToFloat(), DL, MVT::f32),
1669 Cvt_Lo);
1670 SDValue Rcp = DAG.getNode(AMDGPUISD::RCP, DL, MVT::f32, Mad1);
1671 SDValue Mul1 = DAG.getNode(ISD::FMUL, DL, MVT::f32, Rcp,
1672 DAG.getConstantFP(APInt(32, 0x5f7ffffc).bitsToFloat(), DL, MVT::f32));
1673 SDValue Mul2 = DAG.getNode(ISD::FMUL, DL, MVT::f32, Mul1,
1674 DAG.getConstantFP(APInt(32, 0x2f800000).bitsToFloat(), DL, MVT::f32));
1675 SDValue Trunc = DAG.getNode(ISD::FTRUNC, DL, MVT::f32, Mul2);
1676 SDValue Mad2 = DAG.getNode(FMAD, DL, MVT::f32, Trunc,
1677 DAG.getConstantFP(APInt(32, 0xcf800000).bitsToFloat(), DL, MVT::f32),
1678 Mul1);
1679 SDValue Rcp_Lo = DAG.getNode(ISD::FP_TO_UINT, DL, HalfVT, Mad2);
1680 SDValue Rcp_Hi = DAG.getNode(ISD::FP_TO_UINT, DL, HalfVT, Trunc);
1681 SDValue Rcp64 = DAG.getBitcast(VT,
1682 DAG.getBuildVector(MVT::v2i32, DL, {Rcp_Lo, Rcp_Hi}));
1683
1684 SDValue Zero64 = DAG.getConstant(0, DL, VT);
1685 SDValue One64 = DAG.getConstant(1, DL, VT);
1686 SDValue Zero1 = DAG.getConstant(0, DL, MVT::i1);
1687 SDVTList HalfCarryVT = DAG.getVTList(HalfVT, MVT::i1);
1688
1689 SDValue Neg_RHS = DAG.getNode(ISD::SUB, DL, VT, Zero64, RHS);
1690 SDValue Mullo1 = DAG.getNode(ISD::MUL, DL, VT, Neg_RHS, Rcp64);
1691 SDValue Mulhi1 = DAG.getNode(ISD::MULHU, DL, VT, Rcp64, Mullo1);
1692 SDValue Mulhi1_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mulhi1,
1693 Zero);
1694 SDValue Mulhi1_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mulhi1,
1695 One);
1696
1697 SDValue Add1_Lo = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Rcp_Lo,
1698 Mulhi1_Lo, Zero1);
1699 SDValue Add1_Hi = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Rcp_Hi,
1700 Mulhi1_Hi, Add1_Lo.getValue(1));
1701 SDValue Add1_HiNc = DAG.getNode(ISD::ADD, DL, HalfVT, Rcp_Hi, Mulhi1_Hi);
1702 SDValue Add1 = DAG.getBitcast(VT,
1703 DAG.getBuildVector(MVT::v2i32, DL, {Add1_Lo, Add1_Hi}));
1704
1705 SDValue Mullo2 = DAG.getNode(ISD::MUL, DL, VT, Neg_RHS, Add1);
1706 SDValue Mulhi2 = DAG.getNode(ISD::MULHU, DL, VT, Add1, Mullo2);
1707 SDValue Mulhi2_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mulhi2,
1708 Zero);
1709 SDValue Mulhi2_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mulhi2,
1710 One);
1711
1712 SDValue Add2_Lo = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add1_Lo,
1713 Mulhi2_Lo, Zero1);
1714 SDValue Add2_HiC = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add1_HiNc,
1715 Mulhi2_Hi, Add1_Lo.getValue(1));
1716 SDValue Add2_Hi = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add2_HiC,
1717 Zero, Add2_Lo.getValue(1));
1718 SDValue Add2 = DAG.getBitcast(VT,
1719 DAG.getBuildVector(MVT::v2i32, DL, {Add2_Lo, Add2_Hi}));
1720 SDValue Mulhi3 = DAG.getNode(ISD::MULHU, DL, VT, LHS, Add2);
1721
1722 SDValue Mul3 = DAG.getNode(ISD::MUL, DL, VT, RHS, Mulhi3);
1723
1724 SDValue Mul3_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mul3, Zero);
1725 SDValue Mul3_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mul3, One);
1726 SDValue Sub1_Lo = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, LHS_Lo,
1727 Mul3_Lo, Zero1);
1728 SDValue Sub1_Hi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, LHS_Hi,
1729 Mul3_Hi, Sub1_Lo.getValue(1));
1730 SDValue Sub1_Mi = DAG.getNode(ISD::SUB, DL, HalfVT, LHS_Hi, Mul3_Hi);
1731 SDValue Sub1 = DAG.getBitcast(VT,
1732 DAG.getBuildVector(MVT::v2i32, DL, {Sub1_Lo, Sub1_Hi}));
1733
1734 SDValue MinusOne = DAG.getConstant(0xffffffffu, DL, HalfVT);
1735 SDValue C1 = DAG.getSelectCC(DL, Sub1_Hi, RHS_Hi, MinusOne, Zero,
1736 ISD::SETUGE);
1737 SDValue C2 = DAG.getSelectCC(DL, Sub1_Lo, RHS_Lo, MinusOne, Zero,
1738 ISD::SETUGE);
1739 SDValue C3 = DAG.getSelectCC(DL, Sub1_Hi, RHS_Hi, C2, C1, ISD::SETEQ);
1740
1741 // TODO: Here and below portions of the code can be enclosed into if/endif.
1742 // Currently control flow is unconditional and we have 4 selects after
1743 // potential endif to substitute PHIs.
1744
1745 // if C3 != 0 ...
1746 SDValue Sub2_Lo = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub1_Lo,
1747 RHS_Lo, Zero1);
1748 SDValue Sub2_Mi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub1_Mi,
1749 RHS_Hi, Sub1_Lo.getValue(1));
1750 SDValue Sub2_Hi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub2_Mi,
1751 Zero, Sub2_Lo.getValue(1));
1752 SDValue Sub2 = DAG.getBitcast(VT,
1753 DAG.getBuildVector(MVT::v2i32, DL, {Sub2_Lo, Sub2_Hi}));
1754
1755 SDValue Add3 = DAG.getNode(ISD::ADD, DL, VT, Mulhi3, One64);
1756
1757 SDValue C4 = DAG.getSelectCC(DL, Sub2_Hi, RHS_Hi, MinusOne, Zero,
1758 ISD::SETUGE);
1759 SDValue C5 = DAG.getSelectCC(DL, Sub2_Lo, RHS_Lo, MinusOne, Zero,
1760 ISD::SETUGE);
1761 SDValue C6 = DAG.getSelectCC(DL, Sub2_Hi, RHS_Hi, C5, C4, ISD::SETEQ);
1762
1763 // if (C6 != 0)
1764 SDValue Add4 = DAG.getNode(ISD::ADD, DL, VT, Add3, One64);
1765
1766 SDValue Sub3_Lo = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub2_Lo,
1767 RHS_Lo, Zero1);
1768 SDValue Sub3_Mi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub2_Mi,
1769 RHS_Hi, Sub2_Lo.getValue(1));
1770 SDValue Sub3_Hi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub3_Mi,
1771 Zero, Sub3_Lo.getValue(1));
1772 SDValue Sub3 = DAG.getBitcast(VT,
1773 DAG.getBuildVector(MVT::v2i32, DL, {Sub3_Lo, Sub3_Hi}));
1774
1775 // endif C6
1776 // endif C3
1777
1778 SDValue Sel1 = DAG.getSelectCC(DL, C6, Zero, Add4, Add3, ISD::SETNE);
1779 SDValue Div = DAG.getSelectCC(DL, C3, Zero, Sel1, Mulhi3, ISD::SETNE);
1780
1781 SDValue Sel2 = DAG.getSelectCC(DL, C6, Zero, Sub3, Sub2, ISD::SETNE);
1782 SDValue Rem = DAG.getSelectCC(DL, C3, Zero, Sel2, Sub1, ISD::SETNE);
1783
1784 Results.push_back(Div);
1785 Results.push_back(Rem);
1786
1787 return;
1788 }
1789
1790 // r600 expandion.
1791 // Get Speculative values
1792 SDValue DIV_Part = DAG.getNode(ISD::UDIV, DL, HalfVT, LHS_Hi, RHS_Lo);
1793 SDValue REM_Part = DAG.getNode(ISD::UREM, DL, HalfVT, LHS_Hi, RHS_Lo);
1794
1795 SDValue REM_Lo = DAG.getSelectCC(DL, RHS_Hi, Zero, REM_Part, LHS_Hi, ISD::SETEQ);
1796 SDValue REM = DAG.getBuildVector(MVT::v2i32, DL, {REM_Lo, Zero});
1797 REM = DAG.getNode(ISD::BITCAST, DL, MVT::i64, REM);
1798
1799 SDValue DIV_Hi = DAG.getSelectCC(DL, RHS_Hi, Zero, DIV_Part, Zero, ISD::SETEQ);
1800 SDValue DIV_Lo = Zero;
1801
1802 const unsigned halfBitWidth = HalfVT.getSizeInBits();
1803
1804 for (unsigned i = 0; i < halfBitWidth; ++i) {
1805 const unsigned bitPos = halfBitWidth - i - 1;
1806 SDValue POS = DAG.getConstant(bitPos, DL, HalfVT);
1807 // Get value of high bit
1808 SDValue HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS);
1809 HBit = DAG.getNode(ISD::AND, DL, HalfVT, HBit, One);
1810 HBit = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, HBit);
1811
1812 // Shift
1813 REM = DAG.getNode(ISD::SHL, DL, VT, REM, DAG.getConstant(1, DL, VT));
1814 // Add LHS high bit
1815 REM = DAG.getNode(ISD::OR, DL, VT, REM, HBit);
1816
1817 SDValue BIT = DAG.getConstant(1ULL << bitPos, DL, HalfVT);
1818 SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, Zero, ISD::SETUGE);
1819
1820 DIV_Lo = DAG.getNode(ISD::OR, DL, HalfVT, DIV_Lo, realBIT);
1821
1822 // Update REM
1823 SDValue REM_sub = DAG.getNode(ISD::SUB, DL, VT, REM, RHS);
1824 REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETUGE);
1825 }
1826
1827 SDValue DIV = DAG.getBuildVector(MVT::v2i32, DL, {DIV_Lo, DIV_Hi});
1828 DIV = DAG.getNode(ISD::BITCAST, DL, MVT::i64, DIV);
1829 Results.push_back(DIV);
1830 Results.push_back(REM);
1831 }
1832
1833 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
1834 SelectionDAG &DAG) const {
1835 SDLoc DL(Op);
1836 EVT VT = Op.getValueType();
1837
1838 if (VT == MVT::i64) {
1839 SmallVector<SDValue, 2> Results;
1840 LowerUDIVREM64(Op, DAG, Results);
1841 return DAG.getMergeValues(Results, DL);
1842 }
1843
1844 if (VT == MVT::i32) {
1845 if (SDValue Res = LowerDIVREM24(Op, DAG, false))
1846 return Res;
1847 }
1848
1849 SDValue Num = Op.getOperand(0);
1850 SDValue Den = Op.getOperand(1);
1851
1852 // RCP = URECIP(Den) = 2^32 / Den + e
1853 // e is rounding error.
1854 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
1855
1856 // RCP_LO = mul(RCP, Den) */
1857 SDValue RCP_LO = DAG.getNode(ISD::MUL, DL, VT, RCP, Den);
1858
1859 // RCP_HI = mulhu (RCP, Den) */
1860 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
1861
1862 // NEG_RCP_LO = -RCP_LO
1863 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
1864 RCP_LO);
1865
1866 // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
1867 SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, DL, VT),
1868 NEG_RCP_LO, RCP_LO,
1869 ISD::SETEQ);
1870 // Calculate the rounding error from the URECIP instruction
1871 // E = mulhu(ABS_RCP_LO, RCP)
1872 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
1873
1874 // RCP_A_E = RCP + E
1875 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
1876
1877 // RCP_S_E = RCP - E
1878 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
1879
1880 // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
1881 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, DL, VT),
1882 RCP_A_E, RCP_S_E,
1883 ISD::SETEQ);
1884 // Quotient = mulhu(Tmp0, Num)
1885 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
1886
1887 // Num_S_Remainder = Quotient * Den
1888 SDValue Num_S_Remainder = DAG.getNode(ISD::MUL, DL, VT, Quotient, Den);
1889
1890 // Remainder = Num - Num_S_Remainder
1891 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
1892
1893 // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
1894 SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
1895 DAG.getConstant(-1, DL, VT),
1896 DAG.getConstant(0, DL, VT),
1897 ISD::SETUGE);
1898 // Remainder_GE_Zero = (Num >= Num_S_Remainder ? -1 : 0)
1899 SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Num,
1900 Num_S_Remainder,
1901 DAG.getConstant(-1, DL, VT),
1902 DAG.getConstant(0, DL, VT),
1903 ISD::SETUGE);
1904 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
1905 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
1906 Remainder_GE_Zero);
1907
1908 // Calculate Division result:
1909
1910 // Quotient_A_One = Quotient + 1
1911 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
1912 DAG.getConstant(1, DL, VT));
1913
1914 // Quotient_S_One = Quotient - 1
1915 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
1916 DAG.getConstant(1, DL, VT));
1917
1918 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
1919 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, DL, VT),
1920 Quotient, Quotient_A_One, ISD::SETEQ);
1921
1922 // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
1923 Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, DL, VT),
1924 Quotient_S_One, Div, ISD::SETEQ);
1925
1926 // Calculate Rem result:
1927
1928 // Remainder_S_Den = Remainder - Den
1929 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
1930
1931 // Remainder_A_Den = Remainder + Den
1932 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
1933
1934 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
1935 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, DL, VT),
1936 Remainder, Remainder_S_Den, ISD::SETEQ);
1937
1938 // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
1939 Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, DL, VT),
1940 Remainder_A_Den, Rem, ISD::SETEQ);
1941 SDValue Ops[2] = {
1942 Div,
1943 Rem
1944 };
1945 return DAG.getMergeValues(Ops, DL);
1946 }
1947
1948 SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,
1949 SelectionDAG &DAG) const {
1950 SDLoc DL(Op);
1951 EVT VT = Op.getValueType();
1952
1953 SDValue LHS = Op.getOperand(0);
1954 SDValue RHS = Op.getOperand(1);
1955
1956 SDValue Zero = DAG.getConstant(0, DL, VT);
1957 SDValue NegOne = DAG.getConstant(-1, DL, VT);
1958
1959 if (VT == MVT::i32) {
1960 if (SDValue Res = LowerDIVREM24(Op, DAG, true))
1961 return Res;
1962 }
1963
1964 if (VT == MVT::i64 &&
1965 DAG.ComputeNumSignBits(LHS) > 32 &&
1966 DAG.ComputeNumSignBits(RHS) > 32) {
1967 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
1968
1969 //HiLo split
1970 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, Zero);
1971 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, Zero);
1972 SDValue DIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
1973 LHS_Lo, RHS_Lo);
1974 SDValue Res[2] = {
1975 DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(0)),
1976 DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(1))
1977 };
1978 return DAG.getMergeValues(Res, DL);
1979 }
1980
1981 SDValue LHSign = DAG.getSelectCC(DL, LHS, Zero, NegOne, Zero, ISD::SETLT);
1982 SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT);
1983 SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign);
1984 SDValue RSign = LHSign; // Remainder sign is the same as LHS
1985
1986 LHS = DAG.getNode(ISD::ADD, DL, VT, LHS, LHSign);
1987 RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign);
1988
1989 LHS = DAG.getNode(ISD::XOR, DL, VT, LHS, LHSign);
1990 RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign);
1991
1992 SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS);
1993 SDValue Rem = Div.getValue(1);
1994
1995 Div = DAG.getNode(ISD::XOR, DL, VT, Div, DSign);
1996 Rem = DAG.getNode(ISD::XOR, DL, VT, Rem, RSign);
1997
1998 Div = DAG.getNode(ISD::SUB, DL, VT, Div, DSign);
1999 Rem = DAG.getNode(ISD::SUB, DL, VT, Rem, RSign);
2000
2001 SDValue Res[2] = {
2002 Div,
2003 Rem
2004 };
2005 return DAG.getMergeValues(Res, DL);
2006 }
2007
2008 // (frem x, y) -> (fsub x, (fmul (ftrunc (fdiv x, y)), y))
2009 SDValue AMDGPUTargetLowering::LowerFREM(SDValue Op, SelectionDAG &DAG) const {
2010 SDLoc SL(Op);
2011 EVT VT = Op.getValueType();
2012 SDValue X = Op.getOperand(0);
2013 SDValue Y = Op.getOperand(1);
2014
2015 // TODO: Should this propagate fast-math-flags?
2016
2017 SDValue Div = DAG.getNode(ISD::FDIV, SL, VT, X, Y);
2018 SDValue Floor = DAG.getNode(ISD::FTRUNC, SL, VT, Div);
2019 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Floor, Y);
2020
2021 return DAG.getNode(ISD::FSUB, SL, VT, X, Mul);
2022 }
2023
2024 SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const {
2025 SDLoc SL(Op);
2026 SDValue Src = Op.getOperand(0);
2027
2028 // result = trunc(src)
2029 // if (src > 0.0 && src != result)
2030 // result += 1.0
2031
2032 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2033
2034 const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64);
2035 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f64);
2036
2037 EVT SetCCVT =
2038 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64);
2039
2040 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOGT);
2041 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
2042 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
2043
2044 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, One, Zero);
2045 // TODO: Should this propagate fast-math-flags?
2046 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
2047 }
2048
2049 static SDValue extractF64Exponent(SDValue Hi, const SDLoc &SL,
2050 SelectionDAG &DAG) {
2051 const unsigned FractBits = 52;
2052 const unsigned ExpBits = 11;
2053
2054 SDValue ExpPart = DAG.getNode(AMDGPUISD::BFE_U32, SL, MVT::i32,
2055 Hi,
2056 DAG.getConstant(FractBits - 32, SL, MVT::i32),
2057 DAG.getConstant(ExpBits, SL, MVT::i32));
2058 SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart,
2059 DAG.getConstant(1023, SL, MVT::i32));
2060
2061 return Exp;
2062 }
2063
2064 SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {
2065 SDLoc SL(Op);
2066 SDValue Src = Op.getOperand(0);
2067
2068 assert(Op.getValueType() == MVT::f64);
2069
2070 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
2071 const SDValue One = DAG.getConstant(1, SL, MVT::i32);
2072
2073 SDValue VecSrc = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
2074
2075 // Extract the upper half, since this is where we will find the sign and
2076 // exponent.
2077 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One);
2078
2079 SDValue Exp = extractF64Exponent(Hi, SL, DAG);
2080
2081 const unsigned FractBits = 52;
2082
2083 // Extract the sign bit.
2084 const SDValue SignBitMask = DAG.getConstant(UINT32_C(1) << 31, SL, MVT::i32);
2085 SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask);
2086
2087 // Extend back to 64-bits.
2088 SDValue SignBit64 = DAG.getBuildVector(MVT::v2i32, SL, {Zero, SignBit});
2089 SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64);
2090
2091 SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src);
2092 const SDValue FractMask
2093 = DAG.getConstant((UINT64_C(1) << FractBits) - 1, SL, MVT::i64);
2094
2095 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp);
2096 SDValue Not = DAG.getNOT(SL, Shr, MVT::i64);
2097 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not);
2098
2099 EVT SetCCVT =
2100 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i32);
2101
2102 const SDValue FiftyOne = DAG.getConstant(FractBits - 1, SL, MVT::i32);
2103
2104 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
2105 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
2106
2107 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0);
2108 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1);
2109
2110 return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2);
2111 }
2112
2113 SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {
2114 SDLoc SL(Op);
2115 SDValue Src = Op.getOperand(0);
2116
2117 assert(Op.getValueType() == MVT::f64);
2118
2119 APFloat C1Val(APFloat::IEEEdouble(), "0x1.0p+52");
2120 SDValue C1 = DAG.getConstantFP(C1Val, SL, MVT::f64);
2121 SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src);
2122
2123 // TODO: Should this propagate fast-math-flags?
2124
2125 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign);
2126 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign);
2127
2128 SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src);
2129
2130 APFloat C2Val(APFloat::IEEEdouble(), "0x1.fffffffffffffp+51");
2131 SDValue C2 = DAG.getConstantFP(C2Val, SL, MVT::f64);
2132
2133 EVT SetCCVT =
2134 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64);
2135 SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT);
2136
2137 return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2);
2138 }
2139
2140 SDValue AMDGPUTargetLowering::LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const {
2141 // FNEARBYINT and FRINT are the same, except in their handling of FP
2142 // exceptions. Those aren't really meaningful for us, and OpenCL only has
2143 // rint, so just treat them as equivalent.
2144 return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0));
2145 }
2146
2147 // XXX - May require not supporting f32 denormals?
2148
2149 // Don't handle v2f16. The extra instructions to scalarize and repack around the
2150 // compare and vselect end up producing worse code than scalarizing the whole
2151 // operation.
2152 SDValue AMDGPUTargetLowering::LowerFROUND32_16(SDValue Op, SelectionDAG &DAG) const {
2153 SDLoc SL(Op);
2154 SDValue X = Op.getOperand(0);
2155 EVT VT = Op.getValueType();
2156
2157 SDValue T = DAG.getNode(ISD::FTRUNC, SL, VT, X);
2158
2159 // TODO: Should this propagate fast-math-flags?
2160
2161 SDValue Diff = DAG.getNode(ISD::FSUB, SL, VT, X, T);
2162
2163 SDValue AbsDiff = DAG.getNode(ISD::FABS, SL, VT, Diff);
2164
2165 const SDValue Zero = DAG.getConstantFP(0.0, SL, VT);
2166 const SDValue One = DAG.getConstantFP(1.0, SL, VT);
2167 const SDValue Half = DAG.getConstantFP(0.5, SL, VT);
2168
2169 SDValue SignOne = DAG.getNode(ISD::FCOPYSIGN, SL, VT, One, X);
2170
2171 EVT SetCCVT =
2172 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
2173
2174 SDValue Cmp = DAG.getSetCC(SL, SetCCVT, AbsDiff, Half, ISD::SETOGE);
2175
2176 SDValue Sel = DAG.getNode(ISD::SELECT, SL, VT, Cmp, SignOne, Zero);
2177
2178 return DAG.getNode(ISD::FADD, SL, VT, T, Sel);
2179 }
2180
2181 SDValue AMDGPUTargetLowering::LowerFROUND64(SDValue Op, SelectionDAG &DAG) const {
2182 SDLoc SL(Op);
2183 SDValue X = Op.getOperand(0);
2184
2185 SDValue L = DAG.getNode(ISD::BITCAST, SL, MVT::i64, X);
2186
2187 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
2188 const SDValue One = DAG.getConstant(1, SL, MVT::i32);
2189 const SDValue NegOne = DAG.getConstant(-1, SL, MVT::i32);
2190 const SDValue FiftyOne = DAG.getConstant(51, SL, MVT::i32);
2191 EVT SetCCVT =
2192 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i32);
2193
2194 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, X);
2195
2196 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, One);
2197
2198 SDValue Exp = extractF64Exponent(Hi, SL, DAG);
2199
2200 const SDValue Mask = DAG.getConstant(INT64_C(0x000fffffffffffff), SL,
2201 MVT::i64);
2202
2203 SDValue M = DAG.getNode(ISD::SRA, SL, MVT::i64, Mask, Exp);
2204 SDValue D = DAG.getNode(ISD::SRA, SL, MVT::i64,
2205 DAG.getConstant(INT64_C(0x0008000000000000), SL,
2206 MVT::i64),
2207 Exp);
2208
2209 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, L, M);
2210 SDValue Tmp1 = DAG.getSetCC(SL, SetCCVT,
2211 DAG.getConstant(0, SL, MVT::i64), Tmp0,
2212 ISD::SETNE);
2213
2214 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, Tmp1,
2215 D, DAG.getConstant(0, SL, MVT::i64));
2216 SDValue K = DAG.getNode(ISD::ADD, SL, MVT::i64, L, Tmp2);
2217
2218 K = DAG.getNode(ISD::AND, SL, MVT::i64, K, DAG.getNOT(SL, M, MVT::i64));
2219 K = DAG.getNode(ISD::BITCAST, SL, MVT::f64, K);
2220
2221 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
2222 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
2223 SDValue ExpEqNegOne = DAG.getSetCC(SL, SetCCVT, NegOne, Exp, ISD::SETEQ);
2224
2225 SDValue Mag = DAG.getNode(ISD::SELECT, SL, MVT::f64,
2226 ExpEqNegOne,
2227 DAG.getConstantFP(1.0, SL, MVT::f64),
2228 DAG.getConstantFP(0.0, SL, MVT::f64));
2229
2230 SDValue S = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, Mag, X);
2231
2232 K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpLt0, S, K);
2233 K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpGt51, X, K);
2234
2235 return K;
2236 }
2237
2238 SDValue AMDGPUTargetLowering::LowerFROUND(SDValue Op, SelectionDAG &DAG) const {
2239 EVT VT = Op.getValueType();
2240
2241 if (VT == MVT::f32 || VT == MVT::f16)
2242 return LowerFROUND32_16(Op, DAG);
2243
2244 if (VT == MVT::f64)
2245 return LowerFROUND64(Op, DAG);
2246
2247 llvm_unreachable("unhandled type");
2248 }
2249
2250 SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {
2251 SDLoc SL(Op);
2252 SDValue Src = Op.getOperand(0);
2253
2254 // result = trunc(src);
2255 // if (src < 0.0 && src != result)
2256 // result += -1.0.
2257
2258 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2259
2260 const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64);
2261 const SDValue NegOne = DAG.getConstantFP(-1.0, SL, MVT::f64);
2262
2263 EVT SetCCVT =
2264 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64);
2265
2266 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOLT);
2267 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
2268 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
2269
2270 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, NegOne, Zero);
2271 // TODO: Should this propagate fast-math-flags?
2272 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
2273 }
2274
2275 SDValue AMDGPUTargetLowering::LowerFLOG(SDValue Op, SelectionDAG &DAG,
2276 double Log2BaseInverted) const {
2277 EVT VT = Op.getValueType();
2278
2279 SDLoc SL(Op);
2280 SDValue Operand = Op.getOperand(0);
2281 SDValue Log2Operand = DAG.getNode(ISD::FLOG2, SL, VT, Operand);
2282 SDValue Log2BaseInvertedOperand = DAG.getConstantFP(Log2BaseInverted, SL, VT);
2283
2284 return DAG.getNode(ISD::FMUL, SL, VT, Log2Operand, Log2BaseInvertedOperand);
2285 }
2286
2287 // Return M_LOG2E of appropriate type
2288 static SDValue getLog2EVal(SelectionDAG &DAG, const SDLoc &SL, EVT VT) {
2289 switch (VT.getScalarType().getSimpleVT().SimpleTy) {
2290 case MVT::f32:
2291 return DAG.getConstantFP(1.44269504088896340735992468100189214f, SL, VT);
2292 case MVT::f16:
2293 return DAG.getConstantFP(
2294 APFloat(APFloat::IEEEhalf(), "1.44269504088896340735992468100189214"),
2295 SL, VT);
2296 case MVT::f64:
2297 return DAG.getConstantFP(
2298 APFloat(APFloat::IEEEdouble(), "0x1.71547652b82fep+0"), SL, VT);
2299 default:
2300 llvm_unreachable("unsupported fp type");
2301 }
2302 }
2303
2304 // exp2(M_LOG2E_F * f);
2305 SDValue AMDGPUTargetLowering::lowerFEXP(SDValue Op, SelectionDAG &DAG) const {
2306 EVT VT = Op.getValueType();
2307 SDLoc SL(Op);
2308 SDValue Src = Op.getOperand(0);
2309
2310 const SDValue K = getLog2EVal(DAG, SL, VT);
2311 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Src, K, Op->getFlags());
2312 return DAG.getNode(ISD::FEXP2, SL, VT, Mul, Op->getFlags());
2313 }
2314
2315 static bool isCtlzOpc(unsigned Opc) {
2316 return Opc == ISD::CTLZ || Opc == ISD::CTLZ_ZERO_UNDEF;
2317 }
2318
2319 static bool isCttzOpc(unsigned Opc) {
2320 return Opc == ISD::CTTZ || Opc == ISD::CTTZ_ZERO_UNDEF;
2321 }
2322
2323 SDValue AMDGPUTargetLowering::LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const {
2324 SDLoc SL(Op);
2325 SDValue Src = Op.getOperand(0);
2326 bool ZeroUndef = Op.getOpcode() == ISD::CTTZ_ZERO_UNDEF ||
2327 Op.getOpcode() == ISD::CTLZ_ZERO_UNDEF;
2328
2329 unsigned ISDOpc, NewOpc;
2330 if (isCtlzOpc(Op.getOpcode())) {
2331 ISDOpc = ISD::CTLZ_ZERO_UNDEF;
2332 NewOpc = AMDGPUISD::FFBH_U32;
2333 } else if (isCttzOpc(Op.getOpcode())) {
2334 ISDOpc = ISD::CTTZ_ZERO_UNDEF;
2335 NewOpc = AMDGPUISD::FFBL_B32;
2336 } else
2337 llvm_unreachable("Unexpected OPCode!!!");
2338
2339
2340 if (ZeroUndef && Src.getValueType() == MVT::i32)
2341 return DAG.getNode(NewOpc, SL, MVT::i32, Src);
2342
2343 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
2344
2345 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
2346 const SDValue One = DAG.getConstant(1, SL, MVT::i32);
2347
2348 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero);
2349 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One);
2350
2351 EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(),
2352 *DAG.getContext(), MVT::i32);
2353
2354 SDValue HiOrLo = isCtlzOpc(Op.getOpcode()) ? Hi : Lo;
2355 SDValue Hi0orLo0 = DAG.getSetCC(SL, SetCCVT, HiOrLo, Zero, ISD::SETEQ);
2356
2357 SDValue OprLo = DAG.getNode(ISDOpc, SL, MVT::i32, Lo);
2358 SDValue OprHi = DAG.getNode(ISDOpc, SL, MVT::i32, Hi);
2359
2360 const SDValue Bits32 = DAG.getConstant(32, SL, MVT::i32);
2361 SDValue Add, NewOpr;
2362 if (isCtlzOpc(Op.getOpcode())) {
2363 Add = DAG.getNode(ISD::ADD, SL, MVT::i32, OprLo, Bits32);
2364 // ctlz(x) = hi_32(x) == 0 ? ctlz(lo_32(x)) + 32 : ctlz(hi_32(x))
2365 NewOpr = DAG.getNode(ISD::SELECT, SL, MVT::i32, Hi0orLo0, Add, OprHi);
2366 } else {
2367 Add = DAG.getNode(ISD::ADD, SL, MVT::i32, OprHi, Bits32);
2368 // cttz(x) = lo_32(x) == 0 ? cttz(hi_32(x)) + 32 : cttz(lo_32(x))
2369 NewOpr = DAG.getNode(ISD::SELECT, SL, MVT::i32, Hi0orLo0, Add, OprLo);
2370 }
2371
2372 if (!ZeroUndef) {
2373 // Test if the full 64-bit input is zero.
2374
2375 // FIXME: DAG combines turn what should be an s_and_b64 into a v_or_b32,
2376 // which we probably don't want.
2377 SDValue LoOrHi = isCtlzOpc(Op.getOpcode()) ? Lo : Hi;
2378 SDValue Lo0OrHi0 = DAG.getSetCC(SL, SetCCVT, LoOrHi, Zero, ISD::SETEQ);
2379 SDValue SrcIsZero = DAG.getNode(ISD::AND, SL, SetCCVT, Lo0OrHi0, Hi0orLo0);
2380
2381 // TODO: If i64 setcc is half rate, it can result in 1 fewer instruction
2382 // with the same cycles, otherwise it is slower.
2383 // SDValue SrcIsZero = DAG.getSetCC(SL, SetCCVT, Src,
2384 // DAG.getConstant(0, SL, MVT::i64), ISD::SETEQ);
2385
2386 const SDValue Bits32 = DAG.getConstant(64, SL, MVT::i32);
2387
2388 // The instruction returns -1 for 0 input, but the defined intrinsic
2389 // behavior is to return the number of bits.
2390 NewOpr = DAG.getNode(ISD::SELECT, SL, MVT::i32,
2391 SrcIsZero, Bits32, NewOpr);
2392 }
2393
2394 return DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i64, NewOpr);
2395 }
2396
2397 SDValue AMDGPUTargetLowering::LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG,
2398 bool Signed) const {
2399 // Unsigned
2400 // cul2f(ulong u)
2401 //{
2402 // uint lz = clz(u);
2403 // uint e = (u != 0) ? 127U + 63U - lz : 0;
2404 // u = (u << lz) & 0x7fffffffffffffffUL;
2405 // ulong t = u & 0xffffffffffUL;
2406 // uint v = (e << 23) | (uint)(u >> 40);
2407 // uint r = t > 0x8000000000UL ? 1U : (t == 0x8000000000UL ? v & 1U : 0U);
2408 // return as_float(v + r);
2409 //}
2410 // Signed
2411 // cl2f(long l)
2412 //{
2413 // long s = l >> 63;
2414 // float r = cul2f((l + s) ^ s);
2415 // return s ? -r : r;
2416 //}
2417
2418 SDLoc SL(Op);
2419 SDValue Src = Op.getOperand(0);
2420 SDValue L = Src;
2421
2422 SDValue S;
2423 if (Signed) {
2424 const SDValue SignBit = DAG.getConstant(63, SL, MVT::i64);
2425 S = DAG.getNode(ISD::SRA, SL, MVT::i64, L, SignBit);
2426
2427 SDValue LPlusS = DAG.getNode(ISD::ADD, SL, MVT::i64, L, S);
2428 L = DAG.getNode(ISD::XOR, SL, MVT::i64, LPlusS, S);
2429 }
2430
2431 EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(),
2432 *DAG.getContext(), MVT::f32);
2433
2434
2435 SDValue ZeroI32 = DAG.getConstant(0, SL, MVT::i32);
2436 SDValue ZeroI64 = DAG.getConstant(0, SL, MVT::i64);
2437 SDValue LZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SL, MVT::i64, L);
2438 LZ = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LZ);
2439
2440 SDValue K = DAG.getConstant(127U + 63U, SL, MVT::i32);
2441 SDValue E = DAG.getSelect(SL, MVT::i32,
2442 DAG.getSetCC(SL, SetCCVT, L, ZeroI64, ISD::SETNE),
2443 DAG.getNode(ISD::SUB, SL, MVT::i32, K, LZ),
2444 ZeroI32);
2445
2446 SDValue U = DAG.getNode(ISD::AND, SL, MVT::i64,
2447 DAG.getNode(ISD::SHL, SL, MVT::i64, L, LZ),
2448 DAG.getConstant((-1ULL) >> 1, SL, MVT::i64));
2449
2450 SDValue T = DAG.getNode(ISD::AND, SL, MVT::i64, U,
2451 DAG.getConstant(0xffffffffffULL, SL, MVT::i64));
2452
2453 SDValue UShl = DAG.getNode(ISD::SRL, SL, MVT::i64,
2454 U, DAG.getConstant(40, SL, MVT::i64));
2455
2456 SDValue V = DAG.getNode(ISD::OR, SL, MVT::i32,
2457 DAG.getNode(ISD::SHL, SL, MVT::i32, E, DAG.getConstant(23, SL, MVT::i32)),
2458 DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, UShl));
2459
2460 SDValue C = DAG.getConstant(0x8000000000ULL, SL, MVT::i64);
2461 SDValue RCmp = DAG.getSetCC(SL, SetCCVT, T, C, ISD::SETUGT);
2462 SDValue TCmp = DAG.getSetCC(SL, SetCCVT, T, C, ISD::SETEQ);
2463
2464 SDValue One = DAG.getConstant(1, SL, MVT::i32);
2465
2466 SDValue VTrunc1 = DAG.getNode(ISD::AND, SL, MVT::i32, V, One);
2467
2468 SDValue R = DAG.getSelect(SL, MVT::i32,
2469 RCmp,
2470 One,
2471 DAG.getSelect(SL, MVT::i32, TCmp, VTrunc1, ZeroI32));
2472 R = DAG.getNode(ISD::ADD, SL, MVT::i32, V, R);
2473 R = DAG.getNode(ISD::BITCAST, SL, MVT::f32, R);
2474
2475 if (!Signed)
2476 return R;
2477
2478 SDValue RNeg = DAG.getNode(ISD::FNEG, SL, MVT::f32, R);
2479 return DAG.getSelect(SL, MVT::f32, DAG.getSExtOrTrunc(S, SL, SetCCVT), RNeg, R);
2480 }
2481
2482 SDValue AMDGPUTargetLowering::LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG,
2483 bool Signed) const {
2484 SDLoc SL(Op);
2485 SDValue Src = Op.getOperand(0);
2486
2487 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
2488
2489 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
2490 DAG.getConstant(0, SL, MVT::i32));
2491 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
2492 DAG.getConstant(1, SL, MVT::i32));
2493
2494 SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
2495 SL, MVT::f64, Hi);
2496
2497 SDValue CvtLo = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f64, Lo);
2498
2499 SDValue LdExp = DAG.getNode(AMDGPUISD::LDEXP, SL, MVT::f64, CvtHi,
2500 DAG.getConstant(32, SL, MVT::i32));
2501 // TODO: Should this propagate fast-math-flags?
2502 return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo);
2503 }
2504
2505 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
2506 SelectionDAG &DAG) const {
2507 assert(Op.getOperand(0).getValueType() == MVT::i64 &&
2508 "operation should be legal");
2509
2510 // TODO: Factor out code common with LowerSINT_TO_FP.
2511
2512 EVT DestVT = Op.getValueType();
2513 if (Subtarget->has16BitInsts() && DestVT == MVT::f16) {
2514 SDLoc DL(Op);
2515 SDValue Src = Op.getOperand(0);
2516
2517 SDValue IntToFp32 = DAG.getNode(Op.getOpcode(), DL, MVT::f32, Src);
2518 SDValue FPRoundFlag = DAG.getIntPtrConstant(0, SDLoc(Op));
2519 SDValue FPRound =
2520 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag);
2521
2522 return FPRound;
2523 }
2524
2525 if (DestVT == MVT::f32)
2526 return LowerINT_TO_FP32(Op, DAG, false);
2527
2528 assert(DestVT == MVT::f64);
2529 return LowerINT_TO_FP64(Op, DAG, false);
2530 }
2531
2532 SDValue AMDGPUTargetLowering::LowerSINT_TO_FP(SDValue Op,
2533 SelectionDAG &DAG) const {
2534 assert(Op.getOperand(0).getValueType() == MVT::i64 &&
2535 "operation should be legal");
2536
2537 // TODO: Factor out code common with LowerUINT_TO_FP.
2538
2539 EVT DestVT = Op.getValueType();
2540 if (Subtarget->has16BitInsts() && DestVT == MVT::f16) {
2541 SDLoc DL(Op);
2542 SDValue Src = Op.getOperand(0);
2543
2544 SDValue IntToFp32 = DAG.getNode(Op.getOpcode(), DL, MVT::f32, Src);
2545 SDValue FPRoundFlag = DAG.getIntPtrConstant(0, SDLoc(Op));
2546 SDValue FPRound =
2547 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag);
2548
2549 return FPRound;
2550 }
2551
2552 if (DestVT == MVT::f32)
2553 return LowerINT_TO_FP32(Op, DAG, true);
2554
2555 assert(DestVT == MVT::f64);
2556 return LowerINT_TO_FP64(Op, DAG, true);
2557 }
2558
2559 SDValue AMDGPUTargetLowering::LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG,
2560 bool Signed) const {
2561 SDLoc SL(Op);
2562
2563 SDValue Src = Op.getOperand(0);
2564
2565 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2566
2567 SDValue K0 = DAG.getConstantFP(BitsToDouble(UINT64_C(0x3df0000000000000)), SL,
2568 MVT::f64);
2569 SDValue K1 = DAG.getConstantFP(BitsToDouble(UINT64_C(0xc1f0000000000000)), SL,
2570 MVT::f64);
2571 // TODO: Should this propagate fast-math-flags?
2572 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, Trunc, K0);
2573
2574 SDValue FloorMul = DAG.getNode(ISD::FFLOOR, SL, MVT::f64, Mul);
2575
2576
2577 SDValue Fma = DAG.getNode(ISD::FMA, SL, MVT::f64, FloorMul, K1, Trunc);
2578
2579 SDValue Hi = DAG.getNode(Signed ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, SL,
2580 MVT::i32, FloorMul);
2581 SDValue Lo = DAG.getNode(ISD::FP_TO_UINT, SL, MVT::i32, Fma);
2582
2583 SDValue Result = DAG.getBuildVector(MVT::v2i32, SL, {Lo, Hi});
2584
2585 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Result);
2586 }
2587
2588 SDValue AMDGPUTargetLowering::LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const {
2589 SDLoc DL(Op);
2590 SDValue N0 = Op.getOperand(0);
2591
2592 // Convert to target node to get known bits
2593 if (N0.getValueType() == MVT::f32)
2594 return DAG.getNode(AMDGPUISD::FP_TO_FP16, DL, Op.getValueType(), N0);
2595
2596 if (getTargetMachine().Options.UnsafeFPMath) {
2597 // There is a generic expand for FP_TO_FP16 with unsafe fast math.
2598 return SDValue();
2599 }
2600
2601 assert(N0.getSimpleValueType() == MVT::f64);
2602
2603 // f64 -> f16 conversion using round-to-nearest-even rounding mode.
2604 const unsigned ExpMask = 0x7ff;
2605 const unsigned ExpBiasf64 = 1023;
2606 const unsigned ExpBiasf16 = 15;
2607 SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
2608 SDValue One = DAG.getConstant(1, DL, MVT::i32);
2609 SDValue U = DAG.getNode(ISD::BITCAST, DL, MVT::i64, N0);
2610 SDValue UH = DAG.getNode(ISD::SRL, DL, MVT::i64, U,
2611 DAG.getConstant(32, DL, MVT::i64));
2612 UH = DAG.getZExtOrTrunc(UH, DL, MVT::i32);
2613 U = DAG.getZExtOrTrunc(U, DL, MVT::i32);
2614 SDValue E = DAG.getNode(ISD::SRL, DL, MVT::i32, UH,
2615 DAG.getConstant(20, DL, MVT::i64));
2616 E = DAG.getNode(ISD::AND, DL, MVT::i32, E,
2617 DAG.getConstant(ExpMask, DL, MVT::i32));
2618 // Subtract the fp64 exponent bias (1023) to get the real exponent and
2619 // add the f16 bias (15) to get the biased exponent for the f16 format.
2620 E = DAG.getNode(ISD::ADD, DL, MVT::i32, E,
2621 DAG.getConstant(-ExpBiasf64 + ExpBiasf16, DL, MVT::i32));
2622
2623 SDValue M = DAG.getNode(ISD::SRL, DL, MVT::i32, UH,
2624 DAG.getConstant(8, DL, MVT::i32));
2625 M = DAG.getNode(ISD::AND, DL, MVT::i32, M,
2626 DAG.getConstant(0xffe, DL, MVT::i32));
2627
2628 SDValue MaskedSig = DAG.getNode(ISD::AND, DL, MVT::i32, UH,
2629 DAG.getConstant(0x1ff, DL, MVT::i32));
2630 MaskedSig = DAG.getNode(ISD::OR, DL, MVT::i32, MaskedSig, U);
2631
2632 SDValue Lo40Set = DAG.getSelectCC(DL, MaskedSig, Zero, Zero, One, ISD::SETEQ);
2633 M = DAG.getNode(ISD::OR, DL, MVT::i32, M, Lo40Set);
2634
2635 // (M != 0 ? 0x0200 : 0) | 0x7c00;
2636 SDValue I = DAG.getNode(ISD::OR, DL, MVT::i32,
2637 DAG.getSelectCC(DL, M, Zero, DAG.getConstant(0x0200, DL, MVT::i32),
2638 Zero, ISD::SETNE), DAG.getConstant(0x7c00, DL, MVT::i32));
2639
2640 // N = M | (E << 12);
2641 SDValue N = DAG.getNode(ISD::OR, DL, MVT::i32, M,
2642 DAG.getNode(ISD::SHL, DL, MVT::i32, E,
2643 DAG.getConstant(12, DL, MVT::i32)));
2644
2645 // B = clamp(1-E, 0, 13);
2646 SDValue OneSubExp = DAG.getNode(ISD::SUB, DL, MVT::i32,
2647 One, E);
2648 SDValue B = DAG.getNode(ISD::SMAX, DL, MVT::i32, OneSubExp, Zero);
2649 B = DAG.getNode(ISD::SMIN, DL, MVT::i32, B,
2650 DAG.getConstant(13, DL, MVT::i32));
2651
2652 SDValue SigSetHigh = DAG.getNode(ISD::OR, DL, MVT::i32, M,
2653 DAG.getConstant(0x1000, DL, MVT::i32));
2654
2655 SDValue D = DAG.getNode(ISD::SRL, DL, MVT::i32, SigSetHigh, B);
2656 SDValue D0 = DAG.getNode(ISD::SHL, DL, MVT::i32, D, B);
2657 SDValue D1 = DAG.getSelectCC(DL, D0, SigSetHigh, One, Zero, ISD::SETNE);
2658 D = DAG.getNode(ISD::OR, DL, MVT::i32, D, D1);
2659
2660 SDValue V = DAG.getSelectCC(DL, E, One, D, N, ISD::SETLT);
2661 SDValue VLow3 = DAG.getNode(ISD::AND, DL, MVT::i32, V,
2662 DAG.getConstant(0x7, DL, MVT::i32));
2663 V = DAG.getNode(ISD::SRL, DL, MVT::i32, V,
2664 DAG.getConstant(2, DL, MVT::i32));
2665 SDValue V0 = DAG.getSelectCC(DL, VLow3, DAG.getConstant(3, DL, MVT::i32),
2666 One, Zero, ISD::SETEQ);
2667 SDValue V1 = DAG.getSelectCC(DL, VLow3, DAG.getConstant(5, DL, MVT::i32),
2668 One, Zero, ISD::SETGT);
2669 V1 = DAG.getNode(ISD::OR, DL, MVT::i32, V0, V1);
2670 V = DAG.getNode(ISD::ADD, DL, MVT::i32, V, V1);
2671
2672 V = DAG.getSelectCC(DL, E, DAG.getConstant(30, DL, MVT::i32),
2673 DAG.getConstant(0x7c00, DL, MVT::i32), V, ISD::SETGT);
2674 V = DAG.getSelectCC(DL, E, DAG.getConstant(1039, DL, MVT::i32),
2675 I, V, ISD::SETEQ);
2676
2677 // Extract the sign bit.
2678 SDValue Sign = DAG.getNode(ISD::SRL, DL, MVT::i32, UH,
2679 DAG.getConstant(16, DL, MVT::i32));
2680 Sign = DAG.getNode(ISD::AND, DL, MVT::i32, Sign,
2681 DAG.getConstant(0x8000, DL, MVT::i32));
2682
2683 V = DAG.getNode(ISD::OR, DL, MVT::i32, Sign, V);
2684 return DAG.getZExtOrTrunc(V, DL, Op.getValueType());
2685 }
2686
2687 SDValue AMDGPUTargetLowering::LowerFP_TO_SINT(SDValue Op,
2688 SelectionDAG &DAG) const {
2689 SDValue Src = Op.getOperand(0);
2690
2691 // TODO: Factor out code common with LowerFP_TO_UINT.
2692
2693 EVT SrcVT = Src.getValueType();
2694 if (Subtarget->has16BitInsts() && SrcVT == MVT::f16) {
2695 SDLoc DL(Op);
2696
2697 SDValue FPExtend = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, Src);
2698 SDValue FpToInt32 =
2699 DAG.getNode(Op.getOpcode(), DL, MVT::i64, FPExtend);
2700
2701 return FpToInt32;
2702 }
2703
2704 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2705 return LowerFP64_TO_INT(Op, DAG, true);
2706
2707 return SDValue();
2708 }
2709
2710 SDValue AMDGPUTargetLowering::LowerFP_TO_UINT(SDValue Op,
2711 SelectionDAG &DAG) const {
2712 SDValue Src = Op.getOperand(0);
2713
2714 // TODO: Factor out code common with LowerFP_TO_SINT.
2715
2716 EVT SrcVT = Src.getValueType();
2717 if (Subtarget->has16BitInsts() && SrcVT == MVT::f16) {
2718 SDLoc DL(Op);
2719
2720 SDValue FPExtend = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, Src);
2721 SDValue FpToInt32 =
2722 DAG.getNode(Op.getOpcode(), DL, MVT::i64, FPExtend);
2723
2724 return FpToInt32;
2725 }
2726
2727 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2728 return LowerFP64_TO_INT(Op, DAG, false);
2729
2730 return SDValue();
2731 }
2732
2733 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
2734 SelectionDAG &DAG) const {
2735 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
2736 MVT VT = Op.getSimpleValueType();
2737 MVT ScalarVT = VT.getScalarType();
2738
2739 assert(VT.isVector());
2740
2741 SDValue Src = Op.getOperand(0);
2742 SDLoc DL(Op);
2743
2744 // TODO: Don't scalarize on Evergreen?
2745 unsigned NElts = VT.getVectorNumElements();
2746 SmallVector<SDValue, 8> Args;
2747 DAG.ExtractVectorElements(Src, Args, 0, NElts);
2748
2749 SDValue VTOp = DAG.getValueType(ExtraVT.getScalarType());
2750 for (unsigned I = 0; I < NElts; ++I)
2751 Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);
2752
2753 return DAG.getBuildVector(VT, DL, Args);
2754 }
2755
2756 //===----------------------------------------------------------------------===//
2757 // Custom DAG optimizations
2758 //===----------------------------------------------------------------------===//
2759
2760 static bool isU24(SDValue Op, SelectionDAG &DAG) {
2761 return AMDGPUTargetLowering::numBitsUnsigned(Op, DAG) <= 24;
2762 }
2763
2764 static bool isI24(SDValue Op, SelectionDAG &DAG) {
2765 EVT VT = Op.getValueType();
2766 return VT.getSizeInBits() >= 24 && // Types less than 24-bit should be treated
2767 // as unsigned 24-bit values.
2768 AMDGPUTargetLowering::numBitsSigned(Op, DAG) < 24;
2769 }
2770
2771 static SDValue simplifyI24(SDNode *Node24,
2772 TargetLowering::DAGCombinerInfo &DCI) {
2773 SelectionDAG &DAG = DCI.DAG;
2774 SDValue LHS = Node24->getOperand(0);
2775 SDValue RHS = Node24->getOperand(1);
2776
2777 APInt Demanded = APInt::getLowBitsSet(LHS.getValueSizeInBits(), 24);
2778
2779 // First try to simplify using GetDemandedBits which allows the operands to
2780 // have other uses, but will only perform simplifications that involve
2781 // bypassing some nodes for this user.
2782 SDValue DemandedLHS = DAG.GetDemandedBits(LHS, Demanded);
2783 SDValue DemandedRHS = DAG.GetDemandedBits(RHS, Demanded);
2784 if (DemandedLHS || DemandedRHS)
2785 return DAG.getNode(Node24->getOpcode(), SDLoc(Node24), Node24->getVTList(),
2786 DemandedLHS ? DemandedLHS : LHS,
2787 DemandedRHS ? DemandedRHS : RHS);
2788
2789 // Now try SimplifyDemandedBits which can simplify the nodes used by our
2790 // operands if this node is the only user.
2791 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2792 if (TLI.SimplifyDemandedBits(LHS, Demanded, DCI))
2793 return SDValue(Node24, 0);
2794 if (TLI.SimplifyDemandedBits(RHS, Demanded, DCI))
2795 return SDValue(Node24, 0);
2796
2797 return SDValue();
2798 }
2799
2800 template <typename IntTy>
2801 static SDValue constantFoldBFE(SelectionDAG &DAG, IntTy Src0, uint32_t Offset,
2802 uint32_t Width, const SDLoc &DL) {
2803 if (Width + Offset < 32) {
2804 uint32_t Shl = static_cast<uint32_t>(Src0) << (32 - Offset - Width);
2805 IntTy Result = static_cast<IntTy>(Shl) >> (32 - Width);
2806 return DAG.getConstant(Result, DL, MVT::i32);
2807 }
2808
2809 return DAG.getConstant(Src0 >> Offset, DL, MVT::i32);
2810 }
2811
2812 static bool hasVolatileUser(SDNode *Val) {
2813 for (SDNode *U : Val->uses()) {
2814 if (MemSDNode *M = dyn_cast<MemSDNode>(U)) {
2815 if (M->isVolatile())
2816 return true;
2817 }
2818 }
2819
2820 return false;
2821 }
2822
2823 bool AMDGPUTargetLowering::shouldCombineMemoryType(EVT VT) const {
2824 // i32 vectors are the canonical memory type.
2825 if (VT.getScalarType() == MVT::i32 || isTypeLegal(VT))
2826 return false;
2827
2828 if (!VT.isByteSized())
2829 return false;
2830
2831 unsigned Size = VT.getStoreSize();
2832
2833 if ((Size == 1 || Size == 2 || Size == 4) && !VT.isVector())
2834 return false;
2835
2836 if (Size == 3 || (Size > 4 && (Size % 4 != 0)))
2837 return false;
2838
2839 return true;
2840 }
2841
2842 // Find a load or store from corresponding pattern root.
2843 // Roots may be build_vector, bitconvert or their combinations.
2844 static MemSDNode* findMemSDNode(SDNode *N) {
2845 N = AMDGPUTargetLowering::stripBitcast(SDValue(N,0)).getNode();
2846 if (MemSDNode *MN = dyn_cast<MemSDNode>(N))
2847 return MN;
2848 assert(isa<BuildVectorSDNode>(N));
2849 for (SDValue V : N->op_values())
2850 if (MemSDNode *MN =
2851 dyn_cast<MemSDNode>(AMDGPUTargetLowering::stripBitcast(V)))
2852 return MN;
2853 llvm_unreachable("cannot find MemSDNode in the pattern!");
2854 }
2855
2856 bool AMDGPUTargetLowering::SelectFlatOffset(bool IsSigned,
2857 SelectionDAG &DAG,
2858 SDNode *N,
2859 SDValue Addr,
2860 SDValue &VAddr,
2861 SDValue &Offset,
2862 SDValue &SLC) const {
2863 const GCNSubtarget &ST =
2864 DAG.getMachineFunction().getSubtarget<GCNSubtarget>();
2865 int64_t OffsetVal = 0;
2866
2867 if (ST.hasFlatInstOffsets() &&
2868 (!ST.hasFlatSegmentOffsetBug() ||
2869 findMemSDNode(N)->getAddressSpace() != AMDGPUAS::FLAT_ADDRESS) &&
2870 DAG.isBaseWithConstantOffset(Addr)) {
2871 SDValue N0 = Addr.getOperand(0);
2872 SDValue N1 = Addr.getOperand(1);
2873 int64_t COffsetVal = cast<ConstantSDNode>(N1)->getSExtValue();
2874
2875 const SIInstrInfo *TII = ST.getInstrInfo();
2876 if (TII->isLegalFLATOffset(COffsetVal, findMemSDNode(N)->getAddressSpace(),
2877 IsSigned)) {
2878 Addr = N0;
2879 OffsetVal = COffsetVal;
2880 }
2881 }
2882
2883 VAddr = Addr;
2884 Offset = DAG.getTargetConstant(OffsetVal, SDLoc(), MVT::i16);
2885 SLC = DAG.getTargetConstant(0, SDLoc(), MVT::i1);
2886
2887 return true;
2888 }
2889
2890 // Replace load of an illegal type with a store of a bitcast to a friendlier
2891 // type.
2892 SDValue AMDGPUTargetLowering::performLoadCombine(SDNode *N,
2893 DAGCombinerInfo &DCI) const {
2894 if (!DCI.isBeforeLegalize())
2895 return SDValue();
2896
2897 LoadSDNode *LN = cast<LoadSDNode>(N);
2898 if (LN->isVolatile() || !ISD::isNormalLoad(LN) || hasVolatileUser(LN))
2899 return SDValue();
2900
2901 SDLoc SL(N);
2902 SelectionDAG &DAG = DCI.DAG;
2903 EVT VT = LN->getMemoryVT();
2904
2905 unsigned Size = VT.getStoreSize();
2906 unsigned Align = LN->getAlignment();
2907 if (Align < Size && isTypeLegal(VT)) {
2908 bool IsFast;
2909 unsigned AS = LN->getAddressSpace();
2910
2911 // Expand unaligned loads earlier than legalization. Due to visitation order
2912 // problems during legalization, the emitted instructions to pack and unpack
2913 // the bytes again are not eliminated in the case of an unaligned copy.
2914 if (!allowsMisalignedMemoryAccesses(
2915 VT, AS, Align, LN->getMemOperand()->getFlags(), &IsFast)) {
2916 if (VT.isVector())
2917 return scalarizeVectorLoad(LN, DAG);
2918
2919 SDValue Ops[2];
2920 std::tie(Ops[0], Ops[1]) = expandUnalignedLoad(LN, DAG);
2921 return DAG.getMergeValues(Ops, SDLoc(N));
2922 }
2923
2924 if (!IsFast)
2925 return SDValue();
2926 }
2927
2928 if (!shouldCombineMemoryType(VT))
2929 return SDValue();
2930
2931 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT);
2932
2933 SDValue NewLoad
2934 = DAG.getLoad(NewVT, SL, LN->getChain(),
2935 LN->getBasePtr(), LN->getMemOperand());
2936
2937 SDValue BC = DAG.getNode(ISD::BITCAST, SL, VT, NewLoad);
2938 DCI.CombineTo(N, BC, NewLoad.getValue(1));
2939 return SDValue(N, 0);
2940 }
2941
2942 // Replace store of an illegal type with a store of a bitcast to a friendlier
2943 // type.
2944 SDValue AMDGPUTargetLowering::performStoreCombine(SDNode *N,
2945 DAGCombinerInfo &DCI) const {
2946 if (!DCI.isBeforeLegalize())
2947 return SDValue();
2948
2949 StoreSDNode *SN = cast<StoreSDNode>(N);
2950 if (SN->isVolatile() || !ISD::isNormalStore(SN))
2951 return SDValue();
2952
2953 EVT VT = SN->getMemoryVT();
2954 unsigned Size = VT.getStoreSize();
2955
2956 SDLoc SL(N);
2957 SelectionDAG &DAG = DCI.DAG;
2958 unsigned Align = SN->getAlignment();
2959 if (Align < Size && isTypeLegal(VT)) {
2960 bool IsFast;
2961 unsigned AS = SN->getAddressSpace();
2962
2963 // Expand unaligned stores earlier than legalization. Due to visitation
2964 // order problems during legalization, the emitted instructions to pack and
2965 // unpack the bytes again are not eliminated in the case of an unaligned
2966 // copy.
2967 if (!allowsMisalignedMemoryAccesses(
2968 VT, AS, Align, SN->getMemOperand()->getFlags(), &IsFast)) {
2969 if (VT.isVector())
2970 return scalarizeVectorStore(SN, DAG);
2971
2972 return expandUnalignedStore(SN, DAG);
2973 }
2974
2975 if (!IsFast)
2976 return SDValue();
2977 }
2978
2979 if (!shouldCombineMemoryType(VT))
2980 return SDValue();
2981
2982 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT);
2983 SDValue Val = SN->getValue();
2984
2985 //DCI.AddToWorklist(Val.getNode());
2986
2987 bool OtherUses = !Val.hasOneUse();
2988 SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, NewVT, Val);
2989 if (OtherUses) {
2990 SDValue CastBack = DAG.getNode(ISD::BITCAST, SL, VT, CastVal);
2991 DAG.ReplaceAllUsesOfValueWith(Val, CastBack);
2992 }
2993
2994 return DAG.getStore(SN->getChain(), SL, CastVal,
2995 SN->getBasePtr(), SN->getMemOperand());
2996 }
2997
2998 // FIXME: This should go in generic DAG combiner with an isTruncateFree check,
2999 // but isTruncateFree is inaccurate for i16 now because of SALU vs. VALU
3000 // issues.
3001 SDValue AMDGPUTargetLowering::performAssertSZExtCombine(SDNode *N,
3002 DAGCombinerInfo &DCI) const {
3003 SelectionDAG &DAG = DCI.DAG;
3004 SDValue N0 = N->getOperand(0);
3005
3006 // (vt2 (assertzext (truncate vt0:x), vt1)) ->
3007 // (vt2 (truncate (assertzext vt0:x, vt1)))
3008 if (N0.getOpcode() == ISD::TRUNCATE) {
3009 SDValue N1 = N->getOperand(1);
3010 EVT ExtVT = cast<VTSDNode>(N1)->getVT();
3011 SDLoc SL(N);
3012
3013 SDValue Src = N0.getOperand(0);
3014 EVT SrcVT = Src.getValueType();
3015 if (SrcVT.bitsGE(ExtVT)) {
3016 SDValue NewInReg = DAG.getNode(N->getOpcode(), SL, SrcVT, Src, N1);
3017 return DAG.getNode(ISD::TRUNCATE, SL, N->getValueType(0), NewInReg);
3018 }
3019 }
3020
3021 return SDValue();
3022 }
3023 /// Split the 64-bit value \p LHS into two 32-bit components, and perform the
3024 /// binary operation \p Opc to it with the corresponding constant operands.
3025 SDValue AMDGPUTargetLowering::splitBinaryBitConstantOpImpl(
3026 DAGCombinerInfo &DCI, const SDLoc &SL,
3027 unsigned Opc, SDValue LHS,
3028 uint32_t ValLo, uint32_t ValHi) const {
3029 SelectionDAG &DAG = DCI.DAG;
3030 SDValue Lo, Hi;
3031 std::tie(Lo, Hi) = split64BitValue(LHS, DAG);
3032
3033 SDValue LoRHS = DAG.getConstant(ValLo, SL, MVT::i32);
3034 SDValue HiRHS = DAG.getConstant(ValHi, SL, MVT::i32);
3035
3036 SDValue LoAnd = DAG.getNode(Opc, SL, MVT::i32, Lo, LoRHS);
3037 SDValue HiAnd = DAG.getNode(Opc, SL, MVT::i32, Hi, HiRHS);
3038
3039 // Re-visit the ands. It's possible we eliminated one of them and it could
3040 // simplify the vector.
3041 DCI.AddToWorklist(Lo.getNode());
3042 DCI.AddToWorklist(Hi.getNode());
3043
3044 SDValue Vec = DAG.getBuildVector(MVT::v2i32, SL, {LoAnd, HiAnd});
3045 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec);
3046 }
3047
3048 SDValue AMDGPUTargetLowering::performShlCombine(SDNode *N,
3049 DAGCombinerInfo &DCI) const {
3050 EVT VT = N->getValueType(0);
3051
3052 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
3053 if (!RHS)
3054 return SDValue();
3055
3056 SDValue LHS = N->getOperand(0);
3057 unsigned RHSVal = RHS->getZExtValue();
3058 if (!RHSVal)
3059 return LHS;
3060
3061 SDLoc SL(N);
3062 SelectionDAG &DAG = DCI.DAG;
3063
3064 switch (LHS->getOpcode()) {
3065 default:
3066 break;
3067 case ISD::ZERO_EXTEND:
3068 case ISD::SIGN_EXTEND:
3069 case ISD::ANY_EXTEND: {
3070 SDValue X = LHS->getOperand(0);
3071
3072 if (VT == MVT::i32 && RHSVal == 16 && X.getValueType() == MVT::i16 &&
3073 isOperationLegal(ISD::BUILD_VECTOR, MVT::v2i16)) {
3074 // Prefer build_vector as the canonical form if packed types are legal.
3075 // (shl ([asz]ext i16:x), 16 -> build_vector 0, x
3076 SDValue Vec = DAG.getBuildVector(MVT::v2i16, SL,
3077 { DAG.getConstant(0, SL, MVT::i16), LHS->getOperand(0) });
3078 return DAG.getNode(ISD::BITCAST, SL, MVT::i32, Vec);
3079 }
3080
3081 // shl (ext x) => zext (shl x), if shift does not overflow int
3082 if (VT != MVT::i64)
3083 break;
3084 KnownBits Known = DAG.computeKnownBits(X);
3085 unsigned LZ = Known.countMinLeadingZeros();
3086 if (LZ < RHSVal)
3087 break;
3088 EVT XVT = X.getValueType();
3089 SDValue Shl = DAG.getNode(ISD::SHL, SL, XVT, X, SDValue(RHS, 0));
3090 return DAG.getZExtOrTrunc(Shl, SL, VT);
3091 }
3092 }
3093
3094 if (VT != MVT::i64)
3095 return SDValue();
3096
3097 // i64 (shl x, C) -> (build_pair 0, (shl x, C -32))
3098
3099 // On some subtargets, 64-bit shift is a quarter rate instruction. In the
3100 // common case, splitting this into a move and a 32-bit shift is faster and
3101 // the same code size.
3102 if (RHSVal < 32)
3103 return SDValue();
3104
3105 SDValue ShiftAmt = DAG.getConstant(RHSVal - 32, SL, MVT::i32);
3106
3107 SDValue Lo = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LHS);
3108 SDValue NewShift = DAG.getNode(ISD::SHL, SL, MVT::i32, Lo, ShiftAmt);
3109
3110 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
3111
3112 SDValue Vec = DAG.getBuildVector(MVT::v2i32, SL, {Zero, NewShift});
3113 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec);
3114 }
3115
3116 SDValue AMDGPUTargetLowering::performSraCombine(SDNode *N,
3117 DAGCombinerInfo &DCI) const {
3118 if (N->getValueType(0) != MVT::i64)
3119 return SDValue();
3120
3121 const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
3122 if (!RHS)
3123 return SDValue();
3124
3125 SelectionDAG &DAG = DCI.DAG;
3126 SDLoc SL(N);
3127 unsigned RHSVal = RHS->getZExtValue();
3128
3129 // (sra i64:x, 32) -> build_pair x, (sra hi_32(x), 31)
3130 if (RHSVal == 32) {
3131 SDValue Hi = getHiHalf64(N->getOperand(0), DAG);
3132 SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi,
3133 DAG.getConstant(31, SL, MVT::i32));
3134
3135 SDValue BuildVec = DAG.getBuildVector(MVT::v2i32, SL, {Hi, NewShift});
3136 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildVec);
3137 }
3138
3139 // (sra i64:x, 63) -> build_pair (sra hi_32(x), 31), (sra hi_32(x), 31)
3140 if (RHSVal == 63) {
3141 SDValue Hi = getHiHalf64(N->getOperand(0), DAG);
3142 SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi,
3143 DAG.getConstant(31, SL, MVT::i32));
3144 SDValue BuildVec = DAG.getBuildVector(MVT::v2i32, SL, {NewShift, NewShift});
3145 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildVec);
3146 }
3147
3148 return SDValue();
3149 }
3150
3151 SDValue AMDGPUTargetLowering::performSrlCombine(SDNode *N,
3152 DAGCombinerInfo &DCI) const {
3153 auto *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
3154 if (!RHS)
3155 return SDValue();
3156
3157 EVT VT = N->getValueType(0);
3158 SDValue LHS = N->getOperand(0);
3159 unsigned ShiftAmt = RHS->getZExtValue();
3160 SelectionDAG &DAG = DCI.DAG;
3161 SDLoc SL(N);
3162
3163 // fold (srl (and x, c1 << c2), c2) -> (and (srl(x, c2), c1)
3164 // this improves the ability to match BFE patterns in isel.
3165 if (LHS.getOpcode() == ISD::AND) {
3166 if (auto *Mask = dyn_cast<ConstantSDNode>(LHS.getOperand(1))) {
3167 if (Mask->getAPIntValue().isShiftedMask() &&
3168 Mask->getAPIntValue().countTrailingZeros() == ShiftAmt) {
3169 return DAG.getNode(
3170 ISD::AND, SL, VT,
3171 DAG.getNode(ISD::SRL, SL, VT, LHS.getOperand(0), N->getOperand(1)),
3172 DAG.getNode(ISD::SRL, SL, VT, LHS.getOperand(1), N->getOperand(1)));
3173 }
3174 }
3175 }
3176
3177 if (VT != MVT::i64)
3178 return SDValue();
3179
3180 if (ShiftAmt < 32)
3181 return SDValue();
3182
3183 // srl i64:x, C for C >= 32
3184 // =>
3185 // build_pair (srl hi_32(x), C - 32), 0
3186 SDValue One = DAG.getConstant(1, SL, MVT::i32);
3187 SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
3188
3189 SDValue VecOp = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, LHS);
3190 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecOp, One);
3191
3192 SDValue NewConst = DAG.getConstant(ShiftAmt - 32, SL, MVT::i32);
3193 SDValue NewShift = DAG.getNode(ISD::SRL, SL, MVT::i32, Hi, NewConst);
3194
3195 SDValue BuildPair = DAG.getBuildVector(MVT::v2i32, SL, {NewShift, Zero});
3196
3197 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildPair);
3198 }
3199
3200 SDValue AMDGPUTargetLowering::performTruncateCombine(
3201 SDNode *N, DAGCombinerInfo &DCI) const {
3202 SDLoc SL(N);
3203 SelectionDAG &DAG = DCI.DAG;
3204 EVT VT = N->getValueType(0);
3205 SDValue Src = N->getOperand(0);
3206
3207 // vt1 (truncate (bitcast (build_vector vt0:x, ...))) -> vt1 (bitcast vt0:x)
3208 if (Src.getOpcode() == ISD::BITCAST && !VT.isVector()) {
3209 SDValue Vec = Src.getOperand(0);
3210 if (Vec.getOpcode() == ISD::BUILD_VECTOR) {
3211 SDValue Elt0 = Vec.getOperand(0);
3212 EVT EltVT = Elt0.getValueType();
3213 if (VT.getSizeInBits() <= EltVT.getSizeInBits()) {
3214 if (EltVT.isFloatingPoint()) {
3215 Elt0 = DAG.getNode(ISD::BITCAST, SL,
3216 EltVT.changeTypeToInteger(), Elt0);
3217 }
3218
3219 return DAG.getNode(ISD::TRUNCATE, SL, VT, Elt0);
3220 }
3221 }
3222 }
3223
3224 // Equivalent of above for accessing the high element of a vector as an
3225 // integer operation.
3226 // trunc (srl (bitcast (build_vector x, y))), 16 -> trunc (bitcast y)
3227 if (Src.getOpcode() == ISD::SRL && !VT.isVector()) {
3228 if (auto K = isConstOrConstSplat(Src.getOperand(1))) {
3229 if (2 * K->getZExtValue() == Src.getValueType().getScalarSizeInBits()) {
3230 SDValue BV = stripBitcast(Src.getOperand(0));
3231 if (BV.getOpcode() == ISD::BUILD_VECTOR &&
3232 BV.getValueType().getVectorNumElements() == 2) {
3233 SDValue SrcElt = BV.getOperand(1);
3234 EVT SrcEltVT = SrcElt.getValueType();
3235 if (SrcEltVT.isFloatingPoint()) {
3236 SrcElt = DAG.getNode(ISD::BITCAST, SL,
3237 SrcEltVT.changeTypeToInteger(), SrcElt);
3238 }
3239
3240 return DAG.getNode(ISD::TRUNCATE, SL, VT, SrcElt);
3241 }
3242 }
3243 }
3244 }
3245
3246 // Partially shrink 64-bit shifts to 32-bit if reduced to 16-bit.
3247 //
3248 // i16 (trunc (srl i64:x, K)), K <= 16 ->
3249 // i16 (trunc (srl (i32 (trunc x), K)))
3250 if (VT.getScalarSizeInBits() < 32) {
3251 EVT SrcVT = Src.getValueType();
3252 if (SrcVT.getScalarSizeInBits() > 32 &&
3253 (Src.getOpcode() == ISD::SRL ||
3254 Src.getOpcode() == ISD::SRA ||
3255 Src.getOpcode() == ISD::SHL)) {
3256 SDValue Amt = Src.getOperand(1);
3257 KnownBits Known = DAG.computeKnownBits(Amt);
3258 unsigned Size = VT.getScalarSizeInBits();
3259 if ((Known.isConstant() && Known.getConstant().ule(Size)) ||
3260 (Known.getBitWidth() - Known.countMinLeadingZeros() <= Log2_32(Size))) {
3261 EVT MidVT = VT.isVector() ?
3262 EVT::getVectorVT(*DAG.getContext(), MVT::i32,
3263 VT.getVectorNumElements()) : MVT::i32;
3264
3265 EVT NewShiftVT = getShiftAmountTy(MidVT, DAG.getDataLayout());
3266 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, MidVT,
3267 Src.getOperand(0));
3268 DCI.AddToWorklist(Trunc.getNode());
3269
3270 if (Amt.getValueType() != NewShiftVT) {
3271 Amt = DAG.getZExtOrTrunc(Amt, SL, NewShiftVT);
3272 DCI.AddToWorklist(Amt.getNode());
3273 }
3274
3275 SDValue ShrunkShift = DAG.getNode(Src.getOpcode(), SL, MidVT,
3276 Trunc, Amt);
3277 return DAG.getNode(ISD::TRUNCATE, SL, VT, ShrunkShift);
3278 }
3279 }
3280 }
3281
3282 return SDValue();
3283 }
3284
3285 // We need to specifically handle i64 mul here to avoid unnecessary conversion
3286 // instructions. If we only match on the legalized i64 mul expansion,
3287 // SimplifyDemandedBits will be unable to remove them because there will be
3288 // multiple uses due to the separate mul + mulh[su].
3289 static SDValue getMul24(SelectionDAG &DAG, const SDLoc &SL,
3290 SDValue N0, SDValue N1, unsigned Size, bool Signed) {
3291 if (Size <= 32) {
3292 unsigned MulOpc = Signed ? AMDGPUISD::MUL_I24 : AMDGPUISD::MUL_U24;
3293 return DAG.getNode(MulOpc, SL, MVT::i32, N0, N1);
3294 }
3295
3296 // Because we want to eliminate extension instructions before the
3297 // operation, we need to create a single user here (i.e. not the separate
3298 // mul_lo + mul_hi) so that SimplifyDemandedBits will deal with it.
3299
3300 unsigned MulOpc = Signed ? AMDGPUISD::MUL_LOHI_I24 : AMDGPUISD::MUL_LOHI_U24;
3301
3302 SDValue Mul = DAG.getNode(MulOpc, SL,
3303 DAG.getVTList(MVT::i32, MVT::i32), N0, N1);
3304
3305 return DAG.getNode(ISD::BUILD_PAIR, SL, MVT::i64,
3306 Mul.getValue(0), Mul.getValue(1));
3307 }
3308
3309 SDValue AMDGPUTargetLowering::performMulCombine(SDNode *N,
3310 DAGCombinerInfo &DCI) const {
3311 EVT VT = N->getValueType(0);
3312
3313 unsigned Size = VT.getSizeInBits();
3314 if (VT.isVector() || Size > 64)
3315 return SDValue();
3316
3317 // There are i16 integer mul/mad.
3318 if (Subtarget->has16BitInsts() && VT.getScalarType().bitsLE(MVT::i16))
3319 return SDValue();
3320
3321 SelectionDAG &DAG = DCI.DAG;
3322 SDLoc DL(N);
3323
3324 SDValue N0 = N->getOperand(0);
3325 SDValue N1 = N->getOperand(1);
3326
3327 // SimplifyDemandedBits has the annoying habit of turning useful zero_extends
3328 // in the source into any_extends if the result of the mul is truncated. Since
3329 // we can assume the high bits are whatever we want, use the underlying value
3330 // to avoid the unknown high bits from interfering.
3331 if (N0.getOpcode() == ISD::ANY_EXTEND)
3332 N0 = N0.getOperand(0);
3333
3334 if (N1.getOpcode() == ISD::ANY_EXTEND)
3335 N1 = N1.getOperand(0);
3336
3337 SDValue Mul;
3338
3339 if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) {
3340 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
3341 N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
3342 Mul = getMul24(DAG, DL, N0, N1, Size, false);
3343 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) {
3344 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
3345 N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
3346 Mul = getMul24(DAG, DL, N0, N1, Size, true);
3347 } else {
3348 return SDValue();
3349 }
3350
3351 // We need to use sext even for MUL_U24, because MUL_U24 is used
3352 // for signed multiply of 8 and 16-bit types.
3353 return DAG.getSExtOrTrunc(Mul, DL, VT);
3354 }
3355
3356 SDValue AMDGPUTargetLowering::performMulhsCombine(SDNode *N,
3357 DAGCombinerInfo &DCI) const {
3358 EVT VT = N->getValueType(0);
3359
3360 if (!Subtarget->hasMulI24() || VT.isVector())
3361 return SDValue();
3362
3363 SelectionDAG &DAG = DCI.DAG;
3364 SDLoc DL(N);
3365
3366 SDValue N0 = N->getOperand(0);
3367 SDValue N1 = N->getOperand(1);
3368
3369 if (!isI24(N0, DAG) || !isI24(N1, DAG))
3370 return SDValue();
3371
3372 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
3373 N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
3374
3375 SDValue Mulhi = DAG.getNode(AMDGPUISD::MULHI_I24, DL, MVT::i32, N0, N1);
3376 DCI.AddToWorklist(Mulhi.getNode());
3377 return DAG.getSExtOrTrunc(Mulhi, DL, VT);
3378 }
3379
3380 SDValue AMDGPUTargetLowering::performMulhuCombine(SDNode *N,
3381 DAGCombinerInfo &DCI) const {
3382 EVT VT = N->getValueType(0);
3383
3384 if (!Subtarget->hasMulU24() || VT.isVector() || VT.getSizeInBits() > 32)
3385 return SDValue();
3386
3387 SelectionDAG &DAG = DCI.DAG;
3388 SDLoc DL(N);
3389
3390 SDValue N0 = N->getOperand(0);
3391 SDValue N1 = N->getOperand(1);
3392
3393 if (!isU24(N0, DAG) || !isU24(N1, DAG))
3394 return SDValue();
3395
3396 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
3397 N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
3398
3399 SDValue Mulhi = DAG.getNode(AMDGPUISD::MULHI_U24, DL, MVT::i32, N0, N1);
3400 DCI.AddToWorklist(Mulhi.getNode());
3401 return DAG.getZExtOrTrunc(Mulhi, DL, VT);
3402 }
3403
3404 SDValue AMDGPUTargetLowering::performMulLoHi24Combine(
3405 SDNode *N, DAGCombinerInfo &DCI) const {
3406 SelectionDAG &DAG = DCI.DAG;
3407
3408 // Simplify demanded bits before splitting into multiple users.
3409 if (SDValue V = simplifyI24(N, DCI))
3410 return V;
3411
3412 SDValue N0 = N->getOperand(0);
3413 SDValue N1 = N->getOperand(1);
3414
3415 bool Signed = (N->getOpcode() == AMDGPUISD::MUL_LOHI_I24);
3416
3417 unsigned MulLoOpc = Signed ? AMDGPUISD::MUL_I24 : AMDGPUISD::MUL_U24;
3418 unsigned MulHiOpc = Signed ? AMDGPUISD::MULHI_I24 : AMDGPUISD::MULHI_U24;
3419
3420 SDLoc SL(N);
3421
3422 SDValue MulLo = DAG.getNode(MulLoOpc, SL, MVT::i32, N0, N1);
3423 SDValue MulHi = DAG.getNode(MulHiOpc, SL, MVT::i32, N0, N1);
3424 return DAG.getMergeValues({ MulLo, MulHi }, SL);
3425 }
3426
3427 static bool isNegativeOne(SDValue Val) {
3428 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val))
3429 return C->isAllOnesValue();
3430 return false;
3431 }
3432
3433 SDValue AMDGPUTargetLowering::getFFBX_U32(SelectionDAG &DAG,
3434 SDValue Op,
3435 const SDLoc &DL,
3436 unsigned Opc) const {
3437 EVT VT = Op.getValueType();
3438 EVT LegalVT = getTypeToTransformTo(*DAG.getContext(), VT);
3439 if (LegalVT != MVT::i32 && (Subtarget->has16BitInsts() &&
3440 LegalVT != MVT::i16))
3441 return SDValue();
3442
3443 if (VT != MVT::i32)
3444 Op = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Op);
3445
3446 SDValue FFBX = DAG.getNode(Opc, DL, MVT::i32, Op);
3447 if (VT != MVT::i32)
3448 FFBX = DAG.getNode(ISD::TRUNCATE, DL, VT, FFBX);
3449
3450 return FFBX;
3451 }
3452
3453 // The native instructions return -1 on 0 input. Optimize out a select that
3454 // produces -1 on 0.
3455 //
3456 // TODO: If zero is not undef, we could also do this if the output is compared
3457 // against the bitwidth.
3458 //
3459 // TODO: Should probably combine against FFBH_U32 instead of ctlz directly.
3460 SDValue AMDGPUTargetLowering::performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond,
3461 SDValue LHS, SDValue RHS,
3462 DAGCombinerInfo &DCI) const {
3463 ConstantSDNode *CmpRhs = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
3464 if (!CmpRhs || !CmpRhs->isNullValue())
3465 return SDValue();
3466
3467 SelectionDAG &DAG = DCI.DAG;
3468 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
3469 SDValue CmpLHS = Cond.getOperand(0);
3470
3471 unsigned Opc = isCttzOpc(RHS.getOpcode()) ? AMDGPUISD::FFBL_B32 :
3472 AMDGPUISD::FFBH_U32;
3473
3474 // select (setcc x, 0, eq), -1, (ctlz_zero_undef x) -> ffbh_u32 x
3475 // select (setcc x, 0, eq), -1, (cttz_zero_undef x) -> ffbl_u32 x
3476 if (CCOpcode == ISD::SETEQ &&
3477 (isCtlzOpc(RHS.getOpcode()) || isCttzOpc(RHS.getOpcode())) &&
3478 RHS.getOperand(0) == CmpLHS &&
3479 isNegativeOne(LHS)) {
3480 return getFFBX_U32(DAG, CmpLHS, SL, Opc);
3481 }
3482
3483 // select (setcc x, 0, ne), (ctlz_zero_undef x), -1 -> ffbh_u32 x
3484 // select (setcc x, 0, ne), (cttz_zero_undef x), -1 -> ffbl_u32 x
3485 if (CCOpcode == ISD::SETNE &&
3486 (isCtlzOpc(LHS.getOpcode()) || isCttzOpc(RHS.getOpcode())) &&
3487 LHS.getOperand(0) == CmpLHS &&
3488 isNegativeOne(RHS)) {
3489 return getFFBX_U32(DAG, CmpLHS, SL, Opc);
3490 }
3491
3492 return SDValue();
3493 }
3494
3495 static SDValue distributeOpThroughSelect(TargetLowering::DAGCombinerInfo &DCI,
3496 unsigned Op,
3497 const SDLoc &SL,
3498 SDValue Cond,
3499 SDValue N1,
3500 SDValue N2) {
3501 SelectionDAG &DAG = DCI.DAG;
3502 EVT VT = N1.getValueType();
3503
3504 SDValue NewSelect = DAG.getNode(ISD::SELECT, SL, VT, Cond,
3505 N1.getOperand(0), N2.getOperand(0));
3506 DCI.AddToWorklist(NewSelect.getNode());
3507 return DAG.getNode(Op, SL, VT, NewSelect);
3508 }
3509
3510 // Pull a free FP operation out of a select so it may fold into uses.
3511 //
3512 // select c, (fneg x), (fneg y) -> fneg (select c, x, y)
3513 // select c, (fneg x), k -> fneg (select c, x, (fneg k))
3514 //
3515 // select c, (fabs x), (fabs y) -> fabs (select c, x, y)
3516 // select c, (fabs x), +k -> fabs (select c, x, k)
3517 static SDValue foldFreeOpFromSelect(TargetLowering::DAGCombinerInfo &DCI,
3518 SDValue N) {
3519 SelectionDAG &DAG = DCI.DAG;
3520 SDValue Cond = N.getOperand(0);
3521 SDValue LHS = N.getOperand(1);
3522 SDValue RHS = N.getOperand(2);
3523
3524 EVT VT = N.getValueType();
3525 if ((LHS.getOpcode() == ISD::FABS && RHS.getOpcode() == ISD::FABS) ||
3526 (LHS.getOpcode() == ISD::FNEG && RHS.getOpcode() == ISD::FNEG)) {
3527 return distributeOpThroughSelect(DCI, LHS.getOpcode(),
3528 SDLoc(N), Cond, LHS, RHS);
3529 }
3530
3531 bool Inv = false;
3532 if (RHS.getOpcode() == ISD::FABS || RHS.getOpcode() == ISD::FNEG) {
3533 std::swap(LHS, RHS);
3534 Inv = true;
3535 }
3536
3537 // TODO: Support vector constants.
3538 ConstantFPSDNode *CRHS = dyn_cast<ConstantFPSDNode>(RHS);
3539 if ((LHS.getOpcode() == ISD::FNEG || LHS.getOpcode() == ISD::FABS) && CRHS) {
3540 SDLoc SL(N);
3541 // If one side is an fneg/fabs and the other is a constant, we can push the
3542 // fneg/fabs down. If it's an fabs, the constant needs to be non-negative.
3543 SDValue NewLHS = LHS.getOperand(0);
3544 SDValue NewRHS = RHS;
3545
3546 // Careful: if the neg can be folded up, don't try to pull it back down.
3547 bool ShouldFoldNeg = true;
3548
3549 if (NewLHS.hasOneUse()) {
3550 unsigned Opc = NewLHS.getOpcode();
3551 if (LHS.getOpcode() == ISD::FNEG && fnegFoldsIntoOp(Opc))
3552 ShouldFoldNeg = false;
3553 if (LHS.getOpcode() == ISD::FABS && Opc == ISD::FMUL)
3554 ShouldFoldNeg = false;
3555 }
3556
3557 if (ShouldFoldNeg) {
3558 if (LHS.getOpcode() == ISD::FNEG)
3559 NewRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
3560 else if (CRHS->isNegative())
3561 return SDValue();
3562
3563 if (Inv)
3564 std::swap(NewLHS, NewRHS);
3565
3566 SDValue NewSelect = DAG.getNode(ISD::SELECT, SL, VT,
3567 Cond, NewLHS, NewRHS);
3568 DCI.AddToWorklist(NewSelect.getNode());
3569 return DAG.getNode(LHS.getOpcode(), SL, VT, NewSelect);
3570 }
3571 }
3572
3573 return SDValue();
3574 }
3575
3576
3577 SDValue AMDGPUTargetLowering::performSelectCombine(SDNode *N,
3578 DAGCombinerInfo &DCI) const {
3579 if (SDValue Folded = foldFreeOpFromSelect(DCI, SDValue(N, 0)))
3580 return Folded;
3581
3582 SDValue Cond = N->getOperand(0);
3583 if (Cond.getOpcode() != ISD::SETCC)
3584 return SDValue();
3585
3586 EVT VT = N->getValueType(0);
3587 SDValue LHS = Cond.getOperand(0);
3588 SDValue RHS = Cond.getOperand(1);
3589 SDValue CC = Cond.getOperand(2);
3590
3591 SDValue True = N->getOperand(1);
3592 SDValue False = N->getOperand(2);
3593
3594 if (Cond.hasOneUse()) { // TODO: Look for multiple select uses.
3595 SelectionDAG &DAG = DCI.DAG;
3596 if (DAG.isConstantValueOfAnyType(True) &&
3597 !DAG.isConstantValueOfAnyType(False)) {
3598 // Swap cmp + select pair to move constant to false input.
3599 // This will allow using VOPC cndmasks more often.
3600 // select (setcc x, y), k, x -> select (setccinv x, y), x, k
3601
3602 SDLoc SL(N);
3603 ISD::CondCode NewCC = getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
3604 LHS.getValueType().isInteger());
3605
3606 SDValue NewCond = DAG.getSetCC(SL, Cond.getValueType(), LHS, RHS, NewCC);
3607 return DAG.getNode(ISD::SELECT, SL, VT, NewCond, False, True);
3608 }
3609
3610 if (VT == MVT::f32 && Subtarget->hasFminFmaxLegacy()) {
3611 SDValue MinMax
3612 = combineFMinMaxLegacy(SDLoc(N), VT, LHS, RHS, True, False, CC, DCI);
3613 // Revisit this node so we can catch min3/max3/med3 patterns.
3614 //DCI.AddToWorklist(MinMax.getNode());
3615 return MinMax;
3616 }
3617 }
3618
3619 // There's no reason to not do this if the condition has other uses.
3620 return performCtlz_CttzCombine(SDLoc(N), Cond, True, False, DCI);
3621 }
3622
3623 static bool isInv2Pi(const APFloat &APF) {
3624 static const APFloat KF16(APFloat::IEEEhalf(), APInt(16, 0x3118));
3625 static const APFloat KF32(APFloat::IEEEsingle(), APInt(32, 0x3e22f983));
3626 static const APFloat KF64(APFloat::IEEEdouble(), APInt(64, 0x3fc45f306dc9c882));
3627
3628 return APF.bitwiseIsEqual(KF16) ||
3629 APF.bitwiseIsEqual(KF32) ||
3630 APF.bitwiseIsEqual(KF64);
3631 }
3632
3633 // 0 and 1.0 / (0.5 * pi) do not have inline immmediates, so there is an
3634 // additional cost to negate them.
3635 bool AMDGPUTargetLowering::isConstantCostlierToNegate(SDValue N) const {
3636 if (const ConstantFPSDNode *C = isConstOrConstSplatFP(N)) {
3637 if (C->isZero() && !C->isNegative())
3638 return true;
3639
3640 if (Subtarget->hasInv2PiInlineImm() && isInv2Pi(C->getValueAPF()))
3641 return true;
3642 }
3643
3644 return false;
3645 }
3646
3647 static unsigned inverseMinMax(unsigned Opc) {
3648 switch (Opc) {
3649 case ISD::FMAXNUM:
3650 return ISD::FMINNUM;
3651 case ISD::FMINNUM:
3652 return ISD::FMAXNUM;
3653 case ISD::FMAXNUM_IEEE:
3654 return ISD::FMINNUM_IEEE;
3655 case ISD::FMINNUM_IEEE:
3656 return ISD::FMAXNUM_IEEE;
3657 case AMDGPUISD::FMAX_LEGACY:
3658 return AMDGPUISD::FMIN_LEGACY;
3659 case AMDGPUISD::FMIN_LEGACY:
3660 return AMDGPUISD::FMAX_LEGACY;
3661 default:
3662 llvm_unreachable("invalid min/max opcode");
3663 }
3664 }
3665
3666 SDValue AMDGPUTargetLowering::performFNegCombine(SDNode *N,
3667 DAGCombinerInfo &DCI) const {
3668 SelectionDAG &DAG = DCI.DAG;
3669 SDValue N0 = N->getOperand(0);
3670 EVT VT = N->getValueType(0);
3671
3672 unsigned Opc = N0.getOpcode();
3673
3674 // If the input has multiple uses and we can either fold the negate down, or
3675 // the other uses cannot, give up. This both prevents unprofitable
3676 // transformations and infinite loops: we won't repeatedly try to fold around
3677 // a negate that has no 'good' form.
3678 if (N0.hasOneUse()) {
3679 // This may be able to fold into the source, but at a code size cost. Don't
3680 // fold if the fold into the user is free.
3681 if (allUsesHaveSourceMods(N, 0))
3682 return SDValue();
3683 } else {
3684 if (fnegFoldsIntoOp(Opc) &&
3685 (allUsesHaveSourceMods(N) || !allUsesHaveSourceMods(N0.getNode())))
3686 return SDValue();
3687 }
3688
3689 SDLoc SL(N);
3690 switch (Opc) {
3691 case ISD::FADD: {
3692 if (!mayIgnoreSignedZero(N0))
3693 return SDValue();
3694
3695 // (fneg (fadd x, y)) -> (fadd (fneg x), (fneg y))
3696 SDValue LHS = N0.getOperand(0);
3697 SDValue RHS = N0.getOperand(1);
3698
3699 if (LHS.getOpcode() != ISD::FNEG)
3700 LHS = DAG.getNode(ISD::FNEG, SL, VT, LHS);
3701 else
3702 LHS = LHS.getOperand(0);
3703
3704 if (RHS.getOpcode() != ISD::FNEG)
3705 RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
3706 else
3707 RHS = RHS.getOperand(0);
3708
3709 SDValue Res = DAG.getNode(ISD::FADD, SL, VT, LHS, RHS, N0->getFlags());
3710 if (Res.getOpcode() != ISD::FADD)
3711 return SDValue(); // Op got folded away.
3712 if (!N0.hasOneUse())
3713 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
3714 return Res;
3715 }
3716 case ISD::FMUL:
3717 case AMDGPUISD::FMUL_LEGACY: {
3718 // (fneg (fmul x, y)) -> (fmul x, (fneg y))
3719 // (fneg (fmul_legacy x, y)) -> (fmul_legacy x, (fneg y))
3720 SDValue LHS = N0.getOperand(0);
3721 SDValue RHS = N0.getOperand(1);
3722
3723 if (LHS.getOpcode() == ISD::FNEG)
3724 LHS = LHS.getOperand(0);
3725 else if (RHS.getOpcode() == ISD::FNEG)
3726 RHS = RHS.getOperand(0);
3727 else
3728 RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
3729
3730 SDValue Res = DAG.getNode(Opc, SL, VT, LHS, RHS, N0->getFlags());
3731 if (Res.getOpcode() != Opc)
3732 return SDValue(); // Op got folded away.
3733 if (!N0.hasOneUse())
3734 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
3735 return Res;
3736 }
3737 case ISD::FMA:
3738 case ISD::FMAD: {
3739 if (!mayIgnoreSignedZero(N0))
3740 return SDValue();
3741
3742 // (fneg (fma x, y, z)) -> (fma x, (fneg y), (fneg z))
3743 SDValue LHS = N0.getOperand(0);
3744 SDValue MHS = N0.getOperand(1);
3745 SDValue RHS = N0.getOperand(2);
3746
3747 if (LHS.getOpcode() == ISD::FNEG)
3748 LHS = LHS.getOperand(0);
3749 else if (MHS.getOpcode() == ISD::FNEG)
3750 MHS = MHS.getOperand(0);
3751 else
3752 MHS = DAG.getNode(ISD::FNEG, SL, VT, MHS);
3753
3754 if (RHS.getOpcode() != ISD::FNEG)
3755 RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
3756 else
3757 RHS = RHS.getOperand(0);
3758
3759 SDValue Res = DAG.getNode(Opc, SL, VT, LHS, MHS, RHS);
3760 if (Res.getOpcode() != Opc)
3761 return SDValue(); // Op got folded away.
3762 if (!N0.hasOneUse())
3763 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
3764 return Res;
3765 }
3766 case ISD::FMAXNUM:
3767 case ISD::FMINNUM:
3768 case ISD::FMAXNUM_IEEE:
3769 case ISD::FMINNUM_IEEE:
3770 case AMDGPUISD::FMAX_LEGACY:
3771 case AMDGPUISD::FMIN_LEGACY: {
3772 // fneg (fmaxnum x, y) -> fminnum (fneg x), (fneg y)
3773 // fneg (fminnum x, y) -> fmaxnum (fneg x), (fneg y)
3774 // fneg (fmax_legacy x, y) -> fmin_legacy (fneg x), (fneg y)
3775 // fneg (fmin_legacy x, y) -> fmax_legacy (fneg x), (fneg y)
3776
3777 SDValue LHS = N0.getOperand(0);
3778 SDValue RHS = N0.getOperand(1);
3779
3780 // 0 doesn't have a negated inline immediate.
3781 // TODO: This constant check should be generalized to other operations.
3782 if (isConstantCostlierToNegate(RHS))
3783 return SDValue();
3784
3785 SDValue NegLHS = DAG.getNode(ISD::FNEG, SL, VT, LHS);
3786 SDValue NegRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
3787 unsigned Opposite = inverseMinMax(Opc);
3788
3789 SDValue Res = DAG.getNode(Opposite, SL, VT, NegLHS, NegRHS, N0->getFlags());
3790 if (Res.getOpcode() != Opposite)
3791 return SDValue(); // Op got folded away.
3792 if (!N0.hasOneUse())
3793 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
3794 return Res;
3795 }
3796 case AMDGPUISD::FMED3: {
3797 SDValue Ops[3];
3798 for (unsigned I = 0; I < 3; ++I)
3799 Ops[I] = DAG.getNode(ISD::FNEG, SL, VT, N0->getOperand(I), N0->getFlags());
3800
3801 SDValue Res = DAG.getNode(AMDGPUISD::FMED3, SL, VT, Ops, N0->getFlags());
3802 if (Res.getOpcode() != AMDGPUISD::FMED3)
3803 return SDValue(); // Op got folded away.
3804 if (!N0.hasOneUse())
3805 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
3806 return Res;
3807 }
3808 case ISD::FP_EXTEND:
3809 case ISD::FTRUNC:
3810 case ISD::FRINT:
3811 case ISD::FNEARBYINT: // XXX - Should fround be handled?
3812 case ISD::FSIN:
3813 case ISD::FCANONICALIZE:
3814 case AMDGPUISD::RCP:
3815 case AMDGPUISD::RCP_LEGACY:
3816 case AMDGPUISD::RCP_IFLAG:
3817 case AMDGPUISD::SIN_HW: {
3818 SDValue CvtSrc = N0.getOperand(0);
3819 if (CvtSrc.getOpcode() == ISD::FNEG) {
3820 // (fneg (fp_extend (fneg x))) -> (fp_extend x)
3821 // (fneg (rcp (fneg x))) -> (rcp x)
3822 return DAG.getNode(Opc, SL, VT, CvtSrc.getOperand(0));
3823 }
3824
3825 if (!N0.hasOneUse())
3826 return SDValue();
3827
3828 // (fneg (fp_extend x)) -> (fp_extend (fneg x))
3829 // (fneg (rcp x)) -> (rcp (fneg x))
3830 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc);
3831 return DAG.getNode(Opc, SL, VT, Neg, N0->getFlags());
3832 }
3833 case ISD::FP_ROUND: {
3834 SDValue CvtSrc = N0.getOperand(0);
3835
3836 if (CvtSrc.getOpcode() == ISD::FNEG) {
3837 // (fneg (fp_round (fneg x))) -> (fp_round x)
3838 return DAG.getNode(ISD::FP_ROUND, SL, VT,
3839 CvtSrc.getOperand(0), N0.getOperand(1));
3840 }
3841
3842 if (!N0.hasOneUse())
3843 return SDValue();
3844
3845 // (fneg (fp_round x)) -> (fp_round (fneg x))
3846 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc);
3847 return DAG.getNode(ISD::FP_ROUND, SL, VT, Neg, N0.getOperand(1));
3848 }
3849 case ISD::FP16_TO_FP: {
3850 // v_cvt_f32_f16 supports source modifiers on pre-VI targets without legal
3851 // f16, but legalization of f16 fneg ends up pulling it out of the source.
3852 // Put the fneg back as a legal source operation that can be matched later.
3853 SDLoc SL(N);
3854
3855 SDValue Src = N0.getOperand(0);
3856 EVT SrcVT = Src.getValueType();
3857
3858 // fneg (fp16_to_fp x) -> fp16_to_fp (xor x, 0x8000)
3859 SDValue IntFNeg = DAG.getNode(ISD::XOR, SL, SrcVT, Src,
3860 DAG.getConstant(0x8000, SL, SrcVT));
3861 return DAG.getNode(ISD::FP16_TO_FP, SL, N->getValueType(0), IntFNeg);
3862 }
3863 default:
3864 return SDValue();
3865 }
3866 }
3867
3868 SDValue AMDGPUTargetLowering::performFAbsCombine(SDNode *N,
3869 DAGCombinerInfo &DCI) const {
3870 SelectionDAG &DAG = DCI.DAG;
3871 SDValue N0 = N->getOperand(0);
3872
3873 if (!N0.hasOneUse())
3874 return SDValue();
3875
3876 switch (N0.getOpcode()) {
3877 case ISD::FP16_TO_FP: {
3878 assert(!Subtarget->has16BitInsts() && "should only see if f16 is illegal");
3879 SDLoc SL(N);
3880 SDValue Src = N0.getOperand(0);
3881 EVT SrcVT = Src.getValueType();
3882
3883 // fabs (fp16_to_fp x) -> fp16_to_fp (and x, 0x7fff)
3884 SDValue IntFAbs = DAG.getNode(ISD::AND, SL, SrcVT, Src,
3885 DAG.getConstant(0x7fff, SL, SrcVT));
3886 return DAG.getNode(ISD::FP16_TO_FP, SL, N->getValueType(0), IntFAbs);
3887 }
3888 default:
3889 return SDValue();
3890 }
3891 }
3892
3893 SDValue AMDGPUTargetLowering::performRcpCombine(SDNode *N,
3894 DAGCombinerInfo &DCI) const {
3895 const auto *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
3896 if (!CFP)
3897 return SDValue();
3898
3899 // XXX - Should this flush denormals?
3900 const APFloat &Val = CFP->getValueAPF();
3901 APFloat One(Val.getSemantics(), "1.0");
3902 return DCI.DAG.getConstantFP(One / Val, SDLoc(N), N->getValueType(0));
3903 }
3904
3905 SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
3906 DAGCombinerInfo &DCI) const {
3907 SelectionDAG &DAG = DCI.DAG;
3908 SDLoc DL(N);
3909
3910 switch(N->getOpcode()) {
3911 default:
3912 break;
3913 case ISD::BITCAST: {
3914 EVT DestVT = N->getValueType(0);
3915
3916 // Push casts through vector builds. This helps avoid emitting a large
3917 // number of copies when materializing floating point vector constants.
3918 //
3919 // vNt1 bitcast (vNt0 (build_vector t0:x, t0:y)) =>
3920 // vnt1 = build_vector (t1 (bitcast t0:x)), (t1 (bitcast t0:y))
3921 if (DestVT.isVector()) {
3922 SDValue Src = N->getOperand(0);
3923 if (Src.getOpcode() == ISD::BUILD_VECTOR) {
3924 EVT SrcVT = Src.getValueType();
3925 unsigned NElts = DestVT.getVectorNumElements();
3926
3927 if (SrcVT.getVectorNumElements() == NElts) {
3928 EVT DestEltVT = DestVT.getVectorElementType();
3929
3930 SmallVector<SDValue, 8> CastedElts;
3931 SDLoc SL(N);
3932 for (unsigned I = 0, E = SrcVT.getVectorNumElements(); I != E; ++I) {
3933 SDValue Elt = Src.getOperand(I);
3934 CastedElts.push_back(DAG.getNode(ISD::BITCAST, DL, DestEltVT, Elt));
3935 }
3936
3937 return DAG.getBuildVector(DestVT, SL, CastedElts);
3938 }
3939 }
3940 }
3941
3942 if (DestVT.getSizeInBits() != 64 && !DestVT.isVector())
3943 break;
3944
3945 // Fold bitcasts of constants.
3946 //
3947 // v2i32 (bitcast i64:k) -> build_vector lo_32(k), hi_32(k)
3948 // TODO: Generalize and move to DAGCombiner
3949 SDValue Src = N->getOperand(0);
3950 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Src)) {
3951 if (Src.getValueType() == MVT::i64) {
3952 SDLoc SL(N);
3953 uint64_t CVal = C->getZExtValue();
3954 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
3955 DAG.getConstant(Lo_32(CVal), SL, MVT::i32),
3956 DAG.getConstant(Hi_32(CVal), SL, MVT::i32));
3957 return DAG.getNode(ISD::BITCAST, SL, DestVT, BV);
3958 }
3959 }
3960
3961 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Src)) {
3962 const APInt &Val = C->getValueAPF().bitcastToAPInt();
3963 SDLoc SL(N);
3964 uint64_t CVal = Val.getZExtValue();
3965 SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
3966 DAG.getConstant(Lo_32(CVal), SL, MVT::i32),
3967 DAG.getConstant(Hi_32(CVal), SL, MVT::i32));
3968
3969 return DAG.getNode(ISD::BITCAST, SL, DestVT, Vec);
3970 }
3971
3972 break;
3973 }
3974 case ISD::SHL: {
3975 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
3976 break;
3977
3978 return performShlCombine(N, DCI);
3979 }
3980 case ISD::SRL: {
3981 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
3982 break;
3983
3984 return performSrlCombine(N, DCI);
3985 }
3986 case ISD::SRA: {
3987 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
3988 break;
3989
3990 return performSraCombine(N, DCI);
3991 }
3992 case ISD::TRUNCATE:
3993 return performTruncateCombine(N, DCI);
3994 case ISD::MUL:
3995 return performMulCombine(N, DCI);
3996 case ISD::MULHS:
3997 return performMulhsCombine(N, DCI);
3998 case ISD::MULHU:
3999 return performMulhuCombine(N, DCI);
4000 case AMDGPUISD::MUL_I24:
4001 case AMDGPUISD::MUL_U24:
4002 case AMDGPUISD::MULHI_I24:
4003 case AMDGPUISD::MULHI_U24: {
4004 if (SDValue V = simplifyI24(N, DCI))
4005 return V;
4006 return SDValue();
4007 }
4008 case AMDGPUISD::MUL_LOHI_I24:
4009 case AMDGPUISD::MUL_LOHI_U24:
4010 return performMulLoHi24Combine(N, DCI);
4011 case ISD::SELECT:
4012 return performSelectCombine(N, DCI);
4013 case ISD::FNEG:
4014 return performFNegCombine(N, DCI);
4015 case ISD::FABS:
4016 return performFAbsCombine(N, DCI);
4017 case AMDGPUISD::BFE_I32:
4018 case AMDGPUISD::BFE_U32: {
4019 assert(!N->getValueType(0).isVector() &&
4020 "Vector handling of BFE not implemented");
4021 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
4022 if (!Width)
4023 break;
4024
4025 uint32_t WidthVal = Width->getZExtValue() & 0x1f;
4026 if (WidthVal == 0)
4027 return DAG.getConstant(0, DL, MVT::i32);
4028
4029 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
4030 if (!Offset)
4031 break;
4032
4033 SDValue BitsFrom = N->getOperand(0);
4034 uint32_t OffsetVal = Offset->getZExtValue() & 0x1f;
4035
4036 bool Signed = N->getOpcode() == AMDGPUISD::BFE_I32;
4037
4038 if (OffsetVal == 0) {
4039 // This is already sign / zero extended, so try to fold away extra BFEs.
4040 unsigned SignBits = Signed ? (32 - WidthVal + 1) : (32 - WidthVal);
4041
4042 unsigned OpSignBits = DAG.ComputeNumSignBits(BitsFrom);
4043 if (OpSignBits >= SignBits)
4044 return BitsFrom;
4045
4046 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), WidthVal);
4047 if (Signed) {
4048 // This is a sign_extend_inreg. Replace it to take advantage of existing
4049 // DAG Combines. If not eliminated, we will match back to BFE during
4050 // selection.
4051
4052 // TODO: The sext_inreg of extended types ends, although we can could
4053 // handle them in a single BFE.
4054 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom,
4055 DAG.getValueType(SmallVT));
4056 }
4057
4058 return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT);
4059 }
4060
4061 if (ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(BitsFrom)) {
4062 if (Signed) {
4063 return constantFoldBFE<int32_t>(DAG,
4064 CVal->getSExtValue(),
4065 OffsetVal,
4066 WidthVal,
4067 DL);
4068 }
4069
4070 return constantFoldBFE<uint32_t>(DAG,
4071 CVal->getZExtValue(),
4072 OffsetVal,
4073 WidthVal,
4074 DL);
4075 }
4076
4077 if ((OffsetVal + WidthVal) >= 32 &&
4078 !(Subtarget->hasSDWA() && OffsetVal == 16 && WidthVal == 16)) {
4079 SDValue ShiftVal = DAG.getConstant(OffsetVal, DL, MVT::i32);
4080 return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32,
4081 BitsFrom, ShiftVal);
4082 }
4083
4084 if (BitsFrom.hasOneUse()) {
4085 APInt Demanded = APInt::getBitsSet(32,
4086 OffsetVal,
4087 OffsetVal + WidthVal);
4088
4089 KnownBits Known;
4090 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
4091 !DCI.isBeforeLegalizeOps());
4092 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4093 if (TLI.ShrinkDemandedConstant(BitsFrom, Demanded, TLO) ||
4094 TLI.SimplifyDemandedBits(BitsFrom, Demanded, Known, TLO)) {
4095 DCI.CommitTargetLoweringOpt(TLO);
4096 }
4097 }
4098
4099 break;
4100 }
4101 case ISD::LOAD:
4102 return performLoadCombine(N, DCI);
4103 case ISD::STORE:
4104 return performStoreCombine(N, DCI);
4105 case AMDGPUISD::RCP:
4106 case AMDGPUISD::RCP_IFLAG:
4107 return performRcpCombine(N, DCI);
4108 case ISD::AssertZext:
4109 case ISD::AssertSext:
4110 return performAssertSZExtCombine(N, DCI);
4111 }
4112 return SDValue();
4113 }
4114
4115 //===----------------------------------------------------------------------===//
4116 // Helper functions
4117 //===----------------------------------------------------------------------===//
4118
4119 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
4120 const TargetRegisterClass *RC,
4121 unsigned Reg, EVT VT,
4122 const SDLoc &SL,
4123 bool RawReg) const {
4124 MachineFunction &MF = DAG.getMachineFunction();
4125 MachineRegisterInfo &MRI = MF.getRegInfo();
4126 unsigned VReg;
4127
4128 if (!MRI.isLiveIn(Reg)) {
4129 VReg = MRI.createVirtualRegister(RC);
4130 MRI.addLiveIn(Reg, VReg);
4131 } else {
4132 VReg = MRI.getLiveInVirtReg(Reg);
4133 }
4134
4135 if (RawReg)
4136 return DAG.getRegister(VReg, VT);
4137
4138 return DAG.getCopyFromReg(DAG.getEntryNode(), SL, VReg, VT);
4139 }
4140
4141 SDValue AMDGPUTargetLowering::loadStackInputValue(SelectionDAG &DAG,
4142 EVT VT,
4143 const SDLoc &SL,
4144 int64_t Offset) const {
4145 MachineFunction &MF = DAG.getMachineFunction();
4146 MachineFrameInfo &MFI = MF.getFrameInfo();
4147
4148 int FI = MFI.CreateFixedObject(VT.getStoreSize(), Offset, true);
4149 auto SrcPtrInfo = MachinePointerInfo::getStack(MF, Offset);
4150 SDValue Ptr = DAG.getFrameIndex(FI, MVT::i32);
4151
4152 return DAG.getLoad(VT, SL, DAG.getEntryNode(), Ptr, SrcPtrInfo, 4,
4153 MachineMemOperand::MODereferenceable |
4154 MachineMemOperand::MOInvariant);
4155 }
4156
4157 SDValue AMDGPUTargetLowering::storeStackInputValue(SelectionDAG &DAG,
4158 const SDLoc &SL,
4159 SDValue Chain,
4160 SDValue ArgVal,
4161 int64_t Offset) const {
4162 MachineFunction &MF = DAG.getMachineFunction();
4163 MachinePointerInfo DstInfo = MachinePointerInfo::getStack(MF, Offset);
4164
4165 SDValue Ptr = DAG.getConstant(Offset, SL, MVT::i32);
4166 SDValue Store = DAG.getStore(Chain, SL, ArgVal, Ptr, DstInfo, 4,
4167 MachineMemOperand::MODereferenceable);
4168 return Store;
4169 }
4170
4171 SDValue AMDGPUTargetLowering::loadInputValue(SelectionDAG &DAG,
4172 const TargetRegisterClass *RC,
4173 EVT VT, const SDLoc &SL,
4174 const ArgDescriptor &Arg) const {
4175 assert(Arg && "Attempting to load missing argument");
4176
4177 SDValue V = Arg.isRegister() ?
4178 CreateLiveInRegister(DAG, RC, Arg.getRegister(), VT, SL) :
4179 loadStackInputValue(DAG, VT, SL, Arg.getStackOffset());
4180
4181 if (!Arg.isMasked())
4182 return V;
4183
4184 unsigned Mask = Arg.getMask();
4185 unsigned Shift = countTrailingZeros<unsigned>(Mask);
4186 V = DAG.getNode(ISD::SRL, SL, VT, V,
4187 DAG.getShiftAmountConstant(Shift, VT, SL));
4188 return DAG.getNode(ISD::AND, SL, VT, V,
4189 DAG.getConstant(Mask >> Shift, SL, VT));
4190 }
4191
4192 uint32_t AMDGPUTargetLowering::getImplicitParameterOffset(
4193 const MachineFunction &MF, const ImplicitParameter Param) const {
4194 const AMDGPUMachineFunction *MFI = MF.getInfo<AMDGPUMachineFunction>();
4195 const AMDGPUSubtarget &ST =
4196 AMDGPUSubtarget::get(getTargetMachine(), MF.getFunction());
4197 unsigned ExplicitArgOffset = ST.getExplicitKernelArgOffset(MF.getFunction());
4198 unsigned Alignment = ST.getAlignmentForImplicitArgPtr();
4199 uint64_t ArgOffset = alignTo(MFI->getExplicitKernArgSize(), Alignment) +
4200 ExplicitArgOffset;
4201 switch (Param) {
4202 case GRID_DIM:
4203 return ArgOffset;
4204 case GRID_OFFSET:
4205 return ArgOffset + 4;
4206 }
4207 llvm_unreachable("unexpected implicit parameter type");
4208 }
4209
4210 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
4211
4212 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
4213 switch ((AMDGPUISD::NodeType)Opcode) {
4214 case AMDGPUISD::FIRST_NUMBER: break;
4215 // AMDIL DAG nodes
4216 NODE_NAME_CASE(UMUL);
4217 NODE_NAME_CASE(BRANCH_COND);
4218
4219 // AMDGPU DAG nodes
4220 NODE_NAME_CASE(IF)
4221 NODE_NAME_CASE(ELSE)
4222 NODE_NAME_CASE(LOOP)
4223 NODE_NAME_CASE(CALL)
4224 NODE_NAME_CASE(TC_RETURN)
4225 NODE_NAME_CASE(TRAP)
4226 NODE_NAME_CASE(RET_FLAG)
4227 NODE_NAME_CASE(RETURN_TO_EPILOG)
4228 NODE_NAME_CASE(ENDPGM)
4229 NODE_NAME_CASE(DWORDADDR)
4230 NODE_NAME_CASE(FRACT)
4231 NODE_NAME_CASE(SETCC)
4232 NODE_NAME_CASE(SETREG)
4233 NODE_NAME_CASE(DENORM_MODE)
4234 NODE_NAME_CASE(FMA_W_CHAIN)
4235 NODE_NAME_CASE(FMUL_W_CHAIN)
4236 NODE_NAME_CASE(CLAMP)
4237 NODE_NAME_CASE(COS_HW)
4238 NODE_NAME_CASE(SIN_HW)
4239 NODE_NAME_CASE(FMAX_LEGACY)
4240 NODE_NAME_CASE(FMIN_LEGACY)
4241 NODE_NAME_CASE(FMAX3)
4242 NODE_NAME_CASE(SMAX3)
4243 NODE_NAME_CASE(UMAX3)
4244 NODE_NAME_CASE(FMIN3)
4245 NODE_NAME_CASE(SMIN3)
4246 NODE_NAME_CASE(UMIN3)
4247 NODE_NAME_CASE(FMED3)
4248 NODE_NAME_CASE(SMED3)
4249 NODE_NAME_CASE(UMED3)
4250 NODE_NAME_CASE(FDOT2)
4251 NODE_NAME_CASE(URECIP)
4252 NODE_NAME_CASE(DIV_SCALE)
4253 NODE_NAME_CASE(DIV_FMAS)
4254 NODE_NAME_CASE(DIV_FIXUP)
4255 NODE_NAME_CASE(FMAD_FTZ)
4256 NODE_NAME_CASE(TRIG_PREOP)
4257 NODE_NAME_CASE(RCP)
4258 NODE_NAME_CASE(RSQ)
4259 NODE_NAME_CASE(RCP_LEGACY)
4260 NODE_NAME_CASE(RSQ_LEGACY)
4261 NODE_NAME_CASE(RCP_IFLAG)
4262 NODE_NAME_CASE(FMUL_LEGACY)
4263 NODE_NAME_CASE(RSQ_CLAMP)
4264 NODE_NAME_CASE(LDEXP)
4265 NODE_NAME_CASE(FP_CLASS)
4266 NODE_NAME_CASE(DOT4)
4267 NODE_NAME_CASE(CARRY)
4268 NODE_NAME_CASE(BORROW)
4269 NODE_NAME_CASE(BFE_U32)
4270 NODE_NAME_CASE(BFE_I32)
4271 NODE_NAME_CASE(BFI)
4272 NODE_NAME_CASE(BFM)
4273 NODE_NAME_CASE(FFBH_U32)
4274 NODE_NAME_CASE(FFBH_I32)
4275 NODE_NAME_CASE(FFBL_B32)
4276 NODE_NAME_CASE(MUL_U24)
4277 NODE_NAME_CASE(MUL_I24)
4278 NODE_NAME_CASE(MULHI_U24)
4279 NODE_NAME_CASE(MULHI_I24)
4280 NODE_NAME_CASE(MUL_LOHI_U24)
4281 NODE_NAME_CASE(MUL_LOHI_I24)
4282 NODE_NAME_CASE(MAD_U24)
4283 NODE_NAME_CASE(MAD_I24)
4284 NODE_NAME_CASE(MAD_I64_I32)
4285 NODE_NAME_CASE(MAD_U64_U32)
4286 NODE_NAME_CASE(PERM)
4287 NODE_NAME_CASE(TEXTURE_FETCH)
4288 NODE_NAME_CASE(EXPORT)
4289 NODE_NAME_CASE(EXPORT_DONE)
4290 NODE_NAME_CASE(R600_EXPORT)
4291 NODE_NAME_CASE(CONST_ADDRESS)
4292 NODE_NAME_CASE(REGISTER_LOAD)
4293 NODE_NAME_CASE(REGISTER_STORE)
4294 NODE_NAME_CASE(SAMPLE)
4295 NODE_NAME_CASE(SAMPLEB)
4296 NODE_NAME_CASE(SAMPLED)
4297 NODE_NAME_CASE(SAMPLEL)
4298 NODE_NAME_CASE(CVT_F32_UBYTE0)
4299 NODE_NAME_CASE(CVT_F32_UBYTE1)
4300 NODE_NAME_CASE(CVT_F32_UBYTE2)
4301 NODE_NAME_CASE(CVT_F32_UBYTE3)
4302 NODE_NAME_CASE(CVT_PKRTZ_F16_F32)
4303 NODE_NAME_CASE(CVT_PKNORM_I16_F32)
4304 NODE_NAME_CASE(CVT_PKNORM_U16_F32)
4305 NODE_NAME_CASE(CVT_PK_I16_I32)
4306 NODE_NAME_CASE(CVT_PK_U16_U32)
4307 NODE_NAME_CASE(FP_TO_FP16)
4308 NODE_NAME_CASE(FP16_ZEXT)
4309 NODE_NAME_CASE(BUILD_VERTICAL_VECTOR)
4310 NODE_NAME_CASE(CONST_DATA_PTR)
4311 NODE_NAME_CASE(PC_ADD_REL_OFFSET)
4312 NODE_NAME_CASE(LDS)
4313 NODE_NAME_CASE(KILL)
4314 NODE_NAME_CASE(DUMMY_CHAIN)
4315 case AMDGPUISD::FIRST_MEM_OPCODE_NUMBER: break;
4316 NODE_NAME_CASE(INIT_EXEC)
4317 NODE_NAME_CASE(INIT_EXEC_FROM_INPUT)
4318 NODE_NAME_CASE(SENDMSG)
4319 NODE_NAME_CASE(SENDMSGHALT)
4320 NODE_NAME_CASE(INTERP_MOV)
4321 NODE_NAME_CASE(INTERP_P1)
4322 NODE_NAME_CASE(INTERP_P2)
4323 NODE_NAME_CASE(INTERP_P1LL_F16)
4324 NODE_NAME_CASE(INTERP_P1LV_F16)
4325 NODE_NAME_CASE(INTERP_P2_F16)
4326 NODE_NAME_CASE(LOAD_D16_HI)
4327 NODE_NAME_CASE(LOAD_D16_LO)
4328 NODE_NAME_CASE(LOAD_D16_HI_I8)
4329 NODE_NAME_CASE(LOAD_D16_HI_U8)
4330 NODE_NAME_CASE(LOAD_D16_LO_I8)
4331 NODE_NAME_CASE(LOAD_D16_LO_U8)
4332 NODE_NAME_CASE(STORE_MSKOR)
4333 NODE_NAME_CASE(LOAD_CONSTANT)
4334 NODE_NAME_CASE(TBUFFER_STORE_FORMAT)
4335 NODE_NAME_CASE(TBUFFER_STORE_FORMAT_D16)
4336 NODE_NAME_CASE(TBUFFER_LOAD_FORMAT)
4337 NODE_NAME_CASE(TBUFFER_LOAD_FORMAT_D16)
4338 NODE_NAME_CASE(DS_ORDERED_COUNT)
4339 NODE_NAME_CASE(ATOMIC_CMP_SWAP)
4340 NODE_NAME_CASE(ATOMIC_INC)
4341 NODE_NAME_CASE(ATOMIC_DEC)
4342 NODE_NAME_CASE(ATOMIC_LOAD_FMIN)
4343 NODE_NAME_CASE(ATOMIC_LOAD_FMAX)
4344 NODE_NAME_CASE(BUFFER_LOAD)
4345 NODE_NAME_CASE(BUFFER_LOAD_UBYTE)
4346 NODE_NAME_CASE(BUFFER_LOAD_USHORT)
4347 NODE_NAME_CASE(BUFFER_LOAD_BYTE)
4348 NODE_NAME_CASE(BUFFER_LOAD_SHORT)
4349 NODE_NAME_CASE(BUFFER_LOAD_FORMAT)
4350 NODE_NAME_CASE(BUFFER_LOAD_FORMAT_D16)
4351 NODE_NAME_CASE(SBUFFER_LOAD)
4352 NODE_NAME_CASE(BUFFER_STORE)
4353 NODE_NAME_CASE(BUFFER_STORE_BYTE)
4354 NODE_NAME_CASE(BUFFER_STORE_SHORT)
4355 NODE_NAME_CASE(BUFFER_STORE_FORMAT)
4356 NODE_NAME_CASE(BUFFER_STORE_FORMAT_D16)
4357 NODE_NAME_CASE(BUFFER_ATOMIC_SWAP)
4358 NODE_NAME_CASE(BUFFER_ATOMIC_ADD)
4359 NODE_NAME_CASE(BUFFER_ATOMIC_SUB)
4360 NODE_NAME_CASE(BUFFER_ATOMIC_SMIN)
4361 NODE_NAME_CASE(BUFFER_ATOMIC_UMIN)
4362 NODE_NAME_CASE(BUFFER_ATOMIC_SMAX)
4363 NODE_NAME_CASE(BUFFER_ATOMIC_UMAX)
4364 NODE_NAME_CASE(BUFFER_ATOMIC_AND)
4365 NODE_NAME_CASE(BUFFER_ATOMIC_OR)
4366 NODE_NAME_CASE(BUFFER_ATOMIC_XOR)
4367 NODE_NAME_CASE(BUFFER_ATOMIC_INC)
4368 NODE_NAME_CASE(BUFFER_ATOMIC_DEC)
4369 NODE_NAME_CASE(BUFFER_ATOMIC_CMPSWAP)
4370 NODE_NAME_CASE(BUFFER_ATOMIC_FADD)
4371 NODE_NAME_CASE(BUFFER_ATOMIC_PK_FADD)
4372 NODE_NAME_CASE(ATOMIC_FADD)
4373 NODE_NAME_CASE(ATOMIC_PK_FADD)
4374
4375 case AMDGPUISD::LAST_AMDGPU_ISD_NUMBER: break;
4376 }
4377 return nullptr;
4378 }
4379
4380 SDValue AMDGPUTargetLowering::getSqrtEstimate(SDValue Operand,
4381 SelectionDAG &DAG, int Enabled,
4382 int &RefinementSteps,
4383 bool &UseOneConstNR,
4384 bool Reciprocal) const {
4385 EVT VT = Operand.getValueType();
4386
4387 if (VT == MVT::f32) {
4388 RefinementSteps = 0;
4389 return DAG.getNode(AMDGPUISD::RSQ, SDLoc(Operand), VT, Operand);
4390 }
4391
4392 // TODO: There is also f64 rsq instruction, but the documentation is less
4393 // clear on its precision.
4394
4395 return SDValue();
4396 }
4397
4398 SDValue AMDGPUTargetLowering::getRecipEstimate(SDValue Operand,
4399 SelectionDAG &DAG, int Enabled,
4400 int &RefinementSteps) const {
4401 EVT VT = Operand.getValueType();
4402
4403 if (VT == MVT::f32) {
4404 // Reciprocal, < 1 ulp error.
4405 //
4406 // This reciprocal approximation converges to < 0.5 ulp error with one
4407 // newton rhapson performed with two fused multiple adds (FMAs).
4408
4409 RefinementSteps = 0;
4410 return DAG.getNode(AMDGPUISD::RCP, SDLoc(Operand), VT, Operand);
4411 }
4412
4413 // TODO: There is also f64 rcp instruction, but the documentation is less
4414 // clear on its precision.
4415
4416 return SDValue();
4417 }
4418
4419 void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
4420 const SDValue Op, KnownBits &Known,
4421 const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const {
4422
4423 Known.resetAll(); // Don't know anything.
4424
4425 unsigned Opc = Op.getOpcode();
4426
4427 switch (Opc) {
4428 default:
4429 break;
4430 case AMDGPUISD::CARRY:
4431 case AMDGPUISD::BORROW: {
4432 Known.Zero = APInt::getHighBitsSet(32, 31);
4433 break;
4434 }
4435
4436 case AMDGPUISD::BFE_I32:
4437 case AMDGPUISD::BFE_U32: {
4438 ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2));
4439 if (!CWidth)
4440 return;
4441
4442 uint32_t Width = CWidth->getZExtValue() & 0x1f;
4443
4444 if (Opc == AMDGPUISD::BFE_U32)
4445 Known.Zero = APInt::getHighBitsSet(32, 32 - Width);
4446
4447 break;
4448 }
4449 case AMDGPUISD::FP_TO_FP16:
4450 case AMDGPUISD::FP16_ZEXT: {
4451 unsigned BitWidth = Known.getBitWidth();
4452
4453 // High bits are zero.
4454 Known.Zero = APInt::getHighBitsSet(BitWidth, BitWidth - 16);
4455 break;
4456 }
4457 case AMDGPUISD::MUL_U24:
4458 case AMDGPUISD::MUL_I24: {
4459 KnownBits LHSKnown = DAG.computeKnownBits(Op.getOperand(0), Depth + 1);
4460 KnownBits RHSKnown = DAG.computeKnownBits(Op.getOperand(1), Depth + 1);
4461 unsigned TrailZ = LHSKnown.countMinTrailingZeros() +
4462 RHSKnown.countMinTrailingZeros();
4463 Known.Zero.setLowBits(std::min(TrailZ, 32u));
4464
4465 // Truncate to 24 bits.
4466 LHSKnown = LHSKnown.trunc(24);
4467 RHSKnown = RHSKnown.trunc(24);
4468
4469 bool Negative = false;
4470 if (Opc == AMDGPUISD::MUL_I24) {
4471 unsigned LHSValBits = 24 - LHSKnown.countMinSignBits();
4472 unsigned RHSValBits = 24 - RHSKnown.countMinSignBits();
4473 unsigned MaxValBits = std::min(LHSValBits + RHSValBits, 32u);
4474 if (MaxValBits >= 32)
4475 break;
4476 bool LHSNegative = LHSKnown.isNegative();
4477 bool LHSPositive = LHSKnown.isNonNegative();
4478 bool RHSNegative = RHSKnown.isNegative();
4479 bool RHSPositive = RHSKnown.isNonNegative();
4480 if ((!LHSNegative && !LHSPositive) || (!RHSNegative && !RHSPositive))
4481 break;
4482 Negative = (LHSNegative && RHSPositive) || (LHSPositive && RHSNegative);
4483 if (Negative)
4484 Known.One.setHighBits(32 - MaxValBits);
4485 else
4486 Known.Zero.setHighBits(32 - MaxValBits);
4487 } else {
4488 unsigned LHSValBits = 24 - LHSKnown.countMinLeadingZeros();
4489 unsigned RHSValBits = 24 - RHSKnown.countMinLeadingZeros();
4490 unsigned MaxValBits = std::min(LHSValBits + RHSValBits, 32u);
4491 if (MaxValBits >= 32)
4492 break;
4493 Known.Zero.setHighBits(32 - MaxValBits);
4494 }
4495 break;
4496 }
4497 case AMDGPUISD::PERM: {
4498 ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(Op.getOperand(2));
4499 if (!CMask)
4500 return;
4501
4502 KnownBits LHSKnown = DAG.computeKnownBits(Op.getOperand(0), Depth + 1);
4503 KnownBits RHSKnown = DAG.computeKnownBits(Op.getOperand(1), Depth + 1);
4504 unsigned Sel = CMask->getZExtValue();
4505
4506 for (unsigned I = 0; I < 32; I += 8) {
4507 unsigned SelBits = Sel & 0xff;
4508 if (SelBits < 4) {
4509 SelBits *= 8;
4510 Known.One |= ((RHSKnown.One.getZExtValue() >> SelBits) & 0xff) << I;
4511 Known.Zero |= ((RHSKnown.Zero.getZExtValue() >> SelBits) & 0xff) << I;
4512 } else if (SelBits < 7) {
4513 SelBits = (SelBits & 3) * 8;
4514 Known.One |= ((LHSKnown.One.getZExtValue() >> SelBits) & 0xff) << I;
4515 Known.Zero |= ((LHSKnown.Zero.getZExtValue() >> SelBits) & 0xff) << I;
4516 } else if (SelBits == 0x0c) {
4517 Known.Zero |= 0xFFull << I;
4518 } else if (SelBits > 0x0c) {
4519 Known.One |= 0xFFull << I;
4520 }
4521 Sel >>= 8;
4522 }
4523 break;
4524 }
4525 case AMDGPUISD::BUFFER_LOAD_UBYTE: {
4526 Known.Zero.setHighBits(24);
4527 break;
4528 }
4529 case AMDGPUISD::BUFFER_LOAD_USHORT: {
4530 Known.Zero.setHighBits(16);
4531 break;
4532 }
4533 case AMDGPUISD::LDS: {
4534 auto GA = cast<GlobalAddressSDNode>(Op.getOperand(0).getNode());
4535 unsigned Align = GA->getGlobal()->getAlignment();
4536
4537 Known.Zero.setHighBits(16);
4538 if (Align)
4539 Known.Zero.setLowBits(Log2_32(Align));
4540 break;
4541 }
4542 case ISD::INTRINSIC_WO_CHAIN: {
4543 unsigned IID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4544 switch (IID) {
4545 case Intrinsic::amdgcn_mbcnt_lo:
4546 case Intrinsic::amdgcn_mbcnt_hi: {
4547 const GCNSubtarget &ST =
4548 DAG.getMachineFunction().getSubtarget<GCNSubtarget>();
4549 // These return at most the wavefront size - 1.
4550 unsigned Size = Op.getValueType().getSizeInBits();
4551 Known.Zero.setHighBits(Size - ST.getWavefrontSizeLog2());
4552 break;
4553 }
4554 default:
4555 break;
4556 }
4557 }
4558 }
4559 }
4560
4561 unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(
4562 SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG,
4563 unsigned Depth) const {
4564 switch (Op.getOpcode()) {
4565 case AMDGPUISD::BFE_I32: {
4566 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
4567 if (!Width)
4568 return 1;
4569
4570 unsigned SignBits = 32 - Width->getZExtValue() + 1;
4571 if (!isNullConstant(Op.getOperand(1)))
4572 return SignBits;
4573
4574 // TODO: Could probably figure something out with non-0 offsets.
4575 unsigned Op0SignBits = DAG.ComputeNumSignBits(Op.getOperand(0), Depth + 1);
4576 return std::max(SignBits, Op0SignBits);
4577 }
4578
4579 case AMDGPUISD::BFE_U32: {
4580 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
4581 return Width ? 32 - (Width->getZExtValue() & 0x1f) : 1;
4582 }
4583
4584 case AMDGPUISD::CARRY:
4585 case AMDGPUISD::BORROW:
4586 return 31;
4587 case AMDGPUISD::BUFFER_LOAD_BYTE:
4588 return 25;
4589 case AMDGPUISD::BUFFER_LOAD_SHORT:
4590 return 17;
4591 case AMDGPUISD::BUFFER_LOAD_UBYTE:
4592 return 24;
4593 case AMDGPUISD::BUFFER_LOAD_USHORT:
4594 return 16;
4595 case AMDGPUISD::FP_TO_FP16:
4596 case AMDGPUISD::FP16_ZEXT:
4597 return 16;
4598 default:
4599 return 1;
4600 }
4601 }
4602
4603 bool AMDGPUTargetLowering::isKnownNeverNaNForTargetNode(SDValue Op,
4604 const SelectionDAG &DAG,
4605 bool SNaN,
4606 unsigned Depth) const {
4607 unsigned Opcode = Op.getOpcode();
4608 switch (Opcode) {
4609 case AMDGPUISD::FMIN_LEGACY:
4610 case AMDGPUISD::FMAX_LEGACY: {
4611 if (SNaN)
4612 return true;
4613
4614 // TODO: Can check no nans on one of the operands for each one, but which
4615 // one?
4616 return false;
4617 }
4618 case AMDGPUISD::FMUL_LEGACY:
4619 case AMDGPUISD::CVT_PKRTZ_F16_F32: {
4620 if (SNaN)
4621 return true;
4622 return DAG.isKnownNeverNaN(Op.getOperand(0), SNaN, Depth + 1) &&
4623 DAG.isKnownNeverNaN(Op.getOperand(1), SNaN, Depth + 1);
4624 }
4625 case AMDGPUISD::FMED3:
4626 case AMDGPUISD::FMIN3:
4627 case AMDGPUISD::FMAX3:
4628 case AMDGPUISD::FMAD_FTZ: {
4629 if (SNaN)
4630 return true;
4631 return DAG.isKnownNeverNaN(Op.getOperand(0), SNaN, Depth + 1) &&
4632 DAG.isKnownNeverNaN(Op.getOperand(1), SNaN, Depth + 1) &&
4633 DAG.isKnownNeverNaN(Op.getOperand(2), SNaN, Depth + 1);
4634 }
4635 case AMDGPUISD::CVT_F32_UBYTE0:
4636 case AMDGPUISD::CVT_F32_UBYTE1:
4637 case AMDGPUISD::CVT_F32_UBYTE2:
4638 case AMDGPUISD::CVT_F32_UBYTE3:
4639 return true;
4640
4641 case AMDGPUISD::RCP:
4642 case AMDGPUISD::RSQ:
4643 case AMDGPUISD::RCP_LEGACY:
4644 case AMDGPUISD::RSQ_LEGACY:
4645 case AMDGPUISD::RSQ_CLAMP: {
4646 if (SNaN)
4647 return true;
4648
4649 // TODO: Need is known positive check.
4650 return false;
4651 }
4652 case AMDGPUISD::LDEXP:
4653 case AMDGPUISD::FRACT: {
4654 if (SNaN)
4655 return true;
4656 return DAG.isKnownNeverNaN(Op.getOperand(0), SNaN, Depth + 1);
4657 }
4658 case AMDGPUISD::DIV_SCALE:
4659 case AMDGPUISD::DIV_FMAS:
4660 case AMDGPUISD::DIV_FIXUP:
4661 case AMDGPUISD::TRIG_PREOP:
4662 // TODO: Refine on operands.
4663 return SNaN;
4664 case AMDGPUISD::SIN_HW:
4665 case AMDGPUISD::COS_HW: {
4666 // TODO: Need check for infinity
4667 return SNaN;
4668 }
4669 case ISD::INTRINSIC_WO_CHAIN: {
4670 unsigned IntrinsicID
4671 = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4672 // TODO: Handle more intrinsics
4673 switch (IntrinsicID) {
4674 case Intrinsic::amdgcn_cubeid:
4675 return true;
4676
4677 case Intrinsic::amdgcn_frexp_mant: {
4678 if (SNaN)
4679 return true;
4680 return DAG.isKnownNeverNaN(Op.getOperand(1), SNaN, Depth + 1);
4681 }
4682 case Intrinsic::amdgcn_cvt_pkrtz: {
4683 if (SNaN)
4684 return true;
4685 return DAG.isKnownNeverNaN(Op.getOperand(1), SNaN, Depth + 1) &&
4686 DAG.isKnownNeverNaN(Op.getOperand(2), SNaN, Depth + 1);
4687 }
4688 case Intrinsic::amdgcn_fdot2:
4689 // TODO: Refine on operand
4690 return SNaN;
4691 default:
4692 return false;
4693 }
4694 }
4695 default:
4696 return false;
4697 }
4698 }
4699
4700 TargetLowering::AtomicExpansionKind
4701 AMDGPUTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const {
4702 switch (RMW->getOperation()) {
4703 case AtomicRMWInst::Nand:
4704 case AtomicRMWInst::FAdd:
4705 case AtomicRMWInst::FSub:
4706 return AtomicExpansionKind::CmpXChg;
4707 default:
4708 return AtomicExpansionKind::None;
4709 }
4710 }
The LLVM Project is a collection of modular and reusable compiler and toolchain technologies.