lib/Target/ARM/ARMSubtarget.h

   1 //===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file declares the ARM specific subclass of TargetSubtargetInfo.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #ifndef LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
  14 #define LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
  15
  16 #include "ARMBaseInstrInfo.h"
  17 #include "ARMBaseRegisterInfo.h"
  18 #include "ARMConstantPoolValue.h"
  19 #include "ARMFrameLowering.h"
  20 #include "ARMISelLowering.h"
  21 #include "ARMSelectionDAGInfo.h"
  22 #include "llvm/ADT/Triple.h"
  23 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
  24 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
  25 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
  26 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
  27 #include "llvm/CodeGen/MachineFunction.h"
  28 #include "llvm/CodeGen/TargetSubtargetInfo.h"
  29 #include "llvm/MC/MCInstrItineraries.h"
  30 #include "llvm/MC/MCSchedule.h"
  31 #include "llvm/Target/TargetOptions.h"
  32 #include <memory>
  33 #include <string>
  34
  35 #define GET_SUBTARGETINFO_HEADER
  36 #include "ARMGenSubtargetInfo.inc"
  37
  38 namespace llvm {
  39
  40 class ARMBaseTargetMachine;
  41 class GlobalValue;
  42 class StringRef;
  43
  44 class ARMSubtarget : public ARMGenSubtargetInfo {
  45 protected:
  46   enum ARMProcFamilyEnum {
  47     Others,
  48
  49     CortexA12,
  50     CortexA15,
  51     CortexA17,
  52     CortexA32,
  53     CortexA35,
  54     CortexA5,
  55     CortexA53,
  56     CortexA55,
  57     CortexA57,
  58     CortexA7,
  59     CortexA72,
  60     CortexA73,
  61     CortexA75,
  62     CortexA76,
  63     CortexA8,
  64     CortexA9,
  65     CortexM3,
  66     CortexR4,
  67     CortexR4F,
  68     CortexR5,
  69     CortexR52,
  70     CortexR7,
  71     Exynos,
  72     Krait,
  73     Kryo,
  74     NeoverseN1,
  75     Swift
  76   };
  77   enum ARMProcClassEnum {
  78     None,
  79
  80     AClass,
  81     MClass,
  82     RClass
  83   };
  84   enum ARMArchEnum {
  85     ARMv2,
  86     ARMv2a,
  87     ARMv3,
  88     ARMv3m,
  89     ARMv4,
  90     ARMv4t,
  91     ARMv5,
  92     ARMv5t,
  93     ARMv5te,
  94     ARMv5tej,
  95     ARMv6,
  96     ARMv6k,
  97     ARMv6kz,
  98     ARMv6m,
  99     ARMv6sm,
 100     ARMv6t2,
 101     ARMv7a,
 102     ARMv7em,
 103     ARMv7m,
 104     ARMv7r,
 105     ARMv7ve,
 106     ARMv81a,
 107     ARMv82a,
 108     ARMv83a,
 109     ARMv84a,
 110     ARMv85a,
 111     ARMv8a,
 112     ARMv8mBaseline,
 113     ARMv8mMainline,
 114     ARMv8r,
 115     ARMv81mMainline,
 116   };
 117
 118 public:
 119   /// What kind of timing do load multiple/store multiple instructions have.
 120   enum ARMLdStMultipleTiming {
 121     /// Can load/store 2 registers/cycle.
 122     DoubleIssue,
 123     /// Can load/store 2 registers/cycle, but needs an extra cycle if the access
 124     /// is not 64-bit aligned.
 125     DoubleIssueCheckUnalignedAccess,
 126     /// Can load/store 1 register/cycle.
 127     SingleIssue,
 128     /// Can load/store 1 register/cycle, but needs an extra cycle for address
 129     /// computation and potentially also for register writeback.
 130     SingleIssuePlusExtras,
 131   };
 132
 133 protected:
 134   /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
 135   ARMProcFamilyEnum ARMProcFamily = Others;
 136
 137   /// ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
 138   ARMProcClassEnum ARMProcClass = None;
 139
 140   /// ARMArch - ARM architecture
 141   ARMArchEnum ARMArch = ARMv4t;
 142
 143   /// HasV4TOps, HasV5TOps, HasV5TEOps,
 144   /// HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops, HasV8Ops -
 145   /// Specify whether target support specific ARM ISA variants.
 146   bool HasV4TOps = false;
 147   bool HasV5TOps = false;
 148   bool HasV5TEOps = false;
 149   bool HasV6Ops = false;
 150   bool HasV6MOps = false;
 151   bool HasV6KOps = false;
 152   bool HasV6T2Ops = false;
 153   bool HasV7Ops = false;
 154   bool HasV8Ops = false;
 155   bool HasV8_1aOps = false;
 156   bool HasV8_2aOps = false;
 157   bool HasV8_3aOps = false;
 158   bool HasV8_4aOps = false;
 159   bool HasV8_5aOps = false;
 160   bool HasV8MBaselineOps = false;
 161   bool HasV8MMainlineOps = false;
 162   bool HasV8_1MMainlineOps = false;
 163   bool HasMVEIntegerOps = false;
 164   bool HasMVEFloatOps = false;
 165
 166   /// HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what
 167   /// floating point ISAs are supported.
 168   bool HasVFPv2 = false;
 169   bool HasVFPv3 = false;
 170   bool HasVFPv4 = false;
 171   bool HasFPARMv8 = false;
 172   bool HasNEON = false;
 173   bool HasFPRegs = false;
 174   bool HasFPRegs16 = false;
 175   bool HasFPRegs64 = false;
 176
 177   /// Versions of the VFP flags restricted to single precision, or to
 178   /// 16 d-registers, or both.
 179   bool HasVFPv2SP = false;
 180   bool HasVFPv3SP = false;
 181   bool HasVFPv4SP = false;
 182   bool HasFPARMv8SP = false;
 183   bool HasVFPv2D16 = false;
 184   bool HasVFPv3D16 = false;
 185   bool HasVFPv4D16 = false;
 186   bool HasFPARMv8D16 = false;
 187   bool HasVFPv2D16SP = false;
 188   bool HasVFPv3D16SP = false;
 189   bool HasVFPv4D16SP = false;
 190   bool HasFPARMv8D16SP = false;
 191
 192   /// HasDotProd - True if the ARMv8.2A dot product instructions are supported.
 193   bool HasDotProd = false;
 194
 195   /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
 196   /// specified. Use the method useNEONForSinglePrecisionFP() to
 197   /// determine if NEON should actually be used.
 198   bool UseNEONForSinglePrecisionFP = false;
 199
 200   /// UseMulOps - True if non-microcoded fused integer multiply-add and
 201   /// multiply-subtract instructions should be used.
 202   bool UseMulOps = false;
 203
 204   /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
 205   /// whether the FP VML[AS] instructions are slow (if so, don't use them).
 206   bool SlowFPVMLx = false;
 207
 208   /// HasVMLxForwarding - If true, NEON has special multiplier accumulator
 209   /// forwarding to allow mul + mla being issued back to back.
 210   bool HasVMLxForwarding = false;
 211
 212   /// SlowFPBrcc - True if floating point compare + branch is slow.
 213   bool SlowFPBrcc = false;
 214
 215   /// InThumbMode - True if compiling for Thumb, false for ARM.
 216   bool InThumbMode = false;
 217
 218   /// UseSoftFloat - True if we're using software floating point features.
 219   bool UseSoftFloat = false;
 220
 221   /// UseMISched - True if MachineScheduler should be used for this subtarget.
 222   bool UseMISched = false;
 223
 224   /// DisablePostRAScheduler - False if scheduling should happen again after
 225   /// register allocation.
 226   bool DisablePostRAScheduler = false;
 227
 228   /// UseAA - True if using AA during codegen (DAGCombine, MISched, etc)
 229   bool UseAA = false;
 230
 231   /// HasThumb2 - True if Thumb2 instructions are supported.
 232   bool HasThumb2 = false;
 233
 234   /// NoARM - True if subtarget does not support ARM mode execution.
 235   bool NoARM = false;
 236
 237   /// ReserveR9 - True if R9 is not available as a general purpose register.
 238   bool ReserveR9 = false;
 239
 240   /// NoMovt - True if MOVT / MOVW pairs are not used for materialization of
 241   /// 32-bit imms (including global addresses).
 242   bool NoMovt = false;
 243
 244   /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
 245   /// must be able to synthesize call stubs for interworking between ARM and
 246   /// Thumb.
 247   bool SupportsTailCall = false;
 248
 249   /// HasFP16 - True if subtarget supports half-precision FP conversions
 250   bool HasFP16 = false;
 251
 252   /// HasFullFP16 - True if subtarget supports half-precision FP operations
 253   bool HasFullFP16 = false;
 254
 255   /// HasFP16FML - True if subtarget supports half-precision FP fml operations
 256   bool HasFP16FML = false;
 257
 258   /// HasD32 - True if subtarget has the full 32 double precision
 259   /// FP registers for VFPv3.
 260   bool HasD32 = false;
 261
 262   /// HasHardwareDivide - True if subtarget supports [su]div in Thumb mode
 263   bool HasHardwareDivideInThumb = false;
 264
 265   /// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode
 266   bool HasHardwareDivideInARM = false;
 267
 268   /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
 269   /// instructions.
 270   bool HasDataBarrier = false;
 271
 272   /// HasFullDataBarrier - True if the subtarget supports DFB data barrier
 273   /// instruction.
 274   bool HasFullDataBarrier = false;
 275
 276   /// HasV7Clrex - True if the subtarget supports CLREX instructions
 277   bool HasV7Clrex = false;
 278
 279   /// HasAcquireRelease - True if the subtarget supports v8 atomics (LDA/LDAEX etc)
 280   /// instructions
 281   bool HasAcquireRelease = false;
 282
 283   /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
 284   /// over 16-bit ones.
 285   bool Pref32BitThumb = false;
 286
 287   /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
 288   /// that partially update CPSR and add false dependency on the previous
 289   /// CPSR setting instruction.
 290   bool AvoidCPSRPartialUpdate = false;
 291
 292   /// CheapPredicableCPSRDef - If true, disable +1 predication cost
 293   /// for instructions updating CPSR. Enabled for Cortex-A57.
 294   bool CheapPredicableCPSRDef = false;
 295
 296   /// AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting
 297   /// movs with shifter operand (i.e. asr, lsl, lsr).
 298   bool AvoidMOVsShifterOperand = false;
 299
 300   /// HasRetAddrStack - Some processors perform return stack prediction. CodeGen should
 301   /// avoid issue "normal" call instructions to callees which do not return.
 302   bool HasRetAddrStack = false;
 303
 304   /// HasBranchPredictor - True if the subtarget has a branch predictor. Having
 305   /// a branch predictor or not changes the expected cost of taking a branch
 306   /// which affects the choice of whether to use predicated instructions.
 307   bool HasBranchPredictor = true;
 308
 309   /// HasMPExtension - True if the subtarget supports Multiprocessing
 310   /// extension (ARMv7 only).
 311   bool HasMPExtension = false;
 312
 313   /// HasVirtualization - True if the subtarget supports the Virtualization
 314   /// extension.
 315   bool HasVirtualization = false;
 316
 317   /// HasFP64 - If true, the floating point unit supports double
 318   /// precision.
 319   bool HasFP64 = false;
 320
 321   /// If true, the processor supports the Performance Monitor Extensions. These
 322   /// include a generic cycle-counter as well as more fine-grained (often
 323   /// implementation-specific) events.
 324   bool HasPerfMon = false;
 325
 326   /// HasTrustZone - if true, processor supports TrustZone security extensions
 327   bool HasTrustZone = false;
 328
 329   /// Has8MSecExt - if true, processor supports ARMv8-M Security Extensions
 330   bool Has8MSecExt = false;
 331
 332   /// HasSHA2 - if true, processor supports SHA1 and SHA256
 333   bool HasSHA2 = false;
 334
 335   /// HasAES - if true, processor supports AES
 336   bool HasAES = false;
 337
 338   /// HasCrypto - if true, processor supports Cryptography extensions
 339   bool HasCrypto = false;
 340
 341   /// HasCRC - if true, processor supports CRC instructions
 342   bool HasCRC = false;
 343
 344   /// HasRAS - if true, the processor supports RAS extensions
 345   bool HasRAS = false;
 346
 347   /// HasLOB - if true, the processor supports the Low Overhead Branch extension
 348   bool HasLOB = false;
 349
 350   /// If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are
 351   /// particularly effective at zeroing a VFP register.
 352   bool HasZeroCycleZeroing = false;
 353
 354   /// HasFPAO - if true, processor  does positive address offset computation faster
 355   bool HasFPAO = false;
 356
 357   /// HasFuseAES - if true, processor executes back to back AES instruction
 358   /// pairs faster.
 359   bool HasFuseAES = false;
 360
 361   /// HasFuseLiterals - if true, processor executes back to back
 362   /// bottom and top halves of literal generation faster.
 363   bool HasFuseLiterals = false;
 364
 365   /// If true, if conversion may decide to leave some instructions unpredicated.
 366   bool IsProfitableToUnpredicate = false;
 367
 368   /// If true, VMOV will be favored over VGETLNi32.
 369   bool HasSlowVGETLNi32 = false;
 370
 371   /// If true, VMOV will be favored over VDUP.
 372   bool HasSlowVDUP32 = false;
 373
 374   /// If true, VMOVSR will be favored over VMOVDRR.
 375   bool PreferVMOVSR = false;
 376
 377   /// If true, ISHST barriers will be used for Release semantics.
 378   bool PreferISHST = false;
 379
 380   /// If true, a VLDM/VSTM starting with an odd register number is considered to
 381   /// take more microops than single VLDRS/VSTRS.
 382   bool SlowOddRegister = false;
 383
 384   /// If true, loading into a D subregister will be penalized.
 385   bool SlowLoadDSubregister = false;
 386
 387   /// If true, use a wider stride when allocating VFP registers.
 388   bool UseWideStrideVFP = false;
 389
 390   /// If true, the AGU and NEON/FPU units are multiplexed.
 391   bool HasMuxedUnits = false;
 392
 393   /// If true, VMOVS will never be widened to VMOVD.
 394   bool DontWidenVMOVS = false;
 395
 396   /// If true, splat a register between VFP and NEON instructions.
 397   bool SplatVFPToNeon = false;
 398
 399   /// If true, run the MLx expansion pass.
 400   bool ExpandMLx = false;
 401
 402   /// If true, VFP/NEON VMLA/VMLS have special RAW hazards.
 403   bool HasVMLxHazards = false;
 404
 405   // If true, read thread pointer from coprocessor register.
 406   bool ReadTPHard = false;
 407
 408   /// If true, VMOVRS, VMOVSR and VMOVS will be converted from VFP to NEON.
 409   bool UseNEONForFPMovs = false;
 410
 411   /// If true, VLDn instructions take an extra cycle for unaligned accesses.
 412   bool CheckVLDnAlign = false;
 413
 414   /// If true, VFP instructions are not pipelined.
 415   bool NonpipelinedVFP = false;
 416
 417   /// StrictAlign - If true, the subtarget disallows unaligned memory
 418   /// accesses for some types.  For details, see
 419   /// ARMTargetLowering::allowsMisalignedMemoryAccesses().
 420   bool StrictAlign = false;
 421
 422   /// RestrictIT - If true, the subtarget disallows generation of deprecated IT
 423   ///  blocks to conform to ARMv8 rule.
 424   bool RestrictIT = false;
 425
 426   /// HasDSP - If true, the subtarget supports the DSP (saturating arith
 427   /// and such) instructions.
 428   bool HasDSP = false;
 429
 430   /// NaCl TRAP instruction is generated instead of the regular TRAP.
 431   bool UseNaClTrap = false;
 432
 433   /// Generate calls via indirect call instructions.
 434   bool GenLongCalls = false;
 435
 436   /// Generate code that does not contain data access to code sections.
 437   bool GenExecuteOnly = false;
 438
 439   /// Target machine allowed unsafe FP math (such as use of NEON fp)
 440   bool UnsafeFPMath = false;
 441
 442   /// UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
 443   bool UseSjLjEH = false;
 444
 445   /// Has speculation barrier
 446   bool HasSB = false;
 447
 448   /// Implicitly convert an instruction to a different one if its immediates
 449   /// cannot be encoded. For example, ADD r0, r1, #FFFFFFFF -> SUB r0, r1, #1.
 450   bool NegativeImmediates = true;
 451
 452   /// stackAlignment - The minimum alignment known to hold of the stack frame on
 453   /// entry to the function and which must be maintained by every function.
 454   unsigned stackAlignment = 4;
 455
 456   /// CPUString - String name of used CPU.
 457   std::string CPUString;
 458
 459   unsigned MaxInterleaveFactor = 1;
 460
 461   /// Clearance before partial register updates (in number of instructions)
 462   unsigned PartialUpdateClearance = 0;
 463
 464   /// What kind of timing do load multiple/store multiple have (double issue,
 465   /// single issue etc).
 466   ARMLdStMultipleTiming LdStMultipleTiming = SingleIssue;
 467
 468   /// The adjustment that we need to apply to get the operand latency from the
 469   /// operand cycle returned by the itinerary data for pre-ISel operands.
 470   int PreISelOperandLatencyAdjustment = 2;
 471
 472   /// What alignment is preferred for loop bodies, in log2(bytes).
 473   unsigned PrefLoopAlignment = 0;
 474
 475   /// The cost factor for MVE instructions, representing the multiple beats an
 476   // instruction can take. The default is 2, (set in initSubtargetFeatures so
 477   // that we can use subtarget features less than 2).
 478   unsigned MVEVectorCostFactor = 0;
 479
 480   /// OptMinSize - True if we're optimising for minimum code size, equal to
 481   /// the function attribute.
 482   bool OptMinSize = false;
 483
 484   /// IsLittle - The target is Little Endian
 485   bool IsLittle;
 486
 487   /// TargetTriple - What processor and OS we're targeting.
 488   Triple TargetTriple;
 489
 490   /// SchedModel - Processor specific instruction costs.
 491   MCSchedModel SchedModel;
 492
 493   /// Selected instruction itineraries (one entry per itinerary class.)
 494   InstrItineraryData InstrItins;
 495
 496   /// Options passed via command line that could influence the target
 497   const TargetOptions &Options;
 498
 499   const ARMBaseTargetMachine &TM;
 500
 501 public:
 502   /// This constructor initializes the data members to match that
 503   /// of the specified triple.
 504   ///
 505   ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
 506                const ARMBaseTargetMachine &TM, bool IsLittle,
 507                bool MinSize = false);
 508
 509   /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
 510   /// that still makes it profitable to inline the call.
 511   unsigned getMaxInlineSizeThreshold() const {
 512     return 64;
 513   }
 514
 515   /// ParseSubtargetFeatures - Parses features string setting specified
 516   /// subtarget options.  Definition of function is auto generated by tblgen.
 517   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
 518
 519   /// initializeSubtargetDependencies - Initializes using a CPU and feature string
 520   /// so that we can use initializer lists for subtarget initialization.
 521   ARMSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
 522
 523   const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
 524     return &TSInfo;
 525   }
 526
 527   const ARMBaseInstrInfo *getInstrInfo() const override {
 528     return InstrInfo.get();
 529   }
 530
 531   const ARMTargetLowering *getTargetLowering() const override {
 532     return &TLInfo;
 533   }
 534
 535   const ARMFrameLowering *getFrameLowering() const override {
 536     return FrameLowering.get();
 537   }
 538
 539   const ARMBaseRegisterInfo *getRegisterInfo() const override {
 540     return &InstrInfo->getRegisterInfo();
 541   }
 542
 543   const CallLowering *getCallLowering() const override;
 544   InstructionSelector *getInstructionSelector() const override;
 545   const LegalizerInfo *getLegalizerInfo() const override;
 546   const RegisterBankInfo *getRegBankInfo() const override;
 547
 548 private:
 549   ARMSelectionDAGInfo TSInfo;
 550   // Either Thumb1FrameLowering or ARMFrameLowering.
 551   std::unique_ptr<ARMFrameLowering> FrameLowering;
 552   // Either Thumb1InstrInfo or Thumb2InstrInfo.
 553   std::unique_ptr<ARMBaseInstrInfo> InstrInfo;
 554   ARMTargetLowering   TLInfo;
 555
 556   /// GlobalISel related APIs.
 557   std::unique_ptr<CallLowering> CallLoweringInfo;
 558   std::unique_ptr<InstructionSelector> InstSelector;
 559   std::unique_ptr<LegalizerInfo> Legalizer;
 560   std::unique_ptr<RegisterBankInfo> RegBankInfo;
 561
 562   void initializeEnvironment();
 563   void initSubtargetFeatures(StringRef CPU, StringRef FS);
 564   ARMFrameLowering *initializeFrameLowering(StringRef CPU, StringRef FS);
 565
 566 public:
 567   void computeIssueWidth();
 568
 569   bool hasV4TOps()  const { return HasV4TOps;  }
 570   bool hasV5TOps()  const { return HasV5TOps;  }
 571   bool hasV5TEOps() const { return HasV5TEOps; }
 572   bool hasV6Ops()   const { return HasV6Ops;   }
 573   bool hasV6MOps()  const { return HasV6MOps;  }
 574   bool hasV6KOps()  const { return HasV6KOps; }
 575   bool hasV6T2Ops() const { return HasV6T2Ops; }
 576   bool hasV7Ops()   const { return HasV7Ops;  }
 577   bool hasV8Ops()   const { return HasV8Ops;  }
 578   bool hasV8_1aOps() const { return HasV8_1aOps; }
 579   bool hasV8_2aOps() const { return HasV8_2aOps; }
 580   bool hasV8_3aOps() const { return HasV8_3aOps; }
 581   bool hasV8_4aOps() const { return HasV8_4aOps; }
 582   bool hasV8_5aOps() const { return HasV8_5aOps; }
 583   bool hasV8MBaselineOps() const { return HasV8MBaselineOps; }
 584   bool hasV8MMainlineOps() const { return HasV8MMainlineOps; }
 585   bool hasV8_1MMainlineOps() const { return HasV8_1MMainlineOps; }
 586   bool hasMVEIntegerOps() const { return HasMVEIntegerOps; }
 587   bool hasMVEFloatOps() const { return HasMVEFloatOps; }
 588   bool hasFPRegs() const { return HasFPRegs; }
 589   bool hasFPRegs16() const { return HasFPRegs16; }
 590   bool hasFPRegs64() const { return HasFPRegs64; }
 591
 592   /// @{
 593   /// These functions are obsolete, please consider adding subtarget features
 594   /// or properties instead of calling them.
 595   bool isCortexA5() const { return ARMProcFamily == CortexA5; }
 596   bool isCortexA7() const { return ARMProcFamily == CortexA7; }
 597   bool isCortexA8() const { return ARMProcFamily == CortexA8; }
 598   bool isCortexA9() const { return ARMProcFamily == CortexA9; }
 599   bool isCortexA15() const { return ARMProcFamily == CortexA15; }
 600   bool isSwift()    const { return ARMProcFamily == Swift; }
 601   bool isCortexM3() const { return ARMProcFamily == CortexM3; }
 602   bool isLikeA9() const { return isCortexA9() || isCortexA15() || isKrait(); }
 603   bool isCortexR5() const { return ARMProcFamily == CortexR5; }
 604   bool isKrait() const { return ARMProcFamily == Krait; }
 605   /// @}
 606
 607   bool hasARMOps() const { return !NoARM; }
 608
 609   bool hasVFP2Base() const { return HasVFPv2D16SP; }
 610   bool hasVFP3Base() const { return HasVFPv3D16SP; }
 611   bool hasVFP4Base() const { return HasVFPv4D16SP; }
 612   bool hasFPARMv8Base() const { return HasFPARMv8D16SP; }
 613   bool hasNEON() const { return HasNEON;  }
 614   bool hasSHA2() const { return HasSHA2; }
 615   bool hasAES() const { return HasAES; }
 616   bool hasCrypto() const { return HasCrypto; }
 617   bool hasDotProd() const { return HasDotProd; }
 618   bool hasCRC() const { return HasCRC; }
 619   bool hasRAS() const { return HasRAS; }
 620   bool hasLOB() const { return HasLOB; }
 621   bool hasVirtualization() const { return HasVirtualization; }
 622
 623   bool useNEONForSinglePrecisionFP() const {
 624     return hasNEON() && UseNEONForSinglePrecisionFP;
 625   }
 626
 627   bool hasDivideInThumbMode() const { return HasHardwareDivideInThumb; }
 628   bool hasDivideInARMMode() const { return HasHardwareDivideInARM; }
 629   bool hasDataBarrier() const { return HasDataBarrier; }
 630   bool hasFullDataBarrier() const { return HasFullDataBarrier; }
 631   bool hasV7Clrex() const { return HasV7Clrex; }
 632   bool hasAcquireRelease() const { return HasAcquireRelease; }
 633
 634   bool hasAnyDataBarrier() const {
 635     return HasDataBarrier || (hasV6Ops() && !isThumb());
 636   }
 637
 638   bool useMulOps() const { return UseMulOps; }
 639   bool useFPVMLx() const { return !SlowFPVMLx; }
 640   bool hasVMLxForwarding() const { return HasVMLxForwarding; }
 641   bool isFPBrccSlow() const { return SlowFPBrcc; }
 642   bool hasFP64() const { return HasFP64; }
 643   bool hasPerfMon() const { return HasPerfMon; }
 644   bool hasTrustZone() const { return HasTrustZone; }
 645   bool has8MSecExt() const { return Has8MSecExt; }
 646   bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
 647   bool hasFPAO() const { return HasFPAO; }
 648   bool isProfitableToUnpredicate() const { return IsProfitableToUnpredicate; }
 649   bool hasSlowVGETLNi32() const { return HasSlowVGETLNi32; }
 650   bool hasSlowVDUP32() const { return HasSlowVDUP32; }
 651   bool preferVMOVSR() const { return PreferVMOVSR; }
 652   bool preferISHSTBarriers() const { return PreferISHST; }
 653   bool expandMLx() const { return ExpandMLx; }
 654   bool hasVMLxHazards() const { return HasVMLxHazards; }
 655   bool hasSlowOddRegister() const { return SlowOddRegister; }
 656   bool hasSlowLoadDSubregister() const { return SlowLoadDSubregister; }
 657   bool useWideStrideVFP() const { return UseWideStrideVFP; }
 658   bool hasMuxedUnits() const { return HasMuxedUnits; }
 659   bool dontWidenVMOVS() const { return DontWidenVMOVS; }
 660   bool useSplatVFPToNeon() const { return SplatVFPToNeon; }
 661   bool useNEONForFPMovs() const { return UseNEONForFPMovs; }
 662   bool checkVLDnAccessAlignment() const { return CheckVLDnAlign; }
 663   bool nonpipelinedVFP() const { return NonpipelinedVFP; }
 664   bool prefers32BitThumb() const { return Pref32BitThumb; }
 665   bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
 666   bool cheapPredicableCPSRDef() const { return CheapPredicableCPSRDef; }
 667   bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand; }
 668   bool hasRetAddrStack() const { return HasRetAddrStack; }
 669   bool hasBranchPredictor() const { return HasBranchPredictor; }
 670   bool hasMPExtension() const { return HasMPExtension; }
 671   bool hasDSP() const { return HasDSP; }
 672   bool useNaClTrap() const { return UseNaClTrap; }
 673   bool useSjLjEH() const { return UseSjLjEH; }
 674   bool hasSB() const { return HasSB; }
 675   bool genLongCalls() const { return GenLongCalls; }
 676   bool genExecuteOnly() const { return GenExecuteOnly; }
 677
 678   bool hasFP16() const { return HasFP16; }
 679   bool hasD32() const { return HasD32; }
 680   bool hasFullFP16() const { return HasFullFP16; }
 681   bool hasFP16FML() const { return HasFP16FML; }
 682
 683   bool hasFuseAES() const { return HasFuseAES; }
 684   bool hasFuseLiterals() const { return HasFuseLiterals; }
 685   /// Return true if the CPU supports any kind of instruction fusion.
 686   bool hasFusion() const { return hasFuseAES() || hasFuseLiterals(); }
 687
 688   const Triple &getTargetTriple() const { return TargetTriple; }
 689
 690   bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
 691   bool isTargetIOS() const { return TargetTriple.isiOS(); }
 692   bool isTargetWatchOS() const { return TargetTriple.isWatchOS(); }
 693   bool isTargetWatchABI() const { return TargetTriple.isWatchABI(); }
 694   bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
 695   bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
 696   bool isTargetNetBSD() const { return TargetTriple.isOSNetBSD(); }
 697   bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
 698
 699   bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
 700   bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
 701   bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
 702
 703   // ARM EABI is the bare-metal EABI described in ARM ABI documents and
 704   // can be accessed via -target arm-none-eabi. This is NOT GNUEABI.
 705   // FIXME: Add a flag for bare-metal for that target and set Triple::EABI
 706   // even for GNUEABI, so we can make a distinction here and still conform to
 707   // the EABI on GNU (and Android) mode. This requires change in Clang, too.
 708   // FIXME: The Darwin exception is temporary, while we move users to
 709   // "*-*-*-macho" triples as quickly as possible.
 710   bool isTargetAEABI() const {
 711     return (TargetTriple.getEnvironment() == Triple::EABI ||
 712             TargetTriple.getEnvironment() == Triple::EABIHF) &&
 713            !isTargetDarwin() && !isTargetWindows();
 714   }
 715   bool isTargetGNUAEABI() const {
 716     return (TargetTriple.getEnvironment() == Triple::GNUEABI ||
 717             TargetTriple.getEnvironment() == Triple::GNUEABIHF) &&
 718            !isTargetDarwin() && !isTargetWindows();
 719   }
 720   bool isTargetMuslAEABI() const {
 721     return (TargetTriple.getEnvironment() == Triple::MuslEABI ||
 722             TargetTriple.getEnvironment() == Triple::MuslEABIHF) &&
 723            !isTargetDarwin() && !isTargetWindows();
 724   }
 725
 726   // ARM Targets that support EHABI exception handling standard
 727   // Darwin uses SjLj. Other targets might need more checks.
 728   bool isTargetEHABICompatible() const {
 729     return (TargetTriple.getEnvironment() == Triple::EABI ||
 730             TargetTriple.getEnvironment() == Triple::GNUEABI ||
 731             TargetTriple.getEnvironment() == Triple::MuslEABI ||
 732             TargetTriple.getEnvironment() == Triple::EABIHF ||
 733             TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
 734             TargetTriple.getEnvironment() == Triple::MuslEABIHF ||
 735             isTargetAndroid()) &&
 736            !isTargetDarwin() && !isTargetWindows();
 737   }
 738
 739   bool isTargetHardFloat() const;
 740
 741   bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
 742
 743   bool isXRaySupported() const override;
 744
 745   bool isAPCS_ABI() const;
 746   bool isAAPCS_ABI() const;
 747   bool isAAPCS16_ABI() const;
 748
 749   bool isROPI() const;
 750   bool isRWPI() const;
 751
 752   bool useMachineScheduler() const { return UseMISched; }
 753   bool disablePostRAScheduler() const { return DisablePostRAScheduler; }
 754   bool useSoftFloat() const { return UseSoftFloat; }
 755   bool isThumb() const { return InThumbMode; }
 756   bool hasMinSize() const { return OptMinSize; }
 757   bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
 758   bool isThumb2() const { return InThumbMode && HasThumb2; }
 759   bool hasThumb2() const { return HasThumb2; }
 760   bool isMClass() const { return ARMProcClass == MClass; }
 761   bool isRClass() const { return ARMProcClass == RClass; }
 762   bool isAClass() const { return ARMProcClass == AClass; }
 763   bool isReadTPHard() const { return ReadTPHard; }
 764
 765   bool isR9Reserved() const {
 766     return isTargetMachO() ? (ReserveR9 || !HasV6Ops) : ReserveR9;
 767   }
 768
 769   bool useR7AsFramePointer() const {
 770     return isTargetDarwin() || (!isTargetWindows() && isThumb());
 771   }
 772
 773   /// Returns true if the frame setup is split into two separate pushes (first
 774   /// r0-r7,lr then r8-r11), principally so that the frame pointer is adjacent
 775   /// to lr. This is always required on Thumb1-only targets, as the push and
 776   /// pop instructions can't access the high registers.
 777   bool splitFramePushPop(const MachineFunction &MF) const {
 778     return (useR7AsFramePointer() &&
 779             MF.getTarget().Options.DisableFramePointerElim(MF)) ||
 780            isThumb1Only();
 781   }
 782
 783   bool useStride4VFPs() const;
 784
 785   bool useMovt() const;
 786
 787   bool supportsTailCall() const { return SupportsTailCall; }
 788
 789   bool allowsUnalignedMem() const { return !StrictAlign; }
 790
 791   bool restrictIT() const { return RestrictIT; }
 792
 793   const std::string & getCPUString() const { return CPUString; }
 794
 795   bool isLittle() const { return IsLittle; }
 796
 797   unsigned getMispredictionPenalty() const;
 798
 799   /// Returns true if machine scheduler should be enabled.
 800   bool enableMachineScheduler() const override;
 801
 802   /// True for some subtargets at > -O0.
 803   bool enablePostRAScheduler() const override;
 804
 805   /// Enable use of alias analysis during code generation (during MI
 806   /// scheduling, DAGCombine, etc.).
 807   bool useAA() const override { return UseAA; }
 808
 809   // enableAtomicExpand- True if we need to expand our atomics.
 810   bool enableAtomicExpand() const override;
 811
 812   /// getInstrItins - Return the instruction itineraries based on subtarget
 813   /// selection.
 814   const InstrItineraryData *getInstrItineraryData() const override {
 815     return &InstrItins;
 816   }
 817
 818   /// getStackAlignment - Returns the minimum alignment known to hold of the
 819   /// stack frame on entry to the function and which must be maintained by every
 820   /// function for this subtarget.
 821   unsigned getStackAlignment() const { return stackAlignment; }
 822
 823   unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
 824
 825   unsigned getPartialUpdateClearance() const { return PartialUpdateClearance; }
 826
 827   ARMLdStMultipleTiming getLdStMultipleTiming() const {
 828     return LdStMultipleTiming;
 829   }
 830
 831   int getPreISelOperandLatencyAdjustment() const {
 832     return PreISelOperandLatencyAdjustment;
 833   }
 834
 835   /// True if the GV will be accessed via an indirect symbol.
 836   bool isGVIndirectSymbol(const GlobalValue *GV) const;
 837
 838   /// Returns the constant pool modifier needed to access the GV.
 839   bool isGVInGOT(const GlobalValue *GV) const;
 840
 841   /// True if fast-isel is used.
 842   bool useFastISel() const;
 843
 844   /// Returns the correct return opcode for the current feature set.
 845   /// Use BX if available to allow mixing thumb/arm code, but fall back
 846   /// to plain mov pc,lr on ARMv4.
 847   unsigned getReturnOpcode() const {
 848     if (isThumb())
 849       return ARM::tBX_RET;
 850     if (hasV4TOps())
 851       return ARM::BX_RET;
 852     return ARM::MOVPCLR;
 853   }
 854
 855   /// Allow movt+movw for PIC global address calculation.
 856   /// ELF does not have GOT relocations for movt+movw.
 857   /// ROPI does not use GOT.
 858   bool allowPositionIndependentMovt() const {
 859     return isROPI() || !isTargetELF();
 860   }
 861
 862   unsigned getPrefLoopAlignment() const {
 863     return PrefLoopAlignment;
 864   }
 865
 866   unsigned getMVEVectorCostFactor() const { return MVEVectorCostFactor; }
 867
 868   bool ignoreCSRForAllocationOrder(const MachineFunction &MF,
 869                                    unsigned PhysReg) const override;
 870   unsigned getGPRAllocationOrder(const MachineFunction &MF) const;
 871 };
 872
 873 } // end namespace llvm
 874
 875 #endif  // LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H