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[AMDGPU] Check for immediate SrcC in mfma in AsmParser
[llvm-core.git] / lib / Target / X86 / X86InstrInfo.cpp
blob3077288b794f0a0c91e6fb152896384641432e17
1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the X86 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "X86InstrInfo.h"
14 #include "X86.h"
15 #include "X86InstrBuilder.h"
16 #include "X86InstrFoldTables.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/Sequence.h"
22 #include "llvm/CodeGen/LivePhysRegs.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineDominators.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineModuleInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/StackMaps.h"
31 #include "llvm/IR/DerivedTypes.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/DebugInfoMetadata.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCExpr.h"
36 #include "llvm/MC/MCInst.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Support/ErrorHandling.h"
40 #include "llvm/Support/raw_ostream.h"
41 #include "llvm/Target/TargetOptions.h"
42
43 using namespace llvm;
44
45 #define DEBUG_TYPE "x86-instr-info"
46
47 #define GET_INSTRINFO_CTOR_DTOR
48 #include "X86GenInstrInfo.inc"
49
50 static cl::opt<bool>
51 NoFusing("disable-spill-fusing",
52 cl::desc("Disable fusing of spill code into instructions"),
53 cl::Hidden);
54 static cl::opt<bool>
55 PrintFailedFusing("print-failed-fuse-candidates",
56 cl::desc("Print instructions that the allocator wants to"
57 " fuse, but the X86 backend currently can't"),
58 cl::Hidden);
59 static cl::opt<bool>
60 ReMatPICStubLoad("remat-pic-stub-load",
61 cl::desc("Re-materialize load from stub in PIC mode"),
62 cl::init(false), cl::Hidden);
63 static cl::opt<unsigned>
64 PartialRegUpdateClearance("partial-reg-update-clearance",
65 cl::desc("Clearance between two register writes "
66 "for inserting XOR to avoid partial "
67 "register update"),
68 cl::init(64), cl::Hidden);
69 static cl::opt<unsigned>
70 UndefRegClearance("undef-reg-clearance",
71 cl::desc("How many idle instructions we would like before "
72 "certain undef register reads"),
73 cl::init(128), cl::Hidden);
74
75
76 // Pin the vtable to this file.
77 void X86InstrInfo::anchor() {}
78
79 X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
80 : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
81 : X86::ADJCALLSTACKDOWN32),
82 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
83 : X86::ADJCALLSTACKUP32),
84 X86::CATCHRET,
85 (STI.is64Bit() ? X86::RETQ : X86::RETL)),
86 Subtarget(STI), RI(STI.getTargetTriple()) {
87 }
88
89 bool
90 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
91 unsigned &SrcReg, unsigned &DstReg,
92 unsigned &SubIdx) const {
93 switch (MI.getOpcode()) {
94 default: break;
95 case X86::MOVSX16rr8:
96 case X86::MOVZX16rr8:
97 case X86::MOVSX32rr8:
98 case X86::MOVZX32rr8:
99 case X86::MOVSX64rr8:
100 if (!Subtarget.is64Bit())
101 // It's not always legal to reference the low 8-bit of the larger
102 // register in 32-bit mode.
103 return false;
104 LLVM_FALLTHROUGH;
105 case X86::MOVSX32rr16:
106 case X86::MOVZX32rr16:
107 case X86::MOVSX64rr16:
108 case X86::MOVSX64rr32: {
109 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
110 // Be conservative.
111 return false;
112 SrcReg = MI.getOperand(1).getReg();
113 DstReg = MI.getOperand(0).getReg();
114 switch (MI.getOpcode()) {
115 default: llvm_unreachable("Unreachable!");
116 case X86::MOVSX16rr8:
117 case X86::MOVZX16rr8:
118 case X86::MOVSX32rr8:
119 case X86::MOVZX32rr8:
120 case X86::MOVSX64rr8:
121 SubIdx = X86::sub_8bit;
122 break;
123 case X86::MOVSX32rr16:
124 case X86::MOVZX32rr16:
125 case X86::MOVSX64rr16:
126 SubIdx = X86::sub_16bit;
127 break;
128 case X86::MOVSX64rr32:
129 SubIdx = X86::sub_32bit;
130 break;
131 }
132 return true;
133 }
134 }
135 return false;
136 }
137
138 int X86InstrInfo::getSPAdjust(const MachineInstr &MI) const {
139 const MachineFunction *MF = MI.getParent()->getParent();
140 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
141
142 if (isFrameInstr(MI)) {
143 unsigned StackAlign = TFI->getStackAlignment();
144 int SPAdj = alignTo(getFrameSize(MI), StackAlign);
145 SPAdj -= getFrameAdjustment(MI);
146 if (!isFrameSetup(MI))
147 SPAdj = -SPAdj;
148 return SPAdj;
149 }
150
151 // To know whether a call adjusts the stack, we need information
152 // that is bound to the following ADJCALLSTACKUP pseudo.
153 // Look for the next ADJCALLSTACKUP that follows the call.
154 if (MI.isCall()) {
155 const MachineBasicBlock *MBB = MI.getParent();
156 auto I = ++MachineBasicBlock::const_iterator(MI);
157 for (auto E = MBB->end(); I != E; ++I) {
158 if (I->getOpcode() == getCallFrameDestroyOpcode() ||
159 I->isCall())
160 break;
161 }
162
163 // If we could not find a frame destroy opcode, then it has already
164 // been simplified, so we don't care.
165 if (I->getOpcode() != getCallFrameDestroyOpcode())
166 return 0;
167
168 return -(I->getOperand(1).getImm());
169 }
170
171 // Currently handle only PUSHes we can reasonably expect to see
172 // in call sequences
173 switch (MI.getOpcode()) {
174 default:
175 return 0;
176 case X86::PUSH32i8:
177 case X86::PUSH32r:
178 case X86::PUSH32rmm:
179 case X86::PUSH32rmr:
180 case X86::PUSHi32:
181 return 4;
182 case X86::PUSH64i8:
183 case X86::PUSH64r:
184 case X86::PUSH64rmm:
185 case X86::PUSH64rmr:
186 case X86::PUSH64i32:
187 return 8;
188 }
189 }
190
191 /// Return true and the FrameIndex if the specified
192 /// operand and follow operands form a reference to the stack frame.
193 bool X86InstrInfo::isFrameOperand(const MachineInstr &MI, unsigned int Op,
194 int &FrameIndex) const {
195 if (MI.getOperand(Op + X86::AddrBaseReg).isFI() &&
196 MI.getOperand(Op + X86::AddrScaleAmt).isImm() &&
197 MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
198 MI.getOperand(Op + X86::AddrDisp).isImm() &&
199 MI.getOperand(Op + X86::AddrScaleAmt).getImm() == 1 &&
200 MI.getOperand(Op + X86::AddrIndexReg).getReg() == 0 &&
201 MI.getOperand(Op + X86::AddrDisp).getImm() == 0) {
202 FrameIndex = MI.getOperand(Op + X86::AddrBaseReg).getIndex();
203 return true;
204 }
205 return false;
206 }
207
208 static bool isFrameLoadOpcode(int Opcode, unsigned &MemBytes) {
209 switch (Opcode) {
210 default:
211 return false;
212 case X86::MOV8rm:
213 case X86::KMOVBkm:
214 MemBytes = 1;
215 return true;
216 case X86::MOV16rm:
217 case X86::KMOVWkm:
218 MemBytes = 2;
219 return true;
220 case X86::MOV32rm:
221 case X86::MOVSSrm:
222 case X86::MOVSSrm_alt:
223 case X86::VMOVSSrm:
224 case X86::VMOVSSrm_alt:
225 case X86::VMOVSSZrm:
226 case X86::VMOVSSZrm_alt:
227 case X86::KMOVDkm:
228 MemBytes = 4;
229 return true;
230 case X86::MOV64rm:
231 case X86::LD_Fp64m:
232 case X86::MOVSDrm:
233 case X86::MOVSDrm_alt:
234 case X86::VMOVSDrm:
235 case X86::VMOVSDrm_alt:
236 case X86::VMOVSDZrm:
237 case X86::VMOVSDZrm_alt:
238 case X86::MMX_MOVD64rm:
239 case X86::MMX_MOVQ64rm:
240 case X86::KMOVQkm:
241 MemBytes = 8;
242 return true;
243 case X86::MOVAPSrm:
244 case X86::MOVUPSrm:
245 case X86::MOVAPDrm:
246 case X86::MOVUPDrm:
247 case X86::MOVDQArm:
248 case X86::MOVDQUrm:
249 case X86::VMOVAPSrm:
250 case X86::VMOVUPSrm:
251 case X86::VMOVAPDrm:
252 case X86::VMOVUPDrm:
253 case X86::VMOVDQArm:
254 case X86::VMOVDQUrm:
255 case X86::VMOVAPSZ128rm:
256 case X86::VMOVUPSZ128rm:
257 case X86::VMOVAPSZ128rm_NOVLX:
258 case X86::VMOVUPSZ128rm_NOVLX:
259 case X86::VMOVAPDZ128rm:
260 case X86::VMOVUPDZ128rm:
261 case X86::VMOVDQU8Z128rm:
262 case X86::VMOVDQU16Z128rm:
263 case X86::VMOVDQA32Z128rm:
264 case X86::VMOVDQU32Z128rm:
265 case X86::VMOVDQA64Z128rm:
266 case X86::VMOVDQU64Z128rm:
267 MemBytes = 16;
268 return true;
269 case X86::VMOVAPSYrm:
270 case X86::VMOVUPSYrm:
271 case X86::VMOVAPDYrm:
272 case X86::VMOVUPDYrm:
273 case X86::VMOVDQAYrm:
274 case X86::VMOVDQUYrm:
275 case X86::VMOVAPSZ256rm:
276 case X86::VMOVUPSZ256rm:
277 case X86::VMOVAPSZ256rm_NOVLX:
278 case X86::VMOVUPSZ256rm_NOVLX:
279 case X86::VMOVAPDZ256rm:
280 case X86::VMOVUPDZ256rm:
281 case X86::VMOVDQU8Z256rm:
282 case X86::VMOVDQU16Z256rm:
283 case X86::VMOVDQA32Z256rm:
284 case X86::VMOVDQU32Z256rm:
285 case X86::VMOVDQA64Z256rm:
286 case X86::VMOVDQU64Z256rm:
287 MemBytes = 32;
288 return true;
289 case X86::VMOVAPSZrm:
290 case X86::VMOVUPSZrm:
291 case X86::VMOVAPDZrm:
292 case X86::VMOVUPDZrm:
293 case X86::VMOVDQU8Zrm:
294 case X86::VMOVDQU16Zrm:
295 case X86::VMOVDQA32Zrm:
296 case X86::VMOVDQU32Zrm:
297 case X86::VMOVDQA64Zrm:
298 case X86::VMOVDQU64Zrm:
299 MemBytes = 64;
300 return true;
301 }
302 }
303
304 static bool isFrameStoreOpcode(int Opcode, unsigned &MemBytes) {
305 switch (Opcode) {
306 default:
307 return false;
308 case X86::MOV8mr:
309 case X86::KMOVBmk:
310 MemBytes = 1;
311 return true;
312 case X86::MOV16mr:
313 case X86::KMOVWmk:
314 MemBytes = 2;
315 return true;
316 case X86::MOV32mr:
317 case X86::MOVSSmr:
318 case X86::VMOVSSmr:
319 case X86::VMOVSSZmr:
320 case X86::KMOVDmk:
321 MemBytes = 4;
322 return true;
323 case X86::MOV64mr:
324 case X86::ST_FpP64m:
325 case X86::MOVSDmr:
326 case X86::VMOVSDmr:
327 case X86::VMOVSDZmr:
328 case X86::MMX_MOVD64mr:
329 case X86::MMX_MOVQ64mr:
330 case X86::MMX_MOVNTQmr:
331 case X86::KMOVQmk:
332 MemBytes = 8;
333 return true;
334 case X86::MOVAPSmr:
335 case X86::MOVUPSmr:
336 case X86::MOVAPDmr:
337 case X86::MOVUPDmr:
338 case X86::MOVDQAmr:
339 case X86::MOVDQUmr:
340 case X86::VMOVAPSmr:
341 case X86::VMOVUPSmr:
342 case X86::VMOVAPDmr:
343 case X86::VMOVUPDmr:
344 case X86::VMOVDQAmr:
345 case X86::VMOVDQUmr:
346 case X86::VMOVUPSZ128mr:
347 case X86::VMOVAPSZ128mr:
348 case X86::VMOVUPSZ128mr_NOVLX:
349 case X86::VMOVAPSZ128mr_NOVLX:
350 case X86::VMOVUPDZ128mr:
351 case X86::VMOVAPDZ128mr:
352 case X86::VMOVDQA32Z128mr:
353 case X86::VMOVDQU32Z128mr:
354 case X86::VMOVDQA64Z128mr:
355 case X86::VMOVDQU64Z128mr:
356 case X86::VMOVDQU8Z128mr:
357 case X86::VMOVDQU16Z128mr:
358 MemBytes = 16;
359 return true;
360 case X86::VMOVUPSYmr:
361 case X86::VMOVAPSYmr:
362 case X86::VMOVUPDYmr:
363 case X86::VMOVAPDYmr:
364 case X86::VMOVDQUYmr:
365 case X86::VMOVDQAYmr:
366 case X86::VMOVUPSZ256mr:
367 case X86::VMOVAPSZ256mr:
368 case X86::VMOVUPSZ256mr_NOVLX:
369 case X86::VMOVAPSZ256mr_NOVLX:
370 case X86::VMOVUPDZ256mr:
371 case X86::VMOVAPDZ256mr:
372 case X86::VMOVDQU8Z256mr:
373 case X86::VMOVDQU16Z256mr:
374 case X86::VMOVDQA32Z256mr:
375 case X86::VMOVDQU32Z256mr:
376 case X86::VMOVDQA64Z256mr:
377 case X86::VMOVDQU64Z256mr:
378 MemBytes = 32;
379 return true;
380 case X86::VMOVUPSZmr:
381 case X86::VMOVAPSZmr:
382 case X86::VMOVUPDZmr:
383 case X86::VMOVAPDZmr:
384 case X86::VMOVDQU8Zmr:
385 case X86::VMOVDQU16Zmr:
386 case X86::VMOVDQA32Zmr:
387 case X86::VMOVDQU32Zmr:
388 case X86::VMOVDQA64Zmr:
389 case X86::VMOVDQU64Zmr:
390 MemBytes = 64;
391 return true;
392 }
393 return false;
394 }
395
396 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
397 int &FrameIndex) const {
398 unsigned Dummy;
399 return X86InstrInfo::isLoadFromStackSlot(MI, FrameIndex, Dummy);
400 }
401
402 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
403 int &FrameIndex,
404 unsigned &MemBytes) const {
405 if (isFrameLoadOpcode(MI.getOpcode(), MemBytes))
406 if (MI.getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
407 return MI.getOperand(0).getReg();
408 return 0;
409 }
410
411 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
412 int &FrameIndex) const {
413 unsigned Dummy;
414 if (isFrameLoadOpcode(MI.getOpcode(), Dummy)) {
415 unsigned Reg;
416 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
417 return Reg;
418 // Check for post-frame index elimination operations
419 SmallVector<const MachineMemOperand *, 1> Accesses;
420 if (hasLoadFromStackSlot(MI, Accesses)) {
421 FrameIndex =
422 cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
423 ->getFrameIndex();
424 return 1;
425 }
426 }
427 return 0;
428 }
429
430 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
431 int &FrameIndex) const {
432 unsigned Dummy;
433 return X86InstrInfo::isStoreToStackSlot(MI, FrameIndex, Dummy);
434 }
435
436 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
437 int &FrameIndex,
438 unsigned &MemBytes) const {
439 if (isFrameStoreOpcode(MI.getOpcode(), MemBytes))
440 if (MI.getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
441 isFrameOperand(MI, 0, FrameIndex))
442 return MI.getOperand(X86::AddrNumOperands).getReg();
443 return 0;
444 }
445
446 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
447 int &FrameIndex) const {
448 unsigned Dummy;
449 if (isFrameStoreOpcode(MI.getOpcode(), Dummy)) {
450 unsigned Reg;
451 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
452 return Reg;
453 // Check for post-frame index elimination operations
454 SmallVector<const MachineMemOperand *, 1> Accesses;
455 if (hasStoreToStackSlot(MI, Accesses)) {
456 FrameIndex =
457 cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
458 ->getFrameIndex();
459 return 1;
460 }
461 }
462 return 0;
463 }
464
465 /// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
466 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
467 // Don't waste compile time scanning use-def chains of physregs.
468 if (!Register::isVirtualRegister(BaseReg))
469 return false;
470 bool isPICBase = false;
471 for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
472 E = MRI.def_instr_end(); I != E; ++I) {
473 MachineInstr *DefMI = &*I;
474 if (DefMI->getOpcode() != X86::MOVPC32r)
475 return false;
476 assert(!isPICBase && "More than one PIC base?");
477 isPICBase = true;
478 }
479 return isPICBase;
480 }
481
482 bool X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
483 AliasAnalysis *AA) const {
484 switch (MI.getOpcode()) {
485 default: break;
486 case X86::MOV8rm:
487 case X86::MOV8rm_NOREX:
488 case X86::MOV16rm:
489 case X86::MOV32rm:
490 case X86::MOV64rm:
491 case X86::MOVSSrm:
492 case X86::MOVSSrm_alt:
493 case X86::MOVSDrm:
494 case X86::MOVSDrm_alt:
495 case X86::MOVAPSrm:
496 case X86::MOVUPSrm:
497 case X86::MOVAPDrm:
498 case X86::MOVUPDrm:
499 case X86::MOVDQArm:
500 case X86::MOVDQUrm:
501 case X86::VMOVSSrm:
502 case X86::VMOVSSrm_alt:
503 case X86::VMOVSDrm:
504 case X86::VMOVSDrm_alt:
505 case X86::VMOVAPSrm:
506 case X86::VMOVUPSrm:
507 case X86::VMOVAPDrm:
508 case X86::VMOVUPDrm:
509 case X86::VMOVDQArm:
510 case X86::VMOVDQUrm:
511 case X86::VMOVAPSYrm:
512 case X86::VMOVUPSYrm:
513 case X86::VMOVAPDYrm:
514 case X86::VMOVUPDYrm:
515 case X86::VMOVDQAYrm:
516 case X86::VMOVDQUYrm:
517 case X86::MMX_MOVD64rm:
518 case X86::MMX_MOVQ64rm:
519 // AVX-512
520 case X86::VMOVSSZrm:
521 case X86::VMOVSSZrm_alt:
522 case X86::VMOVSDZrm:
523 case X86::VMOVSDZrm_alt:
524 case X86::VMOVAPDZ128rm:
525 case X86::VMOVAPDZ256rm:
526 case X86::VMOVAPDZrm:
527 case X86::VMOVAPSZ128rm:
528 case X86::VMOVAPSZ256rm:
529 case X86::VMOVAPSZ128rm_NOVLX:
530 case X86::VMOVAPSZ256rm_NOVLX:
531 case X86::VMOVAPSZrm:
532 case X86::VMOVDQA32Z128rm:
533 case X86::VMOVDQA32Z256rm:
534 case X86::VMOVDQA32Zrm:
535 case X86::VMOVDQA64Z128rm:
536 case X86::VMOVDQA64Z256rm:
537 case X86::VMOVDQA64Zrm:
538 case X86::VMOVDQU16Z128rm:
539 case X86::VMOVDQU16Z256rm:
540 case X86::VMOVDQU16Zrm:
541 case X86::VMOVDQU32Z128rm:
542 case X86::VMOVDQU32Z256rm:
543 case X86::VMOVDQU32Zrm:
544 case X86::VMOVDQU64Z128rm:
545 case X86::VMOVDQU64Z256rm:
546 case X86::VMOVDQU64Zrm:
547 case X86::VMOVDQU8Z128rm:
548 case X86::VMOVDQU8Z256rm:
549 case X86::VMOVDQU8Zrm:
550 case X86::VMOVUPDZ128rm:
551 case X86::VMOVUPDZ256rm:
552 case X86::VMOVUPDZrm:
553 case X86::VMOVUPSZ128rm:
554 case X86::VMOVUPSZ256rm:
555 case X86::VMOVUPSZ128rm_NOVLX:
556 case X86::VMOVUPSZ256rm_NOVLX:
557 case X86::VMOVUPSZrm: {
558 // Loads from constant pools are trivially rematerializable.
559 if (MI.getOperand(1 + X86::AddrBaseReg).isReg() &&
560 MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
561 MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
562 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
563 MI.isDereferenceableInvariantLoad(AA)) {
564 Register BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
565 if (BaseReg == 0 || BaseReg == X86::RIP)
566 return true;
567 // Allow re-materialization of PIC load.
568 if (!ReMatPICStubLoad && MI.getOperand(1 + X86::AddrDisp).isGlobal())
569 return false;
570 const MachineFunction &MF = *MI.getParent()->getParent();
571 const MachineRegisterInfo &MRI = MF.getRegInfo();
572 return regIsPICBase(BaseReg, MRI);
573 }
574 return false;
575 }
576
577 case X86::LEA32r:
578 case X86::LEA64r: {
579 if (MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
580 MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
581 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
582 !MI.getOperand(1 + X86::AddrDisp).isReg()) {
583 // lea fi#, lea GV, etc. are all rematerializable.
584 if (!MI.getOperand(1 + X86::AddrBaseReg).isReg())
585 return true;
586 Register BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
587 if (BaseReg == 0)
588 return true;
589 // Allow re-materialization of lea PICBase + x.
590 const MachineFunction &MF = *MI.getParent()->getParent();
591 const MachineRegisterInfo &MRI = MF.getRegInfo();
592 return regIsPICBase(BaseReg, MRI);
593 }
594 return false;
595 }
596 }
597
598 // All other instructions marked M_REMATERIALIZABLE are always trivially
599 // rematerializable.
600 return true;
601 }
602
603 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
604 MachineBasicBlock::iterator I,
605 unsigned DestReg, unsigned SubIdx,
606 const MachineInstr &Orig,
607 const TargetRegisterInfo &TRI) const {
608 bool ClobbersEFLAGS = Orig.modifiesRegister(X86::EFLAGS, &TRI);
609 if (ClobbersEFLAGS && !isSafeToClobberEFLAGS(MBB, I)) {
610 // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side
611 // effects.
612 int Value;
613 switch (Orig.getOpcode()) {
614 case X86::MOV32r0: Value = 0; break;
615 case X86::MOV32r1: Value = 1; break;
616 case X86::MOV32r_1: Value = -1; break;
617 default:
618 llvm_unreachable("Unexpected instruction!");
619 }
620
621 const DebugLoc &DL = Orig.getDebugLoc();
622 BuildMI(MBB, I, DL, get(X86::MOV32ri))
623 .add(Orig.getOperand(0))
624 .addImm(Value);
625 } else {
626 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
627 MBB.insert(I, MI);
628 }
629
630 MachineInstr &NewMI = *std::prev(I);
631 NewMI.substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
632 }
633
634 /// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
635 bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr &MI) const {
636 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
637 MachineOperand &MO = MI.getOperand(i);
638 if (MO.isReg() && MO.isDef() &&
639 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
640 return true;
641 }
642 }
643 return false;
644 }
645
646 /// Check whether the shift count for a machine operand is non-zero.
647 inline static unsigned getTruncatedShiftCount(const MachineInstr &MI,
648 unsigned ShiftAmtOperandIdx) {
649 // The shift count is six bits with the REX.W prefix and five bits without.
650 unsigned ShiftCountMask = (MI.getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
651 unsigned Imm = MI.getOperand(ShiftAmtOperandIdx).getImm();
652 return Imm & ShiftCountMask;
653 }
654
655 /// Check whether the given shift count is appropriate
656 /// can be represented by a LEA instruction.
657 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
658 // Left shift instructions can be transformed into load-effective-address
659 // instructions if we can encode them appropriately.
660 // A LEA instruction utilizes a SIB byte to encode its scale factor.
661 // The SIB.scale field is two bits wide which means that we can encode any
662 // shift amount less than 4.
663 return ShAmt < 4 && ShAmt > 0;
664 }
665
666 bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
667 unsigned Opc, bool AllowSP, Register &NewSrc,
668 bool &isKill, MachineOperand &ImplicitOp,
669 LiveVariables *LV) const {
670 MachineFunction &MF = *MI.getParent()->getParent();
671 const TargetRegisterClass *RC;
672 if (AllowSP) {
673 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
674 } else {
675 RC = Opc != X86::LEA32r ?
676 &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
677 }
678 Register SrcReg = Src.getReg();
679
680 // For both LEA64 and LEA32 the register already has essentially the right
681 // type (32-bit or 64-bit) we may just need to forbid SP.
682 if (Opc != X86::LEA64_32r) {
683 NewSrc = SrcReg;
684 isKill = Src.isKill();
685 assert(!Src.isUndef() && "Undef op doesn't need optimization");
686
687 if (Register::isVirtualRegister(NewSrc) &&
688 !MF.getRegInfo().constrainRegClass(NewSrc, RC))
689 return false;
690
691 return true;
692 }
693
694 // This is for an LEA64_32r and incoming registers are 32-bit. One way or
695 // another we need to add 64-bit registers to the final MI.
696 if (Register::isPhysicalRegister(SrcReg)) {
697 ImplicitOp = Src;
698 ImplicitOp.setImplicit();
699
700 NewSrc = getX86SubSuperRegister(Src.getReg(), 64);
701 isKill = Src.isKill();
702 assert(!Src.isUndef() && "Undef op doesn't need optimization");
703 } else {
704 // Virtual register of the wrong class, we have to create a temporary 64-bit
705 // vreg to feed into the LEA.
706 NewSrc = MF.getRegInfo().createVirtualRegister(RC);
707 MachineInstr *Copy =
708 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(TargetOpcode::COPY))
709 .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
710 .add(Src);
711
712 // Which is obviously going to be dead after we're done with it.
713 isKill = true;
714
715 if (LV)
716 LV->replaceKillInstruction(SrcReg, MI, *Copy);
717 }
718
719 // We've set all the parameters without issue.
720 return true;
721 }
722
723 MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(
724 unsigned MIOpc, MachineFunction::iterator &MFI, MachineInstr &MI,
725 LiveVariables *LV, bool Is8BitOp) const {
726 // We handle 8-bit adds and various 16-bit opcodes in the switch below.
727 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
728 assert((Is8BitOp || RegInfo.getTargetRegisterInfo()->getRegSizeInBits(
729 *RegInfo.getRegClass(MI.getOperand(0).getReg())) == 16) &&
730 "Unexpected type for LEA transform");
731
732 // TODO: For a 32-bit target, we need to adjust the LEA variables with
733 // something like this:
734 // Opcode = X86::LEA32r;
735 // InRegLEA = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
736 // OutRegLEA =
737 // Is8BitOp ? RegInfo.createVirtualRegister(&X86::GR32ABCD_RegClass)
738 // : RegInfo.createVirtualRegister(&X86::GR32RegClass);
739 if (!Subtarget.is64Bit())
740 return nullptr;
741
742 unsigned Opcode = X86::LEA64_32r;
743 Register InRegLEA = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
744 Register OutRegLEA = RegInfo.createVirtualRegister(&X86::GR32RegClass);
745
746 // Build and insert into an implicit UNDEF value. This is OK because
747 // we will be shifting and then extracting the lower 8/16-bits.
748 // This has the potential to cause partial register stall. e.g.
749 // movw (%rbp,%rcx,2), %dx
750 // leal -65(%rdx), %esi
751 // But testing has shown this *does* help performance in 64-bit mode (at
752 // least on modern x86 machines).
753 MachineBasicBlock::iterator MBBI = MI.getIterator();
754 Register Dest = MI.getOperand(0).getReg();
755 Register Src = MI.getOperand(1).getReg();
756 bool IsDead = MI.getOperand(0).isDead();
757 bool IsKill = MI.getOperand(1).isKill();
758 unsigned SubReg = Is8BitOp ? X86::sub_8bit : X86::sub_16bit;
759 assert(!MI.getOperand(1).isUndef() && "Undef op doesn't need optimization");
760 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), InRegLEA);
761 MachineInstr *InsMI =
762 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
763 .addReg(InRegLEA, RegState::Define, SubReg)
764 .addReg(Src, getKillRegState(IsKill));
765
766 MachineInstrBuilder MIB =
767 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(Opcode), OutRegLEA);
768 switch (MIOpc) {
769 default: llvm_unreachable("Unreachable!");
770 case X86::SHL8ri:
771 case X86::SHL16ri: {
772 unsigned ShAmt = MI.getOperand(2).getImm();
773 MIB.addReg(0).addImm(1ULL << ShAmt)
774 .addReg(InRegLEA, RegState::Kill).addImm(0).addReg(0);
775 break;
776 }
777 case X86::INC8r:
778 case X86::INC16r:
779 addRegOffset(MIB, InRegLEA, true, 1);
780 break;
781 case X86::DEC8r:
782 case X86::DEC16r:
783 addRegOffset(MIB, InRegLEA, true, -1);
784 break;
785 case X86::ADD8ri:
786 case X86::ADD8ri_DB:
787 case X86::ADD16ri:
788 case X86::ADD16ri8:
789 case X86::ADD16ri_DB:
790 case X86::ADD16ri8_DB:
791 addRegOffset(MIB, InRegLEA, true, MI.getOperand(2).getImm());
792 break;
793 case X86::ADD8rr:
794 case X86::ADD8rr_DB:
795 case X86::ADD16rr:
796 case X86::ADD16rr_DB: {
797 Register Src2 = MI.getOperand(2).getReg();
798 bool IsKill2 = MI.getOperand(2).isKill();
799 assert(!MI.getOperand(2).isUndef() && "Undef op doesn't need optimization");
800 unsigned InRegLEA2 = 0;
801 MachineInstr *InsMI2 = nullptr;
802 if (Src == Src2) {
803 // ADD8rr/ADD16rr killed %reg1028, %reg1028
804 // just a single insert_subreg.
805 addRegReg(MIB, InRegLEA, true, InRegLEA, false);
806 } else {
807 if (Subtarget.is64Bit())
808 InRegLEA2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
809 else
810 InRegLEA2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
811 // Build and insert into an implicit UNDEF value. This is OK because
812 // we will be shifting and then extracting the lower 8/16-bits.
813 BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), InRegLEA2);
814 InsMI2 = BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(TargetOpcode::COPY))
815 .addReg(InRegLEA2, RegState::Define, SubReg)
816 .addReg(Src2, getKillRegState(IsKill2));
817 addRegReg(MIB, InRegLEA, true, InRegLEA2, true);
818 }
819 if (LV && IsKill2 && InsMI2)
820 LV->replaceKillInstruction(Src2, MI, *InsMI2);
821 break;
822 }
823 }
824
825 MachineInstr *NewMI = MIB;
826 MachineInstr *ExtMI =
827 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
828 .addReg(Dest, RegState::Define | getDeadRegState(IsDead))
829 .addReg(OutRegLEA, RegState::Kill, SubReg);
830
831 if (LV) {
832 // Update live variables.
833 LV->getVarInfo(InRegLEA).Kills.push_back(NewMI);
834 LV->getVarInfo(OutRegLEA).Kills.push_back(ExtMI);
835 if (IsKill)
836 LV->replaceKillInstruction(Src, MI, *InsMI);
837 if (IsDead)
838 LV->replaceKillInstruction(Dest, MI, *ExtMI);
839 }
840
841 return ExtMI;
842 }
843
844 /// This method must be implemented by targets that
845 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
846 /// may be able to convert a two-address instruction into a true
847 /// three-address instruction on demand. This allows the X86 target (for
848 /// example) to convert ADD and SHL instructions into LEA instructions if they
849 /// would require register copies due to two-addressness.
850 ///
851 /// This method returns a null pointer if the transformation cannot be
852 /// performed, otherwise it returns the new instruction.
853 ///
854 MachineInstr *
855 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
856 MachineInstr &MI, LiveVariables *LV) const {
857 // The following opcodes also sets the condition code register(s). Only
858 // convert them to equivalent lea if the condition code register def's
859 // are dead!
860 if (hasLiveCondCodeDef(MI))
861 return nullptr;
862
863 MachineFunction &MF = *MI.getParent()->getParent();
864 // All instructions input are two-addr instructions. Get the known operands.
865 const MachineOperand &Dest = MI.getOperand(0);
866 const MachineOperand &Src = MI.getOperand(1);
867
868 // Ideally, operations with undef should be folded before we get here, but we
869 // can't guarantee it. Bail out because optimizing undefs is a waste of time.
870 // Without this, we have to forward undef state to new register operands to
871 // avoid machine verifier errors.
872 if (Src.isUndef())
873 return nullptr;
874 if (MI.getNumOperands() > 2)
875 if (MI.getOperand(2).isReg() && MI.getOperand(2).isUndef())
876 return nullptr;
877
878 MachineInstr *NewMI = nullptr;
879 bool Is64Bit = Subtarget.is64Bit();
880
881 bool Is8BitOp = false;
882 unsigned MIOpc = MI.getOpcode();
883 switch (MIOpc) {
884 default: llvm_unreachable("Unreachable!");
885 case X86::SHL64ri: {
886 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
887 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
888 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
889
890 // LEA can't handle RSP.
891 if (Register::isVirtualRegister(Src.getReg()) &&
892 !MF.getRegInfo().constrainRegClass(Src.getReg(),
893 &X86::GR64_NOSPRegClass))
894 return nullptr;
895
896 NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
897 .add(Dest)
898 .addReg(0)
899 .addImm(1ULL << ShAmt)
900 .add(Src)
901 .addImm(0)
902 .addReg(0);
903 break;
904 }
905 case X86::SHL32ri: {
906 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
907 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
908 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
909
910 unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
911
912 // LEA can't handle ESP.
913 bool isKill;
914 Register SrcReg;
915 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
916 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
917 SrcReg, isKill, ImplicitOp, LV))
918 return nullptr;
919
920 MachineInstrBuilder MIB =
921 BuildMI(MF, MI.getDebugLoc(), get(Opc))
922 .add(Dest)
923 .addReg(0)
924 .addImm(1ULL << ShAmt)
925 .addReg(SrcReg, getKillRegState(isKill))
926 .addImm(0)
927 .addReg(0);
928 if (ImplicitOp.getReg() != 0)
929 MIB.add(ImplicitOp);
930 NewMI = MIB;
931
932 break;
933 }
934 case X86::SHL8ri:
935 Is8BitOp = true;
936 LLVM_FALLTHROUGH;
937 case X86::SHL16ri: {
938 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
939 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
940 if (!isTruncatedShiftCountForLEA(ShAmt))
941 return nullptr;
942 return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
943 }
944 case X86::INC64r:
945 case X86::INC32r: {
946 assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
947 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r :
948 (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
949 bool isKill;
950 Register SrcReg;
951 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
952 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, SrcReg, isKill,
953 ImplicitOp, LV))
954 return nullptr;
955
956 MachineInstrBuilder MIB =
957 BuildMI(MF, MI.getDebugLoc(), get(Opc))
958 .add(Dest)
959 .addReg(SrcReg, getKillRegState(isKill));
960 if (ImplicitOp.getReg() != 0)
961 MIB.add(ImplicitOp);
962
963 NewMI = addOffset(MIB, 1);
964 break;
965 }
966 case X86::DEC64r:
967 case X86::DEC32r: {
968 assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
969 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
970 : (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
971
972 bool isKill;
973 Register SrcReg;
974 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
975 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, SrcReg, isKill,
976 ImplicitOp, LV))
977 return nullptr;
978
979 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
980 .add(Dest)
981 .addReg(SrcReg, getKillRegState(isKill));
982 if (ImplicitOp.getReg() != 0)
983 MIB.add(ImplicitOp);
984
985 NewMI = addOffset(MIB, -1);
986
987 break;
988 }
989 case X86::DEC8r:
990 case X86::INC8r:
991 Is8BitOp = true;
992 LLVM_FALLTHROUGH;
993 case X86::DEC16r:
994 case X86::INC16r:
995 return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
996 case X86::ADD64rr:
997 case X86::ADD64rr_DB:
998 case X86::ADD32rr:
999 case X86::ADD32rr_DB: {
1000 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1001 unsigned Opc;
1002 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
1003 Opc = X86::LEA64r;
1004 else
1005 Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1006
1007 bool isKill;
1008 Register SrcReg;
1009 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1010 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
1011 SrcReg, isKill, ImplicitOp, LV))
1012 return nullptr;
1013
1014 const MachineOperand &Src2 = MI.getOperand(2);
1015 bool isKill2;
1016 Register SrcReg2;
1017 MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
1018 if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
1019 SrcReg2, isKill2, ImplicitOp2, LV))
1020 return nullptr;
1021
1022 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc)).add(Dest);
1023 if (ImplicitOp.getReg() != 0)
1024 MIB.add(ImplicitOp);
1025 if (ImplicitOp2.getReg() != 0)
1026 MIB.add(ImplicitOp2);
1027
1028 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
1029 if (LV && Src2.isKill())
1030 LV->replaceKillInstruction(SrcReg2, MI, *NewMI);
1031 break;
1032 }
1033 case X86::ADD8rr:
1034 case X86::ADD8rr_DB:
1035 Is8BitOp = true;
1036 LLVM_FALLTHROUGH;
1037 case X86::ADD16rr:
1038 case X86::ADD16rr_DB:
1039 return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
1040 case X86::ADD64ri32:
1041 case X86::ADD64ri8:
1042 case X86::ADD64ri32_DB:
1043 case X86::ADD64ri8_DB:
1044 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1045 NewMI = addOffset(
1046 BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r)).add(Dest).add(Src),
1047 MI.getOperand(2));
1048 break;
1049 case X86::ADD32ri:
1050 case X86::ADD32ri8:
1051 case X86::ADD32ri_DB:
1052 case X86::ADD32ri8_DB: {
1053 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1054 unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1055
1056 bool isKill;
1057 Register SrcReg;
1058 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1059 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
1060 SrcReg, isKill, ImplicitOp, LV))
1061 return nullptr;
1062
1063 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1064 .add(Dest)
1065 .addReg(SrcReg, getKillRegState(isKill));
1066 if (ImplicitOp.getReg() != 0)
1067 MIB.add(ImplicitOp);
1068
1069 NewMI = addOffset(MIB, MI.getOperand(2));
1070 break;
1071 }
1072 case X86::ADD8ri:
1073 case X86::ADD8ri_DB:
1074 Is8BitOp = true;
1075 LLVM_FALLTHROUGH;
1076 case X86::ADD16ri:
1077 case X86::ADD16ri8:
1078 case X86::ADD16ri_DB:
1079 case X86::ADD16ri8_DB:
1080 return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
1081 case X86::SUB8ri:
1082 case X86::SUB16ri8:
1083 case X86::SUB16ri:
1084 /// FIXME: Support these similar to ADD8ri/ADD16ri*.
1085 return nullptr;
1086 case X86::SUB32ri8:
1087 case X86::SUB32ri: {
1088 int64_t Imm = MI.getOperand(2).getImm();
1089 if (!isInt<32>(-Imm))
1090 return nullptr;
1091
1092 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1093 unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1094
1095 bool isKill;
1096 Register SrcReg;
1097 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1098 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
1099 SrcReg, isKill, ImplicitOp, LV))
1100 return nullptr;
1101
1102 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1103 .add(Dest)
1104 .addReg(SrcReg, getKillRegState(isKill));
1105 if (ImplicitOp.getReg() != 0)
1106 MIB.add(ImplicitOp);
1107
1108 NewMI = addOffset(MIB, -Imm);
1109 break;
1110 }
1111
1112 case X86::SUB64ri8:
1113 case X86::SUB64ri32: {
1114 int64_t Imm = MI.getOperand(2).getImm();
1115 if (!isInt<32>(-Imm))
1116 return nullptr;
1117
1118 assert(MI.getNumOperands() >= 3 && "Unknown sub instruction!");
1119
1120 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(),
1121 get(X86::LEA64r)).add(Dest).add(Src);
1122 NewMI = addOffset(MIB, -Imm);
1123 break;
1124 }
1125
1126 case X86::VMOVDQU8Z128rmk:
1127 case X86::VMOVDQU8Z256rmk:
1128 case X86::VMOVDQU8Zrmk:
1129 case X86::VMOVDQU16Z128rmk:
1130 case X86::VMOVDQU16Z256rmk:
1131 case X86::VMOVDQU16Zrmk:
1132 case X86::VMOVDQU32Z128rmk: case X86::VMOVDQA32Z128rmk:
1133 case X86::VMOVDQU32Z256rmk: case X86::VMOVDQA32Z256rmk:
1134 case X86::VMOVDQU32Zrmk: case X86::VMOVDQA32Zrmk:
1135 case X86::VMOVDQU64Z128rmk: case X86::VMOVDQA64Z128rmk:
1136 case X86::VMOVDQU64Z256rmk: case X86::VMOVDQA64Z256rmk:
1137 case X86::VMOVDQU64Zrmk: case X86::VMOVDQA64Zrmk:
1138 case X86::VMOVUPDZ128rmk: case X86::VMOVAPDZ128rmk:
1139 case X86::VMOVUPDZ256rmk: case X86::VMOVAPDZ256rmk:
1140 case X86::VMOVUPDZrmk: case X86::VMOVAPDZrmk:
1141 case X86::VMOVUPSZ128rmk: case X86::VMOVAPSZ128rmk:
1142 case X86::VMOVUPSZ256rmk: case X86::VMOVAPSZ256rmk:
1143 case X86::VMOVUPSZrmk: case X86::VMOVAPSZrmk: {
1144 unsigned Opc;
1145 switch (MIOpc) {
1146 default: llvm_unreachable("Unreachable!");
1147 case X86::VMOVDQU8Z128rmk: Opc = X86::VPBLENDMBZ128rmk; break;
1148 case X86::VMOVDQU8Z256rmk: Opc = X86::VPBLENDMBZ256rmk; break;
1149 case X86::VMOVDQU8Zrmk: Opc = X86::VPBLENDMBZrmk; break;
1150 case X86::VMOVDQU16Z128rmk: Opc = X86::VPBLENDMWZ128rmk; break;
1151 case X86::VMOVDQU16Z256rmk: Opc = X86::VPBLENDMWZ256rmk; break;
1152 case X86::VMOVDQU16Zrmk: Opc = X86::VPBLENDMWZrmk; break;
1153 case X86::VMOVDQU32Z128rmk: Opc = X86::VPBLENDMDZ128rmk; break;
1154 case X86::VMOVDQU32Z256rmk: Opc = X86::VPBLENDMDZ256rmk; break;
1155 case X86::VMOVDQU32Zrmk: Opc = X86::VPBLENDMDZrmk; break;
1156 case X86::VMOVDQU64Z128rmk: Opc = X86::VPBLENDMQZ128rmk; break;
1157 case X86::VMOVDQU64Z256rmk: Opc = X86::VPBLENDMQZ256rmk; break;
1158 case X86::VMOVDQU64Zrmk: Opc = X86::VPBLENDMQZrmk; break;
1159 case X86::VMOVUPDZ128rmk: Opc = X86::VBLENDMPDZ128rmk; break;
1160 case X86::VMOVUPDZ256rmk: Opc = X86::VBLENDMPDZ256rmk; break;
1161 case X86::VMOVUPDZrmk: Opc = X86::VBLENDMPDZrmk; break;
1162 case X86::VMOVUPSZ128rmk: Opc = X86::VBLENDMPSZ128rmk; break;
1163 case X86::VMOVUPSZ256rmk: Opc = X86::VBLENDMPSZ256rmk; break;
1164 case X86::VMOVUPSZrmk: Opc = X86::VBLENDMPSZrmk; break;
1165 case X86::VMOVDQA32Z128rmk: Opc = X86::VPBLENDMDZ128rmk; break;
1166 case X86::VMOVDQA32Z256rmk: Opc = X86::VPBLENDMDZ256rmk; break;
1167 case X86::VMOVDQA32Zrmk: Opc = X86::VPBLENDMDZrmk; break;
1168 case X86::VMOVDQA64Z128rmk: Opc = X86::VPBLENDMQZ128rmk; break;
1169 case X86::VMOVDQA64Z256rmk: Opc = X86::VPBLENDMQZ256rmk; break;
1170 case X86::VMOVDQA64Zrmk: Opc = X86::VPBLENDMQZrmk; break;
1171 case X86::VMOVAPDZ128rmk: Opc = X86::VBLENDMPDZ128rmk; break;
1172 case X86::VMOVAPDZ256rmk: Opc = X86::VBLENDMPDZ256rmk; break;
1173 case X86::VMOVAPDZrmk: Opc = X86::VBLENDMPDZrmk; break;
1174 case X86::VMOVAPSZ128rmk: Opc = X86::VBLENDMPSZ128rmk; break;
1175 case X86::VMOVAPSZ256rmk: Opc = X86::VBLENDMPSZ256rmk; break;
1176 case X86::VMOVAPSZrmk: Opc = X86::VBLENDMPSZrmk; break;
1177 }
1178
1179 NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1180 .add(Dest)
1181 .add(MI.getOperand(2))
1182 .add(Src)
1183 .add(MI.getOperand(3))
1184 .add(MI.getOperand(4))
1185 .add(MI.getOperand(5))
1186 .add(MI.getOperand(6))
1187 .add(MI.getOperand(7));
1188 break;
1189 }
1190 case X86::VMOVDQU8Z128rrk:
1191 case X86::VMOVDQU8Z256rrk:
1192 case X86::VMOVDQU8Zrrk:
1193 case X86::VMOVDQU16Z128rrk:
1194 case X86::VMOVDQU16Z256rrk:
1195 case X86::VMOVDQU16Zrrk:
1196 case X86::VMOVDQU32Z128rrk: case X86::VMOVDQA32Z128rrk:
1197 case X86::VMOVDQU32Z256rrk: case X86::VMOVDQA32Z256rrk:
1198 case X86::VMOVDQU32Zrrk: case X86::VMOVDQA32Zrrk:
1199 case X86::VMOVDQU64Z128rrk: case X86::VMOVDQA64Z128rrk:
1200 case X86::VMOVDQU64Z256rrk: case X86::VMOVDQA64Z256rrk:
1201 case X86::VMOVDQU64Zrrk: case X86::VMOVDQA64Zrrk:
1202 case X86::VMOVUPDZ128rrk: case X86::VMOVAPDZ128rrk:
1203 case X86::VMOVUPDZ256rrk: case X86::VMOVAPDZ256rrk:
1204 case X86::VMOVUPDZrrk: case X86::VMOVAPDZrrk:
1205 case X86::VMOVUPSZ128rrk: case X86::VMOVAPSZ128rrk:
1206 case X86::VMOVUPSZ256rrk: case X86::VMOVAPSZ256rrk:
1207 case X86::VMOVUPSZrrk: case X86::VMOVAPSZrrk: {
1208 unsigned Opc;
1209 switch (MIOpc) {
1210 default: llvm_unreachable("Unreachable!");
1211 case X86::VMOVDQU8Z128rrk: Opc = X86::VPBLENDMBZ128rrk; break;
1212 case X86::VMOVDQU8Z256rrk: Opc = X86::VPBLENDMBZ256rrk; break;
1213 case X86::VMOVDQU8Zrrk: Opc = X86::VPBLENDMBZrrk; break;
1214 case X86::VMOVDQU16Z128rrk: Opc = X86::VPBLENDMWZ128rrk; break;
1215 case X86::VMOVDQU16Z256rrk: Opc = X86::VPBLENDMWZ256rrk; break;
1216 case X86::VMOVDQU16Zrrk: Opc = X86::VPBLENDMWZrrk; break;
1217 case X86::VMOVDQU32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
1218 case X86::VMOVDQU32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
1219 case X86::VMOVDQU32Zrrk: Opc = X86::VPBLENDMDZrrk; break;
1220 case X86::VMOVDQU64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
1221 case X86::VMOVDQU64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
1222 case X86::VMOVDQU64Zrrk: Opc = X86::VPBLENDMQZrrk; break;
1223 case X86::VMOVUPDZ128rrk: Opc = X86::VBLENDMPDZ128rrk; break;
1224 case X86::VMOVUPDZ256rrk: Opc = X86::VBLENDMPDZ256rrk; break;
1225 case X86::VMOVUPDZrrk: Opc = X86::VBLENDMPDZrrk; break;
1226 case X86::VMOVUPSZ128rrk: Opc = X86::VBLENDMPSZ128rrk; break;
1227 case X86::VMOVUPSZ256rrk: Opc = X86::VBLENDMPSZ256rrk; break;
1228 case X86::VMOVUPSZrrk: Opc = X86::VBLENDMPSZrrk; break;
1229 case X86::VMOVDQA32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
1230 case X86::VMOVDQA32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
1231 case X86::VMOVDQA32Zrrk: Opc = X86::VPBLENDMDZrrk; break;
1232 case X86::VMOVDQA64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
1233 case X86::VMOVDQA64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
1234 case X86::VMOVDQA64Zrrk: Opc = X86::VPBLENDMQZrrk; break;
1235 case X86::VMOVAPDZ128rrk: Opc = X86::VBLENDMPDZ128rrk; break;
1236 case X86::VMOVAPDZ256rrk: Opc = X86::VBLENDMPDZ256rrk; break;
1237 case X86::VMOVAPDZrrk: Opc = X86::VBLENDMPDZrrk; break;
1238 case X86::VMOVAPSZ128rrk: Opc = X86::VBLENDMPSZ128rrk; break;
1239 case X86::VMOVAPSZ256rrk: Opc = X86::VBLENDMPSZ256rrk; break;
1240 case X86::VMOVAPSZrrk: Opc = X86::VBLENDMPSZrrk; break;
1241 }
1242
1243 NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1244 .add(Dest)
1245 .add(MI.getOperand(2))
1246 .add(Src)
1247 .add(MI.getOperand(3));
1248 break;
1249 }
1250 }
1251
1252 if (!NewMI) return nullptr;
1253
1254 if (LV) { // Update live variables
1255 if (Src.isKill())
1256 LV->replaceKillInstruction(Src.getReg(), MI, *NewMI);
1257 if (Dest.isDead())
1258 LV->replaceKillInstruction(Dest.getReg(), MI, *NewMI);
1259 }
1260
1261 MFI->insert(MI.getIterator(), NewMI); // Insert the new inst
1262 return NewMI;
1263 }
1264
1265 /// This determines which of three possible cases of a three source commute
1266 /// the source indexes correspond to taking into account any mask operands.
1267 /// All prevents commuting a passthru operand. Returns -1 if the commute isn't
1268 /// possible.
1269 /// Case 0 - Possible to commute the first and second operands.
1270 /// Case 1 - Possible to commute the first and third operands.
1271 /// Case 2 - Possible to commute the second and third operands.
1272 static unsigned getThreeSrcCommuteCase(uint64_t TSFlags, unsigned SrcOpIdx1,
1273 unsigned SrcOpIdx2) {
1274 // Put the lowest index to SrcOpIdx1 to simplify the checks below.
1275 if (SrcOpIdx1 > SrcOpIdx2)
1276 std::swap(SrcOpIdx1, SrcOpIdx2);
1277
1278 unsigned Op1 = 1, Op2 = 2, Op3 = 3;
1279 if (X86II::isKMasked(TSFlags)) {
1280 Op2++;
1281 Op3++;
1282 }
1283
1284 if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op2)
1285 return 0;
1286 if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op3)
1287 return 1;
1288 if (SrcOpIdx1 == Op2 && SrcOpIdx2 == Op3)
1289 return 2;
1290 llvm_unreachable("Unknown three src commute case.");
1291 }
1292
1293 unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands(
1294 const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2,
1295 const X86InstrFMA3Group &FMA3Group) const {
1296
1297 unsigned Opc = MI.getOpcode();
1298
1299 // TODO: Commuting the 1st operand of FMA*_Int requires some additional
1300 // analysis. The commute optimization is legal only if all users of FMA*_Int
1301 // use only the lowest element of the FMA*_Int instruction. Such analysis are
1302 // not implemented yet. So, just return 0 in that case.
1303 // When such analysis are available this place will be the right place for
1304 // calling it.
1305 assert(!(FMA3Group.isIntrinsic() && (SrcOpIdx1 == 1 || SrcOpIdx2 == 1)) &&
1306 "Intrinsic instructions can't commute operand 1");
1307
1308 // Determine which case this commute is or if it can't be done.
1309 unsigned Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1,
1310 SrcOpIdx2);
1311 assert(Case < 3 && "Unexpected case number!");
1312
1313 // Define the FMA forms mapping array that helps to map input FMA form
1314 // to output FMA form to preserve the operation semantics after
1315 // commuting the operands.
1316 const unsigned Form132Index = 0;
1317 const unsigned Form213Index = 1;
1318 const unsigned Form231Index = 2;
1319 static const unsigned FormMapping[][3] = {
1320 // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
1321 // FMA132 A, C, b; ==> FMA231 C, A, b;
1322 // FMA213 B, A, c; ==> FMA213 A, B, c;
1323 // FMA231 C, A, b; ==> FMA132 A, C, b;
1324 { Form231Index, Form213Index, Form132Index },
1325 // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
1326 // FMA132 A, c, B; ==> FMA132 B, c, A;
1327 // FMA213 B, a, C; ==> FMA231 C, a, B;
1328 // FMA231 C, a, B; ==> FMA213 B, a, C;
1329 { Form132Index, Form231Index, Form213Index },
1330 // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
1331 // FMA132 a, C, B; ==> FMA213 a, B, C;
1332 // FMA213 b, A, C; ==> FMA132 b, C, A;
1333 // FMA231 c, A, B; ==> FMA231 c, B, A;
1334 { Form213Index, Form132Index, Form231Index }
1335 };
1336
1337 unsigned FMAForms[3];
1338 FMAForms[0] = FMA3Group.get132Opcode();
1339 FMAForms[1] = FMA3Group.get213Opcode();
1340 FMAForms[2] = FMA3Group.get231Opcode();
1341 unsigned FormIndex;
1342 for (FormIndex = 0; FormIndex < 3; FormIndex++)
1343 if (Opc == FMAForms[FormIndex])
1344 break;
1345
1346 // Everything is ready, just adjust the FMA opcode and return it.
1347 FormIndex = FormMapping[Case][FormIndex];
1348 return FMAForms[FormIndex];
1349 }
1350
1351 static void commuteVPTERNLOG(MachineInstr &MI, unsigned SrcOpIdx1,
1352 unsigned SrcOpIdx2) {
1353 // Determine which case this commute is or if it can't be done.
1354 unsigned Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1,
1355 SrcOpIdx2);
1356 assert(Case < 3 && "Unexpected case value!");
1357
1358 // For each case we need to swap two pairs of bits in the final immediate.
1359 static const uint8_t SwapMasks[3][4] = {
1360 { 0x04, 0x10, 0x08, 0x20 }, // Swap bits 2/4 and 3/5.
1361 { 0x02, 0x10, 0x08, 0x40 }, // Swap bits 1/4 and 3/6.
1362 { 0x02, 0x04, 0x20, 0x40 }, // Swap bits 1/2 and 5/6.
1363 };
1364
1365 uint8_t Imm = MI.getOperand(MI.getNumOperands()-1).getImm();
1366 // Clear out the bits we are swapping.
1367 uint8_t NewImm = Imm & ~(SwapMasks[Case][0] | SwapMasks[Case][1] |
1368 SwapMasks[Case][2] | SwapMasks[Case][3]);
1369 // If the immediate had a bit of the pair set, then set the opposite bit.
1370 if (Imm & SwapMasks[Case][0]) NewImm |= SwapMasks[Case][1];
1371 if (Imm & SwapMasks[Case][1]) NewImm |= SwapMasks[Case][0];
1372 if (Imm & SwapMasks[Case][2]) NewImm |= SwapMasks[Case][3];
1373 if (Imm & SwapMasks[Case][3]) NewImm |= SwapMasks[Case][2];
1374 MI.getOperand(MI.getNumOperands()-1).setImm(NewImm);
1375 }
1376
1377 // Returns true if this is a VPERMI2 or VPERMT2 instruction that can be
1378 // commuted.
1379 static bool isCommutableVPERMV3Instruction(unsigned Opcode) {
1380 #define VPERM_CASES(Suffix) \
1381 case X86::VPERMI2##Suffix##128rr: case X86::VPERMT2##Suffix##128rr: \
1382 case X86::VPERMI2##Suffix##256rr: case X86::VPERMT2##Suffix##256rr: \
1383 case X86::VPERMI2##Suffix##rr: case X86::VPERMT2##Suffix##rr: \
1384 case X86::VPERMI2##Suffix##128rm: case X86::VPERMT2##Suffix##128rm: \
1385 case X86::VPERMI2##Suffix##256rm: case X86::VPERMT2##Suffix##256rm: \
1386 case X86::VPERMI2##Suffix##rm: case X86::VPERMT2##Suffix##rm: \
1387 case X86::VPERMI2##Suffix##128rrkz: case X86::VPERMT2##Suffix##128rrkz: \
1388 case X86::VPERMI2##Suffix##256rrkz: case X86::VPERMT2##Suffix##256rrkz: \
1389 case X86::VPERMI2##Suffix##rrkz: case X86::VPERMT2##Suffix##rrkz: \
1390 case X86::VPERMI2##Suffix##128rmkz: case X86::VPERMT2##Suffix##128rmkz: \
1391 case X86::VPERMI2##Suffix##256rmkz: case X86::VPERMT2##Suffix##256rmkz: \
1392 case X86::VPERMI2##Suffix##rmkz: case X86::VPERMT2##Suffix##rmkz:
1393
1394 #define VPERM_CASES_BROADCAST(Suffix) \
1395 VPERM_CASES(Suffix) \
1396 case X86::VPERMI2##Suffix##128rmb: case X86::VPERMT2##Suffix##128rmb: \
1397 case X86::VPERMI2##Suffix##256rmb: case X86::VPERMT2##Suffix##256rmb: \
1398 case X86::VPERMI2##Suffix##rmb: case X86::VPERMT2##Suffix##rmb: \
1399 case X86::VPERMI2##Suffix##128rmbkz: case X86::VPERMT2##Suffix##128rmbkz: \
1400 case X86::VPERMI2##Suffix##256rmbkz: case X86::VPERMT2##Suffix##256rmbkz: \
1401 case X86::VPERMI2##Suffix##rmbkz: case X86::VPERMT2##Suffix##rmbkz:
1402
1403 switch (Opcode) {
1404 default: return false;
1405 VPERM_CASES(B)
1406 VPERM_CASES_BROADCAST(D)
1407 VPERM_CASES_BROADCAST(PD)
1408 VPERM_CASES_BROADCAST(PS)
1409 VPERM_CASES_BROADCAST(Q)
1410 VPERM_CASES(W)
1411 return true;
1412 }
1413 #undef VPERM_CASES_BROADCAST
1414 #undef VPERM_CASES
1415 }
1416
1417 // Returns commuted opcode for VPERMI2 and VPERMT2 instructions by switching
1418 // from the I opcode to the T opcode and vice versa.
1419 static unsigned getCommutedVPERMV3Opcode(unsigned Opcode) {
1420 #define VPERM_CASES(Orig, New) \
1421 case X86::Orig##128rr: return X86::New##128rr; \
1422 case X86::Orig##128rrkz: return X86::New##128rrkz; \
1423 case X86::Orig##128rm: return X86::New##128rm; \
1424 case X86::Orig##128rmkz: return X86::New##128rmkz; \
1425 case X86::Orig##256rr: return X86::New##256rr; \
1426 case X86::Orig##256rrkz: return X86::New##256rrkz; \
1427 case X86::Orig##256rm: return X86::New##256rm; \
1428 case X86::Orig##256rmkz: return X86::New##256rmkz; \
1429 case X86::Orig##rr: return X86::New##rr; \
1430 case X86::Orig##rrkz: return X86::New##rrkz; \
1431 case X86::Orig##rm: return X86::New##rm; \
1432 case X86::Orig##rmkz: return X86::New##rmkz;
1433
1434 #define VPERM_CASES_BROADCAST(Orig, New) \
1435 VPERM_CASES(Orig, New) \
1436 case X86::Orig##128rmb: return X86::New##128rmb; \
1437 case X86::Orig##128rmbkz: return X86::New##128rmbkz; \
1438 case X86::Orig##256rmb: return X86::New##256rmb; \
1439 case X86::Orig##256rmbkz: return X86::New##256rmbkz; \
1440 case X86::Orig##rmb: return X86::New##rmb; \
1441 case X86::Orig##rmbkz: return X86::New##rmbkz;
1442
1443 switch (Opcode) {
1444 VPERM_CASES(VPERMI2B, VPERMT2B)
1445 VPERM_CASES_BROADCAST(VPERMI2D, VPERMT2D)
1446 VPERM_CASES_BROADCAST(VPERMI2PD, VPERMT2PD)
1447 VPERM_CASES_BROADCAST(VPERMI2PS, VPERMT2PS)
1448 VPERM_CASES_BROADCAST(VPERMI2Q, VPERMT2Q)
1449 VPERM_CASES(VPERMI2W, VPERMT2W)
1450 VPERM_CASES(VPERMT2B, VPERMI2B)
1451 VPERM_CASES_BROADCAST(VPERMT2D, VPERMI2D)
1452 VPERM_CASES_BROADCAST(VPERMT2PD, VPERMI2PD)
1453 VPERM_CASES_BROADCAST(VPERMT2PS, VPERMI2PS)
1454 VPERM_CASES_BROADCAST(VPERMT2Q, VPERMI2Q)
1455 VPERM_CASES(VPERMT2W, VPERMI2W)
1456 }
1457
1458 llvm_unreachable("Unreachable!");
1459 #undef VPERM_CASES_BROADCAST
1460 #undef VPERM_CASES
1461 }
1462
1463 MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
1464 unsigned OpIdx1,
1465 unsigned OpIdx2) const {
1466 auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
1467 if (NewMI)
1468 return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
1469 return MI;
1470 };
1471
1472 switch (MI.getOpcode()) {
1473 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
1474 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
1475 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
1476 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
1477 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
1478 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
1479 unsigned Opc;
1480 unsigned Size;
1481 switch (MI.getOpcode()) {
1482 default: llvm_unreachable("Unreachable!");
1483 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
1484 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
1485 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
1486 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
1487 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
1488 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
1489 }
1490 unsigned Amt = MI.getOperand(3).getImm();
1491 auto &WorkingMI = cloneIfNew(MI);
1492 WorkingMI.setDesc(get(Opc));
1493 WorkingMI.getOperand(3).setImm(Size - Amt);
1494 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1495 OpIdx1, OpIdx2);
1496 }
1497 case X86::PFSUBrr:
1498 case X86::PFSUBRrr: {
1499 // PFSUB x, y: x = x - y
1500 // PFSUBR x, y: x = y - x
1501 unsigned Opc =
1502 (X86::PFSUBRrr == MI.getOpcode() ? X86::PFSUBrr : X86::PFSUBRrr);
1503 auto &WorkingMI = cloneIfNew(MI);
1504 WorkingMI.setDesc(get(Opc));
1505 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1506 OpIdx1, OpIdx2);
1507 }
1508 case X86::BLENDPDrri:
1509 case X86::BLENDPSrri:
1510 case X86::VBLENDPDrri:
1511 case X86::VBLENDPSrri:
1512 // If we're optimizing for size, try to use MOVSD/MOVSS.
1513 if (MI.getParent()->getParent()->getFunction().hasOptSize()) {
1514 unsigned Mask, Opc;
1515 switch (MI.getOpcode()) {
1516 default: llvm_unreachable("Unreachable!");
1517 case X86::BLENDPDrri: Opc = X86::MOVSDrr; Mask = 0x03; break;
1518 case X86::BLENDPSrri: Opc = X86::MOVSSrr; Mask = 0x0F; break;
1519 case X86::VBLENDPDrri: Opc = X86::VMOVSDrr; Mask = 0x03; break;
1520 case X86::VBLENDPSrri: Opc = X86::VMOVSSrr; Mask = 0x0F; break;
1521 }
1522 if ((MI.getOperand(3).getImm() ^ Mask) == 1) {
1523 auto &WorkingMI = cloneIfNew(MI);
1524 WorkingMI.setDesc(get(Opc));
1525 WorkingMI.RemoveOperand(3);
1526 return TargetInstrInfo::commuteInstructionImpl(WorkingMI,
1527 /*NewMI=*/false,
1528 OpIdx1, OpIdx2);
1529 }
1530 }
1531 LLVM_FALLTHROUGH;
1532 case X86::PBLENDWrri:
1533 case X86::VBLENDPDYrri:
1534 case X86::VBLENDPSYrri:
1535 case X86::VPBLENDDrri:
1536 case X86::VPBLENDWrri:
1537 case X86::VPBLENDDYrri:
1538 case X86::VPBLENDWYrri:{
1539 int8_t Mask;
1540 switch (MI.getOpcode()) {
1541 default: llvm_unreachable("Unreachable!");
1542 case X86::BLENDPDrri: Mask = (int8_t)0x03; break;
1543 case X86::BLENDPSrri: Mask = (int8_t)0x0F; break;
1544 case X86::PBLENDWrri: Mask = (int8_t)0xFF; break;
1545 case X86::VBLENDPDrri: Mask = (int8_t)0x03; break;
1546 case X86::VBLENDPSrri: Mask = (int8_t)0x0F; break;
1547 case X86::VBLENDPDYrri: Mask = (int8_t)0x0F; break;
1548 case X86::VBLENDPSYrri: Mask = (int8_t)0xFF; break;
1549 case X86::VPBLENDDrri: Mask = (int8_t)0x0F; break;
1550 case X86::VPBLENDWrri: Mask = (int8_t)0xFF; break;
1551 case X86::VPBLENDDYrri: Mask = (int8_t)0xFF; break;
1552 case X86::VPBLENDWYrri: Mask = (int8_t)0xFF; break;
1553 }
1554 // Only the least significant bits of Imm are used.
1555 // Using int8_t to ensure it will be sign extended to the int64_t that
1556 // setImm takes in order to match isel behavior.
1557 int8_t Imm = MI.getOperand(3).getImm() & Mask;
1558 auto &WorkingMI = cloneIfNew(MI);
1559 WorkingMI.getOperand(3).setImm(Mask ^ Imm);
1560 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1561 OpIdx1, OpIdx2);
1562 }
1563 case X86::INSERTPSrr:
1564 case X86::VINSERTPSrr:
1565 case X86::VINSERTPSZrr: {
1566 unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
1567 unsigned ZMask = Imm & 15;
1568 unsigned DstIdx = (Imm >> 4) & 3;
1569 unsigned SrcIdx = (Imm >> 6) & 3;
1570
1571 // We can commute insertps if we zero 2 of the elements, the insertion is
1572 // "inline" and we don't override the insertion with a zero.
1573 if (DstIdx == SrcIdx && (ZMask & (1 << DstIdx)) == 0 &&
1574 countPopulation(ZMask) == 2) {
1575 unsigned AltIdx = findFirstSet((ZMask | (1 << DstIdx)) ^ 15);
1576 assert(AltIdx < 4 && "Illegal insertion index");
1577 unsigned AltImm = (AltIdx << 6) | (AltIdx << 4) | ZMask;
1578 auto &WorkingMI = cloneIfNew(MI);
1579 WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(AltImm);
1580 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1581 OpIdx1, OpIdx2);
1582 }
1583 return nullptr;
1584 }
1585 case X86::MOVSDrr:
1586 case X86::MOVSSrr:
1587 case X86::VMOVSDrr:
1588 case X86::VMOVSSrr:{
1589 // On SSE41 or later we can commute a MOVSS/MOVSD to a BLENDPS/BLENDPD.
1590 if (Subtarget.hasSSE41()) {
1591 unsigned Mask, Opc;
1592 switch (MI.getOpcode()) {
1593 default: llvm_unreachable("Unreachable!");
1594 case X86::MOVSDrr: Opc = X86::BLENDPDrri; Mask = 0x02; break;
1595 case X86::MOVSSrr: Opc = X86::BLENDPSrri; Mask = 0x0E; break;
1596 case X86::VMOVSDrr: Opc = X86::VBLENDPDrri; Mask = 0x02; break;
1597 case X86::VMOVSSrr: Opc = X86::VBLENDPSrri; Mask = 0x0E; break;
1598 }
1599
1600 auto &WorkingMI = cloneIfNew(MI);
1601 WorkingMI.setDesc(get(Opc));
1602 WorkingMI.addOperand(MachineOperand::CreateImm(Mask));
1603 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1604 OpIdx1, OpIdx2);
1605 }
1606
1607 // Convert to SHUFPD.
1608 assert(MI.getOpcode() == X86::MOVSDrr &&
1609 "Can only commute MOVSDrr without SSE4.1");
1610
1611 auto &WorkingMI = cloneIfNew(MI);
1612 WorkingMI.setDesc(get(X86::SHUFPDrri));
1613 WorkingMI.addOperand(MachineOperand::CreateImm(0x02));
1614 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1615 OpIdx1, OpIdx2);
1616 }
1617 case X86::SHUFPDrri: {
1618 // Commute to MOVSD.
1619 assert(MI.getOperand(3).getImm() == 0x02 && "Unexpected immediate!");
1620 auto &WorkingMI = cloneIfNew(MI);
1621 WorkingMI.setDesc(get(X86::MOVSDrr));
1622 WorkingMI.RemoveOperand(3);
1623 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1624 OpIdx1, OpIdx2);
1625 }
1626 case X86::PCLMULQDQrr:
1627 case X86::VPCLMULQDQrr:
1628 case X86::VPCLMULQDQYrr:
1629 case X86::VPCLMULQDQZrr:
1630 case X86::VPCLMULQDQZ128rr:
1631 case X86::VPCLMULQDQZ256rr: {
1632 // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
1633 // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
1634 unsigned Imm = MI.getOperand(3).getImm();
1635 unsigned Src1Hi = Imm & 0x01;
1636 unsigned Src2Hi = Imm & 0x10;
1637 auto &WorkingMI = cloneIfNew(MI);
1638 WorkingMI.getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
1639 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1640 OpIdx1, OpIdx2);
1641 }
1642 case X86::VPCMPBZ128rri: case X86::VPCMPUBZ128rri:
1643 case X86::VPCMPBZ256rri: case X86::VPCMPUBZ256rri:
1644 case X86::VPCMPBZrri: case X86::VPCMPUBZrri:
1645 case X86::VPCMPDZ128rri: case X86::VPCMPUDZ128rri:
1646 case X86::VPCMPDZ256rri: case X86::VPCMPUDZ256rri:
1647 case X86::VPCMPDZrri: case X86::VPCMPUDZrri:
1648 case X86::VPCMPQZ128rri: case X86::VPCMPUQZ128rri:
1649 case X86::VPCMPQZ256rri: case X86::VPCMPUQZ256rri:
1650 case X86::VPCMPQZrri: case X86::VPCMPUQZrri:
1651 case X86::VPCMPWZ128rri: case X86::VPCMPUWZ128rri:
1652 case X86::VPCMPWZ256rri: case X86::VPCMPUWZ256rri:
1653 case X86::VPCMPWZrri: case X86::VPCMPUWZrri:
1654 case X86::VPCMPBZ128rrik: case X86::VPCMPUBZ128rrik:
1655 case X86::VPCMPBZ256rrik: case X86::VPCMPUBZ256rrik:
1656 case X86::VPCMPBZrrik: case X86::VPCMPUBZrrik:
1657 case X86::VPCMPDZ128rrik: case X86::VPCMPUDZ128rrik:
1658 case X86::VPCMPDZ256rrik: case X86::VPCMPUDZ256rrik:
1659 case X86::VPCMPDZrrik: case X86::VPCMPUDZrrik:
1660 case X86::VPCMPQZ128rrik: case X86::VPCMPUQZ128rrik:
1661 case X86::VPCMPQZ256rrik: case X86::VPCMPUQZ256rrik:
1662 case X86::VPCMPQZrrik: case X86::VPCMPUQZrrik:
1663 case X86::VPCMPWZ128rrik: case X86::VPCMPUWZ128rrik:
1664 case X86::VPCMPWZ256rrik: case X86::VPCMPUWZ256rrik:
1665 case X86::VPCMPWZrrik: case X86::VPCMPUWZrrik: {
1666 // Flip comparison mode immediate (if necessary).
1667 unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm() & 0x7;
1668 Imm = X86::getSwappedVPCMPImm(Imm);
1669 auto &WorkingMI = cloneIfNew(MI);
1670 WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(Imm);
1671 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1672 OpIdx1, OpIdx2);
1673 }
1674 case X86::VPCOMBri: case X86::VPCOMUBri:
1675 case X86::VPCOMDri: case X86::VPCOMUDri:
1676 case X86::VPCOMQri: case X86::VPCOMUQri:
1677 case X86::VPCOMWri: case X86::VPCOMUWri: {
1678 // Flip comparison mode immediate (if necessary).
1679 unsigned Imm = MI.getOperand(3).getImm() & 0x7;
1680 Imm = X86::getSwappedVPCOMImm(Imm);
1681 auto &WorkingMI = cloneIfNew(MI);
1682 WorkingMI.getOperand(3).setImm(Imm);
1683 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1684 OpIdx1, OpIdx2);
1685 }
1686 case X86::VPERM2F128rr:
1687 case X86::VPERM2I128rr: {
1688 // Flip permute source immediate.
1689 // Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi.
1690 // Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi.
1691 int8_t Imm = MI.getOperand(3).getImm() & 0xFF;
1692 auto &WorkingMI = cloneIfNew(MI);
1693 WorkingMI.getOperand(3).setImm(Imm ^ 0x22);
1694 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1695 OpIdx1, OpIdx2);
1696 }
1697 case X86::MOVHLPSrr:
1698 case X86::UNPCKHPDrr:
1699 case X86::VMOVHLPSrr:
1700 case X86::VUNPCKHPDrr:
1701 case X86::VMOVHLPSZrr:
1702 case X86::VUNPCKHPDZ128rr: {
1703 assert(Subtarget.hasSSE2() && "Commuting MOVHLP/UNPCKHPD requires SSE2!");
1704
1705 unsigned Opc = MI.getOpcode();
1706 switch (Opc) {
1707 default: llvm_unreachable("Unreachable!");
1708 case X86::MOVHLPSrr: Opc = X86::UNPCKHPDrr; break;
1709 case X86::UNPCKHPDrr: Opc = X86::MOVHLPSrr; break;
1710 case X86::VMOVHLPSrr: Opc = X86::VUNPCKHPDrr; break;
1711 case X86::VUNPCKHPDrr: Opc = X86::VMOVHLPSrr; break;
1712 case X86::VMOVHLPSZrr: Opc = X86::VUNPCKHPDZ128rr; break;
1713 case X86::VUNPCKHPDZ128rr: Opc = X86::VMOVHLPSZrr; break;
1714 }
1715 auto &WorkingMI = cloneIfNew(MI);
1716 WorkingMI.setDesc(get(Opc));
1717 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1718 OpIdx1, OpIdx2);
1719 }
1720 case X86::CMOV16rr: case X86::CMOV32rr: case X86::CMOV64rr: {
1721 auto &WorkingMI = cloneIfNew(MI);
1722 unsigned OpNo = MI.getDesc().getNumOperands() - 1;
1723 X86::CondCode CC = static_cast<X86::CondCode>(MI.getOperand(OpNo).getImm());
1724 WorkingMI.getOperand(OpNo).setImm(X86::GetOppositeBranchCondition(CC));
1725 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1726 OpIdx1, OpIdx2);
1727 }
1728 case X86::VPTERNLOGDZrri: case X86::VPTERNLOGDZrmi:
1729 case X86::VPTERNLOGDZ128rri: case X86::VPTERNLOGDZ128rmi:
1730 case X86::VPTERNLOGDZ256rri: case X86::VPTERNLOGDZ256rmi:
1731 case X86::VPTERNLOGQZrri: case X86::VPTERNLOGQZrmi:
1732 case X86::VPTERNLOGQZ128rri: case X86::VPTERNLOGQZ128rmi:
1733 case X86::VPTERNLOGQZ256rri: case X86::VPTERNLOGQZ256rmi:
1734 case X86::VPTERNLOGDZrrik:
1735 case X86::VPTERNLOGDZ128rrik:
1736 case X86::VPTERNLOGDZ256rrik:
1737 case X86::VPTERNLOGQZrrik:
1738 case X86::VPTERNLOGQZ128rrik:
1739 case X86::VPTERNLOGQZ256rrik:
1740 case X86::VPTERNLOGDZrrikz: case X86::VPTERNLOGDZrmikz:
1741 case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
1742 case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
1743 case X86::VPTERNLOGQZrrikz: case X86::VPTERNLOGQZrmikz:
1744 case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
1745 case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
1746 case X86::VPTERNLOGDZ128rmbi:
1747 case X86::VPTERNLOGDZ256rmbi:
1748 case X86::VPTERNLOGDZrmbi:
1749 case X86::VPTERNLOGQZ128rmbi:
1750 case X86::VPTERNLOGQZ256rmbi:
1751 case X86::VPTERNLOGQZrmbi:
1752 case X86::VPTERNLOGDZ128rmbikz:
1753 case X86::VPTERNLOGDZ256rmbikz:
1754 case X86::VPTERNLOGDZrmbikz:
1755 case X86::VPTERNLOGQZ128rmbikz:
1756 case X86::VPTERNLOGQZ256rmbikz:
1757 case X86::VPTERNLOGQZrmbikz: {
1758 auto &WorkingMI = cloneIfNew(MI);
1759 commuteVPTERNLOG(WorkingMI, OpIdx1, OpIdx2);
1760 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1761 OpIdx1, OpIdx2);
1762 }
1763 default: {
1764 if (isCommutableVPERMV3Instruction(MI.getOpcode())) {
1765 unsigned Opc = getCommutedVPERMV3Opcode(MI.getOpcode());
1766 auto &WorkingMI = cloneIfNew(MI);
1767 WorkingMI.setDesc(get(Opc));
1768 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1769 OpIdx1, OpIdx2);
1770 }
1771
1772 const X86InstrFMA3Group *FMA3Group = getFMA3Group(MI.getOpcode(),
1773 MI.getDesc().TSFlags);
1774 if (FMA3Group) {
1775 unsigned Opc =
1776 getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2, *FMA3Group);
1777 auto &WorkingMI = cloneIfNew(MI);
1778 WorkingMI.setDesc(get(Opc));
1779 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1780 OpIdx1, OpIdx2);
1781 }
1782
1783 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
1784 }
1785 }
1786 }
1787
1788 bool
1789 X86InstrInfo::findThreeSrcCommutedOpIndices(const MachineInstr &MI,
1790 unsigned &SrcOpIdx1,
1791 unsigned &SrcOpIdx2,
1792 bool IsIntrinsic) const {
1793 uint64_t TSFlags = MI.getDesc().TSFlags;
1794
1795 unsigned FirstCommutableVecOp = 1;
1796 unsigned LastCommutableVecOp = 3;
1797 unsigned KMaskOp = -1U;
1798 if (X86II::isKMasked(TSFlags)) {
1799 // For k-zero-masked operations it is Ok to commute the first vector
1800 // operand.
1801 // For regular k-masked operations a conservative choice is done as the
1802 // elements of the first vector operand, for which the corresponding bit
1803 // in the k-mask operand is set to 0, are copied to the result of the
1804 // instruction.
1805 // TODO/FIXME: The commute still may be legal if it is known that the
1806 // k-mask operand is set to either all ones or all zeroes.
1807 // It is also Ok to commute the 1st operand if all users of MI use only
1808 // the elements enabled by the k-mask operand. For example,
1809 // v4 = VFMADD213PSZrk v1, k, v2, v3; // v1[i] = k[i] ? v2[i]*v1[i]+v3[i]
1810 // : v1[i];
1811 // VMOVAPSZmrk <mem_addr>, k, v4; // this is the ONLY user of v4 ->
1812 // // Ok, to commute v1 in FMADD213PSZrk.
1813
1814 // The k-mask operand has index = 2 for masked and zero-masked operations.
1815 KMaskOp = 2;
1816
1817 // The operand with index = 1 is used as a source for those elements for
1818 // which the corresponding bit in the k-mask is set to 0.
1819 if (X86II::isKMergeMasked(TSFlags))
1820 FirstCommutableVecOp = 3;
1821
1822 LastCommutableVecOp++;
1823 } else if (IsIntrinsic) {
1824 // Commuting the first operand of an intrinsic instruction isn't possible
1825 // unless we can prove that only the lowest element of the result is used.
1826 FirstCommutableVecOp = 2;
1827 }
1828
1829 if (isMem(MI, LastCommutableVecOp))
1830 LastCommutableVecOp--;
1831
1832 // Only the first RegOpsNum operands are commutable.
1833 // Also, the value 'CommuteAnyOperandIndex' is valid here as it means
1834 // that the operand is not specified/fixed.
1835 if (SrcOpIdx1 != CommuteAnyOperandIndex &&
1836 (SrcOpIdx1 < FirstCommutableVecOp || SrcOpIdx1 > LastCommutableVecOp ||
1837 SrcOpIdx1 == KMaskOp))
1838 return false;
1839 if (SrcOpIdx2 != CommuteAnyOperandIndex &&
1840 (SrcOpIdx2 < FirstCommutableVecOp || SrcOpIdx2 > LastCommutableVecOp ||
1841 SrcOpIdx2 == KMaskOp))
1842 return false;
1843
1844 // Look for two different register operands assumed to be commutable
1845 // regardless of the FMA opcode. The FMA opcode is adjusted later.
1846 if (SrcOpIdx1 == CommuteAnyOperandIndex ||
1847 SrcOpIdx2 == CommuteAnyOperandIndex) {
1848 unsigned CommutableOpIdx2 = SrcOpIdx2;
1849
1850 // At least one of operands to be commuted is not specified and
1851 // this method is free to choose appropriate commutable operands.
1852 if (SrcOpIdx1 == SrcOpIdx2)
1853 // Both of operands are not fixed. By default set one of commutable
1854 // operands to the last register operand of the instruction.
1855 CommutableOpIdx2 = LastCommutableVecOp;
1856 else if (SrcOpIdx2 == CommuteAnyOperandIndex)
1857 // Only one of operands is not fixed.
1858 CommutableOpIdx2 = SrcOpIdx1;
1859
1860 // CommutableOpIdx2 is well defined now. Let's choose another commutable
1861 // operand and assign its index to CommutableOpIdx1.
1862 Register Op2Reg = MI.getOperand(CommutableOpIdx2).getReg();
1863
1864 unsigned CommutableOpIdx1;
1865 for (CommutableOpIdx1 = LastCommutableVecOp;
1866 CommutableOpIdx1 >= FirstCommutableVecOp; CommutableOpIdx1--) {
1867 // Just ignore and skip the k-mask operand.
1868 if (CommutableOpIdx1 == KMaskOp)
1869 continue;
1870
1871 // The commuted operands must have different registers.
1872 // Otherwise, the commute transformation does not change anything and
1873 // is useless then.
1874 if (Op2Reg != MI.getOperand(CommutableOpIdx1).getReg())
1875 break;
1876 }
1877
1878 // No appropriate commutable operands were found.
1879 if (CommutableOpIdx1 < FirstCommutableVecOp)
1880 return false;
1881
1882 // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2
1883 // to return those values.
1884 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
1885 CommutableOpIdx1, CommutableOpIdx2))
1886 return false;
1887 }
1888
1889 return true;
1890 }
1891
1892 bool X86InstrInfo::findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
1893 unsigned &SrcOpIdx2) const {
1894 const MCInstrDesc &Desc = MI.getDesc();
1895 if (!Desc.isCommutable())
1896 return false;
1897
1898 switch (MI.getOpcode()) {
1899 case X86::CMPSDrr:
1900 case X86::CMPSSrr:
1901 case X86::CMPPDrri:
1902 case X86::CMPPSrri:
1903 case X86::VCMPSDrr:
1904 case X86::VCMPSSrr:
1905 case X86::VCMPPDrri:
1906 case X86::VCMPPSrri:
1907 case X86::VCMPPDYrri:
1908 case X86::VCMPPSYrri:
1909 case X86::VCMPSDZrr:
1910 case X86::VCMPSSZrr:
1911 case X86::VCMPPDZrri:
1912 case X86::VCMPPSZrri:
1913 case X86::VCMPPDZ128rri:
1914 case X86::VCMPPSZ128rri:
1915 case X86::VCMPPDZ256rri:
1916 case X86::VCMPPSZ256rri:
1917 case X86::VCMPPDZrrik:
1918 case X86::VCMPPSZrrik:
1919 case X86::VCMPPDZ128rrik:
1920 case X86::VCMPPSZ128rrik:
1921 case X86::VCMPPDZ256rrik:
1922 case X86::VCMPPSZ256rrik: {
1923 unsigned OpOffset = X86II::isKMasked(Desc.TSFlags) ? 1 : 0;
1924
1925 // Float comparison can be safely commuted for
1926 // Ordered/Unordered/Equal/NotEqual tests
1927 unsigned Imm = MI.getOperand(3 + OpOffset).getImm() & 0x7;
1928 switch (Imm) {
1929 case 0x00: // EQUAL
1930 case 0x03: // UNORDERED
1931 case 0x04: // NOT EQUAL
1932 case 0x07: // ORDERED
1933 // The indices of the commutable operands are 1 and 2 (or 2 and 3
1934 // when masked).
1935 // Assign them to the returned operand indices here.
1936 return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1 + OpOffset,
1937 2 + OpOffset);
1938 }
1939 return false;
1940 }
1941 case X86::MOVSSrr:
1942 // X86::MOVSDrr is always commutable. MOVSS is only commutable if we can
1943 // form sse4.1 blend. We assume VMOVSSrr/VMOVSDrr is always commutable since
1944 // AVX implies sse4.1.
1945 if (Subtarget.hasSSE41())
1946 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
1947 return false;
1948 case X86::SHUFPDrri:
1949 // We can commute this to MOVSD.
1950 if (MI.getOperand(3).getImm() == 0x02)
1951 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
1952 return false;
1953 case X86::MOVHLPSrr:
1954 case X86::UNPCKHPDrr:
1955 case X86::VMOVHLPSrr:
1956 case X86::VUNPCKHPDrr:
1957 case X86::VMOVHLPSZrr:
1958 case X86::VUNPCKHPDZ128rr:
1959 if (Subtarget.hasSSE2())
1960 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
1961 return false;
1962 case X86::VPTERNLOGDZrri: case X86::VPTERNLOGDZrmi:
1963 case X86::VPTERNLOGDZ128rri: case X86::VPTERNLOGDZ128rmi:
1964 case X86::VPTERNLOGDZ256rri: case X86::VPTERNLOGDZ256rmi:
1965 case X86::VPTERNLOGQZrri: case X86::VPTERNLOGQZrmi:
1966 case X86::VPTERNLOGQZ128rri: case X86::VPTERNLOGQZ128rmi:
1967 case X86::VPTERNLOGQZ256rri: case X86::VPTERNLOGQZ256rmi:
1968 case X86::VPTERNLOGDZrrik:
1969 case X86::VPTERNLOGDZ128rrik:
1970 case X86::VPTERNLOGDZ256rrik:
1971 case X86::VPTERNLOGQZrrik:
1972 case X86::VPTERNLOGQZ128rrik:
1973 case X86::VPTERNLOGQZ256rrik:
1974 case X86::VPTERNLOGDZrrikz: case X86::VPTERNLOGDZrmikz:
1975 case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
1976 case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
1977 case X86::VPTERNLOGQZrrikz: case X86::VPTERNLOGQZrmikz:
1978 case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
1979 case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
1980 case X86::VPTERNLOGDZ128rmbi:
1981 case X86::VPTERNLOGDZ256rmbi:
1982 case X86::VPTERNLOGDZrmbi:
1983 case X86::VPTERNLOGQZ128rmbi:
1984 case X86::VPTERNLOGQZ256rmbi:
1985 case X86::VPTERNLOGQZrmbi:
1986 case X86::VPTERNLOGDZ128rmbikz:
1987 case X86::VPTERNLOGDZ256rmbikz:
1988 case X86::VPTERNLOGDZrmbikz:
1989 case X86::VPTERNLOGQZ128rmbikz:
1990 case X86::VPTERNLOGQZ256rmbikz:
1991 case X86::VPTERNLOGQZrmbikz:
1992 return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
1993 case X86::VPDPWSSDZ128r:
1994 case X86::VPDPWSSDZ128rk:
1995 case X86::VPDPWSSDZ128rkz:
1996 case X86::VPDPWSSDZ256r:
1997 case X86::VPDPWSSDZ256rk:
1998 case X86::VPDPWSSDZ256rkz:
1999 case X86::VPDPWSSDZr:
2000 case X86::VPDPWSSDZrk:
2001 case X86::VPDPWSSDZrkz:
2002 case X86::VPDPWSSDSZ128r:
2003 case X86::VPDPWSSDSZ128rk:
2004 case X86::VPDPWSSDSZ128rkz:
2005 case X86::VPDPWSSDSZ256r:
2006 case X86::VPDPWSSDSZ256rk:
2007 case X86::VPDPWSSDSZ256rkz:
2008 case X86::VPDPWSSDSZr:
2009 case X86::VPDPWSSDSZrk:
2010 case X86::VPDPWSSDSZrkz:
2011 case X86::VPMADD52HUQZ128r:
2012 case X86::VPMADD52HUQZ128rk:
2013 case X86::VPMADD52HUQZ128rkz:
2014 case X86::VPMADD52HUQZ256r:
2015 case X86::VPMADD52HUQZ256rk:
2016 case X86::VPMADD52HUQZ256rkz:
2017 case X86::VPMADD52HUQZr:
2018 case X86::VPMADD52HUQZrk:
2019 case X86::VPMADD52HUQZrkz:
2020 case X86::VPMADD52LUQZ128r:
2021 case X86::VPMADD52LUQZ128rk:
2022 case X86::VPMADD52LUQZ128rkz:
2023 case X86::VPMADD52LUQZ256r:
2024 case X86::VPMADD52LUQZ256rk:
2025 case X86::VPMADD52LUQZ256rkz:
2026 case X86::VPMADD52LUQZr:
2027 case X86::VPMADD52LUQZrk:
2028 case X86::VPMADD52LUQZrkz: {
2029 unsigned CommutableOpIdx1 = 2;
2030 unsigned CommutableOpIdx2 = 3;
2031 if (X86II::isKMasked(Desc.TSFlags)) {
2032 // Skip the mask register.
2033 ++CommutableOpIdx1;
2034 ++CommutableOpIdx2;
2035 }
2036 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
2037 CommutableOpIdx1, CommutableOpIdx2))
2038 return false;
2039 if (!MI.getOperand(SrcOpIdx1).isReg() ||
2040 !MI.getOperand(SrcOpIdx2).isReg())
2041 // No idea.
2042 return false;
2043 return true;
2044 }
2045
2046 default:
2047 const X86InstrFMA3Group *FMA3Group = getFMA3Group(MI.getOpcode(),
2048 MI.getDesc().TSFlags);
2049 if (FMA3Group)
2050 return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2,
2051 FMA3Group->isIntrinsic());
2052
2053 // Handled masked instructions since we need to skip over the mask input
2054 // and the preserved input.
2055 if (X86II::isKMasked(Desc.TSFlags)) {
2056 // First assume that the first input is the mask operand and skip past it.
2057 unsigned CommutableOpIdx1 = Desc.getNumDefs() + 1;
2058 unsigned CommutableOpIdx2 = Desc.getNumDefs() + 2;
2059 // Check if the first input is tied. If there isn't one then we only
2060 // need to skip the mask operand which we did above.
2061 if ((MI.getDesc().getOperandConstraint(Desc.getNumDefs(),
2062 MCOI::TIED_TO) != -1)) {
2063 // If this is zero masking instruction with a tied operand, we need to
2064 // move the first index back to the first input since this must
2065 // be a 3 input instruction and we want the first two non-mask inputs.
2066 // Otherwise this is a 2 input instruction with a preserved input and
2067 // mask, so we need to move the indices to skip one more input.
2068 if (X86II::isKMergeMasked(Desc.TSFlags)) {
2069 ++CommutableOpIdx1;
2070 ++CommutableOpIdx2;
2071 } else {
2072 --CommutableOpIdx1;
2073 }
2074 }
2075
2076 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
2077 CommutableOpIdx1, CommutableOpIdx2))
2078 return false;
2079
2080 if (!MI.getOperand(SrcOpIdx1).isReg() ||
2081 !MI.getOperand(SrcOpIdx2).isReg())
2082 // No idea.
2083 return false;
2084 return true;
2085 }
2086
2087 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2088 }
2089 return false;
2090 }
2091
2092 X86::CondCode X86::getCondFromBranch(const MachineInstr &MI) {
2093 switch (MI.getOpcode()) {
2094 default: return X86::COND_INVALID;
2095 case X86::JCC_1:
2096 return static_cast<X86::CondCode>(
2097 MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
2098 }
2099 }
2100
2101 /// Return condition code of a SETCC opcode.
2102 X86::CondCode X86::getCondFromSETCC(const MachineInstr &MI) {
2103 switch (MI.getOpcode()) {
2104 default: return X86::COND_INVALID;
2105 case X86::SETCCr: case X86::SETCCm:
2106 return static_cast<X86::CondCode>(
2107 MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
2108 }
2109 }
2110
2111 /// Return condition code of a CMov opcode.
2112 X86::CondCode X86::getCondFromCMov(const MachineInstr &MI) {
2113 switch (MI.getOpcode()) {
2114 default: return X86::COND_INVALID;
2115 case X86::CMOV16rr: case X86::CMOV32rr: case X86::CMOV64rr:
2116 case X86::CMOV16rm: case X86::CMOV32rm: case X86::CMOV64rm:
2117 return static_cast<X86::CondCode>(
2118 MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
2119 }
2120 }
2121
2122 /// Return the inverse of the specified condition,
2123 /// e.g. turning COND_E to COND_NE.
2124 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
2125 switch (CC) {
2126 default: llvm_unreachable("Illegal condition code!");
2127 case X86::COND_E: return X86::COND_NE;
2128 case X86::COND_NE: return X86::COND_E;
2129 case X86::COND_L: return X86::COND_GE;
2130 case X86::COND_LE: return X86::COND_G;
2131 case X86::COND_G: return X86::COND_LE;
2132 case X86::COND_GE: return X86::COND_L;
2133 case X86::COND_B: return X86::COND_AE;
2134 case X86::COND_BE: return X86::COND_A;
2135 case X86::COND_A: return X86::COND_BE;
2136 case X86::COND_AE: return X86::COND_B;
2137 case X86::COND_S: return X86::COND_NS;
2138 case X86::COND_NS: return X86::COND_S;
2139 case X86::COND_P: return X86::COND_NP;
2140 case X86::COND_NP: return X86::COND_P;
2141 case X86::COND_O: return X86::COND_NO;
2142 case X86::COND_NO: return X86::COND_O;
2143 case X86::COND_NE_OR_P: return X86::COND_E_AND_NP;
2144 case X86::COND_E_AND_NP: return X86::COND_NE_OR_P;
2145 }
2146 }
2147
2148 /// Assuming the flags are set by MI(a,b), return the condition code if we
2149 /// modify the instructions such that flags are set by MI(b,a).
2150 static X86::CondCode getSwappedCondition(X86::CondCode CC) {
2151 switch (CC) {
2152 default: return X86::COND_INVALID;
2153 case X86::COND_E: return X86::COND_E;
2154 case X86::COND_NE: return X86::COND_NE;
2155 case X86::COND_L: return X86::COND_G;
2156 case X86::COND_LE: return X86::COND_GE;
2157 case X86::COND_G: return X86::COND_L;
2158 case X86::COND_GE: return X86::COND_LE;
2159 case X86::COND_B: return X86::COND_A;
2160 case X86::COND_BE: return X86::COND_AE;
2161 case X86::COND_A: return X86::COND_B;
2162 case X86::COND_AE: return X86::COND_BE;
2163 }
2164 }
2165
2166 std::pair<X86::CondCode, bool>
2167 X86::getX86ConditionCode(CmpInst::Predicate Predicate) {
2168 X86::CondCode CC = X86::COND_INVALID;
2169 bool NeedSwap = false;
2170 switch (Predicate) {
2171 default: break;
2172 // Floating-point Predicates
2173 case CmpInst::FCMP_UEQ: CC = X86::COND_E; break;
2174 case CmpInst::FCMP_OLT: NeedSwap = true; LLVM_FALLTHROUGH;
2175 case CmpInst::FCMP_OGT: CC = X86::COND_A; break;
2176 case CmpInst::FCMP_OLE: NeedSwap = true; LLVM_FALLTHROUGH;
2177 case CmpInst::FCMP_OGE: CC = X86::COND_AE; break;
2178 case CmpInst::FCMP_UGT: NeedSwap = true; LLVM_FALLTHROUGH;
2179 case CmpInst::FCMP_ULT: CC = X86::COND_B; break;
2180 case CmpInst::FCMP_UGE: NeedSwap = true; LLVM_FALLTHROUGH;
2181 case CmpInst::FCMP_ULE: CC = X86::COND_BE; break;
2182 case CmpInst::FCMP_ONE: CC = X86::COND_NE; break;
2183 case CmpInst::FCMP_UNO: CC = X86::COND_P; break;
2184 case CmpInst::FCMP_ORD: CC = X86::COND_NP; break;
2185 case CmpInst::FCMP_OEQ: LLVM_FALLTHROUGH;
2186 case CmpInst::FCMP_UNE: CC = X86::COND_INVALID; break;
2187
2188 // Integer Predicates
2189 case CmpInst::ICMP_EQ: CC = X86::COND_E; break;
2190 case CmpInst::ICMP_NE: CC = X86::COND_NE; break;
2191 case CmpInst::ICMP_UGT: CC = X86::COND_A; break;
2192 case CmpInst::ICMP_UGE: CC = X86::COND_AE; break;
2193 case CmpInst::ICMP_ULT: CC = X86::COND_B; break;
2194 case CmpInst::ICMP_ULE: CC = X86::COND_BE; break;
2195 case CmpInst::ICMP_SGT: CC = X86::COND_G; break;
2196 case CmpInst::ICMP_SGE: CC = X86::COND_GE; break;
2197 case CmpInst::ICMP_SLT: CC = X86::COND_L; break;
2198 case CmpInst::ICMP_SLE: CC = X86::COND_LE; break;
2199 }
2200
2201 return std::make_pair(CC, NeedSwap);
2202 }
2203
2204 /// Return a setcc opcode based on whether it has memory operand.
2205 unsigned X86::getSETOpc(bool HasMemoryOperand) {
2206 return HasMemoryOperand ? X86::SETCCr : X86::SETCCm;
2207 }
2208
2209 /// Return a cmov opcode for the given register size in bytes, and operand type.
2210 unsigned X86::getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand) {
2211 switch(RegBytes) {
2212 default: llvm_unreachable("Illegal register size!");
2213 case 2: return HasMemoryOperand ? X86::CMOV16rm : X86::CMOV16rr;
2214 case 4: return HasMemoryOperand ? X86::CMOV32rm : X86::CMOV32rr;
2215 case 8: return HasMemoryOperand ? X86::CMOV32rm : X86::CMOV64rr;
2216 }
2217 }
2218
2219 /// Get the VPCMP immediate for the given condition.
2220 unsigned X86::getVPCMPImmForCond(ISD::CondCode CC) {
2221 switch (CC) {
2222 default: llvm_unreachable("Unexpected SETCC condition");
2223 case ISD::SETNE: return 4;
2224 case ISD::SETEQ: return 0;
2225 case ISD::SETULT:
2226 case ISD::SETLT: return 1;
2227 case ISD::SETUGT:
2228 case ISD::SETGT: return 6;
2229 case ISD::SETUGE:
2230 case ISD::SETGE: return 5;
2231 case ISD::SETULE:
2232 case ISD::SETLE: return 2;
2233 }
2234 }
2235
2236 /// Get the VPCMP immediate if the opcodes are swapped.
2237 unsigned X86::getSwappedVPCMPImm(unsigned Imm) {
2238 switch (Imm) {
2239 default: llvm_unreachable("Unreachable!");
2240 case 0x01: Imm = 0x06; break; // LT -> NLE
2241 case 0x02: Imm = 0x05; break; // LE -> NLT
2242 case 0x05: Imm = 0x02; break; // NLT -> LE
2243 case 0x06: Imm = 0x01; break; // NLE -> LT
2244 case 0x00: // EQ
2245 case 0x03: // FALSE
2246 case 0x04: // NE
2247 case 0x07: // TRUE
2248 break;
2249 }
2250
2251 return Imm;
2252 }
2253
2254 /// Get the VPCOM immediate if the opcodes are swapped.
2255 unsigned X86::getSwappedVPCOMImm(unsigned Imm) {
2256 switch (Imm) {
2257 default: llvm_unreachable("Unreachable!");
2258 case 0x00: Imm = 0x02; break; // LT -> GT
2259 case 0x01: Imm = 0x03; break; // LE -> GE
2260 case 0x02: Imm = 0x00; break; // GT -> LT
2261 case 0x03: Imm = 0x01; break; // GE -> LE
2262 case 0x04: // EQ
2263 case 0x05: // NE
2264 case 0x06: // FALSE
2265 case 0x07: // TRUE
2266 break;
2267 }
2268
2269 return Imm;
2270 }
2271
2272 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
2273 if (!MI.isTerminator()) return false;
2274
2275 // Conditional branch is a special case.
2276 if (MI.isBranch() && !MI.isBarrier())
2277 return true;
2278 if (!MI.isPredicable())
2279 return true;
2280 return !isPredicated(MI);
2281 }
2282
2283 bool X86InstrInfo::isUnconditionalTailCall(const MachineInstr &MI) const {
2284 switch (MI.getOpcode()) {
2285 case X86::TCRETURNdi:
2286 case X86::TCRETURNri:
2287 case X86::TCRETURNmi:
2288 case X86::TCRETURNdi64:
2289 case X86::TCRETURNri64:
2290 case X86::TCRETURNmi64:
2291 return true;
2292 default:
2293 return false;
2294 }
2295 }
2296
2297 bool X86InstrInfo::canMakeTailCallConditional(
2298 SmallVectorImpl<MachineOperand> &BranchCond,
2299 const MachineInstr &TailCall) const {
2300 if (TailCall.getOpcode() != X86::TCRETURNdi &&
2301 TailCall.getOpcode() != X86::TCRETURNdi64) {
2302 // Only direct calls can be done with a conditional branch.
2303 return false;
2304 }
2305
2306 const MachineFunction *MF = TailCall.getParent()->getParent();
2307 if (Subtarget.isTargetWin64() && MF->hasWinCFI()) {
2308 // Conditional tail calls confuse the Win64 unwinder.
2309 return false;
2310 }
2311
2312 assert(BranchCond.size() == 1);
2313 if (BranchCond[0].getImm() > X86::LAST_VALID_COND) {
2314 // Can't make a conditional tail call with this condition.
2315 return false;
2316 }
2317
2318 const X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
2319 if (X86FI->getTCReturnAddrDelta() != 0 ||
2320 TailCall.getOperand(1).getImm() != 0) {
2321 // A conditional tail call cannot do any stack adjustment.
2322 return false;
2323 }
2324
2325 return true;
2326 }
2327
2328 void X86InstrInfo::replaceBranchWithTailCall(
2329 MachineBasicBlock &MBB, SmallVectorImpl<MachineOperand> &BranchCond,
2330 const MachineInstr &TailCall) const {
2331 assert(canMakeTailCallConditional(BranchCond, TailCall));
2332
2333 MachineBasicBlock::iterator I = MBB.end();
2334 while (I != MBB.begin()) {
2335 --I;
2336 if (I->isDebugInstr())
2337 continue;
2338 if (!I->isBranch())
2339 assert(0 && "Can't find the branch to replace!");
2340
2341 X86::CondCode CC = X86::getCondFromBranch(*I);
2342 assert(BranchCond.size() == 1);
2343 if (CC != BranchCond[0].getImm())
2344 continue;
2345
2346 break;
2347 }
2348
2349 unsigned Opc = TailCall.getOpcode() == X86::TCRETURNdi ? X86::TCRETURNdicc
2350 : X86::TCRETURNdi64cc;
2351
2352 auto MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opc));
2353 MIB->addOperand(TailCall.getOperand(0)); // Destination.
2354 MIB.addImm(0); // Stack offset (not used).
2355 MIB->addOperand(BranchCond[0]); // Condition.
2356 MIB.copyImplicitOps(TailCall); // Regmask and (imp-used) parameters.
2357
2358 // Add implicit uses and defs of all live regs potentially clobbered by the
2359 // call. This way they still appear live across the call.
2360 LivePhysRegs LiveRegs(getRegisterInfo());
2361 LiveRegs.addLiveOuts(MBB);
2362 SmallVector<std::pair<MCPhysReg, const MachineOperand *>, 8> Clobbers;
2363 LiveRegs.stepForward(*MIB, Clobbers);
2364 for (const auto &C : Clobbers) {
2365 MIB.addReg(C.first, RegState::Implicit);
2366 MIB.addReg(C.first, RegState::Implicit | RegState::Define);
2367 }
2368
2369 I->eraseFromParent();
2370 }
2371
2372 // Given a MBB and its TBB, find the FBB which was a fallthrough MBB (it may
2373 // not be a fallthrough MBB now due to layout changes). Return nullptr if the
2374 // fallthrough MBB cannot be identified.
2375 static MachineBasicBlock *getFallThroughMBB(MachineBasicBlock *MBB,
2376 MachineBasicBlock *TBB) {
2377 // Look for non-EHPad successors other than TBB. If we find exactly one, it
2378 // is the fallthrough MBB. If we find zero, then TBB is both the target MBB
2379 // and fallthrough MBB. If we find more than one, we cannot identify the
2380 // fallthrough MBB and should return nullptr.
2381 MachineBasicBlock *FallthroughBB = nullptr;
2382 for (auto SI = MBB->succ_begin(), SE = MBB->succ_end(); SI != SE; ++SI) {
2383 if ((*SI)->isEHPad() || (*SI == TBB && FallthroughBB))
2384 continue;
2385 // Return a nullptr if we found more than one fallthrough successor.
2386 if (FallthroughBB && FallthroughBB != TBB)
2387 return nullptr;
2388 FallthroughBB = *SI;
2389 }
2390 return FallthroughBB;
2391 }
2392
2393 bool X86InstrInfo::AnalyzeBranchImpl(
2394 MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
2395 SmallVectorImpl<MachineOperand> &Cond,
2396 SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
2397
2398 // Start from the bottom of the block and work up, examining the
2399 // terminator instructions.
2400 MachineBasicBlock::iterator I = MBB.end();
2401 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
2402 while (I != MBB.begin()) {
2403 --I;
2404 if (I->isDebugInstr())
2405 continue;
2406
2407 // Working from the bottom, when we see a non-terminator instruction, we're
2408 // done.
2409 if (!isUnpredicatedTerminator(*I))
2410 break;
2411
2412 // A terminator that isn't a branch can't easily be handled by this
2413 // analysis.
2414 if (!I->isBranch())
2415 return true;
2416
2417 // Handle unconditional branches.
2418 if (I->getOpcode() == X86::JMP_1) {
2419 UnCondBrIter = I;
2420
2421 if (!AllowModify) {
2422 TBB = I->getOperand(0).getMBB();
2423 continue;
2424 }
2425
2426 // If the block has any instructions after a JMP, delete them.
2427 while (std::next(I) != MBB.end())
2428 std::next(I)->eraseFromParent();
2429
2430 Cond.clear();
2431 FBB = nullptr;
2432
2433 // Delete the JMP if it's equivalent to a fall-through.
2434 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
2435 TBB = nullptr;
2436 I->eraseFromParent();
2437 I = MBB.end();
2438 UnCondBrIter = MBB.end();
2439 continue;
2440 }
2441
2442 // TBB is used to indicate the unconditional destination.
2443 TBB = I->getOperand(0).getMBB();
2444 continue;
2445 }
2446
2447 // Handle conditional branches.
2448 X86::CondCode BranchCode = X86::getCondFromBranch(*I);
2449 if (BranchCode == X86::COND_INVALID)
2450 return true; // Can't handle indirect branch.
2451
2452 // In practice we should never have an undef eflags operand, if we do
2453 // abort here as we are not prepared to preserve the flag.
2454 if (I->findRegisterUseOperand(X86::EFLAGS)->isUndef())
2455 return true;
2456
2457 // Working from the bottom, handle the first conditional branch.
2458 if (Cond.empty()) {
2459 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
2460 if (AllowModify && UnCondBrIter != MBB.end() &&
2461 MBB.isLayoutSuccessor(TargetBB)) {
2462 // If we can modify the code and it ends in something like:
2463 //
2464 // jCC L1
2465 // jmp L2
2466 // L1:
2467 // ...
2468 // L2:
2469 //
2470 // Then we can change this to:
2471 //
2472 // jnCC L2
2473 // L1:
2474 // ...
2475 // L2:
2476 //
2477 // Which is a bit more efficient.
2478 // We conditionally jump to the fall-through block.
2479 BranchCode = GetOppositeBranchCondition(BranchCode);
2480 MachineBasicBlock::iterator OldInst = I;
2481
2482 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JCC_1))
2483 .addMBB(UnCondBrIter->getOperand(0).getMBB())
2484 .addImm(BranchCode);
2485 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
2486 .addMBB(TargetBB);
2487
2488 OldInst->eraseFromParent();
2489 UnCondBrIter->eraseFromParent();
2490
2491 // Restart the analysis.
2492 UnCondBrIter = MBB.end();
2493 I = MBB.end();
2494 continue;
2495 }
2496
2497 FBB = TBB;
2498 TBB = I->getOperand(0).getMBB();
2499 Cond.push_back(MachineOperand::CreateImm(BranchCode));
2500 CondBranches.push_back(&*I);
2501 continue;
2502 }
2503
2504 // Handle subsequent conditional branches. Only handle the case where all
2505 // conditional branches branch to the same destination and their condition
2506 // opcodes fit one of the special multi-branch idioms.
2507 assert(Cond.size() == 1);
2508 assert(TBB);
2509
2510 // If the conditions are the same, we can leave them alone.
2511 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
2512 auto NewTBB = I->getOperand(0).getMBB();
2513 if (OldBranchCode == BranchCode && TBB == NewTBB)
2514 continue;
2515
2516 // If they differ, see if they fit one of the known patterns. Theoretically,
2517 // we could handle more patterns here, but we shouldn't expect to see them
2518 // if instruction selection has done a reasonable job.
2519 if (TBB == NewTBB &&
2520 ((OldBranchCode == X86::COND_P && BranchCode == X86::COND_NE) ||
2521 (OldBranchCode == X86::COND_NE && BranchCode == X86::COND_P))) {
2522 BranchCode = X86::COND_NE_OR_P;
2523 } else if ((OldBranchCode == X86::COND_NP && BranchCode == X86::COND_NE) ||
2524 (OldBranchCode == X86::COND_E && BranchCode == X86::COND_P)) {
2525 if (NewTBB != (FBB ? FBB : getFallThroughMBB(&MBB, TBB)))
2526 return true;
2527
2528 // X86::COND_E_AND_NP usually has two different branch destinations.
2529 //
2530 // JP B1
2531 // JE B2
2532 // JMP B1
2533 // B1:
2534 // B2:
2535 //
2536 // Here this condition branches to B2 only if NP && E. It has another
2537 // equivalent form:
2538 //
2539 // JNE B1
2540 // JNP B2
2541 // JMP B1
2542 // B1:
2543 // B2:
2544 //
2545 // Similarly it branches to B2 only if E && NP. That is why this condition
2546 // is named with COND_E_AND_NP.
2547 BranchCode = X86::COND_E_AND_NP;
2548 } else
2549 return true;
2550
2551 // Update the MachineOperand.
2552 Cond[0].setImm(BranchCode);
2553 CondBranches.push_back(&*I);
2554 }
2555
2556 return false;
2557 }
2558
2559 bool X86InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
2560 MachineBasicBlock *&TBB,
2561 MachineBasicBlock *&FBB,
2562 SmallVectorImpl<MachineOperand> &Cond,
2563 bool AllowModify) const {
2564 SmallVector<MachineInstr *, 4> CondBranches;
2565 return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
2566 }
2567
2568 bool X86InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB,
2569 MachineBranchPredicate &MBP,
2570 bool AllowModify) const {
2571 using namespace std::placeholders;
2572
2573 SmallVector<MachineOperand, 4> Cond;
2574 SmallVector<MachineInstr *, 4> CondBranches;
2575 if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
2576 AllowModify))
2577 return true;
2578
2579 if (Cond.size() != 1)
2580 return true;
2581
2582 assert(MBP.TrueDest && "expected!");
2583
2584 if (!MBP.FalseDest)
2585 MBP.FalseDest = MBB.getNextNode();
2586
2587 const TargetRegisterInfo *TRI = &getRegisterInfo();
2588
2589 MachineInstr *ConditionDef = nullptr;
2590 bool SingleUseCondition = true;
2591
2592 for (auto I = std::next(MBB.rbegin()), E = MBB.rend(); I != E; ++I) {
2593 if (I->modifiesRegister(X86::EFLAGS, TRI)) {
2594 ConditionDef = &*I;
2595 break;
2596 }
2597
2598 if (I->readsRegister(X86::EFLAGS, TRI))
2599 SingleUseCondition = false;
2600 }
2601
2602 if (!ConditionDef)
2603 return true;
2604
2605 if (SingleUseCondition) {
2606 for (auto *Succ : MBB.successors())
2607 if (Succ->isLiveIn(X86::EFLAGS))
2608 SingleUseCondition = false;
2609 }
2610
2611 MBP.ConditionDef = ConditionDef;
2612 MBP.SingleUseCondition = SingleUseCondition;
2613
2614 // Currently we only recognize the simple pattern:
2615 //
2616 // test %reg, %reg
2617 // je %label
2618 //
2619 const unsigned TestOpcode =
2620 Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
2621
2622 if (ConditionDef->getOpcode() == TestOpcode &&
2623 ConditionDef->getNumOperands() == 3 &&
2624 ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
2625 (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
2626 MBP.LHS = ConditionDef->getOperand(0);
2627 MBP.RHS = MachineOperand::CreateImm(0);
2628 MBP.Predicate = Cond[0].getImm() == X86::COND_NE
2629 ? MachineBranchPredicate::PRED_NE
2630 : MachineBranchPredicate::PRED_EQ;
2631 return false;
2632 }
2633
2634 return true;
2635 }
2636
2637 unsigned X86InstrInfo::removeBranch(MachineBasicBlock &MBB,
2638 int *BytesRemoved) const {
2639 assert(!BytesRemoved && "code size not handled");
2640
2641 MachineBasicBlock::iterator I = MBB.end();
2642 unsigned Count = 0;
2643
2644 while (I != MBB.begin()) {
2645 --I;
2646 if (I->isDebugInstr())
2647 continue;
2648 if (I->getOpcode() != X86::JMP_1 &&
2649 X86::getCondFromBranch(*I) == X86::COND_INVALID)
2650 break;
2651 // Remove the branch.
2652 I->eraseFromParent();
2653 I = MBB.end();
2654 ++Count;
2655 }
2656
2657 return Count;
2658 }
2659
2660 unsigned X86InstrInfo::insertBranch(MachineBasicBlock &MBB,
2661 MachineBasicBlock *TBB,
2662 MachineBasicBlock *FBB,
2663 ArrayRef<MachineOperand> Cond,
2664 const DebugLoc &DL,
2665 int *BytesAdded) const {
2666 // Shouldn't be a fall through.
2667 assert(TBB && "insertBranch must not be told to insert a fallthrough");
2668 assert((Cond.size() == 1 || Cond.size() == 0) &&
2669 "X86 branch conditions have one component!");
2670 assert(!BytesAdded && "code size not handled");
2671
2672 if (Cond.empty()) {
2673 // Unconditional branch?
2674 assert(!FBB && "Unconditional branch with multiple successors!");
2675 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
2676 return 1;
2677 }
2678
2679 // If FBB is null, it is implied to be a fall-through block.
2680 bool FallThru = FBB == nullptr;
2681
2682 // Conditional branch.
2683 unsigned Count = 0;
2684 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
2685 switch (CC) {
2686 case X86::COND_NE_OR_P:
2687 // Synthesize NE_OR_P with two branches.
2688 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NE);
2689 ++Count;
2690 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_P);
2691 ++Count;
2692 break;
2693 case X86::COND_E_AND_NP:
2694 // Use the next block of MBB as FBB if it is null.
2695 if (FBB == nullptr) {
2696 FBB = getFallThroughMBB(&MBB, TBB);
2697 assert(FBB && "MBB cannot be the last block in function when the false "
2698 "body is a fall-through.");
2699 }
2700 // Synthesize COND_E_AND_NP with two branches.
2701 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(FBB).addImm(X86::COND_NE);
2702 ++Count;
2703 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NP);
2704 ++Count;
2705 break;
2706 default: {
2707 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(CC);
2708 ++Count;
2709 }
2710 }
2711 if (!FallThru) {
2712 // Two-way Conditional branch. Insert the second branch.
2713 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
2714 ++Count;
2715 }
2716 return Count;
2717 }
2718
2719 bool X86InstrInfo::
2720 canInsertSelect(const MachineBasicBlock &MBB,
2721 ArrayRef<MachineOperand> Cond,
2722 unsigned TrueReg, unsigned FalseReg,
2723 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
2724 // Not all subtargets have cmov instructions.
2725 if (!Subtarget.hasCMov())
2726 return false;
2727 if (Cond.size() != 1)
2728 return false;
2729 // We cannot do the composite conditions, at least not in SSA form.
2730 if ((X86::CondCode)Cond[0].getImm() > X86::LAST_VALID_COND)
2731 return false;
2732
2733 // Check register classes.
2734 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2735 const TargetRegisterClass *RC =
2736 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
2737 if (!RC)
2738 return false;
2739
2740 // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
2741 if (X86::GR16RegClass.hasSubClassEq(RC) ||
2742 X86::GR32RegClass.hasSubClassEq(RC) ||
2743 X86::GR64RegClass.hasSubClassEq(RC)) {
2744 // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
2745 // Bridge. Probably Ivy Bridge as well.
2746 CondCycles = 2;
2747 TrueCycles = 2;
2748 FalseCycles = 2;
2749 return true;
2750 }
2751
2752 // Can't do vectors.
2753 return false;
2754 }
2755
2756 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
2757 MachineBasicBlock::iterator I,
2758 const DebugLoc &DL, unsigned DstReg,
2759 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
2760 unsigned FalseReg) const {
2761 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2762 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
2763 const TargetRegisterClass &RC = *MRI.getRegClass(DstReg);
2764 assert(Cond.size() == 1 && "Invalid Cond array");
2765 unsigned Opc = X86::getCMovOpcode(TRI.getRegSizeInBits(RC) / 8,
2766 false /*HasMemoryOperand*/);
2767 BuildMI(MBB, I, DL, get(Opc), DstReg)
2768 .addReg(FalseReg)
2769 .addReg(TrueReg)
2770 .addImm(Cond[0].getImm());
2771 }
2772
2773 /// Test if the given register is a physical h register.
2774 static bool isHReg(unsigned Reg) {
2775 return X86::GR8_ABCD_HRegClass.contains(Reg);
2776 }
2777
2778 // Try and copy between VR128/VR64 and GR64 registers.
2779 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
2780 const X86Subtarget &Subtarget) {
2781 bool HasAVX = Subtarget.hasAVX();
2782 bool HasAVX512 = Subtarget.hasAVX512();
2783
2784 // SrcReg(MaskReg) -> DestReg(GR64)
2785 // SrcReg(MaskReg) -> DestReg(GR32)
2786
2787 // All KMASK RegClasses hold the same k registers, can be tested against anyone.
2788 if (X86::VK16RegClass.contains(SrcReg)) {
2789 if (X86::GR64RegClass.contains(DestReg)) {
2790 assert(Subtarget.hasBWI());
2791 return X86::KMOVQrk;
2792 }
2793 if (X86::GR32RegClass.contains(DestReg))
2794 return Subtarget.hasBWI() ? X86::KMOVDrk : X86::KMOVWrk;
2795 }
2796
2797 // SrcReg(GR64) -> DestReg(MaskReg)
2798 // SrcReg(GR32) -> DestReg(MaskReg)
2799
2800 // All KMASK RegClasses hold the same k registers, can be tested against anyone.
2801 if (X86::VK16RegClass.contains(DestReg)) {
2802 if (X86::GR64RegClass.contains(SrcReg)) {
2803 assert(Subtarget.hasBWI());
2804 return X86::KMOVQkr;
2805 }
2806 if (X86::GR32RegClass.contains(SrcReg))
2807 return Subtarget.hasBWI() ? X86::KMOVDkr : X86::KMOVWkr;
2808 }
2809
2810
2811 // SrcReg(VR128) -> DestReg(GR64)
2812 // SrcReg(VR64) -> DestReg(GR64)
2813 // SrcReg(GR64) -> DestReg(VR128)
2814 // SrcReg(GR64) -> DestReg(VR64)
2815
2816 if (X86::GR64RegClass.contains(DestReg)) {
2817 if (X86::VR128XRegClass.contains(SrcReg))
2818 // Copy from a VR128 register to a GR64 register.
2819 return HasAVX512 ? X86::VMOVPQIto64Zrr :
2820 HasAVX ? X86::VMOVPQIto64rr :
2821 X86::MOVPQIto64rr;
2822 if (X86::VR64RegClass.contains(SrcReg))
2823 // Copy from a VR64 register to a GR64 register.
2824 return X86::MMX_MOVD64from64rr;
2825 } else if (X86::GR64RegClass.contains(SrcReg)) {
2826 // Copy from a GR64 register to a VR128 register.
2827 if (X86::VR128XRegClass.contains(DestReg))
2828 return HasAVX512 ? X86::VMOV64toPQIZrr :
2829 HasAVX ? X86::VMOV64toPQIrr :
2830 X86::MOV64toPQIrr;
2831 // Copy from a GR64 register to a VR64 register.
2832 if (X86::VR64RegClass.contains(DestReg))
2833 return X86::MMX_MOVD64to64rr;
2834 }
2835
2836 // SrcReg(VR128) -> DestReg(GR32)
2837 // SrcReg(GR32) -> DestReg(VR128)
2838
2839 if (X86::GR32RegClass.contains(DestReg) &&
2840 X86::VR128XRegClass.contains(SrcReg))
2841 // Copy from a VR128 register to a GR32 register.
2842 return HasAVX512 ? X86::VMOVPDI2DIZrr :
2843 HasAVX ? X86::VMOVPDI2DIrr :
2844 X86::MOVPDI2DIrr;
2845
2846 if (X86::VR128XRegClass.contains(DestReg) &&
2847 X86::GR32RegClass.contains(SrcReg))
2848 // Copy from a VR128 register to a VR128 register.
2849 return HasAVX512 ? X86::VMOVDI2PDIZrr :
2850 HasAVX ? X86::VMOVDI2PDIrr :
2851 X86::MOVDI2PDIrr;
2852 return 0;
2853 }
2854
2855 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
2856 MachineBasicBlock::iterator MI,
2857 const DebugLoc &DL, unsigned DestReg,
2858 unsigned SrcReg, bool KillSrc) const {
2859 // First deal with the normal symmetric copies.
2860 bool HasAVX = Subtarget.hasAVX();
2861 bool HasVLX = Subtarget.hasVLX();
2862 unsigned Opc = 0;
2863 if (X86::GR64RegClass.contains(DestReg, SrcReg))
2864 Opc = X86::MOV64rr;
2865 else if (X86::GR32RegClass.contains(DestReg, SrcReg))
2866 Opc = X86::MOV32rr;
2867 else if (X86::GR16RegClass.contains(DestReg, SrcReg))
2868 Opc = X86::MOV16rr;
2869 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
2870 // Copying to or from a physical H register on x86-64 requires a NOREX
2871 // move. Otherwise use a normal move.
2872 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
2873 Subtarget.is64Bit()) {
2874 Opc = X86::MOV8rr_NOREX;
2875 // Both operands must be encodable without an REX prefix.
2876 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
2877 "8-bit H register can not be copied outside GR8_NOREX");
2878 } else
2879 Opc = X86::MOV8rr;
2880 }
2881 else if (X86::VR64RegClass.contains(DestReg, SrcReg))
2882 Opc = X86::MMX_MOVQ64rr;
2883 else if (X86::VR128XRegClass.contains(DestReg, SrcReg)) {
2884 if (HasVLX)
2885 Opc = X86::VMOVAPSZ128rr;
2886 else if (X86::VR128RegClass.contains(DestReg, SrcReg))
2887 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
2888 else {
2889 // If this an extended register and we don't have VLX we need to use a
2890 // 512-bit move.
2891 Opc = X86::VMOVAPSZrr;
2892 const TargetRegisterInfo *TRI = &getRegisterInfo();
2893 DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_xmm,
2894 &X86::VR512RegClass);
2895 SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm,
2896 &X86::VR512RegClass);
2897 }
2898 } else if (X86::VR256XRegClass.contains(DestReg, SrcReg)) {
2899 if (HasVLX)
2900 Opc = X86::VMOVAPSZ256rr;
2901 else if (X86::VR256RegClass.contains(DestReg, SrcReg))
2902 Opc = X86::VMOVAPSYrr;
2903 else {
2904 // If this an extended register and we don't have VLX we need to use a
2905 // 512-bit move.
2906 Opc = X86::VMOVAPSZrr;
2907 const TargetRegisterInfo *TRI = &getRegisterInfo();
2908 DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_ymm,
2909 &X86::VR512RegClass);
2910 SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm,
2911 &X86::VR512RegClass);
2912 }
2913 } else if (X86::VR512RegClass.contains(DestReg, SrcReg))
2914 Opc = X86::VMOVAPSZrr;
2915 // All KMASK RegClasses hold the same k registers, can be tested against anyone.
2916 else if (X86::VK16RegClass.contains(DestReg, SrcReg))
2917 Opc = Subtarget.hasBWI() ? X86::KMOVQkk : X86::KMOVWkk;
2918 if (!Opc)
2919 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
2920
2921 if (Opc) {
2922 BuildMI(MBB, MI, DL, get(Opc), DestReg)
2923 .addReg(SrcReg, getKillRegState(KillSrc));
2924 return;
2925 }
2926
2927 if (SrcReg == X86::EFLAGS || DestReg == X86::EFLAGS) {
2928 // FIXME: We use a fatal error here because historically LLVM has tried
2929 // lower some of these physreg copies and we want to ensure we get
2930 // reasonable bug reports if someone encounters a case no other testing
2931 // found. This path should be removed after the LLVM 7 release.
2932 report_fatal_error("Unable to copy EFLAGS physical register!");
2933 }
2934
2935 LLVM_DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) << " to "
2936 << RI.getName(DestReg) << '\n');
2937 report_fatal_error("Cannot emit physreg copy instruction");
2938 }
2939
2940 bool X86InstrInfo::isCopyInstrImpl(const MachineInstr &MI,
2941 const MachineOperand *&Src,
2942 const MachineOperand *&Dest) const {
2943 if (MI.isMoveReg()) {
2944 Dest = &MI.getOperand(0);
2945 Src = &MI.getOperand(1);
2946 return true;
2947 }
2948 return false;
2949 }
2950
2951 static unsigned getLoadStoreRegOpcode(unsigned Reg,
2952 const TargetRegisterClass *RC,
2953 bool isStackAligned,
2954 const X86Subtarget &STI,
2955 bool load) {
2956 bool HasAVX = STI.hasAVX();
2957 bool HasAVX512 = STI.hasAVX512();
2958 bool HasVLX = STI.hasVLX();
2959
2960 switch (STI.getRegisterInfo()->getSpillSize(*RC)) {
2961 default:
2962 llvm_unreachable("Unknown spill size");
2963 case 1:
2964 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
2965 if (STI.is64Bit())
2966 // Copying to or from a physical H register on x86-64 requires a NOREX
2967 // move. Otherwise use a normal move.
2968 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
2969 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
2970 return load ? X86::MOV8rm : X86::MOV8mr;
2971 case 2:
2972 if (X86::VK16RegClass.hasSubClassEq(RC))
2973 return load ? X86::KMOVWkm : X86::KMOVWmk;
2974 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
2975 return load ? X86::MOV16rm : X86::MOV16mr;
2976 case 4:
2977 if (X86::GR32RegClass.hasSubClassEq(RC))
2978 return load ? X86::MOV32rm : X86::MOV32mr;
2979 if (X86::FR32XRegClass.hasSubClassEq(RC))
2980 return load ?
2981 (HasAVX512 ? X86::VMOVSSZrm_alt :
2982 HasAVX ? X86::VMOVSSrm_alt :
2983 X86::MOVSSrm_alt) :
2984 (HasAVX512 ? X86::VMOVSSZmr :
2985 HasAVX ? X86::VMOVSSmr :
2986 X86::MOVSSmr);
2987 if (X86::RFP32RegClass.hasSubClassEq(RC))
2988 return load ? X86::LD_Fp32m : X86::ST_Fp32m;
2989 if (X86::VK32RegClass.hasSubClassEq(RC)) {
2990 assert(STI.hasBWI() && "KMOVD requires BWI");
2991 return load ? X86::KMOVDkm : X86::KMOVDmk;
2992 }
2993 // All of these mask pair classes have the same spill size, the same kind
2994 // of kmov instructions can be used with all of them.
2995 if (X86::VK1PAIRRegClass.hasSubClassEq(RC) ||
2996 X86::VK2PAIRRegClass.hasSubClassEq(RC) ||
2997 X86::VK4PAIRRegClass.hasSubClassEq(RC) ||
2998 X86::VK8PAIRRegClass.hasSubClassEq(RC) ||
2999 X86::VK16PAIRRegClass.hasSubClassEq(RC))
3000 return load ? X86::MASKPAIR16LOAD : X86::MASKPAIR16STORE;
3001 llvm_unreachable("Unknown 4-byte regclass");
3002 case 8:
3003 if (X86::GR64RegClass.hasSubClassEq(RC))
3004 return load ? X86::MOV64rm : X86::MOV64mr;
3005 if (X86::FR64XRegClass.hasSubClassEq(RC))
3006 return load ?
3007 (HasAVX512 ? X86::VMOVSDZrm_alt :
3008 HasAVX ? X86::VMOVSDrm_alt :
3009 X86::MOVSDrm_alt) :
3010 (HasAVX512 ? X86::VMOVSDZmr :
3011 HasAVX ? X86::VMOVSDmr :
3012 X86::MOVSDmr);
3013 if (X86::VR64RegClass.hasSubClassEq(RC))
3014 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
3015 if (X86::RFP64RegClass.hasSubClassEq(RC))
3016 return load ? X86::LD_Fp64m : X86::ST_Fp64m;
3017 if (X86::VK64RegClass.hasSubClassEq(RC)) {
3018 assert(STI.hasBWI() && "KMOVQ requires BWI");
3019 return load ? X86::KMOVQkm : X86::KMOVQmk;
3020 }
3021 llvm_unreachable("Unknown 8-byte regclass");
3022 case 10:
3023 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
3024 return load ? X86::LD_Fp80m : X86::ST_FpP80m;
3025 case 16: {
3026 if (X86::VR128XRegClass.hasSubClassEq(RC)) {
3027 // If stack is realigned we can use aligned stores.
3028 if (isStackAligned)
3029 return load ?
3030 (HasVLX ? X86::VMOVAPSZ128rm :
3031 HasAVX512 ? X86::VMOVAPSZ128rm_NOVLX :
3032 HasAVX ? X86::VMOVAPSrm :
3033 X86::MOVAPSrm):
3034 (HasVLX ? X86::VMOVAPSZ128mr :
3035 HasAVX512 ? X86::VMOVAPSZ128mr_NOVLX :
3036 HasAVX ? X86::VMOVAPSmr :
3037 X86::MOVAPSmr);
3038 else
3039 return load ?
3040 (HasVLX ? X86::VMOVUPSZ128rm :
3041 HasAVX512 ? X86::VMOVUPSZ128rm_NOVLX :
3042 HasAVX ? X86::VMOVUPSrm :
3043 X86::MOVUPSrm):
3044 (HasVLX ? X86::VMOVUPSZ128mr :
3045 HasAVX512 ? X86::VMOVUPSZ128mr_NOVLX :
3046 HasAVX ? X86::VMOVUPSmr :
3047 X86::MOVUPSmr);
3048 }
3049 if (X86::BNDRRegClass.hasSubClassEq(RC)) {
3050 if (STI.is64Bit())
3051 return load ? X86::BNDMOV64rm : X86::BNDMOV64mr;
3052 else
3053 return load ? X86::BNDMOV32rm : X86::BNDMOV32mr;
3054 }
3055 llvm_unreachable("Unknown 16-byte regclass");
3056 }
3057 case 32:
3058 assert(X86::VR256XRegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
3059 // If stack is realigned we can use aligned stores.
3060 if (isStackAligned)
3061 return load ?
3062 (HasVLX ? X86::VMOVAPSZ256rm :
3063 HasAVX512 ? X86::VMOVAPSZ256rm_NOVLX :
3064 X86::VMOVAPSYrm) :
3065 (HasVLX ? X86::VMOVAPSZ256mr :
3066 HasAVX512 ? X86::VMOVAPSZ256mr_NOVLX :
3067 X86::VMOVAPSYmr);
3068 else
3069 return load ?
3070 (HasVLX ? X86::VMOVUPSZ256rm :
3071 HasAVX512 ? X86::VMOVUPSZ256rm_NOVLX :
3072 X86::VMOVUPSYrm) :
3073 (HasVLX ? X86::VMOVUPSZ256mr :
3074 HasAVX512 ? X86::VMOVUPSZ256mr_NOVLX :
3075 X86::VMOVUPSYmr);
3076 case 64:
3077 assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
3078 assert(STI.hasAVX512() && "Using 512-bit register requires AVX512");
3079 if (isStackAligned)
3080 return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
3081 else
3082 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3083 }
3084 }
3085
3086 bool X86InstrInfo::getMemOperandWithOffset(
3087 const MachineInstr &MemOp, const MachineOperand *&BaseOp, int64_t &Offset,
3088 const TargetRegisterInfo *TRI) const {
3089 const MCInstrDesc &Desc = MemOp.getDesc();
3090 int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
3091 if (MemRefBegin < 0)
3092 return false;
3093
3094 MemRefBegin += X86II::getOperandBias(Desc);
3095
3096 BaseOp = &MemOp.getOperand(MemRefBegin + X86::AddrBaseReg);
3097 if (!BaseOp->isReg()) // Can be an MO_FrameIndex
3098 return false;
3099
3100 if (MemOp.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
3101 return false;
3102
3103 if (MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
3104 X86::NoRegister)
3105 return false;
3106
3107 const MachineOperand &DispMO = MemOp.getOperand(MemRefBegin + X86::AddrDisp);
3108
3109 // Displacement can be symbolic
3110 if (!DispMO.isImm())
3111 return false;
3112
3113 Offset = DispMO.getImm();
3114
3115 assert(BaseOp->isReg() && "getMemOperandWithOffset only supports base "
3116 "operands of type register.");
3117 return true;
3118 }
3119
3120 static unsigned getStoreRegOpcode(unsigned SrcReg,
3121 const TargetRegisterClass *RC,
3122 bool isStackAligned,
3123 const X86Subtarget &STI) {
3124 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
3125 }
3126
3127
3128 static unsigned getLoadRegOpcode(unsigned DestReg,
3129 const TargetRegisterClass *RC,
3130 bool isStackAligned,
3131 const X86Subtarget &STI) {
3132 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
3133 }
3134
3135 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
3136 MachineBasicBlock::iterator MI,
3137 unsigned SrcReg, bool isKill, int FrameIdx,
3138 const TargetRegisterClass *RC,
3139 const TargetRegisterInfo *TRI) const {
3140 const MachineFunction &MF = *MBB.getParent();
3141 assert(MF.getFrameInfo().getObjectSize(FrameIdx) >= TRI->getSpillSize(*RC) &&
3142 "Stack slot too small for store");
3143 unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
3144 bool isAligned =
3145 (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
3146 RI.canRealignStack(MF);
3147 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
3148 addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc)), FrameIdx)
3149 .addReg(SrcReg, getKillRegState(isKill));
3150 }
3151
3152 void X86InstrInfo::storeRegToAddr(
3153 MachineFunction &MF, unsigned SrcReg, bool isKill,
3154 SmallVectorImpl<MachineOperand> &Addr, const TargetRegisterClass *RC,
3155 ArrayRef<MachineMemOperand *> MMOs,
3156 SmallVectorImpl<MachineInstr *> &NewMIs) const {
3157 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
3158 unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
3159 bool isAligned = !MMOs.empty() && MMOs.front()->getAlignment() >= Alignment;
3160 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
3161 DebugLoc DL;
3162 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
3163 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
3164 MIB.add(Addr[i]);
3165 MIB.addReg(SrcReg, getKillRegState(isKill));
3166 MIB.setMemRefs(MMOs);
3167 NewMIs.push_back(MIB);
3168 }
3169
3170
3171 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
3172 MachineBasicBlock::iterator MI,
3173 unsigned DestReg, int FrameIdx,
3174 const TargetRegisterClass *RC,
3175 const TargetRegisterInfo *TRI) const {
3176 const MachineFunction &MF = *MBB.getParent();
3177 unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
3178 bool isAligned =
3179 (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
3180 RI.canRealignStack(MF);
3181 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
3182 addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc), DestReg), FrameIdx);
3183 }
3184
3185 void X86InstrInfo::loadRegFromAddr(
3186 MachineFunction &MF, unsigned DestReg,
3187 SmallVectorImpl<MachineOperand> &Addr, const TargetRegisterClass *RC,
3188 ArrayRef<MachineMemOperand *> MMOs,
3189 SmallVectorImpl<MachineInstr *> &NewMIs) const {
3190 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
3191 unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
3192 bool isAligned = !MMOs.empty() && MMOs.front()->getAlignment() >= Alignment;
3193 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
3194 DebugLoc DL;
3195 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
3196 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
3197 MIB.add(Addr[i]);
3198 MIB.setMemRefs(MMOs);
3199 NewMIs.push_back(MIB);
3200 }
3201
3202 bool X86InstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
3203 unsigned &SrcReg2, int &CmpMask,
3204 int &CmpValue) const {
3205 switch (MI.getOpcode()) {
3206 default: break;
3207 case X86::CMP64ri32:
3208 case X86::CMP64ri8:
3209 case X86::CMP32ri:
3210 case X86::CMP32ri8:
3211 case X86::CMP16ri:
3212 case X86::CMP16ri8:
3213 case X86::CMP8ri:
3214 SrcReg = MI.getOperand(0).getReg();
3215 SrcReg2 = 0;
3216 if (MI.getOperand(1).isImm()) {
3217 CmpMask = ~0;
3218 CmpValue = MI.getOperand(1).getImm();
3219 } else {
3220 CmpMask = CmpValue = 0;
3221 }
3222 return true;
3223 // A SUB can be used to perform comparison.
3224 case X86::SUB64rm:
3225 case X86::SUB32rm:
3226 case X86::SUB16rm:
3227 case X86::SUB8rm:
3228 SrcReg = MI.getOperand(1).getReg();
3229 SrcReg2 = 0;
3230 CmpMask = 0;
3231 CmpValue = 0;
3232 return true;
3233 case X86::SUB64rr:
3234 case X86::SUB32rr:
3235 case X86::SUB16rr:
3236 case X86::SUB8rr:
3237 SrcReg = MI.getOperand(1).getReg();
3238 SrcReg2 = MI.getOperand(2).getReg();
3239 CmpMask = 0;
3240 CmpValue = 0;
3241 return true;
3242 case X86::SUB64ri32:
3243 case X86::SUB64ri8:
3244 case X86::SUB32ri:
3245 case X86::SUB32ri8:
3246 case X86::SUB16ri:
3247 case X86::SUB16ri8:
3248 case X86::SUB8ri:
3249 SrcReg = MI.getOperand(1).getReg();
3250 SrcReg2 = 0;
3251 if (MI.getOperand(2).isImm()) {
3252 CmpMask = ~0;
3253 CmpValue = MI.getOperand(2).getImm();
3254 } else {
3255 CmpMask = CmpValue = 0;
3256 }
3257 return true;
3258 case X86::CMP64rr:
3259 case X86::CMP32rr:
3260 case X86::CMP16rr:
3261 case X86::CMP8rr:
3262 SrcReg = MI.getOperand(0).getReg();
3263 SrcReg2 = MI.getOperand(1).getReg();
3264 CmpMask = 0;
3265 CmpValue = 0;
3266 return true;
3267 case X86::TEST8rr:
3268 case X86::TEST16rr:
3269 case X86::TEST32rr:
3270 case X86::TEST64rr:
3271 SrcReg = MI.getOperand(0).getReg();
3272 if (MI.getOperand(1).getReg() != SrcReg)
3273 return false;
3274 // Compare against zero.
3275 SrcReg2 = 0;
3276 CmpMask = ~0;
3277 CmpValue = 0;
3278 return true;
3279 }
3280 return false;
3281 }
3282
3283 /// Check whether the first instruction, whose only
3284 /// purpose is to update flags, can be made redundant.
3285 /// CMPrr can be made redundant by SUBrr if the operands are the same.
3286 /// This function can be extended later on.
3287 /// SrcReg, SrcRegs: register operands for FlagI.
3288 /// ImmValue: immediate for FlagI if it takes an immediate.
3289 inline static bool isRedundantFlagInstr(const MachineInstr &FlagI,
3290 unsigned SrcReg, unsigned SrcReg2,
3291 int ImmMask, int ImmValue,
3292 const MachineInstr &OI) {
3293 if (((FlagI.getOpcode() == X86::CMP64rr && OI.getOpcode() == X86::SUB64rr) ||
3294 (FlagI.getOpcode() == X86::CMP32rr && OI.getOpcode() == X86::SUB32rr) ||
3295 (FlagI.getOpcode() == X86::CMP16rr && OI.getOpcode() == X86::SUB16rr) ||
3296 (FlagI.getOpcode() == X86::CMP8rr && OI.getOpcode() == X86::SUB8rr)) &&
3297 ((OI.getOperand(1).getReg() == SrcReg &&
3298 OI.getOperand(2).getReg() == SrcReg2) ||
3299 (OI.getOperand(1).getReg() == SrcReg2 &&
3300 OI.getOperand(2).getReg() == SrcReg)))
3301 return true;
3302
3303 if (ImmMask != 0 &&
3304 ((FlagI.getOpcode() == X86::CMP64ri32 &&
3305 OI.getOpcode() == X86::SUB64ri32) ||
3306 (FlagI.getOpcode() == X86::CMP64ri8 &&
3307 OI.getOpcode() == X86::SUB64ri8) ||
3308 (FlagI.getOpcode() == X86::CMP32ri && OI.getOpcode() == X86::SUB32ri) ||
3309 (FlagI.getOpcode() == X86::CMP32ri8 &&
3310 OI.getOpcode() == X86::SUB32ri8) ||
3311 (FlagI.getOpcode() == X86::CMP16ri && OI.getOpcode() == X86::SUB16ri) ||
3312 (FlagI.getOpcode() == X86::CMP16ri8 &&
3313 OI.getOpcode() == X86::SUB16ri8) ||
3314 (FlagI.getOpcode() == X86::CMP8ri && OI.getOpcode() == X86::SUB8ri)) &&
3315 OI.getOperand(1).getReg() == SrcReg &&
3316 OI.getOperand(2).getImm() == ImmValue)
3317 return true;
3318 return false;
3319 }
3320
3321 /// Check whether the definition can be converted
3322 /// to remove a comparison against zero.
3323 inline static bool isDefConvertible(const MachineInstr &MI, bool &NoSignFlag) {
3324 NoSignFlag = false;
3325
3326 switch (MI.getOpcode()) {
3327 default: return false;
3328
3329 // The shift instructions only modify ZF if their shift count is non-zero.
3330 // N.B.: The processor truncates the shift count depending on the encoding.
3331 case X86::SAR8ri: case X86::SAR16ri: case X86::SAR32ri:case X86::SAR64ri:
3332 case X86::SHR8ri: case X86::SHR16ri: case X86::SHR32ri:case X86::SHR64ri:
3333 return getTruncatedShiftCount(MI, 2) != 0;
3334
3335 // Some left shift instructions can be turned into LEA instructions but only
3336 // if their flags aren't used. Avoid transforming such instructions.
3337 case X86::SHL8ri: case X86::SHL16ri: case X86::SHL32ri:case X86::SHL64ri:{
3338 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
3339 if (isTruncatedShiftCountForLEA(ShAmt)) return false;
3340 return ShAmt != 0;
3341 }
3342
3343 case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
3344 case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
3345 return getTruncatedShiftCount(MI, 3) != 0;
3346
3347 case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
3348 case X86::SUB32ri8: case X86::SUB16ri: case X86::SUB16ri8:
3349 case X86::SUB8ri: case X86::SUB64rr: case X86::SUB32rr:
3350 case X86::SUB16rr: case X86::SUB8rr: case X86::SUB64rm:
3351 case X86::SUB32rm: case X86::SUB16rm: case X86::SUB8rm:
3352 case X86::DEC64r: case X86::DEC32r: case X86::DEC16r: case X86::DEC8r:
3353 case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
3354 case X86::ADD32ri8: case X86::ADD16ri: case X86::ADD16ri8:
3355 case X86::ADD8ri: case X86::ADD64rr: case X86::ADD32rr:
3356 case X86::ADD16rr: case X86::ADD8rr: case X86::ADD64rm:
3357 case X86::ADD32rm: case X86::ADD16rm: case X86::ADD8rm:
3358 case X86::INC64r: case X86::INC32r: case X86::INC16r: case X86::INC8r:
3359 case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
3360 case X86::AND32ri8: case X86::AND16ri: case X86::AND16ri8:
3361 case X86::AND8ri: case X86::AND64rr: case X86::AND32rr:
3362 case X86::AND16rr: case X86::AND8rr: case X86::AND64rm:
3363 case X86::AND32rm: case X86::AND16rm: case X86::AND8rm:
3364 case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
3365 case X86::XOR32ri8: case X86::XOR16ri: case X86::XOR16ri8:
3366 case X86::XOR8ri: case X86::XOR64rr: case X86::XOR32rr:
3367 case X86::XOR16rr: case X86::XOR8rr: case X86::XOR64rm:
3368 case X86::XOR32rm: case X86::XOR16rm: case X86::XOR8rm:
3369 case X86::OR64ri32: case X86::OR64ri8: case X86::OR32ri:
3370 case X86::OR32ri8: case X86::OR16ri: case X86::OR16ri8:
3371 case X86::OR8ri: case X86::OR64rr: case X86::OR32rr:
3372 case X86::OR16rr: case X86::OR8rr: case X86::OR64rm:
3373 case X86::OR32rm: case X86::OR16rm: case X86::OR8rm:
3374 case X86::ADC64ri32: case X86::ADC64ri8: case X86::ADC32ri:
3375 case X86::ADC32ri8: case X86::ADC16ri: case X86::ADC16ri8:
3376 case X86::ADC8ri: case X86::ADC64rr: case X86::ADC32rr:
3377 case X86::ADC16rr: case X86::ADC8rr: case X86::ADC64rm:
3378 case X86::ADC32rm: case X86::ADC16rm: case X86::ADC8rm:
3379 case X86::SBB64ri32: case X86::SBB64ri8: case X86::SBB32ri:
3380 case X86::SBB32ri8: case X86::SBB16ri: case X86::SBB16ri8:
3381 case X86::SBB8ri: case X86::SBB64rr: case X86::SBB32rr:
3382 case X86::SBB16rr: case X86::SBB8rr: case X86::SBB64rm:
3383 case X86::SBB32rm: case X86::SBB16rm: case X86::SBB8rm:
3384 case X86::NEG8r: case X86::NEG16r: case X86::NEG32r: case X86::NEG64r:
3385 case X86::SAR8r1: case X86::SAR16r1: case X86::SAR32r1:case X86::SAR64r1:
3386 case X86::SHR8r1: case X86::SHR16r1: case X86::SHR32r1:case X86::SHR64r1:
3387 case X86::SHL8r1: case X86::SHL16r1: case X86::SHL32r1:case X86::SHL64r1:
3388 case X86::ANDN32rr: case X86::ANDN32rm:
3389 case X86::ANDN64rr: case X86::ANDN64rm:
3390 case X86::BLSI32rr: case X86::BLSI32rm:
3391 case X86::BLSI64rr: case X86::BLSI64rm:
3392 case X86::BLSMSK32rr:case X86::BLSMSK32rm:
3393 case X86::BLSMSK64rr:case X86::BLSMSK64rm:
3394 case X86::BLSR32rr: case X86::BLSR32rm:
3395 case X86::BLSR64rr: case X86::BLSR64rm:
3396 case X86::BZHI32rr: case X86::BZHI32rm:
3397 case X86::BZHI64rr: case X86::BZHI64rm:
3398 case X86::LZCNT16rr: case X86::LZCNT16rm:
3399 case X86::LZCNT32rr: case X86::LZCNT32rm:
3400 case X86::LZCNT64rr: case X86::LZCNT64rm:
3401 case X86::POPCNT16rr:case X86::POPCNT16rm:
3402 case X86::POPCNT32rr:case X86::POPCNT32rm:
3403 case X86::POPCNT64rr:case X86::POPCNT64rm:
3404 case X86::TZCNT16rr: case X86::TZCNT16rm:
3405 case X86::TZCNT32rr: case X86::TZCNT32rm:
3406 case X86::TZCNT64rr: case X86::TZCNT64rm:
3407 case X86::BLCFILL32rr: case X86::BLCFILL32rm:
3408 case X86::BLCFILL64rr: case X86::BLCFILL64rm:
3409 case X86::BLCI32rr: case X86::BLCI32rm:
3410 case X86::BLCI64rr: case X86::BLCI64rm:
3411 case X86::BLCIC32rr: case X86::BLCIC32rm:
3412 case X86::BLCIC64rr: case X86::BLCIC64rm:
3413 case X86::BLCMSK32rr: case X86::BLCMSK32rm:
3414 case X86::BLCMSK64rr: case X86::BLCMSK64rm:
3415 case X86::BLCS32rr: case X86::BLCS32rm:
3416 case X86::BLCS64rr: case X86::BLCS64rm:
3417 case X86::BLSFILL32rr: case X86::BLSFILL32rm:
3418 case X86::BLSFILL64rr: case X86::BLSFILL64rm:
3419 case X86::BLSIC32rr: case X86::BLSIC32rm:
3420 case X86::BLSIC64rr: case X86::BLSIC64rm:
3421 case X86::T1MSKC32rr: case X86::T1MSKC32rm:
3422 case X86::T1MSKC64rr: case X86::T1MSKC64rm:
3423 case X86::TZMSK32rr: case X86::TZMSK32rm:
3424 case X86::TZMSK64rr: case X86::TZMSK64rm:
3425 return true;
3426 case X86::BEXTR32rr: case X86::BEXTR64rr:
3427 case X86::BEXTR32rm: case X86::BEXTR64rm:
3428 case X86::BEXTRI32ri: case X86::BEXTRI32mi:
3429 case X86::BEXTRI64ri: case X86::BEXTRI64mi:
3430 // BEXTR doesn't update the sign flag so we can't use it.
3431 NoSignFlag = true;
3432 return true;
3433 }
3434 }
3435
3436 /// Check whether the use can be converted to remove a comparison against zero.
3437 static X86::CondCode isUseDefConvertible(const MachineInstr &MI) {
3438 switch (MI.getOpcode()) {
3439 default: return X86::COND_INVALID;
3440 case X86::NEG8r:
3441 case X86::NEG16r:
3442 case X86::NEG32r:
3443 case X86::NEG64r:
3444 return X86::COND_AE;
3445 case X86::LZCNT16rr:
3446 case X86::LZCNT32rr:
3447 case X86::LZCNT64rr:
3448 return X86::COND_B;
3449 case X86::POPCNT16rr:
3450 case X86::POPCNT32rr:
3451 case X86::POPCNT64rr:
3452 return X86::COND_E;
3453 case X86::TZCNT16rr:
3454 case X86::TZCNT32rr:
3455 case X86::TZCNT64rr:
3456 return X86::COND_B;
3457 case X86::BSF16rr:
3458 case X86::BSF32rr:
3459 case X86::BSF64rr:
3460 case X86::BSR16rr:
3461 case X86::BSR32rr:
3462 case X86::BSR64rr:
3463 return X86::COND_E;
3464 case X86::BLSI32rr:
3465 case X86::BLSI64rr:
3466 return X86::COND_AE;
3467 case X86::BLSR32rr:
3468 case X86::BLSR64rr:
3469 case X86::BLSMSK32rr:
3470 case X86::BLSMSK64rr:
3471 return X86::COND_B;
3472 // TODO: TBM instructions.
3473 }
3474 }
3475
3476 /// Check if there exists an earlier instruction that
3477 /// operates on the same source operands and sets flags in the same way as
3478 /// Compare; remove Compare if possible.
3479 bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
3480 unsigned SrcReg2, int CmpMask,
3481 int CmpValue,
3482 const MachineRegisterInfo *MRI) const {
3483 // Check whether we can replace SUB with CMP.
3484 switch (CmpInstr.getOpcode()) {
3485 default: break;
3486 case X86::SUB64ri32:
3487 case X86::SUB64ri8:
3488 case X86::SUB32ri:
3489 case X86::SUB32ri8:
3490 case X86::SUB16ri:
3491 case X86::SUB16ri8:
3492 case X86::SUB8ri:
3493 case X86::SUB64rm:
3494 case X86::SUB32rm:
3495 case X86::SUB16rm:
3496 case X86::SUB8rm:
3497 case X86::SUB64rr:
3498 case X86::SUB32rr:
3499 case X86::SUB16rr:
3500 case X86::SUB8rr: {
3501 if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg()))
3502 return false;
3503 // There is no use of the destination register, we can replace SUB with CMP.
3504 unsigned NewOpcode = 0;
3505 switch (CmpInstr.getOpcode()) {
3506 default: llvm_unreachable("Unreachable!");
3507 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break;
3508 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break;
3509 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break;
3510 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break;
3511 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break;
3512 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break;
3513 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break;
3514 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break;
3515 case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
3516 case X86::SUB64ri8: NewOpcode = X86::CMP64ri8; break;
3517 case X86::SUB32ri: NewOpcode = X86::CMP32ri; break;
3518 case X86::SUB32ri8: NewOpcode = X86::CMP32ri8; break;
3519 case X86::SUB16ri: NewOpcode = X86::CMP16ri; break;
3520 case X86::SUB16ri8: NewOpcode = X86::CMP16ri8; break;
3521 case X86::SUB8ri: NewOpcode = X86::CMP8ri; break;
3522 }
3523 CmpInstr.setDesc(get(NewOpcode));
3524 CmpInstr.RemoveOperand(0);
3525 // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
3526 if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
3527 NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
3528 return false;
3529 }
3530 }
3531
3532 // Get the unique definition of SrcReg.
3533 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
3534 if (!MI) return false;
3535
3536 // CmpInstr is the first instruction of the BB.
3537 MachineBasicBlock::iterator I = CmpInstr, Def = MI;
3538
3539 // If we are comparing against zero, check whether we can use MI to update
3540 // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
3541 bool IsCmpZero = (CmpMask != 0 && CmpValue == 0);
3542 if (IsCmpZero && MI->getParent() != CmpInstr.getParent())
3543 return false;
3544
3545 // If we have a use of the source register between the def and our compare
3546 // instruction we can eliminate the compare iff the use sets EFLAGS in the
3547 // right way.
3548 bool ShouldUpdateCC = false;
3549 bool NoSignFlag = false;
3550 X86::CondCode NewCC = X86::COND_INVALID;
3551 if (IsCmpZero && !isDefConvertible(*MI, NoSignFlag)) {
3552 // Scan forward from the use until we hit the use we're looking for or the
3553 // compare instruction.
3554 for (MachineBasicBlock::iterator J = MI;; ++J) {
3555 // Do we have a convertible instruction?
3556 NewCC = isUseDefConvertible(*J);
3557 if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
3558 J->getOperand(1).getReg() == SrcReg) {
3559 assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
3560 ShouldUpdateCC = true; // Update CC later on.
3561 // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
3562 // with the new def.
3563 Def = J;
3564 MI = &*Def;
3565 break;
3566 }
3567
3568 if (J == I)
3569 return false;
3570 }
3571 }
3572
3573 // We are searching for an earlier instruction that can make CmpInstr
3574 // redundant and that instruction will be saved in Sub.
3575 MachineInstr *Sub = nullptr;
3576 const TargetRegisterInfo *TRI = &getRegisterInfo();
3577
3578 // We iterate backward, starting from the instruction before CmpInstr and
3579 // stop when reaching the definition of a source register or done with the BB.
3580 // RI points to the instruction before CmpInstr.
3581 // If the definition is in this basic block, RE points to the definition;
3582 // otherwise, RE is the rend of the basic block.
3583 MachineBasicBlock::reverse_iterator
3584 RI = ++I.getReverse(),
3585 RE = CmpInstr.getParent() == MI->getParent()
3586 ? Def.getReverse() /* points to MI */
3587 : CmpInstr.getParent()->rend();
3588 MachineInstr *Movr0Inst = nullptr;
3589 for (; RI != RE; ++RI) {
3590 MachineInstr &Instr = *RI;
3591 // Check whether CmpInstr can be made redundant by the current instruction.
3592 if (!IsCmpZero && isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpMask,
3593 CmpValue, Instr)) {
3594 Sub = &Instr;
3595 break;
3596 }
3597
3598 if (Instr.modifiesRegister(X86::EFLAGS, TRI) ||
3599 Instr.readsRegister(X86::EFLAGS, TRI)) {
3600 // This instruction modifies or uses EFLAGS.
3601
3602 // MOV32r0 etc. are implemented with xor which clobbers condition code.
3603 // They are safe to move up, if the definition to EFLAGS is dead and
3604 // earlier instructions do not read or write EFLAGS.
3605 if (!Movr0Inst && Instr.getOpcode() == X86::MOV32r0 &&
3606 Instr.registerDefIsDead(X86::EFLAGS, TRI)) {
3607 Movr0Inst = &Instr;
3608 continue;
3609 }
3610
3611 // We can't remove CmpInstr.
3612 return false;
3613 }
3614 }
3615
3616 // Return false if no candidates exist.
3617 if (!IsCmpZero && !Sub)
3618 return false;
3619
3620 bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
3621 Sub->getOperand(2).getReg() == SrcReg);
3622
3623 // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
3624 // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
3625 // If we are done with the basic block, we need to check whether EFLAGS is
3626 // live-out.
3627 bool IsSafe = false;
3628 SmallVector<std::pair<MachineInstr*, X86::CondCode>, 4> OpsToUpdate;
3629 MachineBasicBlock::iterator E = CmpInstr.getParent()->end();
3630 for (++I; I != E; ++I) {
3631 const MachineInstr &Instr = *I;
3632 bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
3633 bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
3634 // We should check the usage if this instruction uses and updates EFLAGS.
3635 if (!UseEFLAGS && ModifyEFLAGS) {
3636 // It is safe to remove CmpInstr if EFLAGS is updated again.
3637 IsSafe = true;
3638 break;
3639 }
3640 if (!UseEFLAGS && !ModifyEFLAGS)
3641 continue;
3642
3643 // EFLAGS is used by this instruction.
3644 X86::CondCode OldCC = X86::COND_INVALID;
3645 if (IsCmpZero || IsSwapped) {
3646 // We decode the condition code from opcode.
3647 if (Instr.isBranch())
3648 OldCC = X86::getCondFromBranch(Instr);
3649 else {
3650 OldCC = X86::getCondFromSETCC(Instr);
3651 if (OldCC == X86::COND_INVALID)
3652 OldCC = X86::getCondFromCMov(Instr);
3653 }
3654 if (OldCC == X86::COND_INVALID) return false;
3655 }
3656 X86::CondCode ReplacementCC = X86::COND_INVALID;
3657 if (IsCmpZero) {
3658 switch (OldCC) {
3659 default: break;
3660 case X86::COND_A: case X86::COND_AE:
3661 case X86::COND_B: case X86::COND_BE:
3662 case X86::COND_G: case X86::COND_GE:
3663 case X86::COND_L: case X86::COND_LE:
3664 case X86::COND_O: case X86::COND_NO:
3665 // CF and OF are used, we can't perform this optimization.
3666 return false;
3667 case X86::COND_S: case X86::COND_NS:
3668 // If SF is used, but the instruction doesn't update the SF, then we
3669 // can't do the optimization.
3670 if (NoSignFlag)
3671 return false;
3672 break;
3673 }
3674
3675 // If we're updating the condition code check if we have to reverse the
3676 // condition.
3677 if (ShouldUpdateCC)
3678 switch (OldCC) {
3679 default:
3680 return false;
3681 case X86::COND_E:
3682 ReplacementCC = NewCC;
3683 break;
3684 case X86::COND_NE:
3685 ReplacementCC = GetOppositeBranchCondition(NewCC);
3686 break;
3687 }
3688 } else if (IsSwapped) {
3689 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
3690 // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
3691 // We swap the condition code and synthesize the new opcode.
3692 ReplacementCC = getSwappedCondition(OldCC);
3693 if (ReplacementCC == X86::COND_INVALID) return false;
3694 }
3695
3696 if ((ShouldUpdateCC || IsSwapped) && ReplacementCC != OldCC) {
3697 // Push the MachineInstr to OpsToUpdate.
3698 // If it is safe to remove CmpInstr, the condition code of these
3699 // instructions will be modified.
3700 OpsToUpdate.push_back(std::make_pair(&*I, ReplacementCC));
3701 }
3702 if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
3703 // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
3704 IsSafe = true;
3705 break;
3706 }
3707 }
3708
3709 // If EFLAGS is not killed nor re-defined, we should check whether it is
3710 // live-out. If it is live-out, do not optimize.
3711 if ((IsCmpZero || IsSwapped) && !IsSafe) {
3712 MachineBasicBlock *MBB = CmpInstr.getParent();
3713 for (MachineBasicBlock *Successor : MBB->successors())
3714 if (Successor->isLiveIn(X86::EFLAGS))
3715 return false;
3716 }
3717
3718 // The instruction to be updated is either Sub or MI.
3719 Sub = IsCmpZero ? MI : Sub;
3720 // Move Movr0Inst to the appropriate place before Sub.
3721 if (Movr0Inst) {
3722 // Look backwards until we find a def that doesn't use the current EFLAGS.
3723 Def = Sub;
3724 MachineBasicBlock::reverse_iterator InsertI = Def.getReverse(),
3725 InsertE = Sub->getParent()->rend();
3726 for (; InsertI != InsertE; ++InsertI) {
3727 MachineInstr *Instr = &*InsertI;
3728 if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
3729 Instr->modifiesRegister(X86::EFLAGS, TRI)) {
3730 Sub->getParent()->remove(Movr0Inst);
3731 Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
3732 Movr0Inst);
3733 break;
3734 }
3735 }
3736 if (InsertI == InsertE)
3737 return false;
3738 }
3739
3740 // Make sure Sub instruction defines EFLAGS and mark the def live.
3741 MachineOperand *FlagDef = Sub->findRegisterDefOperand(X86::EFLAGS);
3742 assert(FlagDef && "Unable to locate a def EFLAGS operand");
3743 FlagDef->setIsDead(false);
3744
3745 CmpInstr.eraseFromParent();
3746
3747 // Modify the condition code of instructions in OpsToUpdate.
3748 for (auto &Op : OpsToUpdate) {
3749 Op.first->getOperand(Op.first->getDesc().getNumOperands() - 1)
3750 .setImm(Op.second);
3751 }
3752 return true;
3753 }
3754
3755 /// Try to remove the load by folding it to a register
3756 /// operand at the use. We fold the load instructions if load defines a virtual
3757 /// register, the virtual register is used once in the same BB, and the
3758 /// instructions in-between do not load or store, and have no side effects.
3759 MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr &MI,
3760 const MachineRegisterInfo *MRI,
3761 unsigned &FoldAsLoadDefReg,
3762 MachineInstr *&DefMI) const {
3763 // Check whether we can move DefMI here.
3764 DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
3765 assert(DefMI);
3766 bool SawStore = false;
3767 if (!DefMI->isSafeToMove(nullptr, SawStore))
3768 return nullptr;
3769
3770 // Collect information about virtual register operands of MI.
3771 SmallVector<unsigned, 1> SrcOperandIds;
3772 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
3773 MachineOperand &MO = MI.getOperand(i);
3774 if (!MO.isReg())
3775 continue;
3776 Register Reg = MO.getReg();
3777 if (Reg != FoldAsLoadDefReg)
3778 continue;
3779 // Do not fold if we have a subreg use or a def.
3780 if (MO.getSubReg() || MO.isDef())
3781 return nullptr;
3782 SrcOperandIds.push_back(i);
3783 }
3784 if (SrcOperandIds.empty())
3785 return nullptr;
3786
3787 // Check whether we can fold the def into SrcOperandId.
3788 if (MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandIds, *DefMI)) {
3789 FoldAsLoadDefReg = 0;
3790 return FoldMI;
3791 }
3792
3793 return nullptr;
3794 }
3795
3796 /// Expand a single-def pseudo instruction to a two-addr
3797 /// instruction with two undef reads of the register being defined.
3798 /// This is used for mapping:
3799 /// %xmm4 = V_SET0
3800 /// to:
3801 /// %xmm4 = PXORrr undef %xmm4, undef %xmm4
3802 ///
3803 static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
3804 const MCInstrDesc &Desc) {
3805 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
3806 Register Reg = MIB->getOperand(0).getReg();
3807 MIB->setDesc(Desc);
3808
3809 // MachineInstr::addOperand() will insert explicit operands before any
3810 // implicit operands.
3811 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
3812 // But we don't trust that.
3813 assert(MIB->getOperand(1).getReg() == Reg &&
3814 MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
3815 return true;
3816 }
3817
3818 /// Expand a single-def pseudo instruction to a two-addr
3819 /// instruction with two %k0 reads.
3820 /// This is used for mapping:
3821 /// %k4 = K_SET1
3822 /// to:
3823 /// %k4 = KXNORrr %k0, %k0
3824 static bool Expand2AddrKreg(MachineInstrBuilder &MIB,
3825 const MCInstrDesc &Desc, unsigned Reg) {
3826 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
3827 MIB->setDesc(Desc);
3828 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
3829 return true;
3830 }
3831
3832 static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
3833 bool MinusOne) {
3834 MachineBasicBlock &MBB = *MIB->getParent();
3835 DebugLoc DL = MIB->getDebugLoc();
3836 Register Reg = MIB->getOperand(0).getReg();
3837
3838 // Insert the XOR.
3839 BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
3840 .addReg(Reg, RegState::Undef)
3841 .addReg(Reg, RegState::Undef);
3842
3843 // Turn the pseudo into an INC or DEC.
3844 MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
3845 MIB.addReg(Reg);
3846
3847 return true;
3848 }
3849
3850 static bool ExpandMOVImmSExti8(MachineInstrBuilder &MIB,
3851 const TargetInstrInfo &TII,
3852 const X86Subtarget &Subtarget) {
3853 MachineBasicBlock &MBB = *MIB->getParent();
3854 DebugLoc DL = MIB->getDebugLoc();
3855 int64_t Imm = MIB->getOperand(1).getImm();
3856 assert(Imm != 0 && "Using push/pop for 0 is not efficient.");
3857 MachineBasicBlock::iterator I = MIB.getInstr();
3858
3859 int StackAdjustment;
3860
3861 if (Subtarget.is64Bit()) {
3862 assert(MIB->getOpcode() == X86::MOV64ImmSExti8 ||
3863 MIB->getOpcode() == X86::MOV32ImmSExti8);
3864
3865 // Can't use push/pop lowering if the function might write to the red zone.
3866 X86MachineFunctionInfo *X86FI =
3867 MBB.getParent()->getInfo<X86MachineFunctionInfo>();
3868 if (X86FI->getUsesRedZone()) {
3869 MIB->setDesc(TII.get(MIB->getOpcode() ==
3870 X86::MOV32ImmSExti8 ? X86::MOV32ri : X86::MOV64ri));
3871 return true;
3872 }
3873
3874 // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and
3875 // widen the register if necessary.
3876 StackAdjustment = 8;
3877 BuildMI(MBB, I, DL, TII.get(X86::PUSH64i8)).addImm(Imm);
3878 MIB->setDesc(TII.get(X86::POP64r));
3879 MIB->getOperand(0)
3880 .setReg(getX86SubSuperRegister(MIB->getOperand(0).getReg(), 64));
3881 } else {
3882 assert(MIB->getOpcode() == X86::MOV32ImmSExti8);
3883 StackAdjustment = 4;
3884 BuildMI(MBB, I, DL, TII.get(X86::PUSH32i8)).addImm(Imm);
3885 MIB->setDesc(TII.get(X86::POP32r));
3886 }
3887
3888 // Build CFI if necessary.
3889 MachineFunction &MF = *MBB.getParent();
3890 const X86FrameLowering *TFL = Subtarget.getFrameLowering();
3891 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
3892 bool NeedsDwarfCFI =
3893 !IsWin64Prologue &&
3894 (MF.getMMI().hasDebugInfo() || MF.getFunction().needsUnwindTableEntry());
3895 bool EmitCFI = !TFL->hasFP(MF) && NeedsDwarfCFI;
3896 if (EmitCFI) {
3897 TFL->BuildCFI(MBB, I, DL,
3898 MCCFIInstruction::createAdjustCfaOffset(nullptr, StackAdjustment));
3899 TFL->BuildCFI(MBB, std::next(I), DL,
3900 MCCFIInstruction::createAdjustCfaOffset(nullptr, -StackAdjustment));
3901 }
3902
3903 return true;
3904 }
3905
3906 // LoadStackGuard has so far only been implemented for 64-bit MachO. Different
3907 // code sequence is needed for other targets.
3908 static void expandLoadStackGuard(MachineInstrBuilder &MIB,
3909 const TargetInstrInfo &TII) {
3910 MachineBasicBlock &MBB = *MIB->getParent();
3911 DebugLoc DL = MIB->getDebugLoc();
3912 Register Reg = MIB->getOperand(0).getReg();
3913 const GlobalValue *GV =
3914 cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
3915 auto Flags = MachineMemOperand::MOLoad |
3916 MachineMemOperand::MODereferenceable |
3917 MachineMemOperand::MOInvariant;
3918 MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
3919 MachinePointerInfo::getGOT(*MBB.getParent()), Flags, 8, 8);
3920 MachineBasicBlock::iterator I = MIB.getInstr();
3921
3922 BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
3923 .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
3924 .addMemOperand(MMO);
3925 MIB->setDebugLoc(DL);
3926 MIB->setDesc(TII.get(X86::MOV64rm));
3927 MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
3928 }
3929
3930 static bool expandXorFP(MachineInstrBuilder &MIB, const TargetInstrInfo &TII) {
3931 MachineBasicBlock &MBB = *MIB->getParent();
3932 MachineFunction &MF = *MBB.getParent();
3933 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
3934 const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
3935 unsigned XorOp =
3936 MIB->getOpcode() == X86::XOR64_FP ? X86::XOR64rr : X86::XOR32rr;
3937 MIB->setDesc(TII.get(XorOp));
3938 MIB.addReg(TRI->getFrameRegister(MF), RegState::Undef);
3939 return true;
3940 }
3941
3942 // This is used to handle spills for 128/256-bit registers when we have AVX512,
3943 // but not VLX. If it uses an extended register we need to use an instruction
3944 // that loads the lower 128/256-bit, but is available with only AVX512F.
3945 static bool expandNOVLXLoad(MachineInstrBuilder &MIB,
3946 const TargetRegisterInfo *TRI,
3947 const MCInstrDesc &LoadDesc,
3948 const MCInstrDesc &BroadcastDesc,
3949 unsigned SubIdx) {
3950 Register DestReg = MIB->getOperand(0).getReg();
3951 // Check if DestReg is XMM16-31 or YMM16-31.
3952 if (TRI->getEncodingValue(DestReg) < 16) {
3953 // We can use a normal VEX encoded load.
3954 MIB->setDesc(LoadDesc);
3955 } else {
3956 // Use a 128/256-bit VBROADCAST instruction.
3957 MIB->setDesc(BroadcastDesc);
3958 // Change the destination to a 512-bit register.
3959 DestReg = TRI->getMatchingSuperReg(DestReg, SubIdx, &X86::VR512RegClass);
3960 MIB->getOperand(0).setReg(DestReg);
3961 }
3962 return true;
3963 }
3964
3965 // This is used to handle spills for 128/256-bit registers when we have AVX512,
3966 // but not VLX. If it uses an extended register we need to use an instruction
3967 // that stores the lower 128/256-bit, but is available with only AVX512F.
3968 static bool expandNOVLXStore(MachineInstrBuilder &MIB,
3969 const TargetRegisterInfo *TRI,
3970 const MCInstrDesc &StoreDesc,
3971 const MCInstrDesc &ExtractDesc,
3972 unsigned SubIdx) {
3973 Register SrcReg = MIB->getOperand(X86::AddrNumOperands).getReg();
3974 // Check if DestReg is XMM16-31 or YMM16-31.
3975 if (TRI->getEncodingValue(SrcReg) < 16) {
3976 // We can use a normal VEX encoded store.
3977 MIB->setDesc(StoreDesc);
3978 } else {
3979 // Use a VEXTRACTF instruction.
3980 MIB->setDesc(ExtractDesc);
3981 // Change the destination to a 512-bit register.
3982 SrcReg = TRI->getMatchingSuperReg(SrcReg, SubIdx, &X86::VR512RegClass);
3983 MIB->getOperand(X86::AddrNumOperands).setReg(SrcReg);
3984 MIB.addImm(0x0); // Append immediate to extract from the lower bits.
3985 }
3986
3987 return true;
3988 }
3989
3990 static bool expandSHXDROT(MachineInstrBuilder &MIB, const MCInstrDesc &Desc) {
3991 MIB->setDesc(Desc);
3992 int64_t ShiftAmt = MIB->getOperand(2).getImm();
3993 // Temporarily remove the immediate so we can add another source register.
3994 MIB->RemoveOperand(2);
3995 // Add the register. Don't copy the kill flag if there is one.
3996 MIB.addReg(MIB->getOperand(1).getReg(),
3997 getUndefRegState(MIB->getOperand(1).isUndef()));
3998 // Add back the immediate.
3999 MIB.addImm(ShiftAmt);
4000 return true;
4001 }
4002
4003 bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
4004 bool HasAVX = Subtarget.hasAVX();
4005 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
4006 switch (MI.getOpcode()) {
4007 case X86::MOV32r0:
4008 return Expand2AddrUndef(MIB, get(X86::XOR32rr));
4009 case X86::MOV32r1:
4010 return expandMOV32r1(MIB, *this, /*MinusOne=*/ false);
4011 case X86::MOV32r_1:
4012 return expandMOV32r1(MIB, *this, /*MinusOne=*/ true);
4013 case X86::MOV32ImmSExti8:
4014 case X86::MOV64ImmSExti8:
4015 return ExpandMOVImmSExti8(MIB, *this, Subtarget);
4016 case X86::SETB_C8r:
4017 return Expand2AddrUndef(MIB, get(X86::SBB8rr));
4018 case X86::SETB_C16r:
4019 return Expand2AddrUndef(MIB, get(X86::SBB16rr));
4020 case X86::SETB_C32r:
4021 return Expand2AddrUndef(MIB, get(X86::SBB32rr));
4022 case X86::SETB_C64r:
4023 return Expand2AddrUndef(MIB, get(X86::SBB64rr));
4024 case X86::MMX_SET0:
4025 return Expand2AddrUndef(MIB, get(X86::MMX_PXORirr));
4026 case X86::V_SET0:
4027 case X86::FsFLD0SS:
4028 case X86::FsFLD0SD:
4029 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
4030 case X86::AVX_SET0: {
4031 assert(HasAVX && "AVX not supported");
4032 const TargetRegisterInfo *TRI = &getRegisterInfo();
4033 Register SrcReg = MIB->getOperand(0).getReg();
4034 Register XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
4035 MIB->getOperand(0).setReg(XReg);
4036 Expand2AddrUndef(MIB, get(X86::VXORPSrr));
4037 MIB.addReg(SrcReg, RegState::ImplicitDefine);
4038 return true;
4039 }
4040 case X86::AVX512_128_SET0:
4041 case X86::AVX512_FsFLD0SS:
4042 case X86::AVX512_FsFLD0SD: {
4043 bool HasVLX = Subtarget.hasVLX();
4044 Register SrcReg = MIB->getOperand(0).getReg();
4045 const TargetRegisterInfo *TRI = &getRegisterInfo();
4046 if (HasVLX || TRI->getEncodingValue(SrcReg) < 16)
4047 return Expand2AddrUndef(MIB,
4048 get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
4049 // Extended register without VLX. Use a larger XOR.
4050 SrcReg =
4051 TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm, &X86::VR512RegClass);
4052 MIB->getOperand(0).setReg(SrcReg);
4053 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4054 }
4055 case X86::AVX512_256_SET0:
4056 case X86::AVX512_512_SET0: {
4057 bool HasVLX = Subtarget.hasVLX();
4058 Register SrcReg = MIB->getOperand(0).getReg();
4059 const TargetRegisterInfo *TRI = &getRegisterInfo();
4060 if (HasVLX || TRI->getEncodingValue(SrcReg) < 16) {
4061 Register XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
4062 MIB->getOperand(0).setReg(XReg);
4063 Expand2AddrUndef(MIB,
4064 get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
4065 MIB.addReg(SrcReg, RegState::ImplicitDefine);
4066 return true;
4067 }
4068 if (MI.getOpcode() == X86::AVX512_256_SET0) {
4069 // No VLX so we must reference a zmm.
4070 unsigned ZReg =
4071 TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm, &X86::VR512RegClass);
4072 MIB->getOperand(0).setReg(ZReg);
4073 }
4074 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4075 }
4076 case X86::V_SETALLONES:
4077 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
4078 case X86::AVX2_SETALLONES:
4079 return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
4080 case X86::AVX1_SETALLONES: {
4081 Register Reg = MIB->getOperand(0).getReg();
4082 // VCMPPSYrri with an immediate 0xf should produce VCMPTRUEPS.
4083 MIB->setDesc(get(X86::VCMPPSYrri));
4084 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xf);
4085 return true;
4086 }
4087 case X86::AVX512_512_SETALLONES: {
4088 Register Reg = MIB->getOperand(0).getReg();
4089 MIB->setDesc(get(X86::VPTERNLOGDZrri));
4090 // VPTERNLOGD needs 3 register inputs and an immediate.
4091 // 0xff will return 1s for any input.
4092 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef)
4093 .addReg(Reg, RegState::Undef).addImm(0xff);
4094 return true;
4095 }
4096 case X86::AVX512_512_SEXT_MASK_32:
4097 case X86::AVX512_512_SEXT_MASK_64: {
4098 Register Reg = MIB->getOperand(0).getReg();
4099 Register MaskReg = MIB->getOperand(1).getReg();
4100 unsigned MaskState = getRegState(MIB->getOperand(1));
4101 unsigned Opc = (MI.getOpcode() == X86::AVX512_512_SEXT_MASK_64) ?
4102 X86::VPTERNLOGQZrrikz : X86::VPTERNLOGDZrrikz;
4103 MI.RemoveOperand(1);
4104 MIB->setDesc(get(Opc));
4105 // VPTERNLOG needs 3 register inputs and an immediate.
4106 // 0xff will return 1s for any input.
4107 MIB.addReg(Reg, RegState::Undef).addReg(MaskReg, MaskState)
4108 .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xff);
4109 return true;
4110 }
4111 case X86::VMOVAPSZ128rm_NOVLX:
4112 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSrm),
4113 get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
4114 case X86::VMOVUPSZ128rm_NOVLX:
4115 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSrm),
4116 get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
4117 case X86::VMOVAPSZ256rm_NOVLX:
4118 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSYrm),
4119 get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
4120 case X86::VMOVUPSZ256rm_NOVLX:
4121 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSYrm),
4122 get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
4123 case X86::VMOVAPSZ128mr_NOVLX:
4124 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSmr),
4125 get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
4126 case X86::VMOVUPSZ128mr_NOVLX:
4127 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSmr),
4128 get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
4129 case X86::VMOVAPSZ256mr_NOVLX:
4130 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSYmr),
4131 get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
4132 case X86::VMOVUPSZ256mr_NOVLX:
4133 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSYmr),
4134 get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
4135 case X86::MOV32ri64: {
4136 Register Reg = MIB->getOperand(0).getReg();
4137 Register Reg32 = RI.getSubReg(Reg, X86::sub_32bit);
4138 MI.setDesc(get(X86::MOV32ri));
4139 MIB->getOperand(0).setReg(Reg32);
4140 MIB.addReg(Reg, RegState::ImplicitDefine);
4141 return true;
4142 }
4143
4144 // KNL does not recognize dependency-breaking idioms for mask registers,
4145 // so kxnor %k1, %k1, %k2 has a RAW dependence on %k1.
4146 // Using %k0 as the undef input register is a performance heuristic based
4147 // on the assumption that %k0 is used less frequently than the other mask
4148 // registers, since it is not usable as a write mask.
4149 // FIXME: A more advanced approach would be to choose the best input mask
4150 // register based on context.
4151 case X86::KSET0W: return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0);
4152 case X86::KSET0D: return Expand2AddrKreg(MIB, get(X86::KXORDrr), X86::K0);
4153 case X86::KSET0Q: return Expand2AddrKreg(MIB, get(X86::KXORQrr), X86::K0);
4154 case X86::KSET1W: return Expand2AddrKreg(MIB, get(X86::KXNORWrr), X86::K0);
4155 case X86::KSET1D: return Expand2AddrKreg(MIB, get(X86::KXNORDrr), X86::K0);
4156 case X86::KSET1Q: return Expand2AddrKreg(MIB, get(X86::KXNORQrr), X86::K0);
4157 case TargetOpcode::LOAD_STACK_GUARD:
4158 expandLoadStackGuard(MIB, *this);
4159 return true;
4160 case X86::XOR64_FP:
4161 case X86::XOR32_FP:
4162 return expandXorFP(MIB, *this);
4163 case X86::SHLDROT32ri: return expandSHXDROT(MIB, get(X86::SHLD32rri8));
4164 case X86::SHLDROT64ri: return expandSHXDROT(MIB, get(X86::SHLD64rri8));
4165 case X86::SHRDROT32ri: return expandSHXDROT(MIB, get(X86::SHRD32rri8));
4166 case X86::SHRDROT64ri: return expandSHXDROT(MIB, get(X86::SHRD64rri8));
4167 case X86::ADD8rr_DB: MIB->setDesc(get(X86::OR8rr)); break;
4168 case X86::ADD16rr_DB: MIB->setDesc(get(X86::OR16rr)); break;
4169 case X86::ADD32rr_DB: MIB->setDesc(get(X86::OR32rr)); break;
4170 case X86::ADD64rr_DB: MIB->setDesc(get(X86::OR64rr)); break;
4171 case X86::ADD8ri_DB: MIB->setDesc(get(X86::OR8ri)); break;
4172 case X86::ADD16ri_DB: MIB->setDesc(get(X86::OR16ri)); break;
4173 case X86::ADD32ri_DB: MIB->setDesc(get(X86::OR32ri)); break;
4174 case X86::ADD64ri32_DB: MIB->setDesc(get(X86::OR64ri32)); break;
4175 case X86::ADD16ri8_DB: MIB->setDesc(get(X86::OR16ri8)); break;
4176 case X86::ADD32ri8_DB: MIB->setDesc(get(X86::OR32ri8)); break;
4177 case X86::ADD64ri8_DB: MIB->setDesc(get(X86::OR64ri8)); break;
4178 }
4179 return false;
4180 }
4181
4182 /// Return true for all instructions that only update
4183 /// the first 32 or 64-bits of the destination register and leave the rest
4184 /// unmodified. This can be used to avoid folding loads if the instructions
4185 /// only update part of the destination register, and the non-updated part is
4186 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
4187 /// instructions breaks the partial register dependency and it can improve
4188 /// performance. e.g.:
4189 ///
4190 /// movss (%rdi), %xmm0
4191 /// cvtss2sd %xmm0, %xmm0
4192 ///
4193 /// Instead of
4194 /// cvtss2sd (%rdi), %xmm0
4195 ///
4196 /// FIXME: This should be turned into a TSFlags.
4197 ///
4198 static bool hasPartialRegUpdate(unsigned Opcode,
4199 const X86Subtarget &Subtarget,
4200 bool ForLoadFold = false) {
4201 switch (Opcode) {
4202 case X86::CVTSI2SSrr:
4203 case X86::CVTSI2SSrm:
4204 case X86::CVTSI642SSrr:
4205 case X86::CVTSI642SSrm:
4206 case X86::CVTSI2SDrr:
4207 case X86::CVTSI2SDrm:
4208 case X86::CVTSI642SDrr:
4209 case X86::CVTSI642SDrm:
4210 // Load folding won't effect the undef register update since the input is
4211 // a GPR.
4212 return !ForLoadFold;
4213 case X86::CVTSD2SSrr:
4214 case X86::CVTSD2SSrm:
4215 case X86::CVTSS2SDrr:
4216 case X86::CVTSS2SDrm:
4217 case X86::MOVHPDrm:
4218 case X86::MOVHPSrm:
4219 case X86::MOVLPDrm:
4220 case X86::MOVLPSrm:
4221 case X86::RCPSSr:
4222 case X86::RCPSSm:
4223 case X86::RCPSSr_Int:
4224 case X86::RCPSSm_Int:
4225 case X86::ROUNDSDr:
4226 case X86::ROUNDSDm:
4227 case X86::ROUNDSSr:
4228 case X86::ROUNDSSm:
4229 case X86::RSQRTSSr:
4230 case X86::RSQRTSSm:
4231 case X86::RSQRTSSr_Int:
4232 case X86::RSQRTSSm_Int:
4233 case X86::SQRTSSr:
4234 case X86::SQRTSSm:
4235 case X86::SQRTSSr_Int:
4236 case X86::SQRTSSm_Int:
4237 case X86::SQRTSDr:
4238 case X86::SQRTSDm:
4239 case X86::SQRTSDr_Int:
4240 case X86::SQRTSDm_Int:
4241 return true;
4242 // GPR
4243 case X86::POPCNT32rm:
4244 case X86::POPCNT32rr:
4245 case X86::POPCNT64rm:
4246 case X86::POPCNT64rr:
4247 return Subtarget.hasPOPCNTFalseDeps();
4248 case X86::LZCNT32rm:
4249 case X86::LZCNT32rr:
4250 case X86::LZCNT64rm:
4251 case X86::LZCNT64rr:
4252 case X86::TZCNT32rm:
4253 case X86::TZCNT32rr:
4254 case X86::TZCNT64rm:
4255 case X86::TZCNT64rr:
4256 return Subtarget.hasLZCNTFalseDeps();
4257 }
4258
4259 return false;
4260 }
4261
4262 /// Inform the BreakFalseDeps pass how many idle
4263 /// instructions we would like before a partial register update.
4264 unsigned X86InstrInfo::getPartialRegUpdateClearance(
4265 const MachineInstr &MI, unsigned OpNum,
4266 const TargetRegisterInfo *TRI) const {
4267 if (OpNum != 0 || !hasPartialRegUpdate(MI.getOpcode(), Subtarget))
4268 return 0;
4269
4270 // If MI is marked as reading Reg, the partial register update is wanted.
4271 const MachineOperand &MO = MI.getOperand(0);
4272 Register Reg = MO.getReg();
4273 if (Register::isVirtualRegister(Reg)) {
4274 if (MO.readsReg() || MI.readsVirtualRegister(Reg))
4275 return 0;
4276 } else {
4277 if (MI.readsRegister(Reg, TRI))
4278 return 0;
4279 }
4280
4281 // If any instructions in the clearance range are reading Reg, insert a
4282 // dependency breaking instruction, which is inexpensive and is likely to
4283 // be hidden in other instruction's cycles.
4284 return PartialRegUpdateClearance;
4285 }
4286
4287 // Return true for any instruction the copies the high bits of the first source
4288 // operand into the unused high bits of the destination operand.
4289 static bool hasUndefRegUpdate(unsigned Opcode, bool ForLoadFold = false) {
4290 switch (Opcode) {
4291 case X86::VCVTSI2SSrr:
4292 case X86::VCVTSI2SSrm:
4293 case X86::VCVTSI2SSrr_Int:
4294 case X86::VCVTSI2SSrm_Int:
4295 case X86::VCVTSI642SSrr:
4296 case X86::VCVTSI642SSrm:
4297 case X86::VCVTSI642SSrr_Int:
4298 case X86::VCVTSI642SSrm_Int:
4299 case X86::VCVTSI2SDrr:
4300 case X86::VCVTSI2SDrm:
4301 case X86::VCVTSI2SDrr_Int:
4302 case X86::VCVTSI2SDrm_Int:
4303 case X86::VCVTSI642SDrr:
4304 case X86::VCVTSI642SDrm:
4305 case X86::VCVTSI642SDrr_Int:
4306 case X86::VCVTSI642SDrm_Int:
4307 // AVX-512
4308 case X86::VCVTSI2SSZrr:
4309 case X86::VCVTSI2SSZrm:
4310 case X86::VCVTSI2SSZrr_Int:
4311 case X86::VCVTSI2SSZrrb_Int:
4312 case X86::VCVTSI2SSZrm_Int:
4313 case X86::VCVTSI642SSZrr:
4314 case X86::VCVTSI642SSZrm:
4315 case X86::VCVTSI642SSZrr_Int:
4316 case X86::VCVTSI642SSZrrb_Int:
4317 case X86::VCVTSI642SSZrm_Int:
4318 case X86::VCVTSI2SDZrr:
4319 case X86::VCVTSI2SDZrm:
4320 case X86::VCVTSI2SDZrr_Int:
4321 case X86::VCVTSI2SDZrm_Int:
4322 case X86::VCVTSI642SDZrr:
4323 case X86::VCVTSI642SDZrm:
4324 case X86::VCVTSI642SDZrr_Int:
4325 case X86::VCVTSI642SDZrrb_Int:
4326 case X86::VCVTSI642SDZrm_Int:
4327 case X86::VCVTUSI2SSZrr:
4328 case X86::VCVTUSI2SSZrm:
4329 case X86::VCVTUSI2SSZrr_Int:
4330 case X86::VCVTUSI2SSZrrb_Int:
4331 case X86::VCVTUSI2SSZrm_Int:
4332 case X86::VCVTUSI642SSZrr:
4333 case X86::VCVTUSI642SSZrm:
4334 case X86::VCVTUSI642SSZrr_Int:
4335 case X86::VCVTUSI642SSZrrb_Int:
4336 case X86::VCVTUSI642SSZrm_Int:
4337 case X86::VCVTUSI2SDZrr:
4338 case X86::VCVTUSI2SDZrm:
4339 case X86::VCVTUSI2SDZrr_Int:
4340 case X86::VCVTUSI2SDZrm_Int:
4341 case X86::VCVTUSI642SDZrr:
4342 case X86::VCVTUSI642SDZrm:
4343 case X86::VCVTUSI642SDZrr_Int:
4344 case X86::VCVTUSI642SDZrrb_Int:
4345 case X86::VCVTUSI642SDZrm_Int:
4346 // Load folding won't effect the undef register update since the input is
4347 // a GPR.
4348 return !ForLoadFold;
4349 case X86::VCVTSD2SSrr:
4350 case X86::VCVTSD2SSrm:
4351 case X86::VCVTSD2SSrr_Int:
4352 case X86::VCVTSD2SSrm_Int:
4353 case X86::VCVTSS2SDrr:
4354 case X86::VCVTSS2SDrm:
4355 case X86::VCVTSS2SDrr_Int:
4356 case X86::VCVTSS2SDrm_Int:
4357 case X86::VRCPSSr:
4358 case X86::VRCPSSr_Int:
4359 case X86::VRCPSSm:
4360 case X86::VRCPSSm_Int:
4361 case X86::VROUNDSDr:
4362 case X86::VROUNDSDm:
4363 case X86::VROUNDSDr_Int:
4364 case X86::VROUNDSDm_Int:
4365 case X86::VROUNDSSr:
4366 case X86::VROUNDSSm:
4367 case X86::VROUNDSSr_Int:
4368 case X86::VROUNDSSm_Int:
4369 case X86::VRSQRTSSr:
4370 case X86::VRSQRTSSr_Int:
4371 case X86::VRSQRTSSm:
4372 case X86::VRSQRTSSm_Int:
4373 case X86::VSQRTSSr:
4374 case X86::VSQRTSSr_Int:
4375 case X86::VSQRTSSm:
4376 case X86::VSQRTSSm_Int:
4377 case X86::VSQRTSDr:
4378 case X86::VSQRTSDr_Int:
4379 case X86::VSQRTSDm:
4380 case X86::VSQRTSDm_Int:
4381 // AVX-512
4382 case X86::VCVTSD2SSZrr:
4383 case X86::VCVTSD2SSZrr_Int:
4384 case X86::VCVTSD2SSZrrb_Int:
4385 case X86::VCVTSD2SSZrm:
4386 case X86::VCVTSD2SSZrm_Int:
4387 case X86::VCVTSS2SDZrr:
4388 case X86::VCVTSS2SDZrr_Int:
4389 case X86::VCVTSS2SDZrrb_Int:
4390 case X86::VCVTSS2SDZrm:
4391 case X86::VCVTSS2SDZrm_Int:
4392 case X86::VGETEXPSDZr:
4393 case X86::VGETEXPSDZrb:
4394 case X86::VGETEXPSDZm:
4395 case X86::VGETEXPSSZr:
4396 case X86::VGETEXPSSZrb:
4397 case X86::VGETEXPSSZm:
4398 case X86::VGETMANTSDZrri:
4399 case X86::VGETMANTSDZrrib:
4400 case X86::VGETMANTSDZrmi:
4401 case X86::VGETMANTSSZrri:
4402 case X86::VGETMANTSSZrrib:
4403 case X86::VGETMANTSSZrmi:
4404 case X86::VRNDSCALESDZr:
4405 case X86::VRNDSCALESDZr_Int:
4406 case X86::VRNDSCALESDZrb_Int:
4407 case X86::VRNDSCALESDZm:
4408 case X86::VRNDSCALESDZm_Int:
4409 case X86::VRNDSCALESSZr:
4410 case X86::VRNDSCALESSZr_Int:
4411 case X86::VRNDSCALESSZrb_Int:
4412 case X86::VRNDSCALESSZm:
4413 case X86::VRNDSCALESSZm_Int:
4414 case X86::VRCP14SDZrr:
4415 case X86::VRCP14SDZrm:
4416 case X86::VRCP14SSZrr:
4417 case X86::VRCP14SSZrm:
4418 case X86::VRCP28SDZr:
4419 case X86::VRCP28SDZrb:
4420 case X86::VRCP28SDZm:
4421 case X86::VRCP28SSZr:
4422 case X86::VRCP28SSZrb:
4423 case X86::VRCP28SSZm:
4424 case X86::VREDUCESSZrmi:
4425 case X86::VREDUCESSZrri:
4426 case X86::VREDUCESSZrrib:
4427 case X86::VRSQRT14SDZrr:
4428 case X86::VRSQRT14SDZrm:
4429 case X86::VRSQRT14SSZrr:
4430 case X86::VRSQRT14SSZrm:
4431 case X86::VRSQRT28SDZr:
4432 case X86::VRSQRT28SDZrb:
4433 case X86::VRSQRT28SDZm:
4434 case X86::VRSQRT28SSZr:
4435 case X86::VRSQRT28SSZrb:
4436 case X86::VRSQRT28SSZm:
4437 case X86::VSQRTSSZr:
4438 case X86::VSQRTSSZr_Int:
4439 case X86::VSQRTSSZrb_Int:
4440 case X86::VSQRTSSZm:
4441 case X86::VSQRTSSZm_Int:
4442 case X86::VSQRTSDZr:
4443 case X86::VSQRTSDZr_Int:
4444 case X86::VSQRTSDZrb_Int:
4445 case X86::VSQRTSDZm:
4446 case X86::VSQRTSDZm_Int:
4447 return true;
4448 }
4449
4450 return false;
4451 }
4452
4453 /// Inform the BreakFalseDeps pass how many idle instructions we would like
4454 /// before certain undef register reads.
4455 ///
4456 /// This catches the VCVTSI2SD family of instructions:
4457 ///
4458 /// vcvtsi2sdq %rax, undef %xmm0, %xmm14
4459 ///
4460 /// We should to be careful *not* to catch VXOR idioms which are presumably
4461 /// handled specially in the pipeline:
4462 ///
4463 /// vxorps undef %xmm1, undef %xmm1, %xmm1
4464 ///
4465 /// Like getPartialRegUpdateClearance, this makes a strong assumption that the
4466 /// high bits that are passed-through are not live.
4467 unsigned
4468 X86InstrInfo::getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
4469 const TargetRegisterInfo *TRI) const {
4470 if (!hasUndefRegUpdate(MI.getOpcode()))
4471 return 0;
4472
4473 // Set the OpNum parameter to the first source operand.
4474 OpNum = 1;
4475
4476 const MachineOperand &MO = MI.getOperand(OpNum);
4477 if (MO.isUndef() && Register::isPhysicalRegister(MO.getReg())) {
4478 return UndefRegClearance;
4479 }
4480 return 0;
4481 }
4482
4483 void X86InstrInfo::breakPartialRegDependency(
4484 MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const {
4485 Register Reg = MI.getOperand(OpNum).getReg();
4486 // If MI kills this register, the false dependence is already broken.
4487 if (MI.killsRegister(Reg, TRI))
4488 return;
4489
4490 if (X86::VR128RegClass.contains(Reg)) {
4491 // These instructions are all floating point domain, so xorps is the best
4492 // choice.
4493 unsigned Opc = Subtarget.hasAVX() ? X86::VXORPSrr : X86::XORPSrr;
4494 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(Opc), Reg)
4495 .addReg(Reg, RegState::Undef)
4496 .addReg(Reg, RegState::Undef);
4497 MI.addRegisterKilled(Reg, TRI, true);
4498 } else if (X86::VR256RegClass.contains(Reg)) {
4499 // Use vxorps to clear the full ymm register.
4500 // It wants to read and write the xmm sub-register.
4501 Register XReg = TRI->getSubReg(Reg, X86::sub_xmm);
4502 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::VXORPSrr), XReg)
4503 .addReg(XReg, RegState::Undef)
4504 .addReg(XReg, RegState::Undef)
4505 .addReg(Reg, RegState::ImplicitDefine);
4506 MI.addRegisterKilled(Reg, TRI, true);
4507 } else if (X86::GR64RegClass.contains(Reg)) {
4508 // Using XOR32rr because it has shorter encoding and zeros up the upper bits
4509 // as well.
4510 Register XReg = TRI->getSubReg(Reg, X86::sub_32bit);
4511 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), XReg)
4512 .addReg(XReg, RegState::Undef)
4513 .addReg(XReg, RegState::Undef)
4514 .addReg(Reg, RegState::ImplicitDefine);
4515 MI.addRegisterKilled(Reg, TRI, true);
4516 } else if (X86::GR32RegClass.contains(Reg)) {
4517 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), Reg)
4518 .addReg(Reg, RegState::Undef)
4519 .addReg(Reg, RegState::Undef);
4520 MI.addRegisterKilled(Reg, TRI, true);
4521 }
4522 }
4523
4524 static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs,
4525 int PtrOffset = 0) {
4526 unsigned NumAddrOps = MOs.size();
4527
4528 if (NumAddrOps < 4) {
4529 // FrameIndex only - add an immediate offset (whether its zero or not).
4530 for (unsigned i = 0; i != NumAddrOps; ++i)
4531 MIB.add(MOs[i]);
4532 addOffset(MIB, PtrOffset);
4533 } else {
4534 // General Memory Addressing - we need to add any offset to an existing
4535 // offset.
4536 assert(MOs.size() == 5 && "Unexpected memory operand list length");
4537 for (unsigned i = 0; i != NumAddrOps; ++i) {
4538 const MachineOperand &MO = MOs[i];
4539 if (i == 3 && PtrOffset != 0) {
4540 MIB.addDisp(MO, PtrOffset);
4541 } else {
4542 MIB.add(MO);
4543 }
4544 }
4545 }
4546 }
4547
4548 static void updateOperandRegConstraints(MachineFunction &MF,
4549 MachineInstr &NewMI,
4550 const TargetInstrInfo &TII) {
4551 MachineRegisterInfo &MRI = MF.getRegInfo();
4552 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
4553
4554 for (int Idx : llvm::seq<int>(0, NewMI.getNumOperands())) {
4555 MachineOperand &MO = NewMI.getOperand(Idx);
4556 // We only need to update constraints on virtual register operands.
4557 if (!MO.isReg())
4558 continue;
4559 Register Reg = MO.getReg();
4560 if (!Register::isVirtualRegister(Reg))
4561 continue;
4562
4563 auto *NewRC = MRI.constrainRegClass(
4564 Reg, TII.getRegClass(NewMI.getDesc(), Idx, &TRI, MF));
4565 if (!NewRC) {
4566 LLVM_DEBUG(
4567 dbgs() << "WARNING: Unable to update register constraint for operand "
4568 << Idx << " of instruction:\n";
4569 NewMI.dump(); dbgs() << "\n");
4570 }
4571 }
4572 }
4573
4574 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
4575 ArrayRef<MachineOperand> MOs,
4576 MachineBasicBlock::iterator InsertPt,
4577 MachineInstr &MI,
4578 const TargetInstrInfo &TII) {
4579 // Create the base instruction with the memory operand as the first part.
4580 // Omit the implicit operands, something BuildMI can't do.
4581 MachineInstr *NewMI =
4582 MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
4583 MachineInstrBuilder MIB(MF, NewMI);
4584 addOperands(MIB, MOs);
4585
4586 // Loop over the rest of the ri operands, converting them over.
4587 unsigned NumOps = MI.getDesc().getNumOperands() - 2;
4588 for (unsigned i = 0; i != NumOps; ++i) {
4589 MachineOperand &MO = MI.getOperand(i + 2);
4590 MIB.add(MO);
4591 }
4592 for (unsigned i = NumOps + 2, e = MI.getNumOperands(); i != e; ++i) {
4593 MachineOperand &MO = MI.getOperand(i);
4594 MIB.add(MO);
4595 }
4596
4597 updateOperandRegConstraints(MF, *NewMI, TII);
4598
4599 MachineBasicBlock *MBB = InsertPt->getParent();
4600 MBB->insert(InsertPt, NewMI);
4601
4602 return MIB;
4603 }
4604
4605 static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode,
4606 unsigned OpNo, ArrayRef<MachineOperand> MOs,
4607 MachineBasicBlock::iterator InsertPt,
4608 MachineInstr &MI, const TargetInstrInfo &TII,
4609 int PtrOffset = 0) {
4610 // Omit the implicit operands, something BuildMI can't do.
4611 MachineInstr *NewMI =
4612 MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
4613 MachineInstrBuilder MIB(MF, NewMI);
4614
4615 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
4616 MachineOperand &MO = MI.getOperand(i);
4617 if (i == OpNo) {
4618 assert(MO.isReg() && "Expected to fold into reg operand!");
4619 addOperands(MIB, MOs, PtrOffset);
4620 } else {
4621 MIB.add(MO);
4622 }
4623 }
4624
4625 updateOperandRegConstraints(MF, *NewMI, TII);
4626
4627 MachineBasicBlock *MBB = InsertPt->getParent();
4628 MBB->insert(InsertPt, NewMI);
4629
4630 return MIB;
4631 }
4632
4633 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
4634 ArrayRef<MachineOperand> MOs,
4635 MachineBasicBlock::iterator InsertPt,
4636 MachineInstr &MI) {
4637 MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
4638 MI.getDebugLoc(), TII.get(Opcode));
4639 addOperands(MIB, MOs);
4640 return MIB.addImm(0);
4641 }
4642
4643 MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
4644 MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
4645 ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
4646 unsigned Size, unsigned Align) const {
4647 switch (MI.getOpcode()) {
4648 case X86::INSERTPSrr:
4649 case X86::VINSERTPSrr:
4650 case X86::VINSERTPSZrr:
4651 // Attempt to convert the load of inserted vector into a fold load
4652 // of a single float.
4653 if (OpNum == 2) {
4654 unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
4655 unsigned ZMask = Imm & 15;
4656 unsigned DstIdx = (Imm >> 4) & 3;
4657 unsigned SrcIdx = (Imm >> 6) & 3;
4658
4659 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
4660 const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
4661 unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
4662 if ((Size == 0 || Size >= 16) && RCSize >= 16 && 4 <= Align) {
4663 int PtrOffset = SrcIdx * 4;
4664 unsigned NewImm = (DstIdx << 4) | ZMask;
4665 unsigned NewOpCode =
4666 (MI.getOpcode() == X86::VINSERTPSZrr) ? X86::VINSERTPSZrm :
4667 (MI.getOpcode() == X86::VINSERTPSrr) ? X86::VINSERTPSrm :
4668 X86::INSERTPSrm;
4669 MachineInstr *NewMI =
4670 FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset);
4671 NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
4672 return NewMI;
4673 }
4674 }
4675 break;
4676 case X86::MOVHLPSrr:
4677 case X86::VMOVHLPSrr:
4678 case X86::VMOVHLPSZrr:
4679 // Move the upper 64-bits of the second operand to the lower 64-bits.
4680 // To fold the load, adjust the pointer to the upper and use (V)MOVLPS.
4681 // TODO: In most cases AVX doesn't have a 8-byte alignment requirement.
4682 if (OpNum == 2) {
4683 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
4684 const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
4685 unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
4686 if ((Size == 0 || Size >= 16) && RCSize >= 16 && 8 <= Align) {
4687 unsigned NewOpCode =
4688 (MI.getOpcode() == X86::VMOVHLPSZrr) ? X86::VMOVLPSZ128rm :
4689 (MI.getOpcode() == X86::VMOVHLPSrr) ? X86::VMOVLPSrm :
4690 X86::MOVLPSrm;
4691 MachineInstr *NewMI =
4692 FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, 8);
4693 return NewMI;
4694 }
4695 }
4696 break;
4697 case X86::UNPCKLPDrr:
4698 // If we won't be able to fold this to the memory form of UNPCKL, use
4699 // MOVHPD instead. Done as custom because we can't have this in the load
4700 // table twice.
4701 if (OpNum == 2) {
4702 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
4703 const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
4704 unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
4705 if ((Size == 0 || Size >= 16) && RCSize >= 16 && Align < 16) {
4706 MachineInstr *NewMI =
4707 FuseInst(MF, X86::MOVHPDrm, OpNum, MOs, InsertPt, MI, *this);
4708 return NewMI;
4709 }
4710 }
4711 break;
4712 }
4713
4714 return nullptr;
4715 }
4716
4717 static bool shouldPreventUndefRegUpdateMemFold(MachineFunction &MF,
4718 MachineInstr &MI) {
4719 if (!hasUndefRegUpdate(MI.getOpcode(), /*ForLoadFold*/true) ||
4720 !MI.getOperand(1).isReg())
4721 return false;
4722
4723 // The are two cases we need to handle depending on where in the pipeline
4724 // the folding attempt is being made.
4725 // -Register has the undef flag set.
4726 // -Register is produced by the IMPLICIT_DEF instruction.
4727
4728 if (MI.getOperand(1).isUndef())
4729 return true;
4730
4731 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4732 MachineInstr *VRegDef = RegInfo.getUniqueVRegDef(MI.getOperand(1).getReg());
4733 return VRegDef && VRegDef->isImplicitDef();
4734 }
4735
4736
4737 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
4738 MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
4739 ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
4740 unsigned Size, unsigned Align, bool AllowCommute) const {
4741 bool isSlowTwoMemOps = Subtarget.slowTwoMemOps();
4742 bool isTwoAddrFold = false;
4743
4744 // For CPUs that favor the register form of a call or push,
4745 // do not fold loads into calls or pushes, unless optimizing for size
4746 // aggressively.
4747 if (isSlowTwoMemOps && !MF.getFunction().hasMinSize() &&
4748 (MI.getOpcode() == X86::CALL32r || MI.getOpcode() == X86::CALL64r ||
4749 MI.getOpcode() == X86::PUSH16r || MI.getOpcode() == X86::PUSH32r ||
4750 MI.getOpcode() == X86::PUSH64r))
4751 return nullptr;
4752
4753 // Avoid partial and undef register update stalls unless optimizing for size.
4754 if (!MF.getFunction().hasOptSize() &&
4755 (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
4756 shouldPreventUndefRegUpdateMemFold(MF, MI)))
4757 return nullptr;
4758
4759 unsigned NumOps = MI.getDesc().getNumOperands();
4760 bool isTwoAddr =
4761 NumOps > 1 && MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
4762
4763 // FIXME: AsmPrinter doesn't know how to handle
4764 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
4765 if (MI.getOpcode() == X86::ADD32ri &&
4766 MI.getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
4767 return nullptr;
4768
4769 // GOTTPOFF relocation loads can only be folded into add instructions.
4770 // FIXME: Need to exclude other relocations that only support specific
4771 // instructions.
4772 if (MOs.size() == X86::AddrNumOperands &&
4773 MOs[X86::AddrDisp].getTargetFlags() == X86II::MO_GOTTPOFF &&
4774 MI.getOpcode() != X86::ADD64rr)
4775 return nullptr;
4776
4777 MachineInstr *NewMI = nullptr;
4778
4779 // Attempt to fold any custom cases we have.
4780 if (MachineInstr *CustomMI =
4781 foldMemoryOperandCustom(MF, MI, OpNum, MOs, InsertPt, Size, Align))
4782 return CustomMI;
4783
4784 const X86MemoryFoldTableEntry *I = nullptr;
4785
4786 // Folding a memory location into the two-address part of a two-address
4787 // instruction is different than folding it other places. It requires
4788 // replacing the *two* registers with the memory location.
4789 if (isTwoAddr && NumOps >= 2 && OpNum < 2 && MI.getOperand(0).isReg() &&
4790 MI.getOperand(1).isReg() &&
4791 MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
4792 I = lookupTwoAddrFoldTable(MI.getOpcode());
4793 isTwoAddrFold = true;
4794 } else {
4795 if (OpNum == 0) {
4796 if (MI.getOpcode() == X86::MOV32r0) {
4797 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, InsertPt, MI);
4798 if (NewMI)
4799 return NewMI;
4800 }
4801 }
4802
4803 I = lookupFoldTable(MI.getOpcode(), OpNum);
4804 }
4805
4806 if (I != nullptr) {
4807 unsigned Opcode = I->DstOp;
4808 unsigned MinAlign = (I->Flags & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
4809 if (Align < MinAlign)
4810 return nullptr;
4811 bool NarrowToMOV32rm = false;
4812 if (Size) {
4813 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
4814 const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum,
4815 &RI, MF);
4816 unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
4817 if (Size < RCSize) {
4818 // FIXME: Allow scalar intrinsic instructions like ADDSSrm_Int.
4819 // Check if it's safe to fold the load. If the size of the object is
4820 // narrower than the load width, then it's not.
4821 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
4822 return nullptr;
4823 // If this is a 64-bit load, but the spill slot is 32, then we can do
4824 // a 32-bit load which is implicitly zero-extended. This likely is
4825 // due to live interval analysis remat'ing a load from stack slot.
4826 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
4827 return nullptr;
4828 Opcode = X86::MOV32rm;
4829 NarrowToMOV32rm = true;
4830 }
4831 }
4832
4833 if (isTwoAddrFold)
4834 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this);
4835 else
4836 NewMI = FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *this);
4837
4838 if (NarrowToMOV32rm) {
4839 // If this is the special case where we use a MOV32rm to load a 32-bit
4840 // value and zero-extend the top bits. Change the destination register
4841 // to a 32-bit one.
4842 Register DstReg = NewMI->getOperand(0).getReg();
4843 if (Register::isPhysicalRegister(DstReg))
4844 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
4845 else
4846 NewMI->getOperand(0).setSubReg(X86::sub_32bit);
4847 }
4848 return NewMI;
4849 }
4850
4851 // If the instruction and target operand are commutable, commute the
4852 // instruction and try again.
4853 if (AllowCommute) {
4854 unsigned CommuteOpIdx1 = OpNum, CommuteOpIdx2 = CommuteAnyOperandIndex;
4855 if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
4856 bool HasDef = MI.getDesc().getNumDefs();
4857 Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register();
4858 Register Reg1 = MI.getOperand(CommuteOpIdx1).getReg();
4859 Register Reg2 = MI.getOperand(CommuteOpIdx2).getReg();
4860 bool Tied1 =
4861 0 == MI.getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
4862 bool Tied2 =
4863 0 == MI.getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
4864
4865 // If either of the commutable operands are tied to the destination
4866 // then we can not commute + fold.
4867 if ((HasDef && Reg0 == Reg1 && Tied1) ||
4868 (HasDef && Reg0 == Reg2 && Tied2))
4869 return nullptr;
4870
4871 MachineInstr *CommutedMI =
4872 commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
4873 if (!CommutedMI) {
4874 // Unable to commute.
4875 return nullptr;
4876 }
4877 if (CommutedMI != &MI) {
4878 // New instruction. We can't fold from this.
4879 CommutedMI->eraseFromParent();
4880 return nullptr;
4881 }
4882
4883 // Attempt to fold with the commuted version of the instruction.
4884 NewMI = foldMemoryOperandImpl(MF, MI, CommuteOpIdx2, MOs, InsertPt,
4885 Size, Align, /*AllowCommute=*/false);
4886 if (NewMI)
4887 return NewMI;
4888
4889 // Folding failed again - undo the commute before returning.
4890 MachineInstr *UncommutedMI =
4891 commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
4892 if (!UncommutedMI) {
4893 // Unable to commute.
4894 return nullptr;
4895 }
4896 if (UncommutedMI != &MI) {
4897 // New instruction. It doesn't need to be kept.
4898 UncommutedMI->eraseFromParent();
4899 return nullptr;
4900 }
4901
4902 // Return here to prevent duplicate fuse failure report.
4903 return nullptr;
4904 }
4905 }
4906
4907 // No fusion
4908 if (PrintFailedFusing && !MI.isCopy())
4909 dbgs() << "We failed to fuse operand " << OpNum << " in " << MI;
4910 return nullptr;
4911 }
4912
4913 MachineInstr *
4914 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
4915 ArrayRef<unsigned> Ops,
4916 MachineBasicBlock::iterator InsertPt,
4917 int FrameIndex, LiveIntervals *LIS,
4918 VirtRegMap *VRM) const {
4919 // Check switch flag
4920 if (NoFusing)
4921 return nullptr;
4922
4923 // Avoid partial and undef register update stalls unless optimizing for size.
4924 if (!MF.getFunction().hasOptSize() &&
4925 (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
4926 shouldPreventUndefRegUpdateMemFold(MF, MI)))
4927 return nullptr;
4928
4929 // Don't fold subreg spills, or reloads that use a high subreg.
4930 for (auto Op : Ops) {
4931 MachineOperand &MO = MI.getOperand(Op);
4932 auto SubReg = MO.getSubReg();
4933 if (SubReg && (MO.isDef() || SubReg == X86::sub_8bit_hi))
4934 return nullptr;
4935 }
4936
4937 const MachineFrameInfo &MFI = MF.getFrameInfo();
4938 unsigned Size = MFI.getObjectSize(FrameIndex);
4939 unsigned Alignment = MFI.getObjectAlignment(FrameIndex);
4940 // If the function stack isn't realigned we don't want to fold instructions
4941 // that need increased alignment.
4942 if (!RI.needsStackRealignment(MF))
4943 Alignment =
4944 std::min(Alignment, Subtarget.getFrameLowering()->getStackAlignment());
4945 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
4946 unsigned NewOpc = 0;
4947 unsigned RCSize = 0;
4948 switch (MI.getOpcode()) {
4949 default: return nullptr;
4950 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
4951 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
4952 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
4953 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
4954 }
4955 // Check if it's safe to fold the load. If the size of the object is
4956 // narrower than the load width, then it's not.
4957 if (Size < RCSize)
4958 return nullptr;
4959 // Change to CMPXXri r, 0 first.
4960 MI.setDesc(get(NewOpc));
4961 MI.getOperand(1).ChangeToImmediate(0);
4962 } else if (Ops.size() != 1)
4963 return nullptr;
4964
4965 return foldMemoryOperandImpl(MF, MI, Ops[0],
4966 MachineOperand::CreateFI(FrameIndex), InsertPt,
4967 Size, Alignment, /*AllowCommute=*/true);
4968 }
4969
4970 /// Check if \p LoadMI is a partial register load that we can't fold into \p MI
4971 /// because the latter uses contents that wouldn't be defined in the folded
4972 /// version. For instance, this transformation isn't legal:
4973 /// movss (%rdi), %xmm0
4974 /// addps %xmm0, %xmm0
4975 /// ->
4976 /// addps (%rdi), %xmm0
4977 ///
4978 /// But this one is:
4979 /// movss (%rdi), %xmm0
4980 /// addss %xmm0, %xmm0
4981 /// ->
4982 /// addss (%rdi), %xmm0
4983 ///
4984 static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
4985 const MachineInstr &UserMI,
4986 const MachineFunction &MF) {
4987 unsigned Opc = LoadMI.getOpcode();
4988 unsigned UserOpc = UserMI.getOpcode();
4989 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
4990 const TargetRegisterClass *RC =
4991 MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg());
4992 unsigned RegSize = TRI.getRegSizeInBits(*RC);
4993
4994 if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm || Opc == X86::VMOVSSZrm ||
4995 Opc == X86::MOVSSrm_alt || Opc == X86::VMOVSSrm_alt ||
4996 Opc == X86::VMOVSSZrm_alt) &&
4997 RegSize > 32) {
4998 // These instructions only load 32 bits, we can't fold them if the
4999 // destination register is wider than 32 bits (4 bytes), and its user
5000 // instruction isn't scalar (SS).
5001 switch (UserOpc) {
5002 case X86::ADDSSrr_Int: case X86::VADDSSrr_Int: case X86::VADDSSZrr_Int:
5003 case X86::CMPSSrr_Int: case X86::VCMPSSrr_Int: case X86::VCMPSSZrr_Int:
5004 case X86::DIVSSrr_Int: case X86::VDIVSSrr_Int: case X86::VDIVSSZrr_Int:
5005 case X86::MAXSSrr_Int: case X86::VMAXSSrr_Int: case X86::VMAXSSZrr_Int:
5006 case X86::MINSSrr_Int: case X86::VMINSSrr_Int: case X86::VMINSSZrr_Int:
5007 case X86::MULSSrr_Int: case X86::VMULSSrr_Int: case X86::VMULSSZrr_Int:
5008 case X86::SUBSSrr_Int: case X86::VSUBSSrr_Int: case X86::VSUBSSZrr_Int:
5009 case X86::VADDSSZrr_Intk: case X86::VADDSSZrr_Intkz:
5010 case X86::VCMPSSZrr_Intk:
5011 case X86::VDIVSSZrr_Intk: case X86::VDIVSSZrr_Intkz:
5012 case X86::VMAXSSZrr_Intk: case X86::VMAXSSZrr_Intkz:
5013 case X86::VMINSSZrr_Intk: case X86::VMINSSZrr_Intkz:
5014 case X86::VMULSSZrr_Intk: case X86::VMULSSZrr_Intkz:
5015 case X86::VSUBSSZrr_Intk: case X86::VSUBSSZrr_Intkz:
5016 case X86::VFMADDSS4rr_Int: case X86::VFNMADDSS4rr_Int:
5017 case X86::VFMSUBSS4rr_Int: case X86::VFNMSUBSS4rr_Int:
5018 case X86::VFMADD132SSr_Int: case X86::VFNMADD132SSr_Int:
5019 case X86::VFMADD213SSr_Int: case X86::VFNMADD213SSr_Int:
5020 case X86::VFMADD231SSr_Int: case X86::VFNMADD231SSr_Int:
5021 case X86::VFMSUB132SSr_Int: case X86::VFNMSUB132SSr_Int:
5022 case X86::VFMSUB213SSr_Int: case X86::VFNMSUB213SSr_Int:
5023 case X86::VFMSUB231SSr_Int: case X86::VFNMSUB231SSr_Int:
5024 case X86::VFMADD132SSZr_Int: case X86::VFNMADD132SSZr_Int:
5025 case X86::VFMADD213SSZr_Int: case X86::VFNMADD213SSZr_Int:
5026 case X86::VFMADD231SSZr_Int: case X86::VFNMADD231SSZr_Int:
5027 case X86::VFMSUB132SSZr_Int: case X86::VFNMSUB132SSZr_Int:
5028 case X86::VFMSUB213SSZr_Int: case X86::VFNMSUB213SSZr_Int:
5029 case X86::VFMSUB231SSZr_Int: case X86::VFNMSUB231SSZr_Int:
5030 case X86::VFMADD132SSZr_Intk: case X86::VFNMADD132SSZr_Intk:
5031 case X86::VFMADD213SSZr_Intk: case X86::VFNMADD213SSZr_Intk:
5032 case X86::VFMADD231SSZr_Intk: case X86::VFNMADD231SSZr_Intk:
5033 case X86::VFMSUB132SSZr_Intk: case X86::VFNMSUB132SSZr_Intk:
5034 case X86::VFMSUB213SSZr_Intk: case X86::VFNMSUB213SSZr_Intk:
5035 case X86::VFMSUB231SSZr_Intk: case X86::VFNMSUB231SSZr_Intk:
5036 case X86::VFMADD132SSZr_Intkz: case X86::VFNMADD132SSZr_Intkz:
5037 case X86::VFMADD213SSZr_Intkz: case X86::VFNMADD213SSZr_Intkz:
5038 case X86::VFMADD231SSZr_Intkz: case X86::VFNMADD231SSZr_Intkz:
5039 case X86::VFMSUB132SSZr_Intkz: case X86::VFNMSUB132SSZr_Intkz:
5040 case X86::VFMSUB213SSZr_Intkz: case X86::VFNMSUB213SSZr_Intkz:
5041 case X86::VFMSUB231SSZr_Intkz: case X86::VFNMSUB231SSZr_Intkz:
5042 return false;
5043 default:
5044 return true;
5045 }
5046 }
5047
5048 if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm || Opc == X86::VMOVSDZrm ||
5049 Opc == X86::MOVSDrm_alt || Opc == X86::VMOVSDrm_alt ||
5050 Opc == X86::VMOVSDZrm_alt) &&
5051 RegSize > 64) {
5052 // These instructions only load 64 bits, we can't fold them if the
5053 // destination register is wider than 64 bits (8 bytes), and its user
5054 // instruction isn't scalar (SD).
5055 switch (UserOpc) {
5056 case X86::ADDSDrr_Int: case X86::VADDSDrr_Int: case X86::VADDSDZrr_Int:
5057 case X86::CMPSDrr_Int: case X86::VCMPSDrr_Int: case X86::VCMPSDZrr_Int:
5058 case X86::DIVSDrr_Int: case X86::VDIVSDrr_Int: case X86::VDIVSDZrr_Int:
5059 case X86::MAXSDrr_Int: case X86::VMAXSDrr_Int: case X86::VMAXSDZrr_Int:
5060 case X86::MINSDrr_Int: case X86::VMINSDrr_Int: case X86::VMINSDZrr_Int:
5061 case X86::MULSDrr_Int: case X86::VMULSDrr_Int: case X86::VMULSDZrr_Int:
5062 case X86::SUBSDrr_Int: case X86::VSUBSDrr_Int: case X86::VSUBSDZrr_Int:
5063 case X86::VADDSDZrr_Intk: case X86::VADDSDZrr_Intkz:
5064 case X86::VCMPSDZrr_Intk:
5065 case X86::VDIVSDZrr_Intk: case X86::VDIVSDZrr_Intkz:
5066 case X86::VMAXSDZrr_Intk: case X86::VMAXSDZrr_Intkz:
5067 case X86::VMINSDZrr_Intk: case X86::VMINSDZrr_Intkz:
5068 case X86::VMULSDZrr_Intk: case X86::VMULSDZrr_Intkz:
5069 case X86::VSUBSDZrr_Intk: case X86::VSUBSDZrr_Intkz:
5070 case X86::VFMADDSD4rr_Int: case X86::VFNMADDSD4rr_Int:
5071 case X86::VFMSUBSD4rr_Int: case X86::VFNMSUBSD4rr_Int:
5072 case X86::VFMADD132SDr_Int: case X86::VFNMADD132SDr_Int:
5073 case X86::VFMADD213SDr_Int: case X86::VFNMADD213SDr_Int:
5074 case X86::VFMADD231SDr_Int: case X86::VFNMADD231SDr_Int:
5075 case X86::VFMSUB132SDr_Int: case X86::VFNMSUB132SDr_Int:
5076 case X86::VFMSUB213SDr_Int: case X86::VFNMSUB213SDr_Int:
5077 case X86::VFMSUB231SDr_Int: case X86::VFNMSUB231SDr_Int:
5078 case X86::VFMADD132SDZr_Int: case X86::VFNMADD132SDZr_Int:
5079 case X86::VFMADD213SDZr_Int: case X86::VFNMADD213SDZr_Int:
5080 case X86::VFMADD231SDZr_Int: case X86::VFNMADD231SDZr_Int:
5081 case X86::VFMSUB132SDZr_Int: case X86::VFNMSUB132SDZr_Int:
5082 case X86::VFMSUB213SDZr_Int: case X86::VFNMSUB213SDZr_Int:
5083 case X86::VFMSUB231SDZr_Int: case X86::VFNMSUB231SDZr_Int:
5084 case X86::VFMADD132SDZr_Intk: case X86::VFNMADD132SDZr_Intk:
5085 case X86::VFMADD213SDZr_Intk: case X86::VFNMADD213SDZr_Intk:
5086 case X86::VFMADD231SDZr_Intk: case X86::VFNMADD231SDZr_Intk:
5087 case X86::VFMSUB132SDZr_Intk: case X86::VFNMSUB132SDZr_Intk:
5088 case X86::VFMSUB213SDZr_Intk: case X86::VFNMSUB213SDZr_Intk:
5089 case X86::VFMSUB231SDZr_Intk: case X86::VFNMSUB231SDZr_Intk:
5090 case X86::VFMADD132SDZr_Intkz: case X86::VFNMADD132SDZr_Intkz:
5091 case X86::VFMADD213SDZr_Intkz: case X86::VFNMADD213SDZr_Intkz:
5092 case X86::VFMADD231SDZr_Intkz: case X86::VFNMADD231SDZr_Intkz:
5093 case X86::VFMSUB132SDZr_Intkz: case X86::VFNMSUB132SDZr_Intkz:
5094 case X86::VFMSUB213SDZr_Intkz: case X86::VFNMSUB213SDZr_Intkz:
5095 case X86::VFMSUB231SDZr_Intkz: case X86::VFNMSUB231SDZr_Intkz:
5096 return false;
5097 default:
5098 return true;
5099 }
5100 }
5101
5102 return false;
5103 }
5104
5105 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
5106 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
5107 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
5108 LiveIntervals *LIS) const {
5109
5110 // TODO: Support the case where LoadMI loads a wide register, but MI
5111 // only uses a subreg.
5112 for (auto Op : Ops) {
5113 if (MI.getOperand(Op).getSubReg())
5114 return nullptr;
5115 }
5116
5117 // If loading from a FrameIndex, fold directly from the FrameIndex.
5118 unsigned NumOps = LoadMI.getDesc().getNumOperands();
5119 int FrameIndex;
5120 if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
5121 if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
5122 return nullptr;
5123 return foldMemoryOperandImpl(MF, MI, Ops, InsertPt, FrameIndex, LIS);
5124 }
5125
5126 // Check switch flag
5127 if (NoFusing) return nullptr;
5128
5129 // Avoid partial and undef register update stalls unless optimizing for size.
5130 if (!MF.getFunction().hasOptSize() &&
5131 (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
5132 shouldPreventUndefRegUpdateMemFold(MF, MI)))
5133 return nullptr;
5134
5135 // Determine the alignment of the load.
5136 unsigned Alignment = 0;
5137 if (LoadMI.hasOneMemOperand())
5138 Alignment = (*LoadMI.memoperands_begin())->getAlignment();
5139 else
5140 switch (LoadMI.getOpcode()) {
5141 case X86::AVX512_512_SET0:
5142 case X86::AVX512_512_SETALLONES:
5143 Alignment = 64;
5144 break;
5145 case X86::AVX2_SETALLONES:
5146 case X86::AVX1_SETALLONES:
5147 case X86::AVX_SET0:
5148 case X86::AVX512_256_SET0:
5149 Alignment = 32;
5150 break;
5151 case X86::V_SET0:
5152 case X86::V_SETALLONES:
5153 case X86::AVX512_128_SET0:
5154 Alignment = 16;
5155 break;
5156 case X86::MMX_SET0:
5157 case X86::FsFLD0SD:
5158 case X86::AVX512_FsFLD0SD:
5159 Alignment = 8;
5160 break;
5161 case X86::FsFLD0SS:
5162 case X86::AVX512_FsFLD0SS:
5163 Alignment = 4;
5164 break;
5165 default:
5166 return nullptr;
5167 }
5168 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5169 unsigned NewOpc = 0;
5170 switch (MI.getOpcode()) {
5171 default: return nullptr;
5172 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
5173 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
5174 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
5175 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
5176 }
5177 // Change to CMPXXri r, 0 first.
5178 MI.setDesc(get(NewOpc));
5179 MI.getOperand(1).ChangeToImmediate(0);
5180 } else if (Ops.size() != 1)
5181 return nullptr;
5182
5183 // Make sure the subregisters match.
5184 // Otherwise we risk changing the size of the load.
5185 if (LoadMI.getOperand(0).getSubReg() != MI.getOperand(Ops[0]).getSubReg())
5186 return nullptr;
5187
5188 SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
5189 switch (LoadMI.getOpcode()) {
5190 case X86::MMX_SET0:
5191 case X86::V_SET0:
5192 case X86::V_SETALLONES:
5193 case X86::AVX2_SETALLONES:
5194 case X86::AVX1_SETALLONES:
5195 case X86::AVX_SET0:
5196 case X86::AVX512_128_SET0:
5197 case X86::AVX512_256_SET0:
5198 case X86::AVX512_512_SET0:
5199 case X86::AVX512_512_SETALLONES:
5200 case X86::FsFLD0SD:
5201 case X86::AVX512_FsFLD0SD:
5202 case X86::FsFLD0SS:
5203 case X86::AVX512_FsFLD0SS: {
5204 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
5205 // Create a constant-pool entry and operands to load from it.
5206
5207 // Medium and large mode can't fold loads this way.
5208 if (MF.getTarget().getCodeModel() != CodeModel::Small &&
5209 MF.getTarget().getCodeModel() != CodeModel::Kernel)
5210 return nullptr;
5211
5212 // x86-32 PIC requires a PIC base register for constant pools.
5213 unsigned PICBase = 0;
5214 if (MF.getTarget().isPositionIndependent()) {
5215 if (Subtarget.is64Bit())
5216 PICBase = X86::RIP;
5217 else
5218 // FIXME: PICBase = getGlobalBaseReg(&MF);
5219 // This doesn't work for several reasons.
5220 // 1. GlobalBaseReg may have been spilled.
5221 // 2. It may not be live at MI.
5222 return nullptr;
5223 }
5224
5225 // Create a constant-pool entry.
5226 MachineConstantPool &MCP = *MF.getConstantPool();
5227 Type *Ty;
5228 unsigned Opc = LoadMI.getOpcode();
5229 if (Opc == X86::FsFLD0SS || Opc == X86::AVX512_FsFLD0SS)
5230 Ty = Type::getFloatTy(MF.getFunction().getContext());
5231 else if (Opc == X86::FsFLD0SD || Opc == X86::AVX512_FsFLD0SD)
5232 Ty = Type::getDoubleTy(MF.getFunction().getContext());
5233 else if (Opc == X86::AVX512_512_SET0 || Opc == X86::AVX512_512_SETALLONES)
5234 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction().getContext()),16);
5235 else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0 ||
5236 Opc == X86::AVX512_256_SET0 || Opc == X86::AVX1_SETALLONES)
5237 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction().getContext()), 8);
5238 else if (Opc == X86::MMX_SET0)
5239 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction().getContext()), 2);
5240 else
5241 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction().getContext()), 4);
5242
5243 bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES ||
5244 Opc == X86::AVX512_512_SETALLONES ||
5245 Opc == X86::AVX1_SETALLONES);
5246 const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
5247 Constant::getNullValue(Ty);
5248 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
5249
5250 // Create operands to load from the constant pool entry.
5251 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
5252 MOs.push_back(MachineOperand::CreateImm(1));
5253 MOs.push_back(MachineOperand::CreateReg(0, false));
5254 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
5255 MOs.push_back(MachineOperand::CreateReg(0, false));
5256 break;
5257 }
5258 default: {
5259 if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
5260 return nullptr;
5261
5262 // Folding a normal load. Just copy the load's address operands.
5263 MOs.append(LoadMI.operands_begin() + NumOps - X86::AddrNumOperands,
5264 LoadMI.operands_begin() + NumOps);
5265 break;
5266 }
5267 }
5268 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, InsertPt,
5269 /*Size=*/0, Alignment, /*AllowCommute=*/true);
5270 }
5271
5272 static SmallVector<MachineMemOperand *, 2>
5273 extractLoadMMOs(ArrayRef<MachineMemOperand *> MMOs, MachineFunction &MF) {
5274 SmallVector<MachineMemOperand *, 2> LoadMMOs;
5275
5276 for (MachineMemOperand *MMO : MMOs) {
5277 if (!MMO->isLoad())
5278 continue;
5279
5280 if (!MMO->isStore()) {
5281 // Reuse the MMO.
5282 LoadMMOs.push_back(MMO);
5283 } else {
5284 // Clone the MMO and unset the store flag.
5285 LoadMMOs.push_back(MF.getMachineMemOperand(
5286 MMO, MMO->getFlags() & ~MachineMemOperand::MOStore));
5287 }
5288 }
5289
5290 return LoadMMOs;
5291 }
5292
5293 static SmallVector<MachineMemOperand *, 2>
5294 extractStoreMMOs(ArrayRef<MachineMemOperand *> MMOs, MachineFunction &MF) {
5295 SmallVector<MachineMemOperand *, 2> StoreMMOs;
5296
5297 for (MachineMemOperand *MMO : MMOs) {
5298 if (!MMO->isStore())
5299 continue;
5300
5301 if (!MMO->isLoad()) {
5302 // Reuse the MMO.
5303 StoreMMOs.push_back(MMO);
5304 } else {
5305 // Clone the MMO and unset the load flag.
5306 StoreMMOs.push_back(MF.getMachineMemOperand(
5307 MMO, MMO->getFlags() & ~MachineMemOperand::MOLoad));
5308 }
5309 }
5310
5311 return StoreMMOs;
5312 }
5313
5314 bool X86InstrInfo::unfoldMemoryOperand(
5315 MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad,
5316 bool UnfoldStore, SmallVectorImpl<MachineInstr *> &NewMIs) const {
5317 const X86MemoryFoldTableEntry *I = lookupUnfoldTable(MI.getOpcode());
5318 if (I == nullptr)
5319 return false;
5320 unsigned Opc = I->DstOp;
5321 unsigned Index = I->Flags & TB_INDEX_MASK;
5322 bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
5323 bool FoldedStore = I->Flags & TB_FOLDED_STORE;
5324 if (UnfoldLoad && !FoldedLoad)
5325 return false;
5326 UnfoldLoad &= FoldedLoad;
5327 if (UnfoldStore && !FoldedStore)
5328 return false;
5329 UnfoldStore &= FoldedStore;
5330
5331 const MCInstrDesc &MCID = get(Opc);
5332 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
5333 // TODO: Check if 32-byte or greater accesses are slow too?
5334 if (!MI.hasOneMemOperand() && RC == &X86::VR128RegClass &&
5335 Subtarget.isUnalignedMem16Slow())
5336 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
5337 // conservatively assume the address is unaligned. That's bad for
5338 // performance.
5339 return false;
5340 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
5341 SmallVector<MachineOperand,2> BeforeOps;
5342 SmallVector<MachineOperand,2> AfterOps;
5343 SmallVector<MachineOperand,4> ImpOps;
5344 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
5345 MachineOperand &Op = MI.getOperand(i);
5346 if (i >= Index && i < Index + X86::AddrNumOperands)
5347 AddrOps.push_back(Op);
5348 else if (Op.isReg() && Op.isImplicit())
5349 ImpOps.push_back(Op);
5350 else if (i < Index)
5351 BeforeOps.push_back(Op);
5352 else if (i > Index)
5353 AfterOps.push_back(Op);
5354 }
5355
5356 // Emit the load instruction.
5357 if (UnfoldLoad) {
5358 auto MMOs = extractLoadMMOs(MI.memoperands(), MF);
5359 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs, NewMIs);
5360 if (UnfoldStore) {
5361 // Address operands cannot be marked isKill.
5362 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
5363 MachineOperand &MO = NewMIs[0]->getOperand(i);
5364 if (MO.isReg())
5365 MO.setIsKill(false);
5366 }
5367 }
5368 }
5369
5370 // Emit the data processing instruction.
5371 MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI.getDebugLoc(), true);
5372 MachineInstrBuilder MIB(MF, DataMI);
5373
5374 if (FoldedStore)
5375 MIB.addReg(Reg, RegState::Define);
5376 for (MachineOperand &BeforeOp : BeforeOps)
5377 MIB.add(BeforeOp);
5378 if (FoldedLoad)
5379 MIB.addReg(Reg);
5380 for (MachineOperand &AfterOp : AfterOps)
5381 MIB.add(AfterOp);
5382 for (MachineOperand &ImpOp : ImpOps) {
5383 MIB.addReg(ImpOp.getReg(),
5384 getDefRegState(ImpOp.isDef()) |
5385 RegState::Implicit |
5386 getKillRegState(ImpOp.isKill()) |
5387 getDeadRegState(ImpOp.isDead()) |
5388 getUndefRegState(ImpOp.isUndef()));
5389 }
5390 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
5391 switch (DataMI->getOpcode()) {
5392 default: break;
5393 case X86::CMP64ri32:
5394 case X86::CMP64ri8:
5395 case X86::CMP32ri:
5396 case X86::CMP32ri8:
5397 case X86::CMP16ri:
5398 case X86::CMP16ri8:
5399 case X86::CMP8ri: {
5400 MachineOperand &MO0 = DataMI->getOperand(0);
5401 MachineOperand &MO1 = DataMI->getOperand(1);
5402 if (MO1.getImm() == 0) {
5403 unsigned NewOpc;
5404 switch (DataMI->getOpcode()) {
5405 default: llvm_unreachable("Unreachable!");
5406 case X86::CMP64ri8:
5407 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
5408 case X86::CMP32ri8:
5409 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
5410 case X86::CMP16ri8:
5411 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
5412 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
5413 }
5414 DataMI->setDesc(get(NewOpc));
5415 MO1.ChangeToRegister(MO0.getReg(), false);
5416 }
5417 }
5418 }
5419 NewMIs.push_back(DataMI);
5420
5421 // Emit the store instruction.
5422 if (UnfoldStore) {
5423 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
5424 auto MMOs = extractStoreMMOs(MI.memoperands(), MF);
5425 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs, NewMIs);
5426 }
5427
5428 return true;
5429 }
5430
5431 bool
5432 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
5433 SmallVectorImpl<SDNode*> &NewNodes) const {
5434 if (!N->isMachineOpcode())
5435 return false;
5436
5437 const X86MemoryFoldTableEntry *I = lookupUnfoldTable(N->getMachineOpcode());
5438 if (I == nullptr)
5439 return false;
5440 unsigned Opc = I->DstOp;
5441 unsigned Index = I->Flags & TB_INDEX_MASK;
5442 bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
5443 bool FoldedStore = I->Flags & TB_FOLDED_STORE;
5444 const MCInstrDesc &MCID = get(Opc);
5445 MachineFunction &MF = DAG.getMachineFunction();
5446 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5447 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
5448 unsigned NumDefs = MCID.NumDefs;
5449 std::vector<SDValue> AddrOps;
5450 std::vector<SDValue> BeforeOps;
5451 std::vector<SDValue> AfterOps;
5452 SDLoc dl(N);
5453 unsigned NumOps = N->getNumOperands();
5454 for (unsigned i = 0; i != NumOps-1; ++i) {
5455 SDValue Op = N->getOperand(i);
5456 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
5457 AddrOps.push_back(Op);
5458 else if (i < Index-NumDefs)
5459 BeforeOps.push_back(Op);
5460 else if (i > Index-NumDefs)
5461 AfterOps.push_back(Op);
5462 }
5463 SDValue Chain = N->getOperand(NumOps-1);
5464 AddrOps.push_back(Chain);
5465
5466 // Emit the load instruction.
5467 SDNode *Load = nullptr;
5468 if (FoldedLoad) {
5469 EVT VT = *TRI.legalclasstypes_begin(*RC);
5470 auto MMOs = extractLoadMMOs(cast<MachineSDNode>(N)->memoperands(), MF);
5471 if (MMOs.empty() && RC == &X86::VR128RegClass &&
5472 Subtarget.isUnalignedMem16Slow())
5473 // Do not introduce a slow unaligned load.
5474 return false;
5475 // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
5476 // memory access is slow above.
5477 unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
5478 bool isAligned = !MMOs.empty() && MMOs.front()->getAlignment() >= Alignment;
5479 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl,
5480 VT, MVT::Other, AddrOps);
5481 NewNodes.push_back(Load);
5482
5483 // Preserve memory reference information.
5484 DAG.setNodeMemRefs(cast<MachineSDNode>(Load), MMOs);
5485 }
5486
5487 // Emit the data processing instruction.
5488 std::vector<EVT> VTs;
5489 const TargetRegisterClass *DstRC = nullptr;
5490 if (MCID.getNumDefs() > 0) {
5491 DstRC = getRegClass(MCID, 0, &RI, MF);
5492 VTs.push_back(*TRI.legalclasstypes_begin(*DstRC));
5493 }
5494 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
5495 EVT VT = N->getValueType(i);
5496 if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
5497 VTs.push_back(VT);
5498 }
5499 if (Load)
5500 BeforeOps.push_back(SDValue(Load, 0));
5501 BeforeOps.insert(BeforeOps.end(), AfterOps.begin(), AfterOps.end());
5502 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
5503 switch (Opc) {
5504 default: break;
5505 case X86::CMP64ri32:
5506 case X86::CMP64ri8:
5507 case X86::CMP32ri:
5508 case X86::CMP32ri8:
5509 case X86::CMP16ri:
5510 case X86::CMP16ri8:
5511 case X86::CMP8ri:
5512 if (isNullConstant(BeforeOps[1])) {
5513 switch (Opc) {
5514 default: llvm_unreachable("Unreachable!");
5515 case X86::CMP64ri8:
5516 case X86::CMP64ri32: Opc = X86::TEST64rr; break;
5517 case X86::CMP32ri8:
5518 case X86::CMP32ri: Opc = X86::TEST32rr; break;
5519 case X86::CMP16ri8:
5520 case X86::CMP16ri: Opc = X86::TEST16rr; break;
5521 case X86::CMP8ri: Opc = X86::TEST8rr; break;
5522 }
5523 BeforeOps[1] = BeforeOps[0];
5524 }
5525 }
5526 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
5527 NewNodes.push_back(NewNode);
5528
5529 // Emit the store instruction.
5530 if (FoldedStore) {
5531 AddrOps.pop_back();
5532 AddrOps.push_back(SDValue(NewNode, 0));
5533 AddrOps.push_back(Chain);
5534 auto MMOs = extractStoreMMOs(cast<MachineSDNode>(N)->memoperands(), MF);
5535 if (MMOs.empty() && RC == &X86::VR128RegClass &&
5536 Subtarget.isUnalignedMem16Slow())
5537 // Do not introduce a slow unaligned store.
5538 return false;
5539 // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
5540 // memory access is slow above.
5541 unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
5542 bool isAligned = !MMOs.empty() && MMOs.front()->getAlignment() >= Alignment;
5543 SDNode *Store =
5544 DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
5545 dl, MVT::Other, AddrOps);
5546 NewNodes.push_back(Store);
5547
5548 // Preserve memory reference information.
5549 DAG.setNodeMemRefs(cast<MachineSDNode>(Store), MMOs);
5550 }
5551
5552 return true;
5553 }
5554
5555 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
5556 bool UnfoldLoad, bool UnfoldStore,
5557 unsigned *LoadRegIndex) const {
5558 const X86MemoryFoldTableEntry *I = lookupUnfoldTable(Opc);
5559 if (I == nullptr)
5560 return 0;
5561 bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
5562 bool FoldedStore = I->Flags & TB_FOLDED_STORE;
5563 if (UnfoldLoad && !FoldedLoad)
5564 return 0;
5565 if (UnfoldStore && !FoldedStore)
5566 return 0;
5567 if (LoadRegIndex)
5568 *LoadRegIndex = I->Flags & TB_INDEX_MASK;
5569 return I->DstOp;
5570 }
5571
5572 bool
5573 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
5574 int64_t &Offset1, int64_t &Offset2) const {
5575 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
5576 return false;
5577 unsigned Opc1 = Load1->getMachineOpcode();
5578 unsigned Opc2 = Load2->getMachineOpcode();
5579 switch (Opc1) {
5580 default: return false;
5581 case X86::MOV8rm:
5582 case X86::MOV16rm:
5583 case X86::MOV32rm:
5584 case X86::MOV64rm:
5585 case X86::LD_Fp32m:
5586 case X86::LD_Fp64m:
5587 case X86::LD_Fp80m:
5588 case X86::MOVSSrm:
5589 case X86::MOVSSrm_alt:
5590 case X86::MOVSDrm:
5591 case X86::MOVSDrm_alt:
5592 case X86::MMX_MOVD64rm:
5593 case X86::MMX_MOVQ64rm:
5594 case X86::MOVAPSrm:
5595 case X86::MOVUPSrm:
5596 case X86::MOVAPDrm:
5597 case X86::MOVUPDrm:
5598 case X86::MOVDQArm:
5599 case X86::MOVDQUrm:
5600 // AVX load instructions
5601 case X86::VMOVSSrm:
5602 case X86::VMOVSSrm_alt:
5603 case X86::VMOVSDrm:
5604 case X86::VMOVSDrm_alt:
5605 case X86::VMOVAPSrm:
5606 case X86::VMOVUPSrm:
5607 case X86::VMOVAPDrm:
5608 case X86::VMOVUPDrm:
5609 case X86::VMOVDQArm:
5610 case X86::VMOVDQUrm:
5611 case X86::VMOVAPSYrm:
5612 case X86::VMOVUPSYrm:
5613 case X86::VMOVAPDYrm:
5614 case X86::VMOVUPDYrm:
5615 case X86::VMOVDQAYrm:
5616 case X86::VMOVDQUYrm:
5617 // AVX512 load instructions
5618 case X86::VMOVSSZrm:
5619 case X86::VMOVSSZrm_alt:
5620 case X86::VMOVSDZrm:
5621 case X86::VMOVSDZrm_alt:
5622 case X86::VMOVAPSZ128rm:
5623 case X86::VMOVUPSZ128rm:
5624 case X86::VMOVAPSZ128rm_NOVLX:
5625 case X86::VMOVUPSZ128rm_NOVLX:
5626 case X86::VMOVAPDZ128rm:
5627 case X86::VMOVUPDZ128rm:
5628 case X86::VMOVDQU8Z128rm:
5629 case X86::VMOVDQU16Z128rm:
5630 case X86::VMOVDQA32Z128rm:
5631 case X86::VMOVDQU32Z128rm:
5632 case X86::VMOVDQA64Z128rm:
5633 case X86::VMOVDQU64Z128rm:
5634 case X86::VMOVAPSZ256rm:
5635 case X86::VMOVUPSZ256rm:
5636 case X86::VMOVAPSZ256rm_NOVLX:
5637 case X86::VMOVUPSZ256rm_NOVLX:
5638 case X86::VMOVAPDZ256rm:
5639 case X86::VMOVUPDZ256rm:
5640 case X86::VMOVDQU8Z256rm:
5641 case X86::VMOVDQU16Z256rm:
5642 case X86::VMOVDQA32Z256rm:
5643 case X86::VMOVDQU32Z256rm:
5644 case X86::VMOVDQA64Z256rm:
5645 case X86::VMOVDQU64Z256rm:
5646 case X86::VMOVAPSZrm:
5647 case X86::VMOVUPSZrm:
5648 case X86::VMOVAPDZrm:
5649 case X86::VMOVUPDZrm:
5650 case X86::VMOVDQU8Zrm:
5651 case X86::VMOVDQU16Zrm:
5652 case X86::VMOVDQA32Zrm:
5653 case X86::VMOVDQU32Zrm:
5654 case X86::VMOVDQA64Zrm:
5655 case X86::VMOVDQU64Zrm:
5656 case X86::KMOVBkm:
5657 case X86::KMOVWkm:
5658 case X86::KMOVDkm:
5659 case X86::KMOVQkm:
5660 break;
5661 }
5662 switch (Opc2) {
5663 default: return false;
5664 case X86::MOV8rm:
5665 case X86::MOV16rm:
5666 case X86::MOV32rm:
5667 case X86::MOV64rm:
5668 case X86::LD_Fp32m:
5669 case X86::LD_Fp64m:
5670 case X86::LD_Fp80m:
5671 case X86::MOVSSrm:
5672 case X86::MOVSSrm_alt:
5673 case X86::MOVSDrm:
5674 case X86::MOVSDrm_alt:
5675 case X86::MMX_MOVD64rm:
5676 case X86::MMX_MOVQ64rm:
5677 case X86::MOVAPSrm:
5678 case X86::MOVUPSrm:
5679 case X86::MOVAPDrm:
5680 case X86::MOVUPDrm:
5681 case X86::MOVDQArm:
5682 case X86::MOVDQUrm:
5683 // AVX load instructions
5684 case X86::VMOVSSrm:
5685 case X86::VMOVSSrm_alt:
5686 case X86::VMOVSDrm:
5687 case X86::VMOVSDrm_alt:
5688 case X86::VMOVAPSrm:
5689 case X86::VMOVUPSrm:
5690 case X86::VMOVAPDrm:
5691 case X86::VMOVUPDrm:
5692 case X86::VMOVDQArm:
5693 case X86::VMOVDQUrm:
5694 case X86::VMOVAPSYrm:
5695 case X86::VMOVUPSYrm:
5696 case X86::VMOVAPDYrm:
5697 case X86::VMOVUPDYrm:
5698 case X86::VMOVDQAYrm:
5699 case X86::VMOVDQUYrm:
5700 // AVX512 load instructions
5701 case X86::VMOVSSZrm:
5702 case X86::VMOVSSZrm_alt:
5703 case X86::VMOVSDZrm:
5704 case X86::VMOVSDZrm_alt:
5705 case X86::VMOVAPSZ128rm:
5706 case X86::VMOVUPSZ128rm:
5707 case X86::VMOVAPSZ128rm_NOVLX:
5708 case X86::VMOVUPSZ128rm_NOVLX:
5709 case X86::VMOVAPDZ128rm:
5710 case X86::VMOVUPDZ128rm:
5711 case X86::VMOVDQU8Z128rm:
5712 case X86::VMOVDQU16Z128rm:
5713 case X86::VMOVDQA32Z128rm:
5714 case X86::VMOVDQU32Z128rm:
5715 case X86::VMOVDQA64Z128rm:
5716 case X86::VMOVDQU64Z128rm:
5717 case X86::VMOVAPSZ256rm:
5718 case X86::VMOVUPSZ256rm:
5719 case X86::VMOVAPSZ256rm_NOVLX:
5720 case X86::VMOVUPSZ256rm_NOVLX:
5721 case X86::VMOVAPDZ256rm:
5722 case X86::VMOVUPDZ256rm:
5723 case X86::VMOVDQU8Z256rm:
5724 case X86::VMOVDQU16Z256rm:
5725 case X86::VMOVDQA32Z256rm:
5726 case X86::VMOVDQU32Z256rm:
5727 case X86::VMOVDQA64Z256rm:
5728 case X86::VMOVDQU64Z256rm:
5729 case X86::VMOVAPSZrm:
5730 case X86::VMOVUPSZrm:
5731 case X86::VMOVAPDZrm:
5732 case X86::VMOVUPDZrm:
5733 case X86::VMOVDQU8Zrm:
5734 case X86::VMOVDQU16Zrm:
5735 case X86::VMOVDQA32Zrm:
5736 case X86::VMOVDQU32Zrm:
5737 case X86::VMOVDQA64Zrm:
5738 case X86::VMOVDQU64Zrm:
5739 case X86::KMOVBkm:
5740 case X86::KMOVWkm:
5741 case X86::KMOVDkm:
5742 case X86::KMOVQkm:
5743 break;
5744 }
5745
5746 // Lambda to check if both the loads have the same value for an operand index.
5747 auto HasSameOp = [&](int I) {
5748 return Load1->getOperand(I) == Load2->getOperand(I);
5749 };
5750
5751 // All operands except the displacement should match.
5752 if (!HasSameOp(X86::AddrBaseReg) || !HasSameOp(X86::AddrScaleAmt) ||
5753 !HasSameOp(X86::AddrIndexReg) || !HasSameOp(X86::AddrSegmentReg))
5754 return false;
5755
5756 // Chain Operand must be the same.
5757 if (!HasSameOp(5))
5758 return false;
5759
5760 // Now let's examine if the displacements are constants.
5761 auto Disp1 = dyn_cast<ConstantSDNode>(Load1->getOperand(X86::AddrDisp));
5762 auto Disp2 = dyn_cast<ConstantSDNode>(Load2->getOperand(X86::AddrDisp));
5763 if (!Disp1 || !Disp2)
5764 return false;
5765
5766 Offset1 = Disp1->getSExtValue();
5767 Offset2 = Disp2->getSExtValue();
5768 return true;
5769 }
5770
5771 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
5772 int64_t Offset1, int64_t Offset2,
5773 unsigned NumLoads) const {
5774 assert(Offset2 > Offset1);
5775 if ((Offset2 - Offset1) / 8 > 64)
5776 return false;
5777
5778 unsigned Opc1 = Load1->getMachineOpcode();
5779 unsigned Opc2 = Load2->getMachineOpcode();
5780 if (Opc1 != Opc2)
5781 return false; // FIXME: overly conservative?
5782
5783 switch (Opc1) {
5784 default: break;
5785 case X86::LD_Fp32m:
5786 case X86::LD_Fp64m:
5787 case X86::LD_Fp80m:
5788 case X86::MMX_MOVD64rm:
5789 case X86::MMX_MOVQ64rm:
5790 return false;
5791 }
5792
5793 EVT VT = Load1->getValueType(0);
5794 switch (VT.getSimpleVT().SimpleTy) {
5795 default:
5796 // XMM registers. In 64-bit mode we can be a bit more aggressive since we
5797 // have 16 of them to play with.
5798 if (Subtarget.is64Bit()) {
5799 if (NumLoads >= 3)
5800 return false;
5801 } else if (NumLoads) {
5802 return false;
5803 }
5804 break;
5805 case MVT::i8:
5806 case MVT::i16:
5807 case MVT::i32:
5808 case MVT::i64:
5809 case MVT::f32:
5810 case MVT::f64:
5811 if (NumLoads)
5812 return false;
5813 break;
5814 }
5815
5816 return true;
5817 }
5818
5819 bool X86InstrInfo::
5820 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
5821 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
5822 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
5823 Cond[0].setImm(GetOppositeBranchCondition(CC));
5824 return false;
5825 }
5826
5827 bool X86InstrInfo::
5828 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
5829 // FIXME: Return false for x87 stack register classes for now. We can't
5830 // allow any loads of these registers before FpGet_ST0_80.
5831 return !(RC == &X86::CCRRegClass || RC == &X86::DFCCRRegClass ||
5832 RC == &X86::RFP32RegClass || RC == &X86::RFP64RegClass ||
5833 RC == &X86::RFP80RegClass);
5834 }
5835
5836 /// Return a virtual register initialized with the
5837 /// the global base register value. Output instructions required to
5838 /// initialize the register in the function entry block, if necessary.
5839 ///
5840 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
5841 ///
5842 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
5843 assert((!Subtarget.is64Bit() ||
5844 MF->getTarget().getCodeModel() == CodeModel::Medium ||
5845 MF->getTarget().getCodeModel() == CodeModel::Large) &&
5846 "X86-64 PIC uses RIP relative addressing");
5847
5848 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
5849 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
5850 if (GlobalBaseReg != 0)
5851 return GlobalBaseReg;
5852
5853 // Create the register. The code to initialize it is inserted
5854 // later, by the CGBR pass (below).
5855 MachineRegisterInfo &RegInfo = MF->getRegInfo();
5856 GlobalBaseReg = RegInfo.createVirtualRegister(
5857 Subtarget.is64Bit() ? &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass);
5858 X86FI->setGlobalBaseReg(GlobalBaseReg);
5859 return GlobalBaseReg;
5860 }
5861
5862 // These are the replaceable SSE instructions. Some of these have Int variants
5863 // that we don't include here. We don't want to replace instructions selected
5864 // by intrinsics.
5865 static const uint16_t ReplaceableInstrs[][3] = {
5866 //PackedSingle PackedDouble PackedInt
5867 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr },
5868 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm },
5869 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr },
5870 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr },
5871 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm },
5872 { X86::MOVLPSmr, X86::MOVLPDmr, X86::MOVPQI2QImr },
5873 { X86::MOVSDmr, X86::MOVSDmr, X86::MOVPQI2QImr },
5874 { X86::MOVSSmr, X86::MOVSSmr, X86::MOVPDI2DImr },
5875 { X86::MOVSDrm, X86::MOVSDrm, X86::MOVQI2PQIrm },
5876 { X86::MOVSDrm_alt,X86::MOVSDrm_alt,X86::MOVQI2PQIrm },
5877 { X86::MOVSSrm, X86::MOVSSrm, X86::MOVDI2PDIrm },
5878 { X86::MOVSSrm_alt,X86::MOVSSrm_alt,X86::MOVDI2PDIrm },
5879 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr },
5880 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm },
5881 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr },
5882 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm },
5883 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr },
5884 { X86::ORPSrm, X86::ORPDrm, X86::PORrm },
5885 { X86::ORPSrr, X86::ORPDrr, X86::PORrr },
5886 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm },
5887 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr },
5888 { X86::UNPCKLPDrm, X86::UNPCKLPDrm, X86::PUNPCKLQDQrm },
5889 { X86::MOVLHPSrr, X86::UNPCKLPDrr, X86::PUNPCKLQDQrr },
5890 { X86::UNPCKHPDrm, X86::UNPCKHPDrm, X86::PUNPCKHQDQrm },
5891 { X86::UNPCKHPDrr, X86::UNPCKHPDrr, X86::PUNPCKHQDQrr },
5892 { X86::UNPCKLPSrm, X86::UNPCKLPSrm, X86::PUNPCKLDQrm },
5893 { X86::UNPCKLPSrr, X86::UNPCKLPSrr, X86::PUNPCKLDQrr },
5894 { X86::UNPCKHPSrm, X86::UNPCKHPSrm, X86::PUNPCKHDQrm },
5895 { X86::UNPCKHPSrr, X86::UNPCKHPSrr, X86::PUNPCKHDQrr },
5896 { X86::EXTRACTPSmr, X86::EXTRACTPSmr, X86::PEXTRDmr },
5897 { X86::EXTRACTPSrr, X86::EXTRACTPSrr, X86::PEXTRDrr },
5898 // AVX 128-bit support
5899 { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr },
5900 { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm },
5901 { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr },
5902 { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr },
5903 { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm },
5904 { X86::VMOVLPSmr, X86::VMOVLPDmr, X86::VMOVPQI2QImr },
5905 { X86::VMOVSDmr, X86::VMOVSDmr, X86::VMOVPQI2QImr },
5906 { X86::VMOVSSmr, X86::VMOVSSmr, X86::VMOVPDI2DImr },
5907 { X86::VMOVSDrm, X86::VMOVSDrm, X86::VMOVQI2PQIrm },
5908 { X86::VMOVSDrm_alt,X86::VMOVSDrm_alt,X86::VMOVQI2PQIrm },
5909 { X86::VMOVSSrm, X86::VMOVSSrm, X86::VMOVDI2PDIrm },
5910 { X86::VMOVSSrm_alt,X86::VMOVSSrm_alt,X86::VMOVDI2PDIrm },
5911 { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
5912 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm },
5913 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr },
5914 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm },
5915 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr },
5916 { X86::VORPSrm, X86::VORPDrm, X86::VPORrm },
5917 { X86::VORPSrr, X86::VORPDrr, X86::VPORrr },
5918 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm },
5919 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr },
5920 { X86::VUNPCKLPDrm, X86::VUNPCKLPDrm, X86::VPUNPCKLQDQrm },
5921 { X86::VMOVLHPSrr, X86::VUNPCKLPDrr, X86::VPUNPCKLQDQrr },
5922 { X86::VUNPCKHPDrm, X86::VUNPCKHPDrm, X86::VPUNPCKHQDQrm },
5923 { X86::VUNPCKHPDrr, X86::VUNPCKHPDrr, X86::VPUNPCKHQDQrr },
5924 { X86::VUNPCKLPSrm, X86::VUNPCKLPSrm, X86::VPUNPCKLDQrm },
5925 { X86::VUNPCKLPSrr, X86::VUNPCKLPSrr, X86::VPUNPCKLDQrr },
5926 { X86::VUNPCKHPSrm, X86::VUNPCKHPSrm, X86::VPUNPCKHDQrm },
5927 { X86::VUNPCKHPSrr, X86::VUNPCKHPSrr, X86::VPUNPCKHDQrr },
5928 { X86::VEXTRACTPSmr, X86::VEXTRACTPSmr, X86::VPEXTRDmr },
5929 { X86::VEXTRACTPSrr, X86::VEXTRACTPSrr, X86::VPEXTRDrr },
5930 // AVX 256-bit support
5931 { X86::VMOVAPSYmr, X86::VMOVAPDYmr, X86::VMOVDQAYmr },
5932 { X86::VMOVAPSYrm, X86::VMOVAPDYrm, X86::VMOVDQAYrm },
5933 { X86::VMOVAPSYrr, X86::VMOVAPDYrr, X86::VMOVDQAYrr },
5934 { X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr },
5935 { X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm },
5936 { X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr },
5937 { X86::VPERMPSYrm, X86::VPERMPSYrm, X86::VPERMDYrm },
5938 { X86::VPERMPSYrr, X86::VPERMPSYrr, X86::VPERMDYrr },
5939 { X86::VPERMPDYmi, X86::VPERMPDYmi, X86::VPERMQYmi },
5940 { X86::VPERMPDYri, X86::VPERMPDYri, X86::VPERMQYri },
5941 // AVX512 support
5942 { X86::VMOVLPSZ128mr, X86::VMOVLPDZ128mr, X86::VMOVPQI2QIZmr },
5943 { X86::VMOVNTPSZ128mr, X86::VMOVNTPDZ128mr, X86::VMOVNTDQZ128mr },
5944 { X86::VMOVNTPSZ256mr, X86::VMOVNTPDZ256mr, X86::VMOVNTDQZ256mr },
5945 { X86::VMOVNTPSZmr, X86::VMOVNTPDZmr, X86::VMOVNTDQZmr },
5946 { X86::VMOVSDZmr, X86::VMOVSDZmr, X86::VMOVPQI2QIZmr },
5947 { X86::VMOVSSZmr, X86::VMOVSSZmr, X86::VMOVPDI2DIZmr },
5948 { X86::VMOVSDZrm, X86::VMOVSDZrm, X86::VMOVQI2PQIZrm },
5949 { X86::VMOVSDZrm_alt, X86::VMOVSDZrm_alt, X86::VMOVQI2PQIZrm },
5950 { X86::VMOVSSZrm, X86::VMOVSSZrm, X86::VMOVDI2PDIZrm },
5951 { X86::VMOVSSZrm_alt, X86::VMOVSSZrm_alt, X86::VMOVDI2PDIZrm },
5952 { X86::VBROADCASTSSZ128r, X86::VBROADCASTSSZ128r, X86::VPBROADCASTDZ128r },
5953 { X86::VBROADCASTSSZ128m, X86::VBROADCASTSSZ128m, X86::VPBROADCASTDZ128m },
5954 { X86::VBROADCASTSSZ256r, X86::VBROADCASTSSZ256r, X86::VPBROADCASTDZ256r },
5955 { X86::VBROADCASTSSZ256m, X86::VBROADCASTSSZ256m, X86::VPBROADCASTDZ256m },
5956 { X86::VBROADCASTSSZr, X86::VBROADCASTSSZr, X86::VPBROADCASTDZr },
5957 { X86::VBROADCASTSSZm, X86::VBROADCASTSSZm, X86::VPBROADCASTDZm },
5958 { X86::VMOVDDUPZ128rr, X86::VMOVDDUPZ128rr, X86::VPBROADCASTQZ128r },
5959 { X86::VMOVDDUPZ128rm, X86::VMOVDDUPZ128rm, X86::VPBROADCASTQZ128m },
5960 { X86::VBROADCASTSDZ256r, X86::VBROADCASTSDZ256r, X86::VPBROADCASTQZ256r },
5961 { X86::VBROADCASTSDZ256m, X86::VBROADCASTSDZ256m, X86::VPBROADCASTQZ256m },
5962 { X86::VBROADCASTSDZr, X86::VBROADCASTSDZr, X86::VPBROADCASTQZr },
5963 { X86::VBROADCASTSDZm, X86::VBROADCASTSDZm, X86::VPBROADCASTQZm },
5964 { X86::VINSERTF32x4Zrr, X86::VINSERTF32x4Zrr, X86::VINSERTI32x4Zrr },
5965 { X86::VINSERTF32x4Zrm, X86::VINSERTF32x4Zrm, X86::VINSERTI32x4Zrm },
5966 { X86::VINSERTF32x8Zrr, X86::VINSERTF32x8Zrr, X86::VINSERTI32x8Zrr },
5967 { X86::VINSERTF32x8Zrm, X86::VINSERTF32x8Zrm, X86::VINSERTI32x8Zrm },
5968 { X86::VINSERTF64x2Zrr, X86::VINSERTF64x2Zrr, X86::VINSERTI64x2Zrr },
5969 { X86::VINSERTF64x2Zrm, X86::VINSERTF64x2Zrm, X86::VINSERTI64x2Zrm },
5970 { X86::VINSERTF64x4Zrr, X86::VINSERTF64x4Zrr, X86::VINSERTI64x4Zrr },
5971 { X86::VINSERTF64x4Zrm, X86::VINSERTF64x4Zrm, X86::VINSERTI64x4Zrm },
5972 { X86::VINSERTF32x4Z256rr,X86::VINSERTF32x4Z256rr,X86::VINSERTI32x4Z256rr },
5973 { X86::VINSERTF32x4Z256rm,X86::VINSERTF32x4Z256rm,X86::VINSERTI32x4Z256rm },
5974 { X86::VINSERTF64x2Z256rr,X86::VINSERTF64x2Z256rr,X86::VINSERTI64x2Z256rr },
5975 { X86::VINSERTF64x2Z256rm,X86::VINSERTF64x2Z256rm,X86::VINSERTI64x2Z256rm },
5976 { X86::VEXTRACTF32x4Zrr, X86::VEXTRACTF32x4Zrr, X86::VEXTRACTI32x4Zrr },
5977 { X86::VEXTRACTF32x4Zmr, X86::VEXTRACTF32x4Zmr, X86::VEXTRACTI32x4Zmr },
5978 { X86::VEXTRACTF32x8Zrr, X86::VEXTRACTF32x8Zrr, X86::VEXTRACTI32x8Zrr },
5979 { X86::VEXTRACTF32x8Zmr, X86::VEXTRACTF32x8Zmr, X86::VEXTRACTI32x8Zmr },
5980 { X86::VEXTRACTF64x2Zrr, X86::VEXTRACTF64x2Zrr, X86::VEXTRACTI64x2Zrr },
5981 { X86::VEXTRACTF64x2Zmr, X86::VEXTRACTF64x2Zmr, X86::VEXTRACTI64x2Zmr },
5982 { X86::VEXTRACTF64x4Zrr, X86::VEXTRACTF64x4Zrr, X86::VEXTRACTI64x4Zrr },
5983 { X86::VEXTRACTF64x4Zmr, X86::VEXTRACTF64x4Zmr, X86::VEXTRACTI64x4Zmr },
5984 { X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTI32x4Z256rr },
5985 { X86::VEXTRACTF32x4Z256mr,X86::VEXTRACTF32x4Z256mr,X86::VEXTRACTI32x4Z256mr },
5986 { X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTI64x2Z256rr },
5987 { X86::VEXTRACTF64x2Z256mr,X86::VEXTRACTF64x2Z256mr,X86::VEXTRACTI64x2Z256mr },
5988 { X86::VPERMILPSmi, X86::VPERMILPSmi, X86::VPSHUFDmi },
5989 { X86::VPERMILPSri, X86::VPERMILPSri, X86::VPSHUFDri },
5990 { X86::VPERMILPSZ128mi, X86::VPERMILPSZ128mi, X86::VPSHUFDZ128mi },
5991 { X86::VPERMILPSZ128ri, X86::VPERMILPSZ128ri, X86::VPSHUFDZ128ri },
5992 { X86::VPERMILPSZ256mi, X86::VPERMILPSZ256mi, X86::VPSHUFDZ256mi },
5993 { X86::VPERMILPSZ256ri, X86::VPERMILPSZ256ri, X86::VPSHUFDZ256ri },
5994 { X86::VPERMILPSZmi, X86::VPERMILPSZmi, X86::VPSHUFDZmi },
5995 { X86::VPERMILPSZri, X86::VPERMILPSZri, X86::VPSHUFDZri },
5996 { X86::VPERMPSZ256rm, X86::VPERMPSZ256rm, X86::VPERMDZ256rm },
5997 { X86::VPERMPSZ256rr, X86::VPERMPSZ256rr, X86::VPERMDZ256rr },
5998 { X86::VPERMPDZ256mi, X86::VPERMPDZ256mi, X86::VPERMQZ256mi },
5999 { X86::VPERMPDZ256ri, X86::VPERMPDZ256ri, X86::VPERMQZ256ri },
6000 { X86::VPERMPDZ256rm, X86::VPERMPDZ256rm, X86::VPERMQZ256rm },
6001 { X86::VPERMPDZ256rr, X86::VPERMPDZ256rr, X86::VPERMQZ256rr },
6002 { X86::VPERMPSZrm, X86::VPERMPSZrm, X86::VPERMDZrm },
6003 { X86::VPERMPSZrr, X86::VPERMPSZrr, X86::VPERMDZrr },
6004 { X86::VPERMPDZmi, X86::VPERMPDZmi, X86::VPERMQZmi },
6005 { X86::VPERMPDZri, X86::VPERMPDZri, X86::VPERMQZri },
6006 { X86::VPERMPDZrm, X86::VPERMPDZrm, X86::VPERMQZrm },
6007 { X86::VPERMPDZrr, X86::VPERMPDZrr, X86::VPERMQZrr },
6008 { X86::VUNPCKLPDZ256rm, X86::VUNPCKLPDZ256rm, X86::VPUNPCKLQDQZ256rm },
6009 { X86::VUNPCKLPDZ256rr, X86::VUNPCKLPDZ256rr, X86::VPUNPCKLQDQZ256rr },
6010 { X86::VUNPCKHPDZ256rm, X86::VUNPCKHPDZ256rm, X86::VPUNPCKHQDQZ256rm },
6011 { X86::VUNPCKHPDZ256rr, X86::VUNPCKHPDZ256rr, X86::VPUNPCKHQDQZ256rr },
6012 { X86::VUNPCKLPSZ256rm, X86::VUNPCKLPSZ256rm, X86::VPUNPCKLDQZ256rm },
6013 { X86::VUNPCKLPSZ256rr, X86::VUNPCKLPSZ256rr, X86::VPUNPCKLDQZ256rr },
6014 { X86::VUNPCKHPSZ256rm, X86::VUNPCKHPSZ256rm, X86::VPUNPCKHDQZ256rm },
6015 { X86::VUNPCKHPSZ256rr, X86::VUNPCKHPSZ256rr, X86::VPUNPCKHDQZ256rr },
6016 { X86::VUNPCKLPDZ128rm, X86::VUNPCKLPDZ128rm, X86::VPUNPCKLQDQZ128rm },
6017 { X86::VMOVLHPSZrr, X86::VUNPCKLPDZ128rr, X86::VPUNPCKLQDQZ128rr },
6018 { X86::VUNPCKHPDZ128rm, X86::VUNPCKHPDZ128rm, X86::VPUNPCKHQDQZ128rm },
6019 { X86::VUNPCKHPDZ128rr, X86::VUNPCKHPDZ128rr, X86::VPUNPCKHQDQZ128rr },
6020 { X86::VUNPCKLPSZ128rm, X86::VUNPCKLPSZ128rm, X86::VPUNPCKLDQZ128rm },
6021 { X86::VUNPCKLPSZ128rr, X86::VUNPCKLPSZ128rr, X86::VPUNPCKLDQZ128rr },
6022 { X86::VUNPCKHPSZ128rm, X86::VUNPCKHPSZ128rm, X86::VPUNPCKHDQZ128rm },
6023 { X86::VUNPCKHPSZ128rr, X86::VUNPCKHPSZ128rr, X86::VPUNPCKHDQZ128rr },
6024 { X86::VUNPCKLPDZrm, X86::VUNPCKLPDZrm, X86::VPUNPCKLQDQZrm },
6025 { X86::VUNPCKLPDZrr, X86::VUNPCKLPDZrr, X86::VPUNPCKLQDQZrr },
6026 { X86::VUNPCKHPDZrm, X86::VUNPCKHPDZrm, X86::VPUNPCKHQDQZrm },
6027 { X86::VUNPCKHPDZrr, X86::VUNPCKHPDZrr, X86::VPUNPCKHQDQZrr },
6028 { X86::VUNPCKLPSZrm, X86::VUNPCKLPSZrm, X86::VPUNPCKLDQZrm },
6029 { X86::VUNPCKLPSZrr, X86::VUNPCKLPSZrr, X86::VPUNPCKLDQZrr },
6030 { X86::VUNPCKHPSZrm, X86::VUNPCKHPSZrm, X86::VPUNPCKHDQZrm },
6031 { X86::VUNPCKHPSZrr, X86::VUNPCKHPSZrr, X86::VPUNPCKHDQZrr },
6032 { X86::VEXTRACTPSZmr, X86::VEXTRACTPSZmr, X86::VPEXTRDZmr },
6033 { X86::VEXTRACTPSZrr, X86::VEXTRACTPSZrr, X86::VPEXTRDZrr },
6034 };
6035
6036 static const uint16_t ReplaceableInstrsAVX2[][3] = {
6037 //PackedSingle PackedDouble PackedInt
6038 { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNYrm },
6039 { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNYrr },
6040 { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDYrm },
6041 { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDYrr },
6042 { X86::VORPSYrm, X86::VORPDYrm, X86::VPORYrm },
6043 { X86::VORPSYrr, X86::VORPDYrr, X86::VPORYrr },
6044 { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORYrm },
6045 { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORYrr },
6046 { X86::VPERM2F128rm, X86::VPERM2F128rm, X86::VPERM2I128rm },
6047 { X86::VPERM2F128rr, X86::VPERM2F128rr, X86::VPERM2I128rr },
6048 { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
6049 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
6050 { X86::VMOVDDUPrm, X86::VMOVDDUPrm, X86::VPBROADCASTQrm},
6051 { X86::VMOVDDUPrr, X86::VMOVDDUPrr, X86::VPBROADCASTQrr},
6052 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
6053 { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
6054 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
6055 { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm},
6056 { X86::VBROADCASTF128, X86::VBROADCASTF128, X86::VBROADCASTI128 },
6057 { X86::VBLENDPSYrri, X86::VBLENDPSYrri, X86::VPBLENDDYrri },
6058 { X86::VBLENDPSYrmi, X86::VBLENDPSYrmi, X86::VPBLENDDYrmi },
6059 { X86::VPERMILPSYmi, X86::VPERMILPSYmi, X86::VPSHUFDYmi },
6060 { X86::VPERMILPSYri, X86::VPERMILPSYri, X86::VPSHUFDYri },
6061 { X86::VUNPCKLPDYrm, X86::VUNPCKLPDYrm, X86::VPUNPCKLQDQYrm },
6062 { X86::VUNPCKLPDYrr, X86::VUNPCKLPDYrr, X86::VPUNPCKLQDQYrr },
6063 { X86::VUNPCKHPDYrm, X86::VUNPCKHPDYrm, X86::VPUNPCKHQDQYrm },
6064 { X86::VUNPCKHPDYrr, X86::VUNPCKHPDYrr, X86::VPUNPCKHQDQYrr },
6065 { X86::VUNPCKLPSYrm, X86::VUNPCKLPSYrm, X86::VPUNPCKLDQYrm },
6066 { X86::VUNPCKLPSYrr, X86::VUNPCKLPSYrr, X86::VPUNPCKLDQYrr },
6067 { X86::VUNPCKHPSYrm, X86::VUNPCKHPSYrm, X86::VPUNPCKHDQYrm },
6068 { X86::VUNPCKHPSYrr, X86::VUNPCKHPSYrr, X86::VPUNPCKHDQYrr },
6069 };
6070
6071 static const uint16_t ReplaceableInstrsFP[][3] = {
6072 //PackedSingle PackedDouble
6073 { X86::MOVLPSrm, X86::MOVLPDrm, X86::INSTRUCTION_LIST_END },
6074 { X86::MOVHPSrm, X86::MOVHPDrm, X86::INSTRUCTION_LIST_END },
6075 { X86::MOVHPSmr, X86::MOVHPDmr, X86::INSTRUCTION_LIST_END },
6076 { X86::VMOVLPSrm, X86::VMOVLPDrm, X86::INSTRUCTION_LIST_END },
6077 { X86::VMOVHPSrm, X86::VMOVHPDrm, X86::INSTRUCTION_LIST_END },
6078 { X86::VMOVHPSmr, X86::VMOVHPDmr, X86::INSTRUCTION_LIST_END },
6079 { X86::VMOVLPSZ128rm, X86::VMOVLPDZ128rm, X86::INSTRUCTION_LIST_END },
6080 { X86::VMOVHPSZ128rm, X86::VMOVHPDZ128rm, X86::INSTRUCTION_LIST_END },
6081 { X86::VMOVHPSZ128mr, X86::VMOVHPDZ128mr, X86::INSTRUCTION_LIST_END },
6082 };
6083
6084 static const uint16_t ReplaceableInstrsAVX2InsertExtract[][3] = {
6085 //PackedSingle PackedDouble PackedInt
6086 { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
6087 { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
6088 { X86::VINSERTF128rm, X86::VINSERTF128rm, X86::VINSERTI128rm },
6089 { X86::VINSERTF128rr, X86::VINSERTF128rr, X86::VINSERTI128rr },
6090 };
6091
6092 static const uint16_t ReplaceableInstrsAVX512[][4] = {
6093 // Two integer columns for 64-bit and 32-bit elements.
6094 //PackedSingle PackedDouble PackedInt PackedInt
6095 { X86::VMOVAPSZ128mr, X86::VMOVAPDZ128mr, X86::VMOVDQA64Z128mr, X86::VMOVDQA32Z128mr },
6096 { X86::VMOVAPSZ128rm, X86::VMOVAPDZ128rm, X86::VMOVDQA64Z128rm, X86::VMOVDQA32Z128rm },
6097 { X86::VMOVAPSZ128rr, X86::VMOVAPDZ128rr, X86::VMOVDQA64Z128rr, X86::VMOVDQA32Z128rr },
6098 { X86::VMOVUPSZ128mr, X86::VMOVUPDZ128mr, X86::VMOVDQU64Z128mr, X86::VMOVDQU32Z128mr },
6099 { X86::VMOVUPSZ128rm, X86::VMOVUPDZ128rm, X86::VMOVDQU64Z128rm, X86::VMOVDQU32Z128rm },
6100 { X86::VMOVAPSZ256mr, X86::VMOVAPDZ256mr, X86::VMOVDQA64Z256mr, X86::VMOVDQA32Z256mr },
6101 { X86::VMOVAPSZ256rm, X86::VMOVAPDZ256rm, X86::VMOVDQA64Z256rm, X86::VMOVDQA32Z256rm },
6102 { X86::VMOVAPSZ256rr, X86::VMOVAPDZ256rr, X86::VMOVDQA64Z256rr, X86::VMOVDQA32Z256rr },
6103 { X86::VMOVUPSZ256mr, X86::VMOVUPDZ256mr, X86::VMOVDQU64Z256mr, X86::VMOVDQU32Z256mr },
6104 { X86::VMOVUPSZ256rm, X86::VMOVUPDZ256rm, X86::VMOVDQU64Z256rm, X86::VMOVDQU32Z256rm },
6105 { X86::VMOVAPSZmr, X86::VMOVAPDZmr, X86::VMOVDQA64Zmr, X86::VMOVDQA32Zmr },
6106 { X86::VMOVAPSZrm, X86::VMOVAPDZrm, X86::VMOVDQA64Zrm, X86::VMOVDQA32Zrm },
6107 { X86::VMOVAPSZrr, X86::VMOVAPDZrr, X86::VMOVDQA64Zrr, X86::VMOVDQA32Zrr },
6108 { X86::VMOVUPSZmr, X86::VMOVUPDZmr, X86::VMOVDQU64Zmr, X86::VMOVDQU32Zmr },
6109 { X86::VMOVUPSZrm, X86::VMOVUPDZrm, X86::VMOVDQU64Zrm, X86::VMOVDQU32Zrm },
6110 };
6111
6112 static const uint16_t ReplaceableInstrsAVX512DQ[][4] = {
6113 // Two integer columns for 64-bit and 32-bit elements.
6114 //PackedSingle PackedDouble PackedInt PackedInt
6115 { X86::VANDNPSZ128rm, X86::VANDNPDZ128rm, X86::VPANDNQZ128rm, X86::VPANDNDZ128rm },
6116 { X86::VANDNPSZ128rr, X86::VANDNPDZ128rr, X86::VPANDNQZ128rr, X86::VPANDNDZ128rr },
6117 { X86::VANDPSZ128rm, X86::VANDPDZ128rm, X86::VPANDQZ128rm, X86::VPANDDZ128rm },
6118 { X86::VANDPSZ128rr, X86::VANDPDZ128rr, X86::VPANDQZ128rr, X86::VPANDDZ128rr },
6119 { X86::VORPSZ128rm, X86::VORPDZ128rm, X86::VPORQZ128rm, X86::VPORDZ128rm },
6120 { X86::VORPSZ128rr, X86::VORPDZ128rr, X86::VPORQZ128rr, X86::VPORDZ128rr },
6121 { X86::VXORPSZ128rm, X86::VXORPDZ128rm, X86::VPXORQZ128rm, X86::VPXORDZ128rm },
6122 { X86::VXORPSZ128rr, X86::VXORPDZ128rr, X86::VPXORQZ128rr, X86::VPXORDZ128rr },
6123 { X86::VANDNPSZ256rm, X86::VANDNPDZ256rm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm },
6124 { X86::VANDNPSZ256rr, X86::VANDNPDZ256rr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr },
6125 { X86::VANDPSZ256rm, X86::VANDPDZ256rm, X86::VPANDQZ256rm, X86::VPANDDZ256rm },
6126 { X86::VANDPSZ256rr, X86::VANDPDZ256rr, X86::VPANDQZ256rr, X86::VPANDDZ256rr },
6127 { X86::VORPSZ256rm, X86::VORPDZ256rm, X86::VPORQZ256rm, X86::VPORDZ256rm },
6128 { X86::VORPSZ256rr, X86::VORPDZ256rr, X86::VPORQZ256rr, X86::VPORDZ256rr },
6129 { X86::VXORPSZ256rm, X86::VXORPDZ256rm, X86::VPXORQZ256rm, X86::VPXORDZ256rm },
6130 { X86::VXORPSZ256rr, X86::VXORPDZ256rr, X86::VPXORQZ256rr, X86::VPXORDZ256rr },
6131 { X86::VANDNPSZrm, X86::VANDNPDZrm, X86::VPANDNQZrm, X86::VPANDNDZrm },
6132 { X86::VANDNPSZrr, X86::VANDNPDZrr, X86::VPANDNQZrr, X86::VPANDNDZrr },
6133 { X86::VANDPSZrm, X86::VANDPDZrm, X86::VPANDQZrm, X86::VPANDDZrm },
6134 { X86::VANDPSZrr, X86::VANDPDZrr, X86::VPANDQZrr, X86::VPANDDZrr },
6135 { X86::VORPSZrm, X86::VORPDZrm, X86::VPORQZrm, X86::VPORDZrm },
6136 { X86::VORPSZrr, X86::VORPDZrr, X86::VPORQZrr, X86::VPORDZrr },
6137 { X86::VXORPSZrm, X86::VXORPDZrm, X86::VPXORQZrm, X86::VPXORDZrm },
6138 { X86::VXORPSZrr, X86::VXORPDZrr, X86::VPXORQZrr, X86::VPXORDZrr },
6139 };
6140
6141 static const uint16_t ReplaceableInstrsAVX512DQMasked[][4] = {
6142 // Two integer columns for 64-bit and 32-bit elements.
6143 //PackedSingle PackedDouble
6144 //PackedInt PackedInt
6145 { X86::VANDNPSZ128rmk, X86::VANDNPDZ128rmk,
6146 X86::VPANDNQZ128rmk, X86::VPANDNDZ128rmk },
6147 { X86::VANDNPSZ128rmkz, X86::VANDNPDZ128rmkz,
6148 X86::VPANDNQZ128rmkz, X86::VPANDNDZ128rmkz },
6149 { X86::VANDNPSZ128rrk, X86::VANDNPDZ128rrk,
6150 X86::VPANDNQZ128rrk, X86::VPANDNDZ128rrk },
6151 { X86::VANDNPSZ128rrkz, X86::VANDNPDZ128rrkz,
6152 X86::VPANDNQZ128rrkz, X86::VPANDNDZ128rrkz },
6153 { X86::VANDPSZ128rmk, X86::VANDPDZ128rmk,
6154 X86::VPANDQZ128rmk, X86::VPANDDZ128rmk },
6155 { X86::VANDPSZ128rmkz, X86::VANDPDZ128rmkz,
6156 X86::VPANDQZ128rmkz, X86::VPANDDZ128rmkz },
6157 { X86::VANDPSZ128rrk, X86::VANDPDZ128rrk,
6158 X86::VPANDQZ128rrk, X86::VPANDDZ128rrk },
6159 { X86::VANDPSZ128rrkz, X86::VANDPDZ128rrkz,
6160 X86::VPANDQZ128rrkz, X86::VPANDDZ128rrkz },
6161 { X86::VORPSZ128rmk, X86::VORPDZ128rmk,
6162 X86::VPORQZ128rmk, X86::VPORDZ128rmk },
6163 { X86::VORPSZ128rmkz, X86::VORPDZ128rmkz,
6164 X86::VPORQZ128rmkz, X86::VPORDZ128rmkz },
6165 { X86::VORPSZ128rrk, X86::VORPDZ128rrk,
6166 X86::VPORQZ128rrk, X86::VPORDZ128rrk },
6167 { X86::VORPSZ128rrkz, X86::VORPDZ128rrkz,
6168 X86::VPORQZ128rrkz, X86::VPORDZ128rrkz },
6169 { X86::VXORPSZ128rmk, X86::VXORPDZ128rmk,
6170 X86::VPXORQZ128rmk, X86::VPXORDZ128rmk },
6171 { X86::VXORPSZ128rmkz, X86::VXORPDZ128rmkz,
6172 X86::VPXORQZ128rmkz, X86::VPXORDZ128rmkz },
6173 { X86::VXORPSZ128rrk, X86::VXORPDZ128rrk,
6174 X86::VPXORQZ128rrk, X86::VPXORDZ128rrk },
6175 { X86::VXORPSZ128rrkz, X86::VXORPDZ128rrkz,
6176 X86::VPXORQZ128rrkz, X86::VPXORDZ128rrkz },
6177 { X86::VANDNPSZ256rmk, X86::VANDNPDZ256rmk,
6178 X86::VPANDNQZ256rmk, X86::VPANDNDZ256rmk },
6179 { X86::VANDNPSZ256rmkz, X86::VANDNPDZ256rmkz,
6180 X86::VPANDNQZ256rmkz, X86::VPANDNDZ256rmkz },
6181 { X86::VANDNPSZ256rrk, X86::VANDNPDZ256rrk,
6182 X86::VPANDNQZ256rrk, X86::VPANDNDZ256rrk },
6183 { X86::VANDNPSZ256rrkz, X86::VANDNPDZ256rrkz,
6184 X86::VPANDNQZ256rrkz, X86::VPANDNDZ256rrkz },
6185 { X86::VANDPSZ256rmk, X86::VANDPDZ256rmk,
6186 X86::VPANDQZ256rmk, X86::VPANDDZ256rmk },
6187 { X86::VANDPSZ256rmkz, X86::VANDPDZ256rmkz,
6188 X86::VPANDQZ256rmkz, X86::VPANDDZ256rmkz },
6189 { X86::VANDPSZ256rrk, X86::VANDPDZ256rrk,
6190 X86::VPANDQZ256rrk, X86::VPANDDZ256rrk },
6191 { X86::VANDPSZ256rrkz, X86::VANDPDZ256rrkz,
6192 X86::VPANDQZ256rrkz, X86::VPANDDZ256rrkz },
6193 { X86::VORPSZ256rmk, X86::VORPDZ256rmk,
6194 X86::VPORQZ256rmk, X86::VPORDZ256rmk },
6195 { X86::VORPSZ256rmkz, X86::VORPDZ256rmkz,
6196 X86::VPORQZ256rmkz, X86::VPORDZ256rmkz },
6197 { X86::VORPSZ256rrk, X86::VORPDZ256rrk,
6198 X86::VPORQZ256rrk, X86::VPORDZ256rrk },
6199 { X86::VORPSZ256rrkz, X86::VORPDZ256rrkz,
6200 X86::VPORQZ256rrkz, X86::VPORDZ256rrkz },
6201 { X86::VXORPSZ256rmk, X86::VXORPDZ256rmk,
6202 X86::VPXORQZ256rmk, X86::VPXORDZ256rmk },
6203 { X86::VXORPSZ256rmkz, X86::VXORPDZ256rmkz,
6204 X86::VPXORQZ256rmkz, X86::VPXORDZ256rmkz },
6205 { X86::VXORPSZ256rrk, X86::VXORPDZ256rrk,
6206 X86::VPXORQZ256rrk, X86::VPXORDZ256rrk },
6207 { X86::VXORPSZ256rrkz, X86::VXORPDZ256rrkz,
6208 X86::VPXORQZ256rrkz, X86::VPXORDZ256rrkz },
6209 { X86::VANDNPSZrmk, X86::VANDNPDZrmk,
6210 X86::VPANDNQZrmk, X86::VPANDNDZrmk },
6211 { X86::VANDNPSZrmkz, X86::VANDNPDZrmkz,
6212 X86::VPANDNQZrmkz, X86::VPANDNDZrmkz },
6213 { X86::VANDNPSZrrk, X86::VANDNPDZrrk,
6214 X86::VPANDNQZrrk, X86::VPANDNDZrrk },
6215 { X86::VANDNPSZrrkz, X86::VANDNPDZrrkz,
6216 X86::VPANDNQZrrkz, X86::VPANDNDZrrkz },
6217 { X86::VANDPSZrmk, X86::VANDPDZrmk,
6218 X86::VPANDQZrmk, X86::VPANDDZrmk },
6219 { X86::VANDPSZrmkz, X86::VANDPDZrmkz,
6220 X86::VPANDQZrmkz, X86::VPANDDZrmkz },
6221 { X86::VANDPSZrrk, X86::VANDPDZrrk,
6222 X86::VPANDQZrrk, X86::VPANDDZrrk },
6223 { X86::VANDPSZrrkz, X86::VANDPDZrrkz,
6224 X86::VPANDQZrrkz, X86::VPANDDZrrkz },
6225 { X86::VORPSZrmk, X86::VORPDZrmk,
6226 X86::VPORQZrmk, X86::VPORDZrmk },
6227 { X86::VORPSZrmkz, X86::VORPDZrmkz,
6228 X86::VPORQZrmkz, X86::VPORDZrmkz },
6229 { X86::VORPSZrrk, X86::VORPDZrrk,
6230 X86::VPORQZrrk, X86::VPORDZrrk },
6231 { X86::VORPSZrrkz, X86::VORPDZrrkz,
6232 X86::VPORQZrrkz, X86::VPORDZrrkz },
6233 { X86::VXORPSZrmk, X86::VXORPDZrmk,
6234 X86::VPXORQZrmk, X86::VPXORDZrmk },
6235 { X86::VXORPSZrmkz, X86::VXORPDZrmkz,
6236 X86::VPXORQZrmkz, X86::VPXORDZrmkz },
6237 { X86::VXORPSZrrk, X86::VXORPDZrrk,
6238 X86::VPXORQZrrk, X86::VPXORDZrrk },
6239 { X86::VXORPSZrrkz, X86::VXORPDZrrkz,
6240 X86::VPXORQZrrkz, X86::VPXORDZrrkz },
6241 // Broadcast loads can be handled the same as masked operations to avoid
6242 // changing element size.
6243 { X86::VANDNPSZ128rmb, X86::VANDNPDZ128rmb,
6244 X86::VPANDNQZ128rmb, X86::VPANDNDZ128rmb },
6245 { X86::VANDPSZ128rmb, X86::VANDPDZ128rmb,
6246 X86::VPANDQZ128rmb, X86::VPANDDZ128rmb },
6247 { X86::VORPSZ128rmb, X86::VORPDZ128rmb,
6248 X86::VPORQZ128rmb, X86::VPORDZ128rmb },
6249 { X86::VXORPSZ128rmb, X86::VXORPDZ128rmb,
6250 X86::VPXORQZ128rmb, X86::VPXORDZ128rmb },
6251 { X86::VANDNPSZ256rmb, X86::VANDNPDZ256rmb,
6252 X86::VPANDNQZ256rmb, X86::VPANDNDZ256rmb },
6253 { X86::VANDPSZ256rmb, X86::VANDPDZ256rmb,
6254 X86::VPANDQZ256rmb, X86::VPANDDZ256rmb },
6255 { X86::VORPSZ256rmb, X86::VORPDZ256rmb,
6256 X86::VPORQZ256rmb, X86::VPORDZ256rmb },
6257 { X86::VXORPSZ256rmb, X86::VXORPDZ256rmb,
6258 X86::VPXORQZ256rmb, X86::VPXORDZ256rmb },
6259 { X86::VANDNPSZrmb, X86::VANDNPDZrmb,
6260 X86::VPANDNQZrmb, X86::VPANDNDZrmb },
6261 { X86::VANDPSZrmb, X86::VANDPDZrmb,
6262 X86::VPANDQZrmb, X86::VPANDDZrmb },
6263 { X86::VANDPSZrmb, X86::VANDPDZrmb,
6264 X86::VPANDQZrmb, X86::VPANDDZrmb },
6265 { X86::VORPSZrmb, X86::VORPDZrmb,
6266 X86::VPORQZrmb, X86::VPORDZrmb },
6267 { X86::VXORPSZrmb, X86::VXORPDZrmb,
6268 X86::VPXORQZrmb, X86::VPXORDZrmb },
6269 { X86::VANDNPSZ128rmbk, X86::VANDNPDZ128rmbk,
6270 X86::VPANDNQZ128rmbk, X86::VPANDNDZ128rmbk },
6271 { X86::VANDPSZ128rmbk, X86::VANDPDZ128rmbk,
6272 X86::VPANDQZ128rmbk, X86::VPANDDZ128rmbk },
6273 { X86::VORPSZ128rmbk, X86::VORPDZ128rmbk,
6274 X86::VPORQZ128rmbk, X86::VPORDZ128rmbk },
6275 { X86::VXORPSZ128rmbk, X86::VXORPDZ128rmbk,
6276 X86::VPXORQZ128rmbk, X86::VPXORDZ128rmbk },
6277 { X86::VANDNPSZ256rmbk, X86::VANDNPDZ256rmbk,
6278 X86::VPANDNQZ256rmbk, X86::VPANDNDZ256rmbk },
6279 { X86::VANDPSZ256rmbk, X86::VANDPDZ256rmbk,
6280 X86::VPANDQZ256rmbk, X86::VPANDDZ256rmbk },
6281 { X86::VORPSZ256rmbk, X86::VORPDZ256rmbk,
6282 X86::VPORQZ256rmbk, X86::VPORDZ256rmbk },
6283 { X86::VXORPSZ256rmbk, X86::VXORPDZ256rmbk,
6284 X86::VPXORQZ256rmbk, X86::VPXORDZ256rmbk },
6285 { X86::VANDNPSZrmbk, X86::VANDNPDZrmbk,
6286 X86::VPANDNQZrmbk, X86::VPANDNDZrmbk },
6287 { X86::VANDPSZrmbk, X86::VANDPDZrmbk,
6288 X86::VPANDQZrmbk, X86::VPANDDZrmbk },
6289 { X86::VANDPSZrmbk, X86::VANDPDZrmbk,
6290 X86::VPANDQZrmbk, X86::VPANDDZrmbk },
6291 { X86::VORPSZrmbk, X86::VORPDZrmbk,
6292 X86::VPORQZrmbk, X86::VPORDZrmbk },
6293 { X86::VXORPSZrmbk, X86::VXORPDZrmbk,
6294 X86::VPXORQZrmbk, X86::VPXORDZrmbk },
6295 { X86::VANDNPSZ128rmbkz,X86::VANDNPDZ128rmbkz,
6296 X86::VPANDNQZ128rmbkz,X86::VPANDNDZ128rmbkz},
6297 { X86::VANDPSZ128rmbkz, X86::VANDPDZ128rmbkz,
6298 X86::VPANDQZ128rmbkz, X86::VPANDDZ128rmbkz },
6299 { X86::VORPSZ128rmbkz, X86::VORPDZ128rmbkz,
6300 X86::VPORQZ128rmbkz, X86::VPORDZ128rmbkz },
6301 { X86::VXORPSZ128rmbkz, X86::VXORPDZ128rmbkz,
6302 X86::VPXORQZ128rmbkz, X86::VPXORDZ128rmbkz },
6303 { X86::VANDNPSZ256rmbkz,X86::VANDNPDZ256rmbkz,
6304 X86::VPANDNQZ256rmbkz,X86::VPANDNDZ256rmbkz},
6305 { X86::VANDPSZ256rmbkz, X86::VANDPDZ256rmbkz,
6306 X86::VPANDQZ256rmbkz, X86::VPANDDZ256rmbkz },
6307 { X86::VORPSZ256rmbkz, X86::VORPDZ256rmbkz,
6308 X86::VPORQZ256rmbkz, X86::VPORDZ256rmbkz },
6309 { X86::VXORPSZ256rmbkz, X86::VXORPDZ256rmbkz,
6310 X86::VPXORQZ256rmbkz, X86::VPXORDZ256rmbkz },
6311 { X86::VANDNPSZrmbkz, X86::VANDNPDZrmbkz,
6312 X86::VPANDNQZrmbkz, X86::VPANDNDZrmbkz },
6313 { X86::VANDPSZrmbkz, X86::VANDPDZrmbkz,
6314 X86::VPANDQZrmbkz, X86::VPANDDZrmbkz },
6315 { X86::VANDPSZrmbkz, X86::VANDPDZrmbkz,
6316 X86::VPANDQZrmbkz, X86::VPANDDZrmbkz },
6317 { X86::VORPSZrmbkz, X86::VORPDZrmbkz,
6318 X86::VPORQZrmbkz, X86::VPORDZrmbkz },
6319 { X86::VXORPSZrmbkz, X86::VXORPDZrmbkz,
6320 X86::VPXORQZrmbkz, X86::VPXORDZrmbkz },
6321 };
6322
6323 // NOTE: These should only be used by the custom domain methods.
6324 static const uint16_t ReplaceableBlendInstrs[][3] = {
6325 //PackedSingle PackedDouble PackedInt
6326 { X86::BLENDPSrmi, X86::BLENDPDrmi, X86::PBLENDWrmi },
6327 { X86::BLENDPSrri, X86::BLENDPDrri, X86::PBLENDWrri },
6328 { X86::VBLENDPSrmi, X86::VBLENDPDrmi, X86::VPBLENDWrmi },
6329 { X86::VBLENDPSrri, X86::VBLENDPDrri, X86::VPBLENDWrri },
6330 { X86::VBLENDPSYrmi, X86::VBLENDPDYrmi, X86::VPBLENDWYrmi },
6331 { X86::VBLENDPSYrri, X86::VBLENDPDYrri, X86::VPBLENDWYrri },
6332 };
6333 static const uint16_t ReplaceableBlendAVX2Instrs[][3] = {
6334 //PackedSingle PackedDouble PackedInt
6335 { X86::VBLENDPSrmi, X86::VBLENDPDrmi, X86::VPBLENDDrmi },
6336 { X86::VBLENDPSrri, X86::VBLENDPDrri, X86::VPBLENDDrri },
6337 { X86::VBLENDPSYrmi, X86::VBLENDPDYrmi, X86::VPBLENDDYrmi },
6338 { X86::VBLENDPSYrri, X86::VBLENDPDYrri, X86::VPBLENDDYrri },
6339 };
6340
6341 // Special table for changing EVEX logic instructions to VEX.
6342 // TODO: Should we run EVEX->VEX earlier?
6343 static const uint16_t ReplaceableCustomAVX512LogicInstrs[][4] = {
6344 // Two integer columns for 64-bit and 32-bit elements.
6345 //PackedSingle PackedDouble PackedInt PackedInt
6346 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNQZ128rm, X86::VPANDNDZ128rm },
6347 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNQZ128rr, X86::VPANDNDZ128rr },
6348 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDQZ128rm, X86::VPANDDZ128rm },
6349 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDQZ128rr, X86::VPANDDZ128rr },
6350 { X86::VORPSrm, X86::VORPDrm, X86::VPORQZ128rm, X86::VPORDZ128rm },
6351 { X86::VORPSrr, X86::VORPDrr, X86::VPORQZ128rr, X86::VPORDZ128rr },
6352 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORQZ128rm, X86::VPXORDZ128rm },
6353 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORQZ128rr, X86::VPXORDZ128rr },
6354 { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm },
6355 { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr },
6356 { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDQZ256rm, X86::VPANDDZ256rm },
6357 { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDQZ256rr, X86::VPANDDZ256rr },
6358 { X86::VORPSYrm, X86::VORPDYrm, X86::VPORQZ256rm, X86::VPORDZ256rm },
6359 { X86::VORPSYrr, X86::VORPDYrr, X86::VPORQZ256rr, X86::VPORDZ256rr },
6360 { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORQZ256rm, X86::VPXORDZ256rm },
6361 { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORQZ256rr, X86::VPXORDZ256rr },
6362 };
6363
6364 // FIXME: Some shuffle and unpack instructions have equivalents in different
6365 // domains, but they require a bit more work than just switching opcodes.
6366
6367 static const uint16_t *lookup(unsigned opcode, unsigned domain,
6368 ArrayRef<uint16_t[3]> Table) {
6369 for (const uint16_t (&Row)[3] : Table)
6370 if (Row[domain-1] == opcode)
6371 return Row;
6372 return nullptr;
6373 }
6374
6375 static const uint16_t *lookupAVX512(unsigned opcode, unsigned domain,
6376 ArrayRef<uint16_t[4]> Table) {
6377 // If this is the integer domain make sure to check both integer columns.
6378 for (const uint16_t (&Row)[4] : Table)
6379 if (Row[domain-1] == opcode || (domain == 3 && Row[3] == opcode))
6380 return Row;
6381 return nullptr;
6382 }
6383
6384 // Helper to attempt to widen/narrow blend masks.
6385 static bool AdjustBlendMask(unsigned OldMask, unsigned OldWidth,
6386 unsigned NewWidth, unsigned *pNewMask = nullptr) {
6387 assert(((OldWidth % NewWidth) == 0 || (NewWidth % OldWidth) == 0) &&
6388 "Illegal blend mask scale");
6389 unsigned NewMask = 0;
6390
6391 if ((OldWidth % NewWidth) == 0) {
6392 unsigned Scale = OldWidth / NewWidth;
6393 unsigned SubMask = (1u << Scale) - 1;
6394 for (unsigned i = 0; i != NewWidth; ++i) {
6395 unsigned Sub = (OldMask >> (i * Scale)) & SubMask;
6396 if (Sub == SubMask)
6397 NewMask |= (1u << i);
6398 else if (Sub != 0x0)
6399 return false;
6400 }
6401 } else {
6402 unsigned Scale = NewWidth / OldWidth;
6403 unsigned SubMask = (1u << Scale) - 1;
6404 for (unsigned i = 0; i != OldWidth; ++i) {
6405 if (OldMask & (1 << i)) {
6406 NewMask |= (SubMask << (i * Scale));
6407 }
6408 }
6409 }
6410
6411 if (pNewMask)
6412 *pNewMask = NewMask;
6413 return true;
6414 }
6415
6416 uint16_t X86InstrInfo::getExecutionDomainCustom(const MachineInstr &MI) const {
6417 unsigned Opcode = MI.getOpcode();
6418 unsigned NumOperands = MI.getDesc().getNumOperands();
6419
6420 auto GetBlendDomains = [&](unsigned ImmWidth, bool Is256) {
6421 uint16_t validDomains = 0;
6422 if (MI.getOperand(NumOperands - 1).isImm()) {
6423 unsigned Imm = MI.getOperand(NumOperands - 1).getImm();
6424 if (AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4))
6425 validDomains |= 0x2; // PackedSingle
6426 if (AdjustBlendMask(Imm, ImmWidth, Is256 ? 4 : 2))
6427 validDomains |= 0x4; // PackedDouble
6428 if (!Is256 || Subtarget.hasAVX2())
6429 validDomains |= 0x8; // PackedInt
6430 }
6431 return validDomains;
6432 };
6433
6434 switch (Opcode) {
6435 case X86::BLENDPDrmi:
6436 case X86::BLENDPDrri:
6437 case X86::VBLENDPDrmi:
6438 case X86::VBLENDPDrri:
6439 return GetBlendDomains(2, false);
6440 case X86::VBLENDPDYrmi:
6441 case X86::VBLENDPDYrri:
6442 return GetBlendDomains(4, true);
6443 case X86::BLENDPSrmi:
6444 case X86::BLENDPSrri:
6445 case X86::VBLENDPSrmi:
6446 case X86::VBLENDPSrri:
6447 case X86::VPBLENDDrmi:
6448 case X86::VPBLENDDrri:
6449 return GetBlendDomains(4, false);
6450 case X86::VBLENDPSYrmi:
6451 case X86::VBLENDPSYrri:
6452 case X86::VPBLENDDYrmi:
6453 case X86::VPBLENDDYrri:
6454 return GetBlendDomains(8, true);
6455 case X86::PBLENDWrmi:
6456 case X86::PBLENDWrri:
6457 case X86::VPBLENDWrmi:
6458 case X86::VPBLENDWrri:
6459 // Treat VPBLENDWY as a 128-bit vector as it repeats the lo/hi masks.
6460 case X86::VPBLENDWYrmi:
6461 case X86::VPBLENDWYrri:
6462 return GetBlendDomains(8, false);
6463 case X86::VPANDDZ128rr: case X86::VPANDDZ128rm:
6464 case X86::VPANDDZ256rr: case X86::VPANDDZ256rm:
6465 case X86::VPANDQZ128rr: case X86::VPANDQZ128rm:
6466 case X86::VPANDQZ256rr: case X86::VPANDQZ256rm:
6467 case X86::VPANDNDZ128rr: case X86::VPANDNDZ128rm:
6468 case X86::VPANDNDZ256rr: case X86::VPANDNDZ256rm:
6469 case X86::VPANDNQZ128rr: case X86::VPANDNQZ128rm:
6470 case X86::VPANDNQZ256rr: case X86::VPANDNQZ256rm:
6471 case X86::VPORDZ128rr: case X86::VPORDZ128rm:
6472 case X86::VPORDZ256rr: case X86::VPORDZ256rm:
6473 case X86::VPORQZ128rr: case X86::VPORQZ128rm:
6474 case X86::VPORQZ256rr: case X86::VPORQZ256rm:
6475 case X86::VPXORDZ128rr: case X86::VPXORDZ128rm:
6476 case X86::VPXORDZ256rr: case X86::VPXORDZ256rm:
6477 case X86::VPXORQZ128rr: case X86::VPXORQZ128rm:
6478 case X86::VPXORQZ256rr: case X86::VPXORQZ256rm:
6479 // If we don't have DQI see if we can still switch from an EVEX integer
6480 // instruction to a VEX floating point instruction.
6481 if (Subtarget.hasDQI())
6482 return 0;
6483
6484 if (RI.getEncodingValue(MI.getOperand(0).getReg()) >= 16)
6485 return 0;
6486 if (RI.getEncodingValue(MI.getOperand(1).getReg()) >= 16)
6487 return 0;
6488 // Register forms will have 3 operands. Memory form will have more.
6489 if (NumOperands == 3 &&
6490 RI.getEncodingValue(MI.getOperand(2).getReg()) >= 16)
6491 return 0;
6492
6493 // All domains are valid.
6494 return 0xe;
6495 case X86::MOVHLPSrr:
6496 // We can swap domains when both inputs are the same register.
6497 // FIXME: This doesn't catch all the cases we would like. If the input
6498 // register isn't KILLed by the instruction, the two address instruction
6499 // pass puts a COPY on one input. The other input uses the original
6500 // register. This prevents the same physical register from being used by
6501 // both inputs.
6502 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg() &&
6503 MI.getOperand(0).getSubReg() == 0 &&
6504 MI.getOperand(1).getSubReg() == 0 &&
6505 MI.getOperand(2).getSubReg() == 0)
6506 return 0x6;
6507 return 0;
6508 case X86::SHUFPDrri:
6509 return 0x6;
6510 }
6511 return 0;
6512 }
6513
6514 bool X86InstrInfo::setExecutionDomainCustom(MachineInstr &MI,
6515 unsigned Domain) const {
6516 assert(Domain > 0 && Domain < 4 && "Invalid execution domain");
6517 uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
6518 assert(dom && "Not an SSE instruction");
6519
6520 unsigned Opcode = MI.getOpcode();
6521 unsigned NumOperands = MI.getDesc().getNumOperands();
6522
6523 auto SetBlendDomain = [&](unsigned ImmWidth, bool Is256) {
6524 if (MI.getOperand(NumOperands - 1).isImm()) {
6525 unsigned Imm = MI.getOperand(NumOperands - 1).getImm() & 255;
6526 Imm = (ImmWidth == 16 ? ((Imm << 8) | Imm) : Imm);
6527 unsigned NewImm = Imm;
6528
6529 const uint16_t *table = lookup(Opcode, dom, ReplaceableBlendInstrs);
6530 if (!table)
6531 table = lookup(Opcode, dom, ReplaceableBlendAVX2Instrs);
6532
6533 if (Domain == 1) { // PackedSingle
6534 AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4, &NewImm);
6535 } else if (Domain == 2) { // PackedDouble
6536 AdjustBlendMask(Imm, ImmWidth, Is256 ? 4 : 2, &NewImm);
6537 } else if (Domain == 3) { // PackedInt
6538 if (Subtarget.hasAVX2()) {
6539 // If we are already VPBLENDW use that, else use VPBLENDD.
6540 if ((ImmWidth / (Is256 ? 2 : 1)) != 8) {
6541 table = lookup(Opcode, dom, ReplaceableBlendAVX2Instrs);
6542 AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4, &NewImm);
6543 }
6544 } else {
6545 assert(!Is256 && "128-bit vector expected");
6546 AdjustBlendMask(Imm, ImmWidth, 8, &NewImm);
6547 }
6548 }
6549
6550 assert(table && table[Domain - 1] && "Unknown domain op");
6551 MI.setDesc(get(table[Domain - 1]));
6552 MI.getOperand(NumOperands - 1).setImm(NewImm & 255);
6553 }
6554 return true;
6555 };
6556
6557 switch (Opcode) {
6558 case X86::BLENDPDrmi:
6559 case X86::BLENDPDrri:
6560 case X86::VBLENDPDrmi:
6561 case X86::VBLENDPDrri:
6562 return SetBlendDomain(2, false);
6563 case X86::VBLENDPDYrmi:
6564 case X86::VBLENDPDYrri:
6565 return SetBlendDomain(4, true);
6566 case X86::BLENDPSrmi:
6567 case X86::BLENDPSrri:
6568 case X86::VBLENDPSrmi:
6569 case X86::VBLENDPSrri:
6570 case X86::VPBLENDDrmi:
6571 case X86::VPBLENDDrri:
6572 return SetBlendDomain(4, false);
6573 case X86::VBLENDPSYrmi:
6574 case X86::VBLENDPSYrri:
6575 case X86::VPBLENDDYrmi:
6576 case X86::VPBLENDDYrri:
6577 return SetBlendDomain(8, true);
6578 case X86::PBLENDWrmi:
6579 case X86::PBLENDWrri:
6580 case X86::VPBLENDWrmi:
6581 case X86::VPBLENDWrri:
6582 return SetBlendDomain(8, false);
6583 case X86::VPBLENDWYrmi:
6584 case X86::VPBLENDWYrri:
6585 return SetBlendDomain(16, true);
6586 case X86::VPANDDZ128rr: case X86::VPANDDZ128rm:
6587 case X86::VPANDDZ256rr: case X86::VPANDDZ256rm:
6588 case X86::VPANDQZ128rr: case X86::VPANDQZ128rm:
6589 case X86::VPANDQZ256rr: case X86::VPANDQZ256rm:
6590 case X86::VPANDNDZ128rr: case X86::VPANDNDZ128rm:
6591 case X86::VPANDNDZ256rr: case X86::VPANDNDZ256rm:
6592 case X86::VPANDNQZ128rr: case X86::VPANDNQZ128rm:
6593 case X86::VPANDNQZ256rr: case X86::VPANDNQZ256rm:
6594 case X86::VPORDZ128rr: case X86::VPORDZ128rm:
6595 case X86::VPORDZ256rr: case X86::VPORDZ256rm:
6596 case X86::VPORQZ128rr: case X86::VPORQZ128rm:
6597 case X86::VPORQZ256rr: case X86::VPORQZ256rm:
6598 case X86::VPXORDZ128rr: case X86::VPXORDZ128rm:
6599 case X86::VPXORDZ256rr: case X86::VPXORDZ256rm:
6600 case X86::VPXORQZ128rr: case X86::VPXORQZ128rm:
6601 case X86::VPXORQZ256rr: case X86::VPXORQZ256rm: {
6602 // Without DQI, convert EVEX instructions to VEX instructions.
6603 if (Subtarget.hasDQI())
6604 return false;
6605
6606 const uint16_t *table = lookupAVX512(MI.getOpcode(), dom,
6607 ReplaceableCustomAVX512LogicInstrs);
6608 assert(table && "Instruction not found in table?");
6609 // Don't change integer Q instructions to D instructions and
6610 // use D intructions if we started with a PS instruction.
6611 if (Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
6612 Domain = 4;
6613 MI.setDesc(get(table[Domain - 1]));
6614 return true;
6615 }
6616 case X86::UNPCKHPDrr:
6617 case X86::MOVHLPSrr:
6618 // We just need to commute the instruction which will switch the domains.
6619 if (Domain != dom && Domain != 3 &&
6620 MI.getOperand(1).getReg() == MI.getOperand(2).getReg() &&
6621 MI.getOperand(0).getSubReg() == 0 &&
6622 MI.getOperand(1).getSubReg() == 0 &&
6623 MI.getOperand(2).getSubReg() == 0) {
6624 commuteInstruction(MI, false);
6625 return true;
6626 }
6627 // We must always return true for MOVHLPSrr.
6628 if (Opcode == X86::MOVHLPSrr)
6629 return true;
6630 break;
6631 case X86::SHUFPDrri: {
6632 if (Domain == 1) {
6633 unsigned Imm = MI.getOperand(3).getImm();
6634 unsigned NewImm = 0x44;
6635 if (Imm & 1) NewImm |= 0x0a;
6636 if (Imm & 2) NewImm |= 0xa0;
6637 MI.getOperand(3).setImm(NewImm);
6638 MI.setDesc(get(X86::SHUFPSrri));
6639 }
6640 return true;
6641 }
6642 }
6643 return false;
6644 }
6645
6646 std::pair<uint16_t, uint16_t>
6647 X86InstrInfo::getExecutionDomain(const MachineInstr &MI) const {
6648 uint16_t domain = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
6649 unsigned opcode = MI.getOpcode();
6650 uint16_t validDomains = 0;
6651 if (domain) {
6652 // Attempt to match for custom instructions.
6653 validDomains = getExecutionDomainCustom(MI);
6654 if (validDomains)
6655 return std::make_pair(domain, validDomains);
6656
6657 if (lookup(opcode, domain, ReplaceableInstrs)) {
6658 validDomains = 0xe;
6659 } else if (lookup(opcode, domain, ReplaceableInstrsAVX2)) {
6660 validDomains = Subtarget.hasAVX2() ? 0xe : 0x6;
6661 } else if (lookup(opcode, domain, ReplaceableInstrsFP)) {
6662 validDomains = 0x6;
6663 } else if (lookup(opcode, domain, ReplaceableInstrsAVX2InsertExtract)) {
6664 // Insert/extract instructions should only effect domain if AVX2
6665 // is enabled.
6666 if (!Subtarget.hasAVX2())
6667 return std::make_pair(0, 0);
6668 validDomains = 0xe;
6669 } else if (lookupAVX512(opcode, domain, ReplaceableInstrsAVX512)) {
6670 validDomains = 0xe;
6671 } else if (Subtarget.hasDQI() && lookupAVX512(opcode, domain,
6672 ReplaceableInstrsAVX512DQ)) {
6673 validDomains = 0xe;
6674 } else if (Subtarget.hasDQI()) {
6675 if (const uint16_t *table = lookupAVX512(opcode, domain,
6676 ReplaceableInstrsAVX512DQMasked)) {
6677 if (domain == 1 || (domain == 3 && table[3] == opcode))
6678 validDomains = 0xa;
6679 else
6680 validDomains = 0xc;
6681 }
6682 }
6683 }
6684 return std::make_pair(domain, validDomains);
6685 }
6686
6687 void X86InstrInfo::setExecutionDomain(MachineInstr &MI, unsigned Domain) const {
6688 assert(Domain>0 && Domain<4 && "Invalid execution domain");
6689 uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
6690 assert(dom && "Not an SSE instruction");
6691
6692 // Attempt to match for custom instructions.
6693 if (setExecutionDomainCustom(MI, Domain))
6694 return;
6695
6696 const uint16_t *table = lookup(MI.getOpcode(), dom, ReplaceableInstrs);
6697 if (!table) { // try the other table
6698 assert((Subtarget.hasAVX2() || Domain < 3) &&
6699 "256-bit vector operations only available in AVX2");
6700 table = lookup(MI.getOpcode(), dom, ReplaceableInstrsAVX2);
6701 }
6702 if (!table) { // try the FP table
6703 table = lookup(MI.getOpcode(), dom, ReplaceableInstrsFP);
6704 assert((!table || Domain < 3) &&
6705 "Can only select PackedSingle or PackedDouble");
6706 }
6707 if (!table) { // try the other table
6708 assert(Subtarget.hasAVX2() &&
6709 "256-bit insert/extract only available in AVX2");
6710 table = lookup(MI.getOpcode(), dom, ReplaceableInstrsAVX2InsertExtract);
6711 }
6712 if (!table) { // try the AVX512 table
6713 assert(Subtarget.hasAVX512() && "Requires AVX-512");
6714 table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512);
6715 // Don't change integer Q instructions to D instructions.
6716 if (table && Domain == 3 && table[3] == MI.getOpcode())
6717 Domain = 4;
6718 }
6719 if (!table) { // try the AVX512DQ table
6720 assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
6721 table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQ);
6722 // Don't change integer Q instructions to D instructions and
6723 // use D intructions if we started with a PS instruction.
6724 if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
6725 Domain = 4;
6726 }
6727 if (!table) { // try the AVX512DQMasked table
6728 assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
6729 table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQMasked);
6730 if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
6731 Domain = 4;
6732 }
6733 assert(table && "Cannot change domain");
6734 MI.setDesc(get(table[Domain - 1]));
6735 }
6736
6737 /// Return the noop instruction to use for a noop.
6738 void X86InstrInfo::getNoop(MCInst &NopInst) const {
6739 NopInst.setOpcode(X86::NOOP);
6740 }
6741
6742 bool X86InstrInfo::isHighLatencyDef(int opc) const {
6743 switch (opc) {
6744 default: return false;
6745 case X86::DIVPDrm:
6746 case X86::DIVPDrr:
6747 case X86::DIVPSrm:
6748 case X86::DIVPSrr:
6749 case X86::DIVSDrm:
6750 case X86::DIVSDrm_Int:
6751 case X86::DIVSDrr:
6752 case X86::DIVSDrr_Int:
6753 case X86::DIVSSrm:
6754 case X86::DIVSSrm_Int:
6755 case X86::DIVSSrr:
6756 case X86::DIVSSrr_Int:
6757 case X86::SQRTPDm:
6758 case X86::SQRTPDr:
6759 case X86::SQRTPSm:
6760 case X86::SQRTPSr:
6761 case X86::SQRTSDm:
6762 case X86::SQRTSDm_Int:
6763 case X86::SQRTSDr:
6764 case X86::SQRTSDr_Int:
6765 case X86::SQRTSSm:
6766 case X86::SQRTSSm_Int:
6767 case X86::SQRTSSr:
6768 case X86::SQRTSSr_Int:
6769 // AVX instructions with high latency
6770 case X86::VDIVPDrm:
6771 case X86::VDIVPDrr:
6772 case X86::VDIVPDYrm:
6773 case X86::VDIVPDYrr:
6774 case X86::VDIVPSrm:
6775 case X86::VDIVPSrr:
6776 case X86::VDIVPSYrm:
6777 case X86::VDIVPSYrr:
6778 case X86::VDIVSDrm:
6779 case X86::VDIVSDrm_Int:
6780 case X86::VDIVSDrr:
6781 case X86::VDIVSDrr_Int:
6782 case X86::VDIVSSrm:
6783 case X86::VDIVSSrm_Int:
6784 case X86::VDIVSSrr:
6785 case X86::VDIVSSrr_Int:
6786 case X86::VSQRTPDm:
6787 case X86::VSQRTPDr:
6788 case X86::VSQRTPDYm:
6789 case X86::VSQRTPDYr:
6790 case X86::VSQRTPSm:
6791 case X86::VSQRTPSr:
6792 case X86::VSQRTPSYm:
6793 case X86::VSQRTPSYr:
6794 case X86::VSQRTSDm:
6795 case X86::VSQRTSDm_Int:
6796 case X86::VSQRTSDr:
6797 case X86::VSQRTSDr_Int:
6798 case X86::VSQRTSSm:
6799 case X86::VSQRTSSm_Int:
6800 case X86::VSQRTSSr:
6801 case X86::VSQRTSSr_Int:
6802 // AVX512 instructions with high latency
6803 case X86::VDIVPDZ128rm:
6804 case X86::VDIVPDZ128rmb:
6805 case X86::VDIVPDZ128rmbk:
6806 case X86::VDIVPDZ128rmbkz:
6807 case X86::VDIVPDZ128rmk:
6808 case X86::VDIVPDZ128rmkz:
6809 case X86::VDIVPDZ128rr:
6810 case X86::VDIVPDZ128rrk:
6811 case X86::VDIVPDZ128rrkz:
6812 case X86::VDIVPDZ256rm:
6813 case X86::VDIVPDZ256rmb:
6814 case X86::VDIVPDZ256rmbk:
6815 case X86::VDIVPDZ256rmbkz:
6816 case X86::VDIVPDZ256rmk:
6817 case X86::VDIVPDZ256rmkz:
6818 case X86::VDIVPDZ256rr:
6819 case X86::VDIVPDZ256rrk:
6820 case X86::VDIVPDZ256rrkz:
6821 case X86::VDIVPDZrrb:
6822 case X86::VDIVPDZrrbk:
6823 case X86::VDIVPDZrrbkz:
6824 case X86::VDIVPDZrm:
6825 case X86::VDIVPDZrmb:
6826 case X86::VDIVPDZrmbk:
6827 case X86::VDIVPDZrmbkz:
6828 case X86::VDIVPDZrmk:
6829 case X86::VDIVPDZrmkz:
6830 case X86::VDIVPDZrr:
6831 case X86::VDIVPDZrrk:
6832 case X86::VDIVPDZrrkz:
6833 case X86::VDIVPSZ128rm:
6834 case X86::VDIVPSZ128rmb:
6835 case X86::VDIVPSZ128rmbk:
6836 case X86::VDIVPSZ128rmbkz:
6837 case X86::VDIVPSZ128rmk:
6838 case X86::VDIVPSZ128rmkz:
6839 case X86::VDIVPSZ128rr:
6840 case X86::VDIVPSZ128rrk:
6841 case X86::VDIVPSZ128rrkz:
6842 case X86::VDIVPSZ256rm:
6843 case X86::VDIVPSZ256rmb:
6844 case X86::VDIVPSZ256rmbk:
6845 case X86::VDIVPSZ256rmbkz:
6846 case X86::VDIVPSZ256rmk:
6847 case X86::VDIVPSZ256rmkz:
6848 case X86::VDIVPSZ256rr:
6849 case X86::VDIVPSZ256rrk:
6850 case X86::VDIVPSZ256rrkz:
6851 case X86::VDIVPSZrrb:
6852 case X86::VDIVPSZrrbk:
6853 case X86::VDIVPSZrrbkz:
6854 case X86::VDIVPSZrm:
6855 case X86::VDIVPSZrmb:
6856 case X86::VDIVPSZrmbk:
6857 case X86::VDIVPSZrmbkz:
6858 case X86::VDIVPSZrmk:
6859 case X86::VDIVPSZrmkz:
6860 case X86::VDIVPSZrr:
6861 case X86::VDIVPSZrrk:
6862 case X86::VDIVPSZrrkz:
6863 case X86::VDIVSDZrm:
6864 case X86::VDIVSDZrr:
6865 case X86::VDIVSDZrm_Int:
6866 case X86::VDIVSDZrm_Intk:
6867 case X86::VDIVSDZrm_Intkz:
6868 case X86::VDIVSDZrr_Int:
6869 case X86::VDIVSDZrr_Intk:
6870 case X86::VDIVSDZrr_Intkz:
6871 case X86::VDIVSDZrrb_Int:
6872 case X86::VDIVSDZrrb_Intk:
6873 case X86::VDIVSDZrrb_Intkz:
6874 case X86::VDIVSSZrm:
6875 case X86::VDIVSSZrr:
6876 case X86::VDIVSSZrm_Int:
6877 case X86::VDIVSSZrm_Intk:
6878 case X86::VDIVSSZrm_Intkz:
6879 case X86::VDIVSSZrr_Int:
6880 case X86::VDIVSSZrr_Intk:
6881 case X86::VDIVSSZrr_Intkz:
6882 case X86::VDIVSSZrrb_Int:
6883 case X86::VDIVSSZrrb_Intk:
6884 case X86::VDIVSSZrrb_Intkz:
6885 case X86::VSQRTPDZ128m:
6886 case X86::VSQRTPDZ128mb:
6887 case X86::VSQRTPDZ128mbk:
6888 case X86::VSQRTPDZ128mbkz:
6889 case X86::VSQRTPDZ128mk:
6890 case X86::VSQRTPDZ128mkz:
6891 case X86::VSQRTPDZ128r:
6892 case X86::VSQRTPDZ128rk:
6893 case X86::VSQRTPDZ128rkz:
6894 case X86::VSQRTPDZ256m:
6895 case X86::VSQRTPDZ256mb:
6896 case X86::VSQRTPDZ256mbk:
6897 case X86::VSQRTPDZ256mbkz:
6898 case X86::VSQRTPDZ256mk:
6899 case X86::VSQRTPDZ256mkz:
6900 case X86::VSQRTPDZ256r:
6901 case X86::VSQRTPDZ256rk:
6902 case X86::VSQRTPDZ256rkz:
6903 case X86::VSQRTPDZm:
6904 case X86::VSQRTPDZmb:
6905 case X86::VSQRTPDZmbk:
6906 case X86::VSQRTPDZmbkz:
6907 case X86::VSQRTPDZmk:
6908 case X86::VSQRTPDZmkz:
6909 case X86::VSQRTPDZr:
6910 case X86::VSQRTPDZrb:
6911 case X86::VSQRTPDZrbk:
6912 case X86::VSQRTPDZrbkz:
6913 case X86::VSQRTPDZrk:
6914 case X86::VSQRTPDZrkz:
6915 case X86::VSQRTPSZ128m:
6916 case X86::VSQRTPSZ128mb:
6917 case X86::VSQRTPSZ128mbk:
6918 case X86::VSQRTPSZ128mbkz:
6919 case X86::VSQRTPSZ128mk:
6920 case X86::VSQRTPSZ128mkz:
6921 case X86::VSQRTPSZ128r:
6922 case X86::VSQRTPSZ128rk:
6923 case X86::VSQRTPSZ128rkz:
6924 case X86::VSQRTPSZ256m:
6925 case X86::VSQRTPSZ256mb:
6926 case X86::VSQRTPSZ256mbk:
6927 case X86::VSQRTPSZ256mbkz:
6928 case X86::VSQRTPSZ256mk:
6929 case X86::VSQRTPSZ256mkz:
6930 case X86::VSQRTPSZ256r:
6931 case X86::VSQRTPSZ256rk:
6932 case X86::VSQRTPSZ256rkz:
6933 case X86::VSQRTPSZm:
6934 case X86::VSQRTPSZmb:
6935 case X86::VSQRTPSZmbk:
6936 case X86::VSQRTPSZmbkz:
6937 case X86::VSQRTPSZmk:
6938 case X86::VSQRTPSZmkz:
6939 case X86::VSQRTPSZr:
6940 case X86::VSQRTPSZrb:
6941 case X86::VSQRTPSZrbk:
6942 case X86::VSQRTPSZrbkz:
6943 case X86::VSQRTPSZrk:
6944 case X86::VSQRTPSZrkz:
6945 case X86::VSQRTSDZm:
6946 case X86::VSQRTSDZm_Int:
6947 case X86::VSQRTSDZm_Intk:
6948 case X86::VSQRTSDZm_Intkz:
6949 case X86::VSQRTSDZr:
6950 case X86::VSQRTSDZr_Int:
6951 case X86::VSQRTSDZr_Intk:
6952 case X86::VSQRTSDZr_Intkz:
6953 case X86::VSQRTSDZrb_Int:
6954 case X86::VSQRTSDZrb_Intk:
6955 case X86::VSQRTSDZrb_Intkz:
6956 case X86::VSQRTSSZm:
6957 case X86::VSQRTSSZm_Int:
6958 case X86::VSQRTSSZm_Intk:
6959 case X86::VSQRTSSZm_Intkz:
6960 case X86::VSQRTSSZr:
6961 case X86::VSQRTSSZr_Int:
6962 case X86::VSQRTSSZr_Intk:
6963 case X86::VSQRTSSZr_Intkz:
6964 case X86::VSQRTSSZrb_Int:
6965 case X86::VSQRTSSZrb_Intk:
6966 case X86::VSQRTSSZrb_Intkz:
6967
6968 case X86::VGATHERDPDYrm:
6969 case X86::VGATHERDPDZ128rm:
6970 case X86::VGATHERDPDZ256rm:
6971 case X86::VGATHERDPDZrm:
6972 case X86::VGATHERDPDrm:
6973 case X86::VGATHERDPSYrm:
6974 case X86::VGATHERDPSZ128rm:
6975 case X86::VGATHERDPSZ256rm:
6976 case X86::VGATHERDPSZrm:
6977 case X86::VGATHERDPSrm:
6978 case X86::VGATHERPF0DPDm:
6979 case X86::VGATHERPF0DPSm:
6980 case X86::VGATHERPF0QPDm:
6981 case X86::VGATHERPF0QPSm:
6982 case X86::VGATHERPF1DPDm:
6983 case X86::VGATHERPF1DPSm:
6984 case X86::VGATHERPF1QPDm:
6985 case X86::VGATHERPF1QPSm:
6986 case X86::VGATHERQPDYrm:
6987 case X86::VGATHERQPDZ128rm:
6988 case X86::VGATHERQPDZ256rm:
6989 case X86::VGATHERQPDZrm:
6990 case X86::VGATHERQPDrm:
6991 case X86::VGATHERQPSYrm:
6992 case X86::VGATHERQPSZ128rm:
6993 case X86::VGATHERQPSZ256rm:
6994 case X86::VGATHERQPSZrm:
6995 case X86::VGATHERQPSrm:
6996 case X86::VPGATHERDDYrm:
6997 case X86::VPGATHERDDZ128rm:
6998 case X86::VPGATHERDDZ256rm:
6999 case X86::VPGATHERDDZrm:
7000 case X86::VPGATHERDDrm:
7001 case X86::VPGATHERDQYrm:
7002 case X86::VPGATHERDQZ128rm:
7003 case X86::VPGATHERDQZ256rm:
7004 case X86::VPGATHERDQZrm:
7005 case X86::VPGATHERDQrm:
7006 case X86::VPGATHERQDYrm:
7007 case X86::VPGATHERQDZ128rm:
7008 case X86::VPGATHERQDZ256rm:
7009 case X86::VPGATHERQDZrm:
7010 case X86::VPGATHERQDrm:
7011 case X86::VPGATHERQQYrm:
7012 case X86::VPGATHERQQZ128rm:
7013 case X86::VPGATHERQQZ256rm:
7014 case X86::VPGATHERQQZrm:
7015 case X86::VPGATHERQQrm:
7016 case X86::VSCATTERDPDZ128mr:
7017 case X86::VSCATTERDPDZ256mr:
7018 case X86::VSCATTERDPDZmr:
7019 case X86::VSCATTERDPSZ128mr:
7020 case X86::VSCATTERDPSZ256mr:
7021 case X86::VSCATTERDPSZmr:
7022 case X86::VSCATTERPF0DPDm:
7023 case X86::VSCATTERPF0DPSm:
7024 case X86::VSCATTERPF0QPDm:
7025 case X86::VSCATTERPF0QPSm:
7026 case X86::VSCATTERPF1DPDm:
7027 case X86::VSCATTERPF1DPSm:
7028 case X86::VSCATTERPF1QPDm:
7029 case X86::VSCATTERPF1QPSm:
7030 case X86::VSCATTERQPDZ128mr:
7031 case X86::VSCATTERQPDZ256mr:
7032 case X86::VSCATTERQPDZmr:
7033 case X86::VSCATTERQPSZ128mr:
7034 case X86::VSCATTERQPSZ256mr:
7035 case X86::VSCATTERQPSZmr:
7036 case X86::VPSCATTERDDZ128mr:
7037 case X86::VPSCATTERDDZ256mr:
7038 case X86::VPSCATTERDDZmr:
7039 case X86::VPSCATTERDQZ128mr:
7040 case X86::VPSCATTERDQZ256mr:
7041 case X86::VPSCATTERDQZmr:
7042 case X86::VPSCATTERQDZ128mr:
7043 case X86::VPSCATTERQDZ256mr:
7044 case X86::VPSCATTERQDZmr:
7045 case X86::VPSCATTERQQZ128mr:
7046 case X86::VPSCATTERQQZ256mr:
7047 case X86::VPSCATTERQQZmr:
7048 return true;
7049 }
7050 }
7051
7052 bool X86InstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel,
7053 const MachineRegisterInfo *MRI,
7054 const MachineInstr &DefMI,
7055 unsigned DefIdx,
7056 const MachineInstr &UseMI,
7057 unsigned UseIdx) const {
7058 return isHighLatencyDef(DefMI.getOpcode());
7059 }
7060
7061 bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst,
7062 const MachineBasicBlock *MBB) const {
7063 assert((Inst.getNumOperands() == 3 || Inst.getNumOperands() == 4) &&
7064 "Reassociation needs binary operators");
7065
7066 // Integer binary math/logic instructions have a third source operand:
7067 // the EFLAGS register. That operand must be both defined here and never
7068 // used; ie, it must be dead. If the EFLAGS operand is live, then we can
7069 // not change anything because rearranging the operands could affect other
7070 // instructions that depend on the exact status flags (zero, sign, etc.)
7071 // that are set by using these particular operands with this operation.
7072 if (Inst.getNumOperands() == 4) {
7073 assert(Inst.getOperand(3).isReg() &&
7074 Inst.getOperand(3).getReg() == X86::EFLAGS &&
7075 "Unexpected operand in reassociable instruction");
7076 if (!Inst.getOperand(3).isDead())
7077 return false;
7078 }
7079
7080 return TargetInstrInfo::hasReassociableOperands(Inst, MBB);
7081 }
7082
7083 // TODO: There are many more machine instruction opcodes to match:
7084 // 1. Other data types (integer, vectors)
7085 // 2. Other math / logic operations (xor, or)
7086 // 3. Other forms of the same operation (intrinsics and other variants)
7087 bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
7088 switch (Inst.getOpcode()) {
7089 case X86::AND8rr:
7090 case X86::AND16rr:
7091 case X86::AND32rr:
7092 case X86::AND64rr:
7093 case X86::OR8rr:
7094 case X86::OR16rr:
7095 case X86::OR32rr:
7096 case X86::OR64rr:
7097 case X86::XOR8rr:
7098 case X86::XOR16rr:
7099 case X86::XOR32rr:
7100 case X86::XOR64rr:
7101 case X86::IMUL16rr:
7102 case X86::IMUL32rr:
7103 case X86::IMUL64rr:
7104 case X86::PANDrr:
7105 case X86::PORrr:
7106 case X86::PXORrr:
7107 case X86::ANDPDrr:
7108 case X86::ANDPSrr:
7109 case X86::ORPDrr:
7110 case X86::ORPSrr:
7111 case X86::XORPDrr:
7112 case X86::XORPSrr:
7113 case X86::PADDBrr:
7114 case X86::PADDWrr:
7115 case X86::PADDDrr:
7116 case X86::PADDQrr:
7117 case X86::PMULLWrr:
7118 case X86::PMULLDrr:
7119 case X86::PMAXSBrr:
7120 case X86::PMAXSDrr:
7121 case X86::PMAXSWrr:
7122 case X86::PMAXUBrr:
7123 case X86::PMAXUDrr:
7124 case X86::PMAXUWrr:
7125 case X86::PMINSBrr:
7126 case X86::PMINSDrr:
7127 case X86::PMINSWrr:
7128 case X86::PMINUBrr:
7129 case X86::PMINUDrr:
7130 case X86::PMINUWrr:
7131 case X86::VPANDrr:
7132 case X86::VPANDYrr:
7133 case X86::VPANDDZ128rr:
7134 case X86::VPANDDZ256rr:
7135 case X86::VPANDDZrr:
7136 case X86::VPANDQZ128rr:
7137 case X86::VPANDQZ256rr:
7138 case X86::VPANDQZrr:
7139 case X86::VPORrr:
7140 case X86::VPORYrr:
7141 case X86::VPORDZ128rr:
7142 case X86::VPORDZ256rr:
7143 case X86::VPORDZrr:
7144 case X86::VPORQZ128rr:
7145 case X86::VPORQZ256rr:
7146 case X86::VPORQZrr:
7147 case X86::VPXORrr:
7148 case X86::VPXORYrr:
7149 case X86::VPXORDZ128rr:
7150 case X86::VPXORDZ256rr:
7151 case X86::VPXORDZrr:
7152 case X86::VPXORQZ128rr:
7153 case X86::VPXORQZ256rr:
7154 case X86::VPXORQZrr:
7155 case X86::VANDPDrr:
7156 case X86::VANDPSrr:
7157 case X86::VANDPDYrr:
7158 case X86::VANDPSYrr:
7159 case X86::VANDPDZ128rr:
7160 case X86::VANDPSZ128rr:
7161 case X86::VANDPDZ256rr:
7162 case X86::VANDPSZ256rr:
7163 case X86::VANDPDZrr:
7164 case X86::VANDPSZrr:
7165 case X86::VORPDrr:
7166 case X86::VORPSrr:
7167 case X86::VORPDYrr:
7168 case X86::VORPSYrr:
7169 case X86::VORPDZ128rr:
7170 case X86::VORPSZ128rr:
7171 case X86::VORPDZ256rr:
7172 case X86::VORPSZ256rr:
7173 case X86::VORPDZrr:
7174 case X86::VORPSZrr:
7175 case X86::VXORPDrr:
7176 case X86::VXORPSrr:
7177 case X86::VXORPDYrr:
7178 case X86::VXORPSYrr:
7179 case X86::VXORPDZ128rr:
7180 case X86::VXORPSZ128rr:
7181 case X86::VXORPDZ256rr:
7182 case X86::VXORPSZ256rr:
7183 case X86::VXORPDZrr:
7184 case X86::VXORPSZrr:
7185 case X86::KADDBrr:
7186 case X86::KADDWrr:
7187 case X86::KADDDrr:
7188 case X86::KADDQrr:
7189 case X86::KANDBrr:
7190 case X86::KANDWrr:
7191 case X86::KANDDrr:
7192 case X86::KANDQrr:
7193 case X86::KORBrr:
7194 case X86::KORWrr:
7195 case X86::KORDrr:
7196 case X86::KORQrr:
7197 case X86::KXORBrr:
7198 case X86::KXORWrr:
7199 case X86::KXORDrr:
7200 case X86::KXORQrr:
7201 case X86::VPADDBrr:
7202 case X86::VPADDWrr:
7203 case X86::VPADDDrr:
7204 case X86::VPADDQrr:
7205 case X86::VPADDBYrr:
7206 case X86::VPADDWYrr:
7207 case X86::VPADDDYrr:
7208 case X86::VPADDQYrr:
7209 case X86::VPADDBZ128rr:
7210 case X86::VPADDWZ128rr:
7211 case X86::VPADDDZ128rr:
7212 case X86::VPADDQZ128rr:
7213 case X86::VPADDBZ256rr:
7214 case X86::VPADDWZ256rr:
7215 case X86::VPADDDZ256rr:
7216 case X86::VPADDQZ256rr:
7217 case X86::VPADDBZrr:
7218 case X86::VPADDWZrr:
7219 case X86::VPADDDZrr:
7220 case X86::VPADDQZrr:
7221 case X86::VPMULLWrr:
7222 case X86::VPMULLWYrr:
7223 case X86::VPMULLWZ128rr:
7224 case X86::VPMULLWZ256rr:
7225 case X86::VPMULLWZrr:
7226 case X86::VPMULLDrr:
7227 case X86::VPMULLDYrr:
7228 case X86::VPMULLDZ128rr:
7229 case X86::VPMULLDZ256rr:
7230 case X86::VPMULLDZrr:
7231 case X86::VPMULLQZ128rr:
7232 case X86::VPMULLQZ256rr:
7233 case X86::VPMULLQZrr:
7234 case X86::VPMAXSBrr:
7235 case X86::VPMAXSBYrr:
7236 case X86::VPMAXSBZ128rr:
7237 case X86::VPMAXSBZ256rr:
7238 case X86::VPMAXSBZrr:
7239 case X86::VPMAXSDrr:
7240 case X86::VPMAXSDYrr:
7241 case X86::VPMAXSDZ128rr:
7242 case X86::VPMAXSDZ256rr:
7243 case X86::VPMAXSDZrr:
7244 case X86::VPMAXSQZ128rr:
7245 case X86::VPMAXSQZ256rr:
7246 case X86::VPMAXSQZrr:
7247 case X86::VPMAXSWrr:
7248 case X86::VPMAXSWYrr:
7249 case X86::VPMAXSWZ128rr:
7250 case X86::VPMAXSWZ256rr:
7251 case X86::VPMAXSWZrr:
7252 case X86::VPMAXUBrr:
7253 case X86::VPMAXUBYrr:
7254 case X86::VPMAXUBZ128rr:
7255 case X86::VPMAXUBZ256rr:
7256 case X86::VPMAXUBZrr:
7257 case X86::VPMAXUDrr:
7258 case X86::VPMAXUDYrr:
7259 case X86::VPMAXUDZ128rr:
7260 case X86::VPMAXUDZ256rr:
7261 case X86::VPMAXUDZrr:
7262 case X86::VPMAXUQZ128rr:
7263 case X86::VPMAXUQZ256rr:
7264 case X86::VPMAXUQZrr:
7265 case X86::VPMAXUWrr:
7266 case X86::VPMAXUWYrr:
7267 case X86::VPMAXUWZ128rr:
7268 case X86::VPMAXUWZ256rr:
7269 case X86::VPMAXUWZrr:
7270 case X86::VPMINSBrr:
7271 case X86::VPMINSBYrr:
7272 case X86::VPMINSBZ128rr:
7273 case X86::VPMINSBZ256rr:
7274 case X86::VPMINSBZrr:
7275 case X86::VPMINSDrr:
7276 case X86::VPMINSDYrr:
7277 case X86::VPMINSDZ128rr:
7278 case X86::VPMINSDZ256rr:
7279 case X86::VPMINSDZrr:
7280 case X86::VPMINSQZ128rr:
7281 case X86::VPMINSQZ256rr:
7282 case X86::VPMINSQZrr:
7283 case X86::VPMINSWrr:
7284 case X86::VPMINSWYrr:
7285 case X86::VPMINSWZ128rr:
7286 case X86::VPMINSWZ256rr:
7287 case X86::VPMINSWZrr:
7288 case X86::VPMINUBrr:
7289 case X86::VPMINUBYrr:
7290 case X86::VPMINUBZ128rr:
7291 case X86::VPMINUBZ256rr:
7292 case X86::VPMINUBZrr:
7293 case X86::VPMINUDrr:
7294 case X86::VPMINUDYrr:
7295 case X86::VPMINUDZ128rr:
7296 case X86::VPMINUDZ256rr:
7297 case X86::VPMINUDZrr:
7298 case X86::VPMINUQZ128rr:
7299 case X86::VPMINUQZ256rr:
7300 case X86::VPMINUQZrr:
7301 case X86::VPMINUWrr:
7302 case X86::VPMINUWYrr:
7303 case X86::VPMINUWZ128rr:
7304 case X86::VPMINUWZ256rr:
7305 case X86::VPMINUWZrr:
7306 // Normal min/max instructions are not commutative because of NaN and signed
7307 // zero semantics, but these are. Thus, there's no need to check for global
7308 // relaxed math; the instructions themselves have the properties we need.
7309 case X86::MAXCPDrr:
7310 case X86::MAXCPSrr:
7311 case X86::MAXCSDrr:
7312 case X86::MAXCSSrr:
7313 case X86::MINCPDrr:
7314 case X86::MINCPSrr:
7315 case X86::MINCSDrr:
7316 case X86::MINCSSrr:
7317 case X86::VMAXCPDrr:
7318 case X86::VMAXCPSrr:
7319 case X86::VMAXCPDYrr:
7320 case X86::VMAXCPSYrr:
7321 case X86::VMAXCPDZ128rr:
7322 case X86::VMAXCPSZ128rr:
7323 case X86::VMAXCPDZ256rr:
7324 case X86::VMAXCPSZ256rr:
7325 case X86::VMAXCPDZrr:
7326 case X86::VMAXCPSZrr:
7327 case X86::VMAXCSDrr:
7328 case X86::VMAXCSSrr:
7329 case X86::VMAXCSDZrr:
7330 case X86::VMAXCSSZrr:
7331 case X86::VMINCPDrr:
7332 case X86::VMINCPSrr:
7333 case X86::VMINCPDYrr:
7334 case X86::VMINCPSYrr:
7335 case X86::VMINCPDZ128rr:
7336 case X86::VMINCPSZ128rr:
7337 case X86::VMINCPDZ256rr:
7338 case X86::VMINCPSZ256rr:
7339 case X86::VMINCPDZrr:
7340 case X86::VMINCPSZrr:
7341 case X86::VMINCSDrr:
7342 case X86::VMINCSSrr:
7343 case X86::VMINCSDZrr:
7344 case X86::VMINCSSZrr:
7345 return true;
7346 case X86::ADDPDrr:
7347 case X86::ADDPSrr:
7348 case X86::ADDSDrr:
7349 case X86::ADDSSrr:
7350 case X86::MULPDrr:
7351 case X86::MULPSrr:
7352 case X86::MULSDrr:
7353 case X86::MULSSrr:
7354 case X86::VADDPDrr:
7355 case X86::VADDPSrr:
7356 case X86::VADDPDYrr:
7357 case X86::VADDPSYrr:
7358 case X86::VADDPDZ128rr:
7359 case X86::VADDPSZ128rr:
7360 case X86::VADDPDZ256rr:
7361 case X86::VADDPSZ256rr:
7362 case X86::VADDPDZrr:
7363 case X86::VADDPSZrr:
7364 case X86::VADDSDrr:
7365 case X86::VADDSSrr:
7366 case X86::VADDSDZrr:
7367 case X86::VADDSSZrr:
7368 case X86::VMULPDrr:
7369 case X86::VMULPSrr:
7370 case X86::VMULPDYrr:
7371 case X86::VMULPSYrr:
7372 case X86::VMULPDZ128rr:
7373 case X86::VMULPSZ128rr:
7374 case X86::VMULPDZ256rr:
7375 case X86::VMULPSZ256rr:
7376 case X86::VMULPDZrr:
7377 case X86::VMULPSZrr:
7378 case X86::VMULSDrr:
7379 case X86::VMULSSrr:
7380 case X86::VMULSDZrr:
7381 case X86::VMULSSZrr:
7382 return Inst.getParent()->getParent()->getTarget().Options.UnsafeFPMath;
7383 default:
7384 return false;
7385 }
7386 }
7387
7388 Optional<ParamLoadedValue>
7389 X86InstrInfo::describeLoadedValue(const MachineInstr &MI) const {
7390 const MachineOperand *Op = nullptr;
7391 DIExpression *Expr = nullptr;
7392
7393 switch (MI.getOpcode()) {
7394 case X86::LEA32r:
7395 case X86::LEA64r:
7396 case X86::LEA64_32r: {
7397 // Operand 4 could be global address. For now we do not support
7398 // such situation.
7399 if (!MI.getOperand(4).isImm() || !MI.getOperand(2).isImm())
7400 return None;
7401
7402 const MachineOperand &Op1 = MI.getOperand(1);
7403 const MachineOperand &Op2 = MI.getOperand(3);
7404 const TargetRegisterInfo *TRI = &getRegisterInfo();
7405 assert(Op2.isReg() && (Op2.getReg() == X86::NoRegister ||
7406 Register::isPhysicalRegister(Op2.getReg())));
7407
7408 // Omit situations like:
7409 // %rsi = lea %rsi, 4, ...
7410 if ((Op1.isReg() && Op1.getReg() == MI.getOperand(0).getReg()) ||
7411 Op2.getReg() == MI.getOperand(0).getReg())
7412 return None;
7413 else if ((Op1.isReg() && Op1.getReg() != X86::NoRegister &&
7414 TRI->regsOverlap(Op1.getReg(), MI.getOperand(0).getReg())) ||
7415 (Op2.getReg() != X86::NoRegister &&
7416 TRI->regsOverlap(Op2.getReg(), MI.getOperand(0).getReg())))
7417 return None;
7418
7419 int64_t Coef = MI.getOperand(2).getImm();
7420 int64_t Offset = MI.getOperand(4).getImm();
7421 SmallVector<uint64_t, 8> Ops;
7422
7423 if ((Op1.isReg() && Op1.getReg() != X86::NoRegister)) {
7424 Op = &Op1;
7425 } else if (Op1.isFI())
7426 Op = &Op1;
7427
7428 if (Op && Op->isReg() && Op->getReg() == Op2.getReg() && Coef > 0) {
7429 Ops.push_back(dwarf::DW_OP_constu);
7430 Ops.push_back(Coef + 1);
7431 Ops.push_back(dwarf::DW_OP_mul);
7432 } else {
7433 if (Op && Op2.getReg() != X86::NoRegister) {
7434 int dwarfReg = TRI->getDwarfRegNum(Op2.getReg(), false);
7435 if (dwarfReg < 0)
7436 return None;
7437 else if (dwarfReg < 32) {
7438 Ops.push_back(dwarf::DW_OP_breg0 + dwarfReg);
7439 Ops.push_back(0);
7440 } else {
7441 Ops.push_back(dwarf::DW_OP_bregx);
7442 Ops.push_back(dwarfReg);
7443 Ops.push_back(0);
7444 }
7445 } else if (!Op) {
7446 assert(Op2.getReg() != X86::NoRegister);
7447 Op = &Op2;
7448 }
7449
7450 if (Coef > 1) {
7451 assert(Op2.getReg() != X86::NoRegister);
7452 Ops.push_back(dwarf::DW_OP_constu);
7453 Ops.push_back(Coef);
7454 Ops.push_back(dwarf::DW_OP_mul);
7455 }
7456
7457 if (((Op1.isReg() && Op1.getReg() != X86::NoRegister) || Op1.isFI()) &&
7458 Op2.getReg() != X86::NoRegister) {
7459 Ops.push_back(dwarf::DW_OP_plus);
7460 }
7461 }
7462
7463 DIExpression::appendOffset(Ops, Offset);
7464 Expr = DIExpression::get(MI.getMF()->getFunction().getContext(), Ops);
7465
7466 return ParamLoadedValue(Op, Expr);;
7467 }
7468 default:
7469 return TargetInstrInfo::describeLoadedValue(MI);
7470 }
7471 }
7472
7473 /// This is an architecture-specific helper function of reassociateOps.
7474 /// Set special operand attributes for new instructions after reassociation.
7475 void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
7476 MachineInstr &OldMI2,
7477 MachineInstr &NewMI1,
7478 MachineInstr &NewMI2) const {
7479 // Integer instructions define an implicit EFLAGS source register operand as
7480 // the third source (fourth total) operand.
7481 if (OldMI1.getNumOperands() != 4 || OldMI2.getNumOperands() != 4)
7482 return;
7483
7484 assert(NewMI1.getNumOperands() == 4 && NewMI2.getNumOperands() == 4 &&
7485 "Unexpected instruction type for reassociation");
7486
7487 MachineOperand &OldOp1 = OldMI1.getOperand(3);
7488 MachineOperand &OldOp2 = OldMI2.getOperand(3);
7489 MachineOperand &NewOp1 = NewMI1.getOperand(3);
7490 MachineOperand &NewOp2 = NewMI2.getOperand(3);
7491
7492 assert(OldOp1.isReg() && OldOp1.getReg() == X86::EFLAGS && OldOp1.isDead() &&
7493 "Must have dead EFLAGS operand in reassociable instruction");
7494 assert(OldOp2.isReg() && OldOp2.getReg() == X86::EFLAGS && OldOp2.isDead() &&
7495 "Must have dead EFLAGS operand in reassociable instruction");
7496
7497 (void)OldOp1;
7498 (void)OldOp2;
7499
7500 assert(NewOp1.isReg() && NewOp1.getReg() == X86::EFLAGS &&
7501 "Unexpected operand in reassociable instruction");
7502 assert(NewOp2.isReg() && NewOp2.getReg() == X86::EFLAGS &&
7503 "Unexpected operand in reassociable instruction");
7504
7505 // Mark the new EFLAGS operands as dead to be helpful to subsequent iterations
7506 // of this pass or other passes. The EFLAGS operands must be dead in these new
7507 // instructions because the EFLAGS operands in the original instructions must
7508 // be dead in order for reassociation to occur.
7509 NewOp1.setIsDead();
7510 NewOp2.setIsDead();
7511 }
7512
7513 std::pair<unsigned, unsigned>
7514 X86InstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
7515 return std::make_pair(TF, 0u);
7516 }
7517
7518 ArrayRef<std::pair<unsigned, const char *>>
7519 X86InstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
7520 using namespace X86II;
7521 static const std::pair<unsigned, const char *> TargetFlags[] = {
7522 {MO_GOT_ABSOLUTE_ADDRESS, "x86-got-absolute-address"},
7523 {MO_PIC_BASE_OFFSET, "x86-pic-base-offset"},
7524 {MO_GOT, "x86-got"},
7525 {MO_GOTOFF, "x86-gotoff"},
7526 {MO_GOTPCREL, "x86-gotpcrel"},
7527 {MO_PLT, "x86-plt"},
7528 {MO_TLSGD, "x86-tlsgd"},
7529 {MO_TLSLD, "x86-tlsld"},
7530 {MO_TLSLDM, "x86-tlsldm"},
7531 {MO_GOTTPOFF, "x86-gottpoff"},
7532 {MO_INDNTPOFF, "x86-indntpoff"},
7533 {MO_TPOFF, "x86-tpoff"},
7534 {MO_DTPOFF, "x86-dtpoff"},
7535 {MO_NTPOFF, "x86-ntpoff"},
7536 {MO_GOTNTPOFF, "x86-gotntpoff"},
7537 {MO_DLLIMPORT, "x86-dllimport"},
7538 {MO_DARWIN_NONLAZY, "x86-darwin-nonlazy"},
7539 {MO_DARWIN_NONLAZY_PIC_BASE, "x86-darwin-nonlazy-pic-base"},
7540 {MO_TLVP, "x86-tlvp"},
7541 {MO_TLVP_PIC_BASE, "x86-tlvp-pic-base"},
7542 {MO_SECREL, "x86-secrel"},
7543 {MO_COFFSTUB, "x86-coffstub"}};
7544 return makeArrayRef(TargetFlags);
7545 }
7546
7547 namespace {
7548 /// Create Global Base Reg pass. This initializes the PIC
7549 /// global base register for x86-32.
7550 struct CGBR : public MachineFunctionPass {
7551 static char ID;
7552 CGBR() : MachineFunctionPass(ID) {}
7553
7554 bool runOnMachineFunction(MachineFunction &MF) override {
7555 const X86TargetMachine *TM =
7556 static_cast<const X86TargetMachine *>(&MF.getTarget());
7557 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
7558
7559 // Don't do anything in the 64-bit small and kernel code models. They use
7560 // RIP-relative addressing for everything.
7561 if (STI.is64Bit() && (TM->getCodeModel() == CodeModel::Small ||
7562 TM->getCodeModel() == CodeModel::Kernel))
7563 return false;
7564
7565 // Only emit a global base reg in PIC mode.
7566 if (!TM->isPositionIndependent())
7567 return false;
7568
7569 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
7570 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
7571
7572 // If we didn't need a GlobalBaseReg, don't insert code.
7573 if (GlobalBaseReg == 0)
7574 return false;
7575
7576 // Insert the set of GlobalBaseReg into the first MBB of the function
7577 MachineBasicBlock &FirstMBB = MF.front();
7578 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
7579 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
7580 MachineRegisterInfo &RegInfo = MF.getRegInfo();
7581 const X86InstrInfo *TII = STI.getInstrInfo();
7582
7583 unsigned PC;
7584 if (STI.isPICStyleGOT())
7585 PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
7586 else
7587 PC = GlobalBaseReg;
7588
7589 if (STI.is64Bit()) {
7590 if (TM->getCodeModel() == CodeModel::Medium) {
7591 // In the medium code model, use a RIP-relative LEA to materialize the
7592 // GOT.
7593 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::LEA64r), PC)
7594 .addReg(X86::RIP)
7595 .addImm(0)
7596 .addReg(0)
7597 .addExternalSymbol("_GLOBAL_OFFSET_TABLE_")
7598 .addReg(0);
7599 } else if (TM->getCodeModel() == CodeModel::Large) {
7600 // In the large code model, we are aiming for this code, though the
7601 // register allocation may vary:
7602 // leaq .LN$pb(%rip), %rax
7603 // movq $_GLOBAL_OFFSET_TABLE_ - .LN$pb, %rcx
7604 // addq %rcx, %rax
7605 // RAX now holds address of _GLOBAL_OFFSET_TABLE_.
7606 Register PBReg = RegInfo.createVirtualRegister(&X86::GR64RegClass);
7607 Register GOTReg = RegInfo.createVirtualRegister(&X86::GR64RegClass);
7608 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::LEA64r), PBReg)
7609 .addReg(X86::RIP)
7610 .addImm(0)
7611 .addReg(0)
7612 .addSym(MF.getPICBaseSymbol())
7613 .addReg(0);
7614 std::prev(MBBI)->setPreInstrSymbol(MF, MF.getPICBaseSymbol());
7615 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOV64ri), GOTReg)
7616 .addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
7617 X86II::MO_PIC_BASE_OFFSET);
7618 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD64rr), PC)
7619 .addReg(PBReg, RegState::Kill)
7620 .addReg(GOTReg, RegState::Kill);
7621 } else {
7622 llvm_unreachable("unexpected code model");
7623 }
7624 } else {
7625 // Operand of MovePCtoStack is completely ignored by asm printer. It's
7626 // only used in JIT code emission as displacement to pc.
7627 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
7628
7629 // If we're using vanilla 'GOT' PIC style, we should use relative
7630 // addressing not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
7631 if (STI.isPICStyleGOT()) {
7632 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel],
7633 // %some_register
7634 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
7635 .addReg(PC)
7636 .addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
7637 X86II::MO_GOT_ABSOLUTE_ADDRESS);
7638 }
7639 }
7640
7641 return true;
7642 }
7643
7644 StringRef getPassName() const override {
7645 return "X86 PIC Global Base Reg Initialization";
7646 }
7647
7648 void getAnalysisUsage(AnalysisUsage &AU) const override {
7649 AU.setPreservesCFG();
7650 MachineFunctionPass::getAnalysisUsage(AU);
7651 }
7652 };
7653 }
7654
7655 char CGBR::ID = 0;
7656 FunctionPass*
7657 llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
7658
7659 namespace {
7660 struct LDTLSCleanup : public MachineFunctionPass {
7661 static char ID;
7662 LDTLSCleanup() : MachineFunctionPass(ID) {}
7663
7664 bool runOnMachineFunction(MachineFunction &MF) override {
7665 if (skipFunction(MF.getFunction()))
7666 return false;
7667
7668 X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
7669 if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
7670 // No point folding accesses if there isn't at least two.
7671 return false;
7672 }
7673
7674 MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
7675 return VisitNode(DT->getRootNode(), 0);
7676 }
7677
7678 // Visit the dominator subtree rooted at Node in pre-order.
7679 // If TLSBaseAddrReg is non-null, then use that to replace any
7680 // TLS_base_addr instructions. Otherwise, create the register
7681 // when the first such instruction is seen, and then use it
7682 // as we encounter more instructions.
7683 bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
7684 MachineBasicBlock *BB = Node->getBlock();
7685 bool Changed = false;
7686
7687 // Traverse the current block.
7688 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
7689 ++I) {
7690 switch (I->getOpcode()) {
7691 case X86::TLS_base_addr32:
7692 case X86::TLS_base_addr64:
7693 if (TLSBaseAddrReg)
7694 I = ReplaceTLSBaseAddrCall(*I, TLSBaseAddrReg);
7695 else
7696 I = SetRegister(*I, &TLSBaseAddrReg);
7697 Changed = true;
7698 break;
7699 default:
7700 break;
7701 }
7702 }
7703
7704 // Visit the children of this block in the dominator tree.
7705 for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
7706 I != E; ++I) {
7707 Changed |= VisitNode(*I, TLSBaseAddrReg);
7708 }
7709
7710 return Changed;
7711 }
7712
7713 // Replace the TLS_base_addr instruction I with a copy from
7714 // TLSBaseAddrReg, returning the new instruction.
7715 MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr &I,
7716 unsigned TLSBaseAddrReg) {
7717 MachineFunction *MF = I.getParent()->getParent();
7718 const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
7719 const bool is64Bit = STI.is64Bit();
7720 const X86InstrInfo *TII = STI.getInstrInfo();
7721
7722 // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
7723 MachineInstr *Copy =
7724 BuildMI(*I.getParent(), I, I.getDebugLoc(),
7725 TII->get(TargetOpcode::COPY), is64Bit ? X86::RAX : X86::EAX)
7726 .addReg(TLSBaseAddrReg);
7727
7728 // Erase the TLS_base_addr instruction.
7729 I.eraseFromParent();
7730
7731 return Copy;
7732 }
7733
7734 // Create a virtual register in *TLSBaseAddrReg, and populate it by
7735 // inserting a copy instruction after I. Returns the new instruction.
7736 MachineInstr *SetRegister(MachineInstr &I, unsigned *TLSBaseAddrReg) {
7737 MachineFunction *MF = I.getParent()->getParent();
7738 const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
7739 const bool is64Bit = STI.is64Bit();
7740 const X86InstrInfo *TII = STI.getInstrInfo();
7741
7742 // Create a virtual register for the TLS base address.
7743 MachineRegisterInfo &RegInfo = MF->getRegInfo();
7744 *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
7745 ? &X86::GR64RegClass
7746 : &X86::GR32RegClass);
7747
7748 // Insert a copy from RAX/EAX to TLSBaseAddrReg.
7749 MachineInstr *Next = I.getNextNode();
7750 MachineInstr *Copy =
7751 BuildMI(*I.getParent(), Next, I.getDebugLoc(),
7752 TII->get(TargetOpcode::COPY), *TLSBaseAddrReg)
7753 .addReg(is64Bit ? X86::RAX : X86::EAX);
7754
7755 return Copy;
7756 }
7757
7758 StringRef getPassName() const override {
7759 return "Local Dynamic TLS Access Clean-up";
7760 }
7761
7762 void getAnalysisUsage(AnalysisUsage &AU) const override {
7763 AU.setPreservesCFG();
7764 AU.addRequired<MachineDominatorTree>();
7765 MachineFunctionPass::getAnalysisUsage(AU);
7766 }
7767 };
7768 }
7769
7770 char LDTLSCleanup::ID = 0;
7771 FunctionPass*
7772 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }
7773
7774 /// Constants defining how certain sequences should be outlined.
7775 ///
7776 /// \p MachineOutlinerDefault implies that the function is called with a call
7777 /// instruction, and a return must be emitted for the outlined function frame.
7778 ///
7779 /// That is,
7780 ///
7781 /// I1 OUTLINED_FUNCTION:
7782 /// I2 --> call OUTLINED_FUNCTION I1
7783 /// I3 I2
7784 /// I3
7785 /// ret
7786 ///
7787 /// * Call construction overhead: 1 (call instruction)
7788 /// * Frame construction overhead: 1 (return instruction)
7789 ///
7790 /// \p MachineOutlinerTailCall implies that the function is being tail called.
7791 /// A jump is emitted instead of a call, and the return is already present in
7792 /// the outlined sequence. That is,
7793 ///
7794 /// I1 OUTLINED_FUNCTION:
7795 /// I2 --> jmp OUTLINED_FUNCTION I1
7796 /// ret I2
7797 /// ret
7798 ///
7799 /// * Call construction overhead: 1 (jump instruction)
7800 /// * Frame construction overhead: 0 (don't need to return)
7801 ///
7802 enum MachineOutlinerClass {
7803 MachineOutlinerDefault,
7804 MachineOutlinerTailCall
7805 };
7806
7807 outliner::OutlinedFunction X86InstrInfo::getOutliningCandidateInfo(
7808 std::vector<outliner::Candidate> &RepeatedSequenceLocs) const {
7809 unsigned SequenceSize =
7810 std::accumulate(RepeatedSequenceLocs[0].front(),
7811 std::next(RepeatedSequenceLocs[0].back()), 0,
7812 [](unsigned Sum, const MachineInstr &MI) {
7813 // FIXME: x86 doesn't implement getInstSizeInBytes, so
7814 // we can't tell the cost. Just assume each instruction
7815 // is one byte.
7816 if (MI.isDebugInstr() || MI.isKill())
7817 return Sum;
7818 return Sum + 1;
7819 });
7820
7821 // FIXME: Use real size in bytes for call and ret instructions.
7822 if (RepeatedSequenceLocs[0].back()->isTerminator()) {
7823 for (outliner::Candidate &C : RepeatedSequenceLocs)
7824 C.setCallInfo(MachineOutlinerTailCall, 1);
7825
7826 return outliner::OutlinedFunction(RepeatedSequenceLocs, SequenceSize,
7827 0, // Number of bytes to emit frame.
7828 MachineOutlinerTailCall // Type of frame.
7829 );
7830 }
7831
7832 for (outliner::Candidate &C : RepeatedSequenceLocs)
7833 C.setCallInfo(MachineOutlinerDefault, 1);
7834
7835 return outliner::OutlinedFunction(RepeatedSequenceLocs, SequenceSize, 1,
7836 MachineOutlinerDefault);
7837 }
7838
7839 bool X86InstrInfo::isFunctionSafeToOutlineFrom(MachineFunction &MF,
7840 bool OutlineFromLinkOnceODRs) const {
7841 const Function &F = MF.getFunction();
7842
7843 // Does the function use a red zone? If it does, then we can't risk messing
7844 // with the stack.
7845 if (Subtarget.getFrameLowering()->has128ByteRedZone(MF)) {
7846 // It could have a red zone. If it does, then we don't want to touch it.
7847 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
7848 if (!X86FI || X86FI->getUsesRedZone())
7849 return false;
7850 }
7851
7852 // If we *don't* want to outline from things that could potentially be deduped
7853 // then return false.
7854 if (!OutlineFromLinkOnceODRs && F.hasLinkOnceODRLinkage())
7855 return false;
7856
7857 // This function is viable for outlining, so return true.
7858 return true;
7859 }
7860
7861 outliner::InstrType
7862 X86InstrInfo::getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const {
7863 MachineInstr &MI = *MIT;
7864 // Don't allow debug values to impact outlining type.
7865 if (MI.isDebugInstr() || MI.isIndirectDebugValue())
7866 return outliner::InstrType::Invisible;
7867
7868 // At this point, KILL instructions don't really tell us much so we can go
7869 // ahead and skip over them.
7870 if (MI.isKill())
7871 return outliner::InstrType::Invisible;
7872
7873 // Is this a tail call? If yes, we can outline as a tail call.
7874 if (isTailCall(MI))
7875 return outliner::InstrType::Legal;
7876
7877 // Is this the terminator of a basic block?
7878 if (MI.isTerminator() || MI.isReturn()) {
7879
7880 // Does its parent have any successors in its MachineFunction?
7881 if (MI.getParent()->succ_empty())
7882 return outliner::InstrType::Legal;
7883
7884 // It does, so we can't tail call it.
7885 return outliner::InstrType::Illegal;
7886 }
7887
7888 // Don't outline anything that modifies or reads from the stack pointer.
7889 //
7890 // FIXME: There are instructions which are being manually built without
7891 // explicit uses/defs so we also have to check the MCInstrDesc. We should be
7892 // able to remove the extra checks once those are fixed up. For example,
7893 // sometimes we might get something like %rax = POP64r 1. This won't be
7894 // caught by modifiesRegister or readsRegister even though the instruction
7895 // really ought to be formed so that modifiesRegister/readsRegister would
7896 // catch it.
7897 if (MI.modifiesRegister(X86::RSP, &RI) || MI.readsRegister(X86::RSP, &RI) ||
7898 MI.getDesc().hasImplicitUseOfPhysReg(X86::RSP) ||
7899 MI.getDesc().hasImplicitDefOfPhysReg(X86::RSP))
7900 return outliner::InstrType::Illegal;
7901
7902 // Outlined calls change the instruction pointer, so don't read from it.
7903 if (MI.readsRegister(X86::RIP, &RI) ||
7904 MI.getDesc().hasImplicitUseOfPhysReg(X86::RIP) ||
7905 MI.getDesc().hasImplicitDefOfPhysReg(X86::RIP))
7906 return outliner::InstrType::Illegal;
7907
7908 // Positions can't safely be outlined.
7909 if (MI.isPosition())
7910 return outliner::InstrType::Illegal;
7911
7912 // Make sure none of the operands of this instruction do anything tricky.
7913 for (const MachineOperand &MOP : MI.operands())
7914 if (MOP.isCPI() || MOP.isJTI() || MOP.isCFIIndex() || MOP.isFI() ||
7915 MOP.isTargetIndex())
7916 return outliner::InstrType::Illegal;
7917
7918 return outliner::InstrType::Legal;
7919 }
7920
7921 void X86InstrInfo::buildOutlinedFrame(MachineBasicBlock &MBB,
7922 MachineFunction &MF,
7923 const outliner::OutlinedFunction &OF)
7924 const {
7925 // If we're a tail call, we already have a return, so don't do anything.
7926 if (OF.FrameConstructionID == MachineOutlinerTailCall)
7927 return;
7928
7929 // We're a normal call, so our sequence doesn't have a return instruction.
7930 // Add it in.
7931 MachineInstr *retq = BuildMI(MF, DebugLoc(), get(X86::RETQ));
7932 MBB.insert(MBB.end(), retq);
7933 }
7934
7935 MachineBasicBlock::iterator
7936 X86InstrInfo::insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
7937 MachineBasicBlock::iterator &It,
7938 MachineFunction &MF,
7939 const outliner::Candidate &C) const {
7940 // Is it a tail call?
7941 if (C.CallConstructionID == MachineOutlinerTailCall) {
7942 // Yes, just insert a JMP.
7943 It = MBB.insert(It,
7944 BuildMI(MF, DebugLoc(), get(X86::TAILJMPd64))
7945 .addGlobalAddress(M.getNamedValue(MF.getName())));
7946 } else {
7947 // No, insert a call.
7948 It = MBB.insert(It,
7949 BuildMI(MF, DebugLoc(), get(X86::CALL64pcrel32))
7950 .addGlobalAddress(M.getNamedValue(MF.getName())));
7951 }
7952
7953 return It;
7954 }
7955
7956 #define GET_INSTRINFO_HELPERS
7957 #include "X86GenInstrInfo.inc"
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