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[AMDGPU] Check for immediate SrcC in mfma in AsmParser
[llvm-core.git] / lib / Target / X86 / X86MCInstLower.cpp
blob2106387114ec1c56b6e67a443d2dbcd58b2c7ba5
1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains code to lower X86 MachineInstrs to their corresponding
10 // MCInst records.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "MCTargetDesc/X86ATTInstPrinter.h"
15 #include "MCTargetDesc/X86BaseInfo.h"
16 #include "MCTargetDesc/X86InstComments.h"
17 #include "MCTargetDesc/X86TargetStreamer.h"
18 #include "Utils/X86ShuffleDecode.h"
19 #include "X86AsmPrinter.h"
20 #include "X86RegisterInfo.h"
21 #include "X86ShuffleDecodeConstantPool.h"
22 #include "llvm/ADT/Optional.h"
23 #include "llvm/ADT/SmallString.h"
24 #include "llvm/ADT/iterator_range.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
28 #include "llvm/CodeGen/MachineOperand.h"
29 #include "llvm/CodeGen/StackMaps.h"
30 #include "llvm/IR/DataLayout.h"
31 #include "llvm/IR/GlobalValue.h"
32 #include "llvm/IR/Mangler.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/MC/MCCodeEmitter.h"
35 #include "llvm/MC/MCContext.h"
36 #include "llvm/MC/MCExpr.h"
37 #include "llvm/MC/MCFixup.h"
38 #include "llvm/MC/MCInst.h"
39 #include "llvm/MC/MCInstBuilder.h"
40 #include "llvm/MC/MCSection.h"
41 #include "llvm/MC/MCSectionELF.h"
42 #include "llvm/MC/MCStreamer.h"
43 #include "llvm/MC/MCSymbol.h"
44 #include "llvm/MC/MCSymbolELF.h"
45 #include "llvm/Target/TargetLoweringObjectFile.h"
46
47 using namespace llvm;
48
49 namespace {
50
51 /// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst.
52 class X86MCInstLower {
53 MCContext &Ctx;
54 const MachineFunction &MF;
55 const TargetMachine &TM;
56 const MCAsmInfo &MAI;
57 X86AsmPrinter &AsmPrinter;
58
59 public:
60 X86MCInstLower(const MachineFunction &MF, X86AsmPrinter &asmprinter);
61
62 Optional<MCOperand> LowerMachineOperand(const MachineInstr *MI,
63 const MachineOperand &MO) const;
64 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
65
66 MCSymbol *GetSymbolFromOperand(const MachineOperand &MO) const;
67 MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
68
69 private:
70 MachineModuleInfoMachO &getMachOMMI() const;
71 };
72
73 } // end anonymous namespace
74
75 // Emit a minimal sequence of nops spanning NumBytes bytes.
76 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
77 const MCSubtargetInfo &STI);
78
79 void X86AsmPrinter::StackMapShadowTracker::count(MCInst &Inst,
80 const MCSubtargetInfo &STI,
81 MCCodeEmitter *CodeEmitter) {
82 if (InShadow) {
83 SmallString<256> Code;
84 SmallVector<MCFixup, 4> Fixups;
85 raw_svector_ostream VecOS(Code);
86 CodeEmitter->encodeInstruction(Inst, VecOS, Fixups, STI);
87 CurrentShadowSize += Code.size();
88 if (CurrentShadowSize >= RequiredShadowSize)
89 InShadow = false; // The shadow is big enough. Stop counting.
90 }
91 }
92
93 void X86AsmPrinter::StackMapShadowTracker::emitShadowPadding(
94 MCStreamer &OutStreamer, const MCSubtargetInfo &STI) {
95 if (InShadow && CurrentShadowSize < RequiredShadowSize) {
96 InShadow = false;
97 EmitNops(OutStreamer, RequiredShadowSize - CurrentShadowSize,
98 MF->getSubtarget<X86Subtarget>().is64Bit(), STI);
99 }
100 }
101
102 void X86AsmPrinter::EmitAndCountInstruction(MCInst &Inst) {
103 OutStreamer->EmitInstruction(Inst, getSubtargetInfo());
104 SMShadowTracker.count(Inst, getSubtargetInfo(), CodeEmitter.get());
105 }
106
107 X86MCInstLower::X86MCInstLower(const MachineFunction &mf,
108 X86AsmPrinter &asmprinter)
109 : Ctx(mf.getContext()), MF(mf), TM(mf.getTarget()), MAI(*TM.getMCAsmInfo()),
110 AsmPrinter(asmprinter) {}
111
112 MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const {
113 return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>();
114 }
115
116 /// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol
117 /// operand to an MCSymbol.
118 MCSymbol *X86MCInstLower::GetSymbolFromOperand(const MachineOperand &MO) const {
119 const DataLayout &DL = MF.getDataLayout();
120 assert((MO.isGlobal() || MO.isSymbol() || MO.isMBB()) &&
121 "Isn't a symbol reference");
122
123 MCSymbol *Sym = nullptr;
124 SmallString<128> Name;
125 StringRef Suffix;
126
127 switch (MO.getTargetFlags()) {
128 case X86II::MO_DLLIMPORT:
129 // Handle dllimport linkage.
130 Name += "__imp_";
131 break;
132 case X86II::MO_COFFSTUB:
133 Name += ".refptr.";
134 break;
135 case X86II::MO_DARWIN_NONLAZY:
136 case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
137 Suffix = "$non_lazy_ptr";
138 break;
139 }
140
141 if (!Suffix.empty())
142 Name += DL.getPrivateGlobalPrefix();
143
144 if (MO.isGlobal()) {
145 const GlobalValue *GV = MO.getGlobal();
146 AsmPrinter.getNameWithPrefix(Name, GV);
147 } else if (MO.isSymbol()) {
148 Mangler::getNameWithPrefix(Name, MO.getSymbolName(), DL);
149 } else if (MO.isMBB()) {
150 assert(Suffix.empty());
151 Sym = MO.getMBB()->getSymbol();
152 }
153
154 Name += Suffix;
155 if (!Sym)
156 Sym = Ctx.getOrCreateSymbol(Name);
157
158 // If the target flags on the operand changes the name of the symbol, do that
159 // before we return the symbol.
160 switch (MO.getTargetFlags()) {
161 default:
162 break;
163 case X86II::MO_COFFSTUB: {
164 MachineModuleInfoCOFF &MMICOFF =
165 MF.getMMI().getObjFileInfo<MachineModuleInfoCOFF>();
166 MachineModuleInfoImpl::StubValueTy &StubSym = MMICOFF.getGVStubEntry(Sym);
167 if (!StubSym.getPointer()) {
168 assert(MO.isGlobal() && "Extern symbol not handled yet");
169 StubSym = MachineModuleInfoImpl::StubValueTy(
170 AsmPrinter.getSymbol(MO.getGlobal()), true);
171 }
172 break;
173 }
174 case X86II::MO_DARWIN_NONLAZY:
175 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: {
176 MachineModuleInfoImpl::StubValueTy &StubSym =
177 getMachOMMI().getGVStubEntry(Sym);
178 if (!StubSym.getPointer()) {
179 assert(MO.isGlobal() && "Extern symbol not handled yet");
180 StubSym = MachineModuleInfoImpl::StubValueTy(
181 AsmPrinter.getSymbol(MO.getGlobal()),
182 !MO.getGlobal()->hasInternalLinkage());
183 }
184 break;
185 }
186 }
187
188 return Sym;
189 }
190
191 MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
192 MCSymbol *Sym) const {
193 // FIXME: We would like an efficient form for this, so we don't have to do a
194 // lot of extra uniquing.
195 const MCExpr *Expr = nullptr;
196 MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None;
197
198 switch (MO.getTargetFlags()) {
199 default:
200 llvm_unreachable("Unknown target flag on GV operand");
201 case X86II::MO_NO_FLAG: // No flag.
202 // These affect the name of the symbol, not any suffix.
203 case X86II::MO_DARWIN_NONLAZY:
204 case X86II::MO_DLLIMPORT:
205 case X86II::MO_COFFSTUB:
206 break;
207
208 case X86II::MO_TLVP:
209 RefKind = MCSymbolRefExpr::VK_TLVP;
210 break;
211 case X86II::MO_TLVP_PIC_BASE:
212 Expr = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx);
213 // Subtract the pic base.
214 Expr = MCBinaryExpr::createSub(
215 Expr, MCSymbolRefExpr::create(MF.getPICBaseSymbol(), Ctx), Ctx);
216 break;
217 case X86II::MO_SECREL:
218 RefKind = MCSymbolRefExpr::VK_SECREL;
219 break;
220 case X86II::MO_TLSGD:
221 RefKind = MCSymbolRefExpr::VK_TLSGD;
222 break;
223 case X86II::MO_TLSLD:
224 RefKind = MCSymbolRefExpr::VK_TLSLD;
225 break;
226 case X86II::MO_TLSLDM:
227 RefKind = MCSymbolRefExpr::VK_TLSLDM;
228 break;
229 case X86II::MO_GOTTPOFF:
230 RefKind = MCSymbolRefExpr::VK_GOTTPOFF;
231 break;
232 case X86II::MO_INDNTPOFF:
233 RefKind = MCSymbolRefExpr::VK_INDNTPOFF;
234 break;
235 case X86II::MO_TPOFF:
236 RefKind = MCSymbolRefExpr::VK_TPOFF;
237 break;
238 case X86II::MO_DTPOFF:
239 RefKind = MCSymbolRefExpr::VK_DTPOFF;
240 break;
241 case X86II::MO_NTPOFF:
242 RefKind = MCSymbolRefExpr::VK_NTPOFF;
243 break;
244 case X86II::MO_GOTNTPOFF:
245 RefKind = MCSymbolRefExpr::VK_GOTNTPOFF;
246 break;
247 case X86II::MO_GOTPCREL:
248 RefKind = MCSymbolRefExpr::VK_GOTPCREL;
249 break;
250 case X86II::MO_GOT:
251 RefKind = MCSymbolRefExpr::VK_GOT;
252 break;
253 case X86II::MO_GOTOFF:
254 RefKind = MCSymbolRefExpr::VK_GOTOFF;
255 break;
256 case X86II::MO_PLT:
257 RefKind = MCSymbolRefExpr::VK_PLT;
258 break;
259 case X86II::MO_ABS8:
260 RefKind = MCSymbolRefExpr::VK_X86_ABS8;
261 break;
262 case X86II::MO_PIC_BASE_OFFSET:
263 case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
264 Expr = MCSymbolRefExpr::create(Sym, Ctx);
265 // Subtract the pic base.
266 Expr = MCBinaryExpr::createSub(
267 Expr, MCSymbolRefExpr::create(MF.getPICBaseSymbol(), Ctx), Ctx);
268 if (MO.isJTI()) {
269 assert(MAI.doesSetDirectiveSuppressReloc());
270 // If .set directive is supported, use it to reduce the number of
271 // relocations the assembler will generate for differences between
272 // local labels. This is only safe when the symbols are in the same
273 // section so we are restricting it to jumptable references.
274 MCSymbol *Label = Ctx.createTempSymbol();
275 AsmPrinter.OutStreamer->EmitAssignment(Label, Expr);
276 Expr = MCSymbolRefExpr::create(Label, Ctx);
277 }
278 break;
279 }
280
281 if (!Expr)
282 Expr = MCSymbolRefExpr::create(Sym, RefKind, Ctx);
283
284 if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
285 Expr = MCBinaryExpr::createAdd(
286 Expr, MCConstantExpr::create(MO.getOffset(), Ctx), Ctx);
287 return MCOperand::createExpr(Expr);
288 }
289
290 /// Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with
291 /// a short fixed-register form.
292 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
293 unsigned ImmOp = Inst.getNumOperands() - 1;
294 assert(Inst.getOperand(0).isReg() &&
295 (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) &&
296 ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
297 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
298 Inst.getNumOperands() == 2) &&
299 "Unexpected instruction!");
300
301 // Check whether the destination register can be fixed.
302 unsigned Reg = Inst.getOperand(0).getReg();
303 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
304 return;
305
306 // If so, rewrite the instruction.
307 MCOperand Saved = Inst.getOperand(ImmOp);
308 Inst = MCInst();
309 Inst.setOpcode(Opcode);
310 Inst.addOperand(Saved);
311 }
312
313 /// If a movsx instruction has a shorter encoding for the used register
314 /// simplify the instruction to use it instead.
315 static void SimplifyMOVSX(MCInst &Inst) {
316 unsigned NewOpcode = 0;
317 unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg();
318 switch (Inst.getOpcode()) {
319 default:
320 llvm_unreachable("Unexpected instruction!");
321 case X86::MOVSX16rr8: // movsbw %al, %ax --> cbtw
322 if (Op0 == X86::AX && Op1 == X86::AL)
323 NewOpcode = X86::CBW;
324 break;
325 case X86::MOVSX32rr16: // movswl %ax, %eax --> cwtl
326 if (Op0 == X86::EAX && Op1 == X86::AX)
327 NewOpcode = X86::CWDE;
328 break;
329 case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq
330 if (Op0 == X86::RAX && Op1 == X86::EAX)
331 NewOpcode = X86::CDQE;
332 break;
333 }
334
335 if (NewOpcode != 0) {
336 Inst = MCInst();
337 Inst.setOpcode(NewOpcode);
338 }
339 }
340
341 /// Simplify things like MOV32rm to MOV32o32a.
342 static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst,
343 unsigned Opcode) {
344 // Don't make these simplifications in 64-bit mode; other assemblers don't
345 // perform them because they make the code larger.
346 if (Printer.getSubtarget().is64Bit())
347 return;
348
349 bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg();
350 unsigned AddrBase = IsStore;
351 unsigned RegOp = IsStore ? 0 : 5;
352 unsigned AddrOp = AddrBase + 3;
353 assert(
354 Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
355 Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() &&
356 Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() &&
357 Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() &&
358 Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() &&
359 (Inst.getOperand(AddrOp).isExpr() || Inst.getOperand(AddrOp).isImm()) &&
360 "Unexpected instruction!");
361
362 // Check whether the destination register can be fixed.
363 unsigned Reg = Inst.getOperand(RegOp).getReg();
364 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
365 return;
366
367 // Check whether this is an absolute address.
368 // FIXME: We know TLVP symbol refs aren't, but there should be a better way
369 // to do this here.
370 bool Absolute = true;
371 if (Inst.getOperand(AddrOp).isExpr()) {
372 const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr();
373 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE))
374 if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP)
375 Absolute = false;
376 }
377
378 if (Absolute &&
379 (Inst.getOperand(AddrBase + X86::AddrBaseReg).getReg() != 0 ||
380 Inst.getOperand(AddrBase + X86::AddrScaleAmt).getImm() != 1 ||
381 Inst.getOperand(AddrBase + X86::AddrIndexReg).getReg() != 0))
382 return;
383
384 // If so, rewrite the instruction.
385 MCOperand Saved = Inst.getOperand(AddrOp);
386 MCOperand Seg = Inst.getOperand(AddrBase + X86::AddrSegmentReg);
387 Inst = MCInst();
388 Inst.setOpcode(Opcode);
389 Inst.addOperand(Saved);
390 Inst.addOperand(Seg);
391 }
392
393 static unsigned getRetOpcode(const X86Subtarget &Subtarget) {
394 return Subtarget.is64Bit() ? X86::RETQ : X86::RETL;
395 }
396
397 Optional<MCOperand>
398 X86MCInstLower::LowerMachineOperand(const MachineInstr *MI,
399 const MachineOperand &MO) const {
400 switch (MO.getType()) {
401 default:
402 MI->print(errs());
403 llvm_unreachable("unknown operand type");
404 case MachineOperand::MO_Register:
405 // Ignore all implicit register operands.
406 if (MO.isImplicit())
407 return None;
408 return MCOperand::createReg(MO.getReg());
409 case MachineOperand::MO_Immediate:
410 return MCOperand::createImm(MO.getImm());
411 case MachineOperand::MO_MachineBasicBlock:
412 case MachineOperand::MO_GlobalAddress:
413 case MachineOperand::MO_ExternalSymbol:
414 return LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
415 case MachineOperand::MO_MCSymbol:
416 return LowerSymbolOperand(MO, MO.getMCSymbol());
417 case MachineOperand::MO_JumpTableIndex:
418 return LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex()));
419 case MachineOperand::MO_ConstantPoolIndex:
420 return LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex()));
421 case MachineOperand::MO_BlockAddress:
422 return LowerSymbolOperand(
423 MO, AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress()));
424 case MachineOperand::MO_RegisterMask:
425 // Ignore call clobbers.
426 return None;
427 }
428 }
429
430 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
431 OutMI.setOpcode(MI->getOpcode());
432
433 for (const MachineOperand &MO : MI->operands())
434 if (auto MaybeMCOp = LowerMachineOperand(MI, MO))
435 OutMI.addOperand(MaybeMCOp.getValue());
436
437 // Handle a few special cases to eliminate operand modifiers.
438 switch (OutMI.getOpcode()) {
439 case X86::LEA64_32r:
440 case X86::LEA64r:
441 case X86::LEA16r:
442 case X86::LEA32r:
443 // LEA should have a segment register, but it must be empty.
444 assert(OutMI.getNumOperands() == 1 + X86::AddrNumOperands &&
445 "Unexpected # of LEA operands");
446 assert(OutMI.getOperand(1 + X86::AddrSegmentReg).getReg() == 0 &&
447 "LEA has segment specified!");
448 break;
449
450 // Commute operands to get a smaller encoding by using VEX.R instead of VEX.B
451 // if one of the registers is extended, but other isn't.
452 case X86::VMOVZPQILo2PQIrr:
453 case X86::VMOVAPDrr:
454 case X86::VMOVAPDYrr:
455 case X86::VMOVAPSrr:
456 case X86::VMOVAPSYrr:
457 case X86::VMOVDQArr:
458 case X86::VMOVDQAYrr:
459 case X86::VMOVDQUrr:
460 case X86::VMOVDQUYrr:
461 case X86::VMOVUPDrr:
462 case X86::VMOVUPDYrr:
463 case X86::VMOVUPSrr:
464 case X86::VMOVUPSYrr: {
465 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
466 X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg())) {
467 unsigned NewOpc;
468 switch (OutMI.getOpcode()) {
469 default: llvm_unreachable("Invalid opcode");
470 case X86::VMOVZPQILo2PQIrr: NewOpc = X86::VMOVPQI2QIrr; break;
471 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
472 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
473 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break;
474 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
475 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break;
476 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
477 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break;
478 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
479 case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break;
480 case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
481 case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break;
482 case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
483 }
484 OutMI.setOpcode(NewOpc);
485 }
486 break;
487 }
488 case X86::VMOVSDrr:
489 case X86::VMOVSSrr: {
490 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
491 X86II::isX86_64ExtendedReg(OutMI.getOperand(2).getReg())) {
492 unsigned NewOpc;
493 switch (OutMI.getOpcode()) {
494 default: llvm_unreachable("Invalid opcode");
495 case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV; break;
496 case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV; break;
497 }
498 OutMI.setOpcode(NewOpc);
499 }
500 break;
501 }
502
503 // TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions used to have
504 // register inputs modeled as normal uses instead of implicit uses. As such,
505 // they we used to truncate off all but the first operand (the callee). This
506 // issue seems to have been fixed at some point. This assert verifies that.
507 case X86::TAILJMPr64:
508 case X86::TAILJMPr64_REX:
509 case X86::CALL64r:
510 case X86::CALL64pcrel32:
511 assert(OutMI.getNumOperands() == 1 && "Unexpected number of operands!");
512 break;
513
514 case X86::EH_RETURN:
515 case X86::EH_RETURN64: {
516 OutMI = MCInst();
517 OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget()));
518 break;
519 }
520
521 case X86::CLEANUPRET: {
522 // Replace CLEANUPRET with the appropriate RET.
523 OutMI = MCInst();
524 OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget()));
525 break;
526 }
527
528 case X86::CATCHRET: {
529 // Replace CATCHRET with the appropriate RET.
530 const X86Subtarget &Subtarget = AsmPrinter.getSubtarget();
531 unsigned ReturnReg = Subtarget.is64Bit() ? X86::RAX : X86::EAX;
532 OutMI = MCInst();
533 OutMI.setOpcode(getRetOpcode(Subtarget));
534 OutMI.addOperand(MCOperand::createReg(ReturnReg));
535 break;
536 }
537
538 // TAILJMPd, TAILJMPd64, TailJMPd_cc - Lower to the correct jump
539 // instruction.
540 {
541 unsigned Opcode;
542 case X86::TAILJMPr:
543 Opcode = X86::JMP32r;
544 goto SetTailJmpOpcode;
545 case X86::TAILJMPd:
546 case X86::TAILJMPd64:
547 Opcode = X86::JMP_1;
548 goto SetTailJmpOpcode;
549
550 SetTailJmpOpcode:
551 assert(OutMI.getNumOperands() == 1 && "Unexpected number of operands!");
552 OutMI.setOpcode(Opcode);
553 break;
554 }
555
556 case X86::TAILJMPd_CC:
557 case X86::TAILJMPd64_CC: {
558 assert(OutMI.getNumOperands() == 2 && "Unexpected number of operands!");
559 OutMI.setOpcode(X86::JCC_1);
560 break;
561 }
562
563 case X86::DEC16r:
564 case X86::DEC32r:
565 case X86::INC16r:
566 case X86::INC32r:
567 // If we aren't in 64-bit mode we can use the 1-byte inc/dec instructions.
568 if (!AsmPrinter.getSubtarget().is64Bit()) {
569 unsigned Opcode;
570 switch (OutMI.getOpcode()) {
571 default: llvm_unreachable("Invalid opcode");
572 case X86::DEC16r: Opcode = X86::DEC16r_alt; break;
573 case X86::DEC32r: Opcode = X86::DEC32r_alt; break;
574 case X86::INC16r: Opcode = X86::INC16r_alt; break;
575 case X86::INC32r: Opcode = X86::INC32r_alt; break;
576 }
577 OutMI.setOpcode(Opcode);
578 }
579 break;
580
581 // We don't currently select the correct instruction form for instructions
582 // which have a short %eax, etc. form. Handle this by custom lowering, for
583 // now.
584 //
585 // Note, we are currently not handling the following instructions:
586 // MOV64ao8, MOV64o8a
587 // XCHG16ar, XCHG32ar, XCHG64ar
588 case X86::MOV8mr_NOREX:
589 case X86::MOV8mr:
590 case X86::MOV8rm_NOREX:
591 case X86::MOV8rm:
592 case X86::MOV16mr:
593 case X86::MOV16rm:
594 case X86::MOV32mr:
595 case X86::MOV32rm: {
596 unsigned NewOpc;
597 switch (OutMI.getOpcode()) {
598 default: llvm_unreachable("Invalid opcode");
599 case X86::MOV8mr_NOREX:
600 case X86::MOV8mr: NewOpc = X86::MOV8o32a; break;
601 case X86::MOV8rm_NOREX:
602 case X86::MOV8rm: NewOpc = X86::MOV8ao32; break;
603 case X86::MOV16mr: NewOpc = X86::MOV16o32a; break;
604 case X86::MOV16rm: NewOpc = X86::MOV16ao32; break;
605 case X86::MOV32mr: NewOpc = X86::MOV32o32a; break;
606 case X86::MOV32rm: NewOpc = X86::MOV32ao32; break;
607 }
608 SimplifyShortMoveForm(AsmPrinter, OutMI, NewOpc);
609 break;
610 }
611
612 case X86::ADC8ri: case X86::ADC16ri: case X86::ADC32ri: case X86::ADC64ri32:
613 case X86::ADD8ri: case X86::ADD16ri: case X86::ADD32ri: case X86::ADD64ri32:
614 case X86::AND8ri: case X86::AND16ri: case X86::AND32ri: case X86::AND64ri32:
615 case X86::CMP8ri: case X86::CMP16ri: case X86::CMP32ri: case X86::CMP64ri32:
616 case X86::OR8ri: case X86::OR16ri: case X86::OR32ri: case X86::OR64ri32:
617 case X86::SBB8ri: case X86::SBB16ri: case X86::SBB32ri: case X86::SBB64ri32:
618 case X86::SUB8ri: case X86::SUB16ri: case X86::SUB32ri: case X86::SUB64ri32:
619 case X86::TEST8ri:case X86::TEST16ri:case X86::TEST32ri:case X86::TEST64ri32:
620 case X86::XOR8ri: case X86::XOR16ri: case X86::XOR32ri: case X86::XOR64ri32: {
621 unsigned NewOpc;
622 switch (OutMI.getOpcode()) {
623 default: llvm_unreachable("Invalid opcode");
624 case X86::ADC8ri: NewOpc = X86::ADC8i8; break;
625 case X86::ADC16ri: NewOpc = X86::ADC16i16; break;
626 case X86::ADC32ri: NewOpc = X86::ADC32i32; break;
627 case X86::ADC64ri32: NewOpc = X86::ADC64i32; break;
628 case X86::ADD8ri: NewOpc = X86::ADD8i8; break;
629 case X86::ADD16ri: NewOpc = X86::ADD16i16; break;
630 case X86::ADD32ri: NewOpc = X86::ADD32i32; break;
631 case X86::ADD64ri32: NewOpc = X86::ADD64i32; break;
632 case X86::AND8ri: NewOpc = X86::AND8i8; break;
633 case X86::AND16ri: NewOpc = X86::AND16i16; break;
634 case X86::AND32ri: NewOpc = X86::AND32i32; break;
635 case X86::AND64ri32: NewOpc = X86::AND64i32; break;
636 case X86::CMP8ri: NewOpc = X86::CMP8i8; break;
637 case X86::CMP16ri: NewOpc = X86::CMP16i16; break;
638 case X86::CMP32ri: NewOpc = X86::CMP32i32; break;
639 case X86::CMP64ri32: NewOpc = X86::CMP64i32; break;
640 case X86::OR8ri: NewOpc = X86::OR8i8; break;
641 case X86::OR16ri: NewOpc = X86::OR16i16; break;
642 case X86::OR32ri: NewOpc = X86::OR32i32; break;
643 case X86::OR64ri32: NewOpc = X86::OR64i32; break;
644 case X86::SBB8ri: NewOpc = X86::SBB8i8; break;
645 case X86::SBB16ri: NewOpc = X86::SBB16i16; break;
646 case X86::SBB32ri: NewOpc = X86::SBB32i32; break;
647 case X86::SBB64ri32: NewOpc = X86::SBB64i32; break;
648 case X86::SUB8ri: NewOpc = X86::SUB8i8; break;
649 case X86::SUB16ri: NewOpc = X86::SUB16i16; break;
650 case X86::SUB32ri: NewOpc = X86::SUB32i32; break;
651 case X86::SUB64ri32: NewOpc = X86::SUB64i32; break;
652 case X86::TEST8ri: NewOpc = X86::TEST8i8; break;
653 case X86::TEST16ri: NewOpc = X86::TEST16i16; break;
654 case X86::TEST32ri: NewOpc = X86::TEST32i32; break;
655 case X86::TEST64ri32: NewOpc = X86::TEST64i32; break;
656 case X86::XOR8ri: NewOpc = X86::XOR8i8; break;
657 case X86::XOR16ri: NewOpc = X86::XOR16i16; break;
658 case X86::XOR32ri: NewOpc = X86::XOR32i32; break;
659 case X86::XOR64ri32: NewOpc = X86::XOR64i32; break;
660 }
661 SimplifyShortImmForm(OutMI, NewOpc);
662 break;
663 }
664
665 // Try to shrink some forms of movsx.
666 case X86::MOVSX16rr8:
667 case X86::MOVSX32rr16:
668 case X86::MOVSX64rr32:
669 SimplifyMOVSX(OutMI);
670 break;
671 }
672 }
673
674 void X86AsmPrinter::LowerTlsAddr(X86MCInstLower &MCInstLowering,
675 const MachineInstr &MI) {
676 bool Is64Bits = MI.getOpcode() == X86::TLS_addr64 ||
677 MI.getOpcode() == X86::TLS_base_addr64;
678 MCContext &Ctx = OutStreamer->getContext();
679
680 MCSymbolRefExpr::VariantKind SRVK;
681 switch (MI.getOpcode()) {
682 case X86::TLS_addr32:
683 case X86::TLS_addr64:
684 SRVK = MCSymbolRefExpr::VK_TLSGD;
685 break;
686 case X86::TLS_base_addr32:
687 SRVK = MCSymbolRefExpr::VK_TLSLDM;
688 break;
689 case X86::TLS_base_addr64:
690 SRVK = MCSymbolRefExpr::VK_TLSLD;
691 break;
692 default:
693 llvm_unreachable("unexpected opcode");
694 }
695
696 const MCSymbolRefExpr *Sym = MCSymbolRefExpr::create(
697 MCInstLowering.GetSymbolFromOperand(MI.getOperand(3)), SRVK, Ctx);
698
699 // As of binutils 2.32, ld has a bogus TLS relaxation error when the GD/LD
700 // code sequence using R_X86_64_GOTPCREL (instead of R_X86_64_GOTPCRELX) is
701 // attempted to be relaxed to IE/LE (binutils PR24784). Work around the bug by
702 // only using GOT when GOTPCRELX is enabled.
703 // TODO Delete the workaround when GOTPCRELX becomes commonplace.
704 bool UseGot = MMI->getModule()->getRtLibUseGOT() &&
705 Ctx.getAsmInfo()->canRelaxRelocations();
706
707 if (Is64Bits) {
708 bool NeedsPadding = SRVK == MCSymbolRefExpr::VK_TLSGD;
709 if (NeedsPadding)
710 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
711 EmitAndCountInstruction(MCInstBuilder(X86::LEA64r)
712 .addReg(X86::RDI)
713 .addReg(X86::RIP)
714 .addImm(1)
715 .addReg(0)
716 .addExpr(Sym)
717 .addReg(0));
718 const MCSymbol *TlsGetAddr = Ctx.getOrCreateSymbol("__tls_get_addr");
719 if (NeedsPadding) {
720 if (!UseGot)
721 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
722 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
723 EmitAndCountInstruction(MCInstBuilder(X86::REX64_PREFIX));
724 }
725 if (UseGot) {
726 const MCExpr *Expr = MCSymbolRefExpr::create(
727 TlsGetAddr, MCSymbolRefExpr::VK_GOTPCREL, Ctx);
728 EmitAndCountInstruction(MCInstBuilder(X86::CALL64m)
729 .addReg(X86::RIP)
730 .addImm(1)
731 .addReg(0)
732 .addExpr(Expr)
733 .addReg(0));
734 } else {
735 EmitAndCountInstruction(
736 MCInstBuilder(X86::CALL64pcrel32)
737 .addExpr(MCSymbolRefExpr::create(TlsGetAddr,
738 MCSymbolRefExpr::VK_PLT, Ctx)));
739 }
740 } else {
741 if (SRVK == MCSymbolRefExpr::VK_TLSGD && !UseGot) {
742 EmitAndCountInstruction(MCInstBuilder(X86::LEA32r)
743 .addReg(X86::EAX)
744 .addReg(0)
745 .addImm(1)
746 .addReg(X86::EBX)
747 .addExpr(Sym)
748 .addReg(0));
749 } else {
750 EmitAndCountInstruction(MCInstBuilder(X86::LEA32r)
751 .addReg(X86::EAX)
752 .addReg(X86::EBX)
753 .addImm(1)
754 .addReg(0)
755 .addExpr(Sym)
756 .addReg(0));
757 }
758
759 const MCSymbol *TlsGetAddr = Ctx.getOrCreateSymbol("___tls_get_addr");
760 if (UseGot) {
761 const MCExpr *Expr =
762 MCSymbolRefExpr::create(TlsGetAddr, MCSymbolRefExpr::VK_GOT, Ctx);
763 EmitAndCountInstruction(MCInstBuilder(X86::CALL32m)
764 .addReg(X86::EBX)
765 .addImm(1)
766 .addReg(0)
767 .addExpr(Expr)
768 .addReg(0));
769 } else {
770 EmitAndCountInstruction(
771 MCInstBuilder(X86::CALLpcrel32)
772 .addExpr(MCSymbolRefExpr::create(TlsGetAddr,
773 MCSymbolRefExpr::VK_PLT, Ctx)));
774 }
775 }
776 }
777
778 /// Emit the largest nop instruction smaller than or equal to \p NumBytes
779 /// bytes. Return the size of nop emitted.
780 static unsigned EmitNop(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
781 const MCSubtargetInfo &STI) {
782 // This works only for 64bit. For 32bit we have to do additional checking if
783 // the CPU supports multi-byte nops.
784 assert(Is64Bit && "EmitNops only supports X86-64");
785
786 unsigned NopSize;
787 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg;
788 IndexReg = Displacement = SegmentReg = 0;
789 BaseReg = X86::RAX;
790 ScaleVal = 1;
791 switch (NumBytes) {
792 case 0:
793 llvm_unreachable("Zero nops?");
794 break;
795 case 1:
796 NopSize = 1;
797 Opc = X86::NOOP;
798 break;
799 case 2:
800 NopSize = 2;
801 Opc = X86::XCHG16ar;
802 break;
803 case 3:
804 NopSize = 3;
805 Opc = X86::NOOPL;
806 break;
807 case 4:
808 NopSize = 4;
809 Opc = X86::NOOPL;
810 Displacement = 8;
811 break;
812 case 5:
813 NopSize = 5;
814 Opc = X86::NOOPL;
815 Displacement = 8;
816 IndexReg = X86::RAX;
817 break;
818 case 6:
819 NopSize = 6;
820 Opc = X86::NOOPW;
821 Displacement = 8;
822 IndexReg = X86::RAX;
823 break;
824 case 7:
825 NopSize = 7;
826 Opc = X86::NOOPL;
827 Displacement = 512;
828 break;
829 case 8:
830 NopSize = 8;
831 Opc = X86::NOOPL;
832 Displacement = 512;
833 IndexReg = X86::RAX;
834 break;
835 case 9:
836 NopSize = 9;
837 Opc = X86::NOOPW;
838 Displacement = 512;
839 IndexReg = X86::RAX;
840 break;
841 default:
842 NopSize = 10;
843 Opc = X86::NOOPW;
844 Displacement = 512;
845 IndexReg = X86::RAX;
846 SegmentReg = X86::CS;
847 break;
848 }
849
850 unsigned NumPrefixes = std::min(NumBytes - NopSize, 5U);
851 NopSize += NumPrefixes;
852 for (unsigned i = 0; i != NumPrefixes; ++i)
853 OS.EmitBytes("\x66");
854
855 switch (Opc) {
856 default: llvm_unreachable("Unexpected opcode");
857 case X86::NOOP:
858 OS.EmitInstruction(MCInstBuilder(Opc), STI);
859 break;
860 case X86::XCHG16ar:
861 OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX).addReg(X86::AX), STI);
862 break;
863 case X86::NOOPL:
864 case X86::NOOPW:
865 OS.EmitInstruction(MCInstBuilder(Opc)
866 .addReg(BaseReg)
867 .addImm(ScaleVal)
868 .addReg(IndexReg)
869 .addImm(Displacement)
870 .addReg(SegmentReg),
871 STI);
872 break;
873 }
874 assert(NopSize <= NumBytes && "We overemitted?");
875 return NopSize;
876 }
877
878 /// Emit the optimal amount of multi-byte nops on X86.
879 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
880 const MCSubtargetInfo &STI) {
881 unsigned NopsToEmit = NumBytes;
882 (void)NopsToEmit;
883 while (NumBytes) {
884 NumBytes -= EmitNop(OS, NumBytes, Is64Bit, STI);
885 assert(NopsToEmit >= NumBytes && "Emitted more than I asked for!");
886 }
887 }
888
889 void X86AsmPrinter::LowerSTATEPOINT(const MachineInstr &MI,
890 X86MCInstLower &MCIL) {
891 assert(Subtarget->is64Bit() && "Statepoint currently only supports X86-64");
892
893 StatepointOpers SOpers(&MI);
894 if (unsigned PatchBytes = SOpers.getNumPatchBytes()) {
895 EmitNops(*OutStreamer, PatchBytes, Subtarget->is64Bit(),
896 getSubtargetInfo());
897 } else {
898 // Lower call target and choose correct opcode
899 const MachineOperand &CallTarget = SOpers.getCallTarget();
900 MCOperand CallTargetMCOp;
901 unsigned CallOpcode;
902 switch (CallTarget.getType()) {
903 case MachineOperand::MO_GlobalAddress:
904 case MachineOperand::MO_ExternalSymbol:
905 CallTargetMCOp = MCIL.LowerSymbolOperand(
906 CallTarget, MCIL.GetSymbolFromOperand(CallTarget));
907 CallOpcode = X86::CALL64pcrel32;
908 // Currently, we only support relative addressing with statepoints.
909 // Otherwise, we'll need a scratch register to hold the target
910 // address. You'll fail asserts during load & relocation if this
911 // symbol is to far away. (TODO: support non-relative addressing)
912 break;
913 case MachineOperand::MO_Immediate:
914 CallTargetMCOp = MCOperand::createImm(CallTarget.getImm());
915 CallOpcode = X86::CALL64pcrel32;
916 // Currently, we only support relative addressing with statepoints.
917 // Otherwise, we'll need a scratch register to hold the target
918 // immediate. You'll fail asserts during load & relocation if this
919 // address is to far away. (TODO: support non-relative addressing)
920 break;
921 case MachineOperand::MO_Register:
922 // FIXME: Add retpoline support and remove this.
923 if (Subtarget->useRetpolineIndirectCalls())
924 report_fatal_error("Lowering register statepoints with retpoline not "
925 "yet implemented.");
926 CallTargetMCOp = MCOperand::createReg(CallTarget.getReg());
927 CallOpcode = X86::CALL64r;
928 break;
929 default:
930 llvm_unreachable("Unsupported operand type in statepoint call target");
931 break;
932 }
933
934 // Emit call
935 MCInst CallInst;
936 CallInst.setOpcode(CallOpcode);
937 CallInst.addOperand(CallTargetMCOp);
938 OutStreamer->EmitInstruction(CallInst, getSubtargetInfo());
939 }
940
941 // Record our statepoint node in the same section used by STACKMAP
942 // and PATCHPOINT
943 SM.recordStatepoint(MI);
944 }
945
946 void X86AsmPrinter::LowerFAULTING_OP(const MachineInstr &FaultingMI,
947 X86MCInstLower &MCIL) {
948 // FAULTING_LOAD_OP <def>, <faltinf type>, <MBB handler>,
949 // <opcode>, <operands>
950
951 Register DefRegister = FaultingMI.getOperand(0).getReg();
952 FaultMaps::FaultKind FK =
953 static_cast<FaultMaps::FaultKind>(FaultingMI.getOperand(1).getImm());
954 MCSymbol *HandlerLabel = FaultingMI.getOperand(2).getMBB()->getSymbol();
955 unsigned Opcode = FaultingMI.getOperand(3).getImm();
956 unsigned OperandsBeginIdx = 4;
957
958 assert(FK < FaultMaps::FaultKindMax && "Invalid Faulting Kind!");
959 FM.recordFaultingOp(FK, HandlerLabel);
960
961 MCInst MI;
962 MI.setOpcode(Opcode);
963
964 if (DefRegister != X86::NoRegister)
965 MI.addOperand(MCOperand::createReg(DefRegister));
966
967 for (auto I = FaultingMI.operands_begin() + OperandsBeginIdx,
968 E = FaultingMI.operands_end();
969 I != E; ++I)
970 if (auto MaybeOperand = MCIL.LowerMachineOperand(&FaultingMI, *I))
971 MI.addOperand(MaybeOperand.getValue());
972
973 OutStreamer->AddComment("on-fault: " + HandlerLabel->getName());
974 OutStreamer->EmitInstruction(MI, getSubtargetInfo());
975 }
976
977 void X86AsmPrinter::LowerFENTRY_CALL(const MachineInstr &MI,
978 X86MCInstLower &MCIL) {
979 bool Is64Bits = Subtarget->is64Bit();
980 MCContext &Ctx = OutStreamer->getContext();
981 MCSymbol *fentry = Ctx.getOrCreateSymbol("__fentry__");
982 const MCSymbolRefExpr *Op =
983 MCSymbolRefExpr::create(fentry, MCSymbolRefExpr::VK_None, Ctx);
984
985 EmitAndCountInstruction(
986 MCInstBuilder(Is64Bits ? X86::CALL64pcrel32 : X86::CALLpcrel32)
987 .addExpr(Op));
988 }
989
990 void X86AsmPrinter::LowerPATCHABLE_OP(const MachineInstr &MI,
991 X86MCInstLower &MCIL) {
992 // PATCHABLE_OP minsize, opcode, operands
993
994 unsigned MinSize = MI.getOperand(0).getImm();
995 unsigned Opcode = MI.getOperand(1).getImm();
996
997 MCInst MCI;
998 MCI.setOpcode(Opcode);
999 for (auto &MO : make_range(MI.operands_begin() + 2, MI.operands_end()))
1000 if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO))
1001 MCI.addOperand(MaybeOperand.getValue());
1002
1003 SmallString<256> Code;
1004 SmallVector<MCFixup, 4> Fixups;
1005 raw_svector_ostream VecOS(Code);
1006 CodeEmitter->encodeInstruction(MCI, VecOS, Fixups, getSubtargetInfo());
1007
1008 if (Code.size() < MinSize) {
1009 if (MinSize == 2 && Opcode == X86::PUSH64r) {
1010 // This is an optimization that lets us get away without emitting a nop in
1011 // many cases.
1012 //
1013 // NB! In some cases the encoding for PUSH64r (e.g. PUSH64r %r9) takes two
1014 // bytes too, so the check on MinSize is important.
1015 MCI.setOpcode(X86::PUSH64rmr);
1016 } else {
1017 unsigned NopSize = EmitNop(*OutStreamer, MinSize, Subtarget->is64Bit(),
1018 getSubtargetInfo());
1019 assert(NopSize == MinSize && "Could not implement MinSize!");
1020 (void)NopSize;
1021 }
1022 }
1023
1024 OutStreamer->EmitInstruction(MCI, getSubtargetInfo());
1025 }
1026
1027 // Lower a stackmap of the form:
1028 // <id>, <shadowBytes>, ...
1029 void X86AsmPrinter::LowerSTACKMAP(const MachineInstr &MI) {
1030 SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
1031 SM.recordStackMap(MI);
1032 unsigned NumShadowBytes = MI.getOperand(1).getImm();
1033 SMShadowTracker.reset(NumShadowBytes);
1034 }
1035
1036 // Lower a patchpoint of the form:
1037 // [<def>], <id>, <numBytes>, <target>, <numArgs>, <cc>, ...
1038 void X86AsmPrinter::LowerPATCHPOINT(const MachineInstr &MI,
1039 X86MCInstLower &MCIL) {
1040 assert(Subtarget->is64Bit() && "Patchpoint currently only supports X86-64");
1041
1042 SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
1043
1044 SM.recordPatchPoint(MI);
1045
1046 PatchPointOpers opers(&MI);
1047 unsigned ScratchIdx = opers.getNextScratchIdx();
1048 unsigned EncodedBytes = 0;
1049 const MachineOperand &CalleeMO = opers.getCallTarget();
1050
1051 // Check for null target. If target is non-null (i.e. is non-zero or is
1052 // symbolic) then emit a call.
1053 if (!(CalleeMO.isImm() && !CalleeMO.getImm())) {
1054 MCOperand CalleeMCOp;
1055 switch (CalleeMO.getType()) {
1056 default:
1057 /// FIXME: Add a verifier check for bad callee types.
1058 llvm_unreachable("Unrecognized callee operand type.");
1059 case MachineOperand::MO_Immediate:
1060 if (CalleeMO.getImm())
1061 CalleeMCOp = MCOperand::createImm(CalleeMO.getImm());
1062 break;
1063 case MachineOperand::MO_ExternalSymbol:
1064 case MachineOperand::MO_GlobalAddress:
1065 CalleeMCOp = MCIL.LowerSymbolOperand(CalleeMO,
1066 MCIL.GetSymbolFromOperand(CalleeMO));
1067 break;
1068 }
1069
1070 // Emit MOV to materialize the target address and the CALL to target.
1071 // This is encoded with 12-13 bytes, depending on which register is used.
1072 Register ScratchReg = MI.getOperand(ScratchIdx).getReg();
1073 if (X86II::isX86_64ExtendedReg(ScratchReg))
1074 EncodedBytes = 13;
1075 else
1076 EncodedBytes = 12;
1077
1078 EmitAndCountInstruction(
1079 MCInstBuilder(X86::MOV64ri).addReg(ScratchReg).addOperand(CalleeMCOp));
1080 // FIXME: Add retpoline support and remove this.
1081 if (Subtarget->useRetpolineIndirectCalls())
1082 report_fatal_error(
1083 "Lowering patchpoint with retpoline not yet implemented.");
1084 EmitAndCountInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg));
1085 }
1086
1087 // Emit padding.
1088 unsigned NumBytes = opers.getNumPatchBytes();
1089 assert(NumBytes >= EncodedBytes &&
1090 "Patchpoint can't request size less than the length of a call.");
1091
1092 EmitNops(*OutStreamer, NumBytes - EncodedBytes, Subtarget->is64Bit(),
1093 getSubtargetInfo());
1094 }
1095
1096 void X86AsmPrinter::LowerPATCHABLE_EVENT_CALL(const MachineInstr &MI,
1097 X86MCInstLower &MCIL) {
1098 assert(Subtarget->is64Bit() && "XRay custom events only supports X86-64");
1099
1100 // We want to emit the following pattern, which follows the x86 calling
1101 // convention to prepare for the trampoline call to be patched in.
1102 //
1103 // .p2align 1, ...
1104 // .Lxray_event_sled_N:
1105 // jmp +N // jump across the instrumentation sled
1106 // ... // set up arguments in register
1107 // callq __xray_CustomEvent@plt // force dependency to symbol
1108 // ...
1109 // <jump here>
1110 //
1111 // After patching, it would look something like:
1112 //
1113 // nopw (2-byte nop)
1114 // ...
1115 // callq __xrayCustomEvent // already lowered
1116 // ...
1117 //
1118 // ---
1119 // First we emit the label and the jump.
1120 auto CurSled = OutContext.createTempSymbol("xray_event_sled_", true);
1121 OutStreamer->AddComment("# XRay Custom Event Log");
1122 OutStreamer->EmitCodeAlignment(2);
1123 OutStreamer->EmitLabel(CurSled);
1124
1125 // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as
1126 // an operand (computed as an offset from the jmp instruction).
1127 // FIXME: Find another less hacky way do force the relative jump.
1128 OutStreamer->EmitBinaryData("\xeb\x0f");
1129
1130 // The default C calling convention will place two arguments into %rcx and
1131 // %rdx -- so we only work with those.
1132 unsigned DestRegs[] = {X86::RDI, X86::RSI};
1133 bool UsedMask[] = {false, false};
1134 // Filled out in loop.
1135 unsigned SrcRegs[] = {0, 0};
1136
1137 // Then we put the operands in the %rdi and %rsi registers. We spill the
1138 // values in the register before we clobber them, and mark them as used in
1139 // UsedMask. In case the arguments are already in the correct register, we use
1140 // emit nops appropriately sized to keep the sled the same size in every
1141 // situation.
1142 for (unsigned I = 0; I < MI.getNumOperands(); ++I)
1143 if (auto Op = MCIL.LowerMachineOperand(&MI, MI.getOperand(I))) {
1144 assert(Op->isReg() && "Only support arguments in registers");
1145 SrcRegs[I] = Op->getReg();
1146 if (SrcRegs[I] != DestRegs[I]) {
1147 UsedMask[I] = true;
1148 EmitAndCountInstruction(
1149 MCInstBuilder(X86::PUSH64r).addReg(DestRegs[I]));
1150 } else {
1151 EmitNops(*OutStreamer, 4, Subtarget->is64Bit(), getSubtargetInfo());
1152 }
1153 }
1154
1155 // Now that the register values are stashed, mov arguments into place.
1156 for (unsigned I = 0; I < MI.getNumOperands(); ++I)
1157 if (SrcRegs[I] != DestRegs[I])
1158 EmitAndCountInstruction(
1159 MCInstBuilder(X86::MOV64rr).addReg(DestRegs[I]).addReg(SrcRegs[I]));
1160
1161 // We emit a hard dependency on the __xray_CustomEvent symbol, which is the
1162 // name of the trampoline to be implemented by the XRay runtime.
1163 auto TSym = OutContext.getOrCreateSymbol("__xray_CustomEvent");
1164 MachineOperand TOp = MachineOperand::CreateMCSymbol(TSym);
1165 if (isPositionIndependent())
1166 TOp.setTargetFlags(X86II::MO_PLT);
1167
1168 // Emit the call instruction.
1169 EmitAndCountInstruction(MCInstBuilder(X86::CALL64pcrel32)
1170 .addOperand(MCIL.LowerSymbolOperand(TOp, TSym)));
1171
1172 // Restore caller-saved and used registers.
1173 for (unsigned I = sizeof UsedMask; I-- > 0;)
1174 if (UsedMask[I])
1175 EmitAndCountInstruction(MCInstBuilder(X86::POP64r).addReg(DestRegs[I]));
1176 else
1177 EmitNops(*OutStreamer, 1, Subtarget->is64Bit(), getSubtargetInfo());
1178
1179 OutStreamer->AddComment("xray custom event end.");
1180
1181 // Record the sled version. Older versions of this sled were spelled
1182 // differently, so we let the runtime handle the different offsets we're
1183 // using.
1184 recordSled(CurSled, MI, SledKind::CUSTOM_EVENT, 1);
1185 }
1186
1187 void X86AsmPrinter::LowerPATCHABLE_TYPED_EVENT_CALL(const MachineInstr &MI,
1188 X86MCInstLower &MCIL) {
1189 assert(Subtarget->is64Bit() && "XRay typed events only supports X86-64");
1190
1191 // We want to emit the following pattern, which follows the x86 calling
1192 // convention to prepare for the trampoline call to be patched in.
1193 //
1194 // .p2align 1, ...
1195 // .Lxray_event_sled_N:
1196 // jmp +N // jump across the instrumentation sled
1197 // ... // set up arguments in register
1198 // callq __xray_TypedEvent@plt // force dependency to symbol
1199 // ...
1200 // <jump here>
1201 //
1202 // After patching, it would look something like:
1203 //
1204 // nopw (2-byte nop)
1205 // ...
1206 // callq __xrayTypedEvent // already lowered
1207 // ...
1208 //
1209 // ---
1210 // First we emit the label and the jump.
1211 auto CurSled = OutContext.createTempSymbol("xray_typed_event_sled_", true);
1212 OutStreamer->AddComment("# XRay Typed Event Log");
1213 OutStreamer->EmitCodeAlignment(2);
1214 OutStreamer->EmitLabel(CurSled);
1215
1216 // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as
1217 // an operand (computed as an offset from the jmp instruction).
1218 // FIXME: Find another less hacky way do force the relative jump.
1219 OutStreamer->EmitBinaryData("\xeb\x14");
1220
1221 // An x86-64 convention may place three arguments into %rcx, %rdx, and R8,
1222 // so we'll work with those. Or we may be called via SystemV, in which case
1223 // we don't have to do any translation.
1224 unsigned DestRegs[] = {X86::RDI, X86::RSI, X86::RDX};
1225 bool UsedMask[] = {false, false, false};
1226
1227 // Will fill out src regs in the loop.
1228 unsigned SrcRegs[] = {0, 0, 0};
1229
1230 // Then we put the operands in the SystemV registers. We spill the values in
1231 // the registers before we clobber them, and mark them as used in UsedMask.
1232 // In case the arguments are already in the correct register, we emit nops
1233 // appropriately sized to keep the sled the same size in every situation.
1234 for (unsigned I = 0; I < MI.getNumOperands(); ++I)
1235 if (auto Op = MCIL.LowerMachineOperand(&MI, MI.getOperand(I))) {
1236 // TODO: Is register only support adequate?
1237 assert(Op->isReg() && "Only supports arguments in registers");
1238 SrcRegs[I] = Op->getReg();
1239 if (SrcRegs[I] != DestRegs[I]) {
1240 UsedMask[I] = true;
1241 EmitAndCountInstruction(
1242 MCInstBuilder(X86::PUSH64r).addReg(DestRegs[I]));
1243 } else {
1244 EmitNops(*OutStreamer, 4, Subtarget->is64Bit(), getSubtargetInfo());
1245 }
1246 }
1247
1248 // In the above loop we only stash all of the destination registers or emit
1249 // nops if the arguments are already in the right place. Doing the actually
1250 // moving is postponed until after all the registers are stashed so nothing
1251 // is clobbers. We've already added nops to account for the size of mov and
1252 // push if the register is in the right place, so we only have to worry about
1253 // emitting movs.
1254 for (unsigned I = 0; I < MI.getNumOperands(); ++I)
1255 if (UsedMask[I])
1256 EmitAndCountInstruction(
1257 MCInstBuilder(X86::MOV64rr).addReg(DestRegs[I]).addReg(SrcRegs[I]));
1258
1259 // We emit a hard dependency on the __xray_TypedEvent symbol, which is the
1260 // name of the trampoline to be implemented by the XRay runtime.
1261 auto TSym = OutContext.getOrCreateSymbol("__xray_TypedEvent");
1262 MachineOperand TOp = MachineOperand::CreateMCSymbol(TSym);
1263 if (isPositionIndependent())
1264 TOp.setTargetFlags(X86II::MO_PLT);
1265
1266 // Emit the call instruction.
1267 EmitAndCountInstruction(MCInstBuilder(X86::CALL64pcrel32)
1268 .addOperand(MCIL.LowerSymbolOperand(TOp, TSym)));
1269
1270 // Restore caller-saved and used registers.
1271 for (unsigned I = sizeof UsedMask; I-- > 0;)
1272 if (UsedMask[I])
1273 EmitAndCountInstruction(MCInstBuilder(X86::POP64r).addReg(DestRegs[I]));
1274 else
1275 EmitNops(*OutStreamer, 1, Subtarget->is64Bit(), getSubtargetInfo());
1276
1277 OutStreamer->AddComment("xray typed event end.");
1278
1279 // Record the sled version.
1280 recordSled(CurSled, MI, SledKind::TYPED_EVENT, 0);
1281 }
1282
1283 void X86AsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI,
1284 X86MCInstLower &MCIL) {
1285 // We want to emit the following pattern:
1286 //
1287 // .p2align 1, ...
1288 // .Lxray_sled_N:
1289 // jmp .tmpN
1290 // # 9 bytes worth of noops
1291 //
1292 // We need the 9 bytes because at runtime, we'd be patching over the full 11
1293 // bytes with the following pattern:
1294 //
1295 // mov %r10, <function id, 32-bit> // 6 bytes
1296 // call <relative offset, 32-bits> // 5 bytes
1297 //
1298 auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
1299 OutStreamer->EmitCodeAlignment(2);
1300 OutStreamer->EmitLabel(CurSled);
1301
1302 // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as
1303 // an operand (computed as an offset from the jmp instruction).
1304 // FIXME: Find another less hacky way do force the relative jump.
1305 OutStreamer->EmitBytes("\xeb\x09");
1306 EmitNops(*OutStreamer, 9, Subtarget->is64Bit(), getSubtargetInfo());
1307 recordSled(CurSled, MI, SledKind::FUNCTION_ENTER);
1308 }
1309
1310 void X86AsmPrinter::LowerPATCHABLE_RET(const MachineInstr &MI,
1311 X86MCInstLower &MCIL) {
1312 // Since PATCHABLE_RET takes the opcode of the return statement as an
1313 // argument, we use that to emit the correct form of the RET that we want.
1314 // i.e. when we see this:
1315 //
1316 // PATCHABLE_RET X86::RET ...
1317 //
1318 // We should emit the RET followed by sleds.
1319 //
1320 // .p2align 1, ...
1321 // .Lxray_sled_N:
1322 // ret # or equivalent instruction
1323 // # 10 bytes worth of noops
1324 //
1325 // This just makes sure that the alignment for the next instruction is 2.
1326 auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
1327 OutStreamer->EmitCodeAlignment(2);
1328 OutStreamer->EmitLabel(CurSled);
1329 unsigned OpCode = MI.getOperand(0).getImm();
1330 MCInst Ret;
1331 Ret.setOpcode(OpCode);
1332 for (auto &MO : make_range(MI.operands_begin() + 1, MI.operands_end()))
1333 if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO))
1334 Ret.addOperand(MaybeOperand.getValue());
1335 OutStreamer->EmitInstruction(Ret, getSubtargetInfo());
1336 EmitNops(*OutStreamer, 10, Subtarget->is64Bit(), getSubtargetInfo());
1337 recordSled(CurSled, MI, SledKind::FUNCTION_EXIT);
1338 }
1339
1340 void X86AsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI,
1341 X86MCInstLower &MCIL) {
1342 // Like PATCHABLE_RET, we have the actual instruction in the operands to this
1343 // instruction so we lower that particular instruction and its operands.
1344 // Unlike PATCHABLE_RET though, we put the sled before the JMP, much like how
1345 // we do it for PATCHABLE_FUNCTION_ENTER. The sled should be very similar to
1346 // the PATCHABLE_FUNCTION_ENTER case, followed by the lowering of the actual
1347 // tail call much like how we have it in PATCHABLE_RET.
1348 auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
1349 OutStreamer->EmitCodeAlignment(2);
1350 OutStreamer->EmitLabel(CurSled);
1351 auto Target = OutContext.createTempSymbol();
1352
1353 // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as
1354 // an operand (computed as an offset from the jmp instruction).
1355 // FIXME: Find another less hacky way do force the relative jump.
1356 OutStreamer->EmitBytes("\xeb\x09");
1357 EmitNops(*OutStreamer, 9, Subtarget->is64Bit(), getSubtargetInfo());
1358 OutStreamer->EmitLabel(Target);
1359 recordSled(CurSled, MI, SledKind::TAIL_CALL);
1360
1361 unsigned OpCode = MI.getOperand(0).getImm();
1362 MCInst TC;
1363 TC.setOpcode(OpCode);
1364
1365 // Before emitting the instruction, add a comment to indicate that this is
1366 // indeed a tail call.
1367 OutStreamer->AddComment("TAILCALL");
1368 for (auto &MO : make_range(MI.operands_begin() + 1, MI.operands_end()))
1369 if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO))
1370 TC.addOperand(MaybeOperand.getValue());
1371 OutStreamer->EmitInstruction(TC, getSubtargetInfo());
1372 }
1373
1374 // Returns instruction preceding MBBI in MachineFunction.
1375 // If MBBI is the first instruction of the first basic block, returns null.
1376 static MachineBasicBlock::const_iterator
1377 PrevCrossBBInst(MachineBasicBlock::const_iterator MBBI) {
1378 const MachineBasicBlock *MBB = MBBI->getParent();
1379 while (MBBI == MBB->begin()) {
1380 if (MBB == &MBB->getParent()->front())
1381 return MachineBasicBlock::const_iterator();
1382 MBB = MBB->getPrevNode();
1383 MBBI = MBB->end();
1384 }
1385 --MBBI;
1386 return MBBI;
1387 }
1388
1389 static const Constant *getConstantFromPool(const MachineInstr &MI,
1390 const MachineOperand &Op) {
1391 if (!Op.isCPI() || Op.getOffset() != 0)
1392 return nullptr;
1393
1394 ArrayRef<MachineConstantPoolEntry> Constants =
1395 MI.getParent()->getParent()->getConstantPool()->getConstants();
1396 const MachineConstantPoolEntry &ConstantEntry = Constants[Op.getIndex()];
1397
1398 // Bail if this is a machine constant pool entry, we won't be able to dig out
1399 // anything useful.
1400 if (ConstantEntry.isMachineConstantPoolEntry())
1401 return nullptr;
1402
1403 const Constant *C = ConstantEntry.Val.ConstVal;
1404 assert((!C || ConstantEntry.getType() == C->getType()) &&
1405 "Expected a constant of the same type!");
1406 return C;
1407 }
1408
1409 static std::string getShuffleComment(const MachineInstr *MI, unsigned SrcOp1Idx,
1410 unsigned SrcOp2Idx, ArrayRef<int> Mask) {
1411 std::string Comment;
1412
1413 // Compute the name for a register. This is really goofy because we have
1414 // multiple instruction printers that could (in theory) use different
1415 // names. Fortunately most people use the ATT style (outside of Windows)
1416 // and they actually agree on register naming here. Ultimately, this is
1417 // a comment, and so its OK if it isn't perfect.
1418 auto GetRegisterName = [](unsigned RegNum) -> StringRef {
1419 return X86ATTInstPrinter::getRegisterName(RegNum);
1420 };
1421
1422 const MachineOperand &DstOp = MI->getOperand(0);
1423 const MachineOperand &SrcOp1 = MI->getOperand(SrcOp1Idx);
1424 const MachineOperand &SrcOp2 = MI->getOperand(SrcOp2Idx);
1425
1426 StringRef DstName = DstOp.isReg() ? GetRegisterName(DstOp.getReg()) : "mem";
1427 StringRef Src1Name =
1428 SrcOp1.isReg() ? GetRegisterName(SrcOp1.getReg()) : "mem";
1429 StringRef Src2Name =
1430 SrcOp2.isReg() ? GetRegisterName(SrcOp2.getReg()) : "mem";
1431
1432 // One source operand, fix the mask to print all elements in one span.
1433 SmallVector<int, 8> ShuffleMask(Mask.begin(), Mask.end());
1434 if (Src1Name == Src2Name)
1435 for (int i = 0, e = ShuffleMask.size(); i != e; ++i)
1436 if (ShuffleMask[i] >= e)
1437 ShuffleMask[i] -= e;
1438
1439 raw_string_ostream CS(Comment);
1440 CS << DstName;
1441
1442 // Handle AVX512 MASK/MASXZ write mask comments.
1443 // MASK: zmmX {%kY}
1444 // MASKZ: zmmX {%kY} {z}
1445 if (SrcOp1Idx > 1) {
1446 assert((SrcOp1Idx == 2 || SrcOp1Idx == 3) && "Unexpected writemask");
1447
1448 const MachineOperand &WriteMaskOp = MI->getOperand(SrcOp1Idx - 1);
1449 if (WriteMaskOp.isReg()) {
1450 CS << " {%" << GetRegisterName(WriteMaskOp.getReg()) << "}";
1451
1452 if (SrcOp1Idx == 2) {
1453 CS << " {z}";
1454 }
1455 }
1456 }
1457
1458 CS << " = ";
1459
1460 for (int i = 0, e = ShuffleMask.size(); i != e; ++i) {
1461 if (i != 0)
1462 CS << ",";
1463 if (ShuffleMask[i] == SM_SentinelZero) {
1464 CS << "zero";
1465 continue;
1466 }
1467
1468 // Otherwise, it must come from src1 or src2. Print the span of elements
1469 // that comes from this src.
1470 bool isSrc1 = ShuffleMask[i] < (int)e;
1471 CS << (isSrc1 ? Src1Name : Src2Name) << '[';
1472
1473 bool IsFirst = true;
1474 while (i != e && ShuffleMask[i] != SM_SentinelZero &&
1475 (ShuffleMask[i] < (int)e) == isSrc1) {
1476 if (!IsFirst)
1477 CS << ',';
1478 else
1479 IsFirst = false;
1480 if (ShuffleMask[i] == SM_SentinelUndef)
1481 CS << "u";
1482 else
1483 CS << ShuffleMask[i] % (int)e;
1484 ++i;
1485 }
1486 CS << ']';
1487 --i; // For loop increments element #.
1488 }
1489 CS.flush();
1490
1491 return Comment;
1492 }
1493
1494 static void printConstant(const APInt &Val, raw_ostream &CS) {
1495 if (Val.getBitWidth() <= 64) {
1496 CS << Val.getZExtValue();
1497 } else {
1498 // print multi-word constant as (w0,w1)
1499 CS << "(";
1500 for (int i = 0, N = Val.getNumWords(); i < N; ++i) {
1501 if (i > 0)
1502 CS << ",";
1503 CS << Val.getRawData()[i];
1504 }
1505 CS << ")";
1506 }
1507 }
1508
1509 static void printConstant(const APFloat &Flt, raw_ostream &CS) {
1510 SmallString<32> Str;
1511 // Force scientific notation to distinquish from integers.
1512 Flt.toString(Str, 0, 0);
1513 CS << Str;
1514 }
1515
1516 static void printConstant(const Constant *COp, raw_ostream &CS) {
1517 if (isa<UndefValue>(COp)) {
1518 CS << "u";
1519 } else if (auto *CI = dyn_cast<ConstantInt>(COp)) {
1520 printConstant(CI->getValue(), CS);
1521 } else if (auto *CF = dyn_cast<ConstantFP>(COp)) {
1522 printConstant(CF->getValueAPF(), CS);
1523 } else {
1524 CS << "?";
1525 }
1526 }
1527
1528 void X86AsmPrinter::EmitSEHInstruction(const MachineInstr *MI) {
1529 assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?");
1530 assert(getSubtarget().isOSWindows() && "SEH_ instruction Windows only");
1531 const X86RegisterInfo *RI =
1532 MF->getSubtarget<X86Subtarget>().getRegisterInfo();
1533
1534 // Use the .cv_fpo directives if we're emitting CodeView on 32-bit x86.
1535 if (EmitFPOData) {
1536 X86TargetStreamer *XTS =
1537 static_cast<X86TargetStreamer *>(OutStreamer->getTargetStreamer());
1538 switch (MI->getOpcode()) {
1539 case X86::SEH_PushReg:
1540 XTS->emitFPOPushReg(MI->getOperand(0).getImm());
1541 break;
1542 case X86::SEH_StackAlloc:
1543 XTS->emitFPOStackAlloc(MI->getOperand(0).getImm());
1544 break;
1545 case X86::SEH_StackAlign:
1546 XTS->emitFPOStackAlign(MI->getOperand(0).getImm());
1547 break;
1548 case X86::SEH_SetFrame:
1549 assert(MI->getOperand(1).getImm() == 0 &&
1550 ".cv_fpo_setframe takes no offset");
1551 XTS->emitFPOSetFrame(MI->getOperand(0).getImm());
1552 break;
1553 case X86::SEH_EndPrologue:
1554 XTS->emitFPOEndPrologue();
1555 break;
1556 case X86::SEH_SaveReg:
1557 case X86::SEH_SaveXMM:
1558 case X86::SEH_PushFrame:
1559 llvm_unreachable("SEH_ directive incompatible with FPO");
1560 break;
1561 default:
1562 llvm_unreachable("expected SEH_ instruction");
1563 }
1564 return;
1565 }
1566
1567 // Otherwise, use the .seh_ directives for all other Windows platforms.
1568 switch (MI->getOpcode()) {
1569 case X86::SEH_PushReg:
1570 OutStreamer->EmitWinCFIPushReg(
1571 RI->getSEHRegNum(MI->getOperand(0).getImm()));
1572 break;
1573
1574 case X86::SEH_SaveReg:
1575 OutStreamer->EmitWinCFISaveReg(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1576 MI->getOperand(1).getImm());
1577 break;
1578
1579 case X86::SEH_SaveXMM:
1580 OutStreamer->EmitWinCFISaveXMM(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1581 MI->getOperand(1).getImm());
1582 break;
1583
1584 case X86::SEH_StackAlloc:
1585 OutStreamer->EmitWinCFIAllocStack(MI->getOperand(0).getImm());
1586 break;
1587
1588 case X86::SEH_SetFrame:
1589 OutStreamer->EmitWinCFISetFrame(
1590 RI->getSEHRegNum(MI->getOperand(0).getImm()),
1591 MI->getOperand(1).getImm());
1592 break;
1593
1594 case X86::SEH_PushFrame:
1595 OutStreamer->EmitWinCFIPushFrame(MI->getOperand(0).getImm());
1596 break;
1597
1598 case X86::SEH_EndPrologue:
1599 OutStreamer->EmitWinCFIEndProlog();
1600 break;
1601
1602 default:
1603 llvm_unreachable("expected SEH_ instruction");
1604 }
1605 }
1606
1607 static unsigned getRegisterWidth(const MCOperandInfo &Info) {
1608 if (Info.RegClass == X86::VR128RegClassID ||
1609 Info.RegClass == X86::VR128XRegClassID)
1610 return 128;
1611 if (Info.RegClass == X86::VR256RegClassID ||
1612 Info.RegClass == X86::VR256XRegClassID)
1613 return 256;
1614 if (Info.RegClass == X86::VR512RegClassID)
1615 return 512;
1616 llvm_unreachable("Unknown register class!");
1617 }
1618
1619 void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
1620 X86MCInstLower MCInstLowering(*MF, *this);
1621 const X86RegisterInfo *RI =
1622 MF->getSubtarget<X86Subtarget>().getRegisterInfo();
1623
1624 // Add a comment about EVEX-2-VEX compression for AVX-512 instrs that
1625 // are compressed from EVEX encoding to VEX encoding.
1626 if (TM.Options.MCOptions.ShowMCEncoding) {
1627 if (MI->getAsmPrinterFlags() & X86::AC_EVEX_2_VEX)
1628 OutStreamer->AddComment("EVEX TO VEX Compression ", false);
1629 }
1630
1631 switch (MI->getOpcode()) {
1632 case TargetOpcode::DBG_VALUE:
1633 llvm_unreachable("Should be handled target independently");
1634
1635 // Emit nothing here but a comment if we can.
1636 case X86::Int_MemBarrier:
1637 OutStreamer->emitRawComment("MEMBARRIER");
1638 return;
1639
1640 case X86::EH_RETURN:
1641 case X86::EH_RETURN64: {
1642 // Lower these as normal, but add some comments.
1643 Register Reg = MI->getOperand(0).getReg();
1644 OutStreamer->AddComment(StringRef("eh_return, addr: %") +
1645 X86ATTInstPrinter::getRegisterName(Reg));
1646 break;
1647 }
1648 case X86::CLEANUPRET: {
1649 // Lower these as normal, but add some comments.
1650 OutStreamer->AddComment("CLEANUPRET");
1651 break;
1652 }
1653
1654 case X86::CATCHRET: {
1655 // Lower these as normal, but add some comments.
1656 OutStreamer->AddComment("CATCHRET");
1657 break;
1658 }
1659
1660 case X86::TAILJMPr:
1661 case X86::TAILJMPm:
1662 case X86::TAILJMPd:
1663 case X86::TAILJMPd_CC:
1664 case X86::TAILJMPr64:
1665 case X86::TAILJMPm64:
1666 case X86::TAILJMPd64:
1667 case X86::TAILJMPd64_CC:
1668 case X86::TAILJMPr64_REX:
1669 case X86::TAILJMPm64_REX:
1670 // Lower these as normal, but add some comments.
1671 OutStreamer->AddComment("TAILCALL");
1672 break;
1673
1674 case X86::TLS_addr32:
1675 case X86::TLS_addr64:
1676 case X86::TLS_base_addr32:
1677 case X86::TLS_base_addr64:
1678 return LowerTlsAddr(MCInstLowering, *MI);
1679
1680 // Loading/storing mask pairs requires two kmov operations. The second one of these
1681 // needs a 2 byte displacement relative to the specified address (with 32 bit spill
1682 // size). The pairs of 1bit masks up to 16 bit masks all use the same spill size,
1683 // they all are stored using MASKPAIR16STORE, loaded using MASKPAIR16LOAD.
1684 //
1685 // The displacement value might wrap around in theory, thus the asserts in both
1686 // cases.
1687 case X86::MASKPAIR16LOAD: {
1688 int64_t Disp = MI->getOperand(1 + X86::AddrDisp).getImm();
1689 assert(Disp >= 0 && Disp <= INT32_MAX - 2 && "Unexpected displacement");
1690 const X86RegisterInfo *RI =
1691 MF->getSubtarget<X86Subtarget>().getRegisterInfo();
1692 Register Reg = MI->getOperand(0).getReg();
1693 Register Reg0 = RI->getSubReg(Reg, X86::sub_mask_0);
1694 Register Reg1 = RI->getSubReg(Reg, X86::sub_mask_1);
1695
1696 // Load the first mask register
1697 MCInstBuilder MIB = MCInstBuilder(X86::KMOVWkm);
1698 MIB.addReg(Reg0);
1699 for (int i = 0; i < X86::AddrNumOperands; ++i) {
1700 auto Op = MCInstLowering.LowerMachineOperand(MI, MI->getOperand(1 + i));
1701 MIB.addOperand(Op.getValue());
1702 }
1703 EmitAndCountInstruction(MIB);
1704
1705 // Load the second mask register of the pair
1706 MIB = MCInstBuilder(X86::KMOVWkm);
1707 MIB.addReg(Reg1);
1708 for (int i = 0; i < X86::AddrNumOperands; ++i) {
1709 if (i == X86::AddrDisp) {
1710 MIB.addImm(Disp + 2);
1711 } else {
1712 auto Op = MCInstLowering.LowerMachineOperand(MI, MI->getOperand(1 + i));
1713 MIB.addOperand(Op.getValue());
1714 }
1715 }
1716 EmitAndCountInstruction(MIB);
1717 return;
1718 }
1719
1720 case X86::MASKPAIR16STORE: {
1721 int64_t Disp = MI->getOperand(X86::AddrDisp).getImm();
1722 assert(Disp >= 0 && Disp <= INT32_MAX - 2 && "Unexpected displacement");
1723 const X86RegisterInfo *RI =
1724 MF->getSubtarget<X86Subtarget>().getRegisterInfo();
1725 Register Reg = MI->getOperand(X86::AddrNumOperands).getReg();
1726 Register Reg0 = RI->getSubReg(Reg, X86::sub_mask_0);
1727 Register Reg1 = RI->getSubReg(Reg, X86::sub_mask_1);
1728
1729 // Store the first mask register
1730 MCInstBuilder MIB = MCInstBuilder(X86::KMOVWmk);
1731 for (int i = 0; i < X86::AddrNumOperands; ++i)
1732 MIB.addOperand(MCInstLowering.LowerMachineOperand(MI, MI->getOperand(i)).getValue());
1733 MIB.addReg(Reg0);
1734 EmitAndCountInstruction(MIB);
1735
1736 // Store the second mask register of the pair
1737 MIB = MCInstBuilder(X86::KMOVWmk);
1738 for (int i = 0; i < X86::AddrNumOperands; ++i) {
1739 if (i == X86::AddrDisp) {
1740 MIB.addImm(Disp + 2);
1741 } else {
1742 auto Op = MCInstLowering.LowerMachineOperand(MI, MI->getOperand(0 + i));
1743 MIB.addOperand(Op.getValue());
1744 }
1745 }
1746 MIB.addReg(Reg1);
1747 EmitAndCountInstruction(MIB);
1748 return;
1749 }
1750
1751 case X86::MOVPC32r: {
1752 // This is a pseudo op for a two instruction sequence with a label, which
1753 // looks like:
1754 // call "L1$pb"
1755 // "L1$pb":
1756 // popl %esi
1757
1758 // Emit the call.
1759 MCSymbol *PICBase = MF->getPICBaseSymbol();
1760 // FIXME: We would like an efficient form for this, so we don't have to do a
1761 // lot of extra uniquing.
1762 EmitAndCountInstruction(
1763 MCInstBuilder(X86::CALLpcrel32)
1764 .addExpr(MCSymbolRefExpr::create(PICBase, OutContext)));
1765
1766 const X86FrameLowering *FrameLowering =
1767 MF->getSubtarget<X86Subtarget>().getFrameLowering();
1768 bool hasFP = FrameLowering->hasFP(*MF);
1769
1770 // TODO: This is needed only if we require precise CFA.
1771 bool HasActiveDwarfFrame = OutStreamer->getNumFrameInfos() &&
1772 !OutStreamer->getDwarfFrameInfos().back().End;
1773
1774 int stackGrowth = -RI->getSlotSize();
1775
1776 if (HasActiveDwarfFrame && !hasFP) {
1777 OutStreamer->EmitCFIAdjustCfaOffset(-stackGrowth);
1778 }
1779
1780 // Emit the label.
1781 OutStreamer->EmitLabel(PICBase);
1782
1783 // popl $reg
1784 EmitAndCountInstruction(
1785 MCInstBuilder(X86::POP32r).addReg(MI->getOperand(0).getReg()));
1786
1787 if (HasActiveDwarfFrame && !hasFP) {
1788 OutStreamer->EmitCFIAdjustCfaOffset(stackGrowth);
1789 }
1790 return;
1791 }
1792
1793 case X86::ADD32ri: {
1794 // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri.
1795 if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS)
1796 break;
1797
1798 // Okay, we have something like:
1799 // EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL)
1800
1801 // For this, we want to print something like:
1802 // MYGLOBAL + (. - PICBASE)
1803 // However, we can't generate a ".", so just emit a new label here and refer
1804 // to it.
1805 MCSymbol *DotSym = OutContext.createTempSymbol();
1806 OutStreamer->EmitLabel(DotSym);
1807
1808 // Now that we have emitted the label, lower the complex operand expression.
1809 MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2));
1810
1811 const MCExpr *DotExpr = MCSymbolRefExpr::create(DotSym, OutContext);
1812 const MCExpr *PICBase =
1813 MCSymbolRefExpr::create(MF->getPICBaseSymbol(), OutContext);
1814 DotExpr = MCBinaryExpr::createSub(DotExpr, PICBase, OutContext);
1815
1816 DotExpr = MCBinaryExpr::createAdd(
1817 MCSymbolRefExpr::create(OpSym, OutContext), DotExpr, OutContext);
1818
1819 EmitAndCountInstruction(MCInstBuilder(X86::ADD32ri)
1820 .addReg(MI->getOperand(0).getReg())
1821 .addReg(MI->getOperand(1).getReg())
1822 .addExpr(DotExpr));
1823 return;
1824 }
1825 case TargetOpcode::STATEPOINT:
1826 return LowerSTATEPOINT(*MI, MCInstLowering);
1827
1828 case TargetOpcode::FAULTING_OP:
1829 return LowerFAULTING_OP(*MI, MCInstLowering);
1830
1831 case TargetOpcode::FENTRY_CALL:
1832 return LowerFENTRY_CALL(*MI, MCInstLowering);
1833
1834 case TargetOpcode::PATCHABLE_OP:
1835 return LowerPATCHABLE_OP(*MI, MCInstLowering);
1836
1837 case TargetOpcode::STACKMAP:
1838 return LowerSTACKMAP(*MI);
1839
1840 case TargetOpcode::PATCHPOINT:
1841 return LowerPATCHPOINT(*MI, MCInstLowering);
1842
1843 case TargetOpcode::PATCHABLE_FUNCTION_ENTER:
1844 return LowerPATCHABLE_FUNCTION_ENTER(*MI, MCInstLowering);
1845
1846 case TargetOpcode::PATCHABLE_RET:
1847 return LowerPATCHABLE_RET(*MI, MCInstLowering);
1848
1849 case TargetOpcode::PATCHABLE_TAIL_CALL:
1850 return LowerPATCHABLE_TAIL_CALL(*MI, MCInstLowering);
1851
1852 case TargetOpcode::PATCHABLE_EVENT_CALL:
1853 return LowerPATCHABLE_EVENT_CALL(*MI, MCInstLowering);
1854
1855 case TargetOpcode::PATCHABLE_TYPED_EVENT_CALL:
1856 return LowerPATCHABLE_TYPED_EVENT_CALL(*MI, MCInstLowering);
1857
1858 case X86::MORESTACK_RET:
1859 EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
1860 return;
1861
1862 case X86::MORESTACK_RET_RESTORE_R10:
1863 // Return, then restore R10.
1864 EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
1865 EmitAndCountInstruction(
1866 MCInstBuilder(X86::MOV64rr).addReg(X86::R10).addReg(X86::RAX));
1867 return;
1868
1869 case X86::SEH_PushReg:
1870 case X86::SEH_SaveReg:
1871 case X86::SEH_SaveXMM:
1872 case X86::SEH_StackAlloc:
1873 case X86::SEH_StackAlign:
1874 case X86::SEH_SetFrame:
1875 case X86::SEH_PushFrame:
1876 case X86::SEH_EndPrologue:
1877 EmitSEHInstruction(MI);
1878 return;
1879
1880 case X86::SEH_Epilogue: {
1881 assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?");
1882 MachineBasicBlock::const_iterator MBBI(MI);
1883 // Check if preceded by a call and emit nop if so.
1884 for (MBBI = PrevCrossBBInst(MBBI);
1885 MBBI != MachineBasicBlock::const_iterator();
1886 MBBI = PrevCrossBBInst(MBBI)) {
1887 // Conservatively assume that pseudo instructions don't emit code and keep
1888 // looking for a call. We may emit an unnecessary nop in some cases.
1889 if (!MBBI->isPseudo()) {
1890 if (MBBI->isCall())
1891 EmitAndCountInstruction(MCInstBuilder(X86::NOOP));
1892 break;
1893 }
1894 }
1895 return;
1896 }
1897
1898 // Lower PSHUFB and VPERMILP normally but add a comment if we can find
1899 // a constant shuffle mask. We won't be able to do this at the MC layer
1900 // because the mask isn't an immediate.
1901 case X86::PSHUFBrm:
1902 case X86::VPSHUFBrm:
1903 case X86::VPSHUFBYrm:
1904 case X86::VPSHUFBZ128rm:
1905 case X86::VPSHUFBZ128rmk:
1906 case X86::VPSHUFBZ128rmkz:
1907 case X86::VPSHUFBZ256rm:
1908 case X86::VPSHUFBZ256rmk:
1909 case X86::VPSHUFBZ256rmkz:
1910 case X86::VPSHUFBZrm:
1911 case X86::VPSHUFBZrmk:
1912 case X86::VPSHUFBZrmkz: {
1913 if (!OutStreamer->isVerboseAsm())
1914 break;
1915 unsigned SrcIdx, MaskIdx;
1916 switch (MI->getOpcode()) {
1917 default: llvm_unreachable("Invalid opcode");
1918 case X86::PSHUFBrm:
1919 case X86::VPSHUFBrm:
1920 case X86::VPSHUFBYrm:
1921 case X86::VPSHUFBZ128rm:
1922 case X86::VPSHUFBZ256rm:
1923 case X86::VPSHUFBZrm:
1924 SrcIdx = 1; MaskIdx = 5; break;
1925 case X86::VPSHUFBZ128rmkz:
1926 case X86::VPSHUFBZ256rmkz:
1927 case X86::VPSHUFBZrmkz:
1928 SrcIdx = 2; MaskIdx = 6; break;
1929 case X86::VPSHUFBZ128rmk:
1930 case X86::VPSHUFBZ256rmk:
1931 case X86::VPSHUFBZrmk:
1932 SrcIdx = 3; MaskIdx = 7; break;
1933 }
1934
1935 assert(MI->getNumOperands() >= 6 &&
1936 "We should always have at least 6 operands!");
1937
1938 const MachineOperand &MaskOp = MI->getOperand(MaskIdx);
1939 if (auto *C = getConstantFromPool(*MI, MaskOp)) {
1940 unsigned Width = getRegisterWidth(MI->getDesc().OpInfo[0]);
1941 SmallVector<int, 64> Mask;
1942 DecodePSHUFBMask(C, Width, Mask);
1943 if (!Mask.empty())
1944 OutStreamer->AddComment(getShuffleComment(MI, SrcIdx, SrcIdx, Mask));
1945 }
1946 break;
1947 }
1948
1949 case X86::VPERMILPSrm:
1950 case X86::VPERMILPSYrm:
1951 case X86::VPERMILPSZ128rm:
1952 case X86::VPERMILPSZ128rmk:
1953 case X86::VPERMILPSZ128rmkz:
1954 case X86::VPERMILPSZ256rm:
1955 case X86::VPERMILPSZ256rmk:
1956 case X86::VPERMILPSZ256rmkz:
1957 case X86::VPERMILPSZrm:
1958 case X86::VPERMILPSZrmk:
1959 case X86::VPERMILPSZrmkz:
1960 case X86::VPERMILPDrm:
1961 case X86::VPERMILPDYrm:
1962 case X86::VPERMILPDZ128rm:
1963 case X86::VPERMILPDZ128rmk:
1964 case X86::VPERMILPDZ128rmkz:
1965 case X86::VPERMILPDZ256rm:
1966 case X86::VPERMILPDZ256rmk:
1967 case X86::VPERMILPDZ256rmkz:
1968 case X86::VPERMILPDZrm:
1969 case X86::VPERMILPDZrmk:
1970 case X86::VPERMILPDZrmkz: {
1971 if (!OutStreamer->isVerboseAsm())
1972 break;
1973 unsigned SrcIdx, MaskIdx;
1974 unsigned ElSize;
1975 switch (MI->getOpcode()) {
1976 default: llvm_unreachable("Invalid opcode");
1977 case X86::VPERMILPSrm:
1978 case X86::VPERMILPSYrm:
1979 case X86::VPERMILPSZ128rm:
1980 case X86::VPERMILPSZ256rm:
1981 case X86::VPERMILPSZrm:
1982 SrcIdx = 1; MaskIdx = 5; ElSize = 32; break;
1983 case X86::VPERMILPSZ128rmkz:
1984 case X86::VPERMILPSZ256rmkz:
1985 case X86::VPERMILPSZrmkz:
1986 SrcIdx = 2; MaskIdx = 6; ElSize = 32; break;
1987 case X86::VPERMILPSZ128rmk:
1988 case X86::VPERMILPSZ256rmk:
1989 case X86::VPERMILPSZrmk:
1990 SrcIdx = 3; MaskIdx = 7; ElSize = 32; break;
1991 case X86::VPERMILPDrm:
1992 case X86::VPERMILPDYrm:
1993 case X86::VPERMILPDZ128rm:
1994 case X86::VPERMILPDZ256rm:
1995 case X86::VPERMILPDZrm:
1996 SrcIdx = 1; MaskIdx = 5; ElSize = 64; break;
1997 case X86::VPERMILPDZ128rmkz:
1998 case X86::VPERMILPDZ256rmkz:
1999 case X86::VPERMILPDZrmkz:
2000 SrcIdx = 2; MaskIdx = 6; ElSize = 64; break;
2001 case X86::VPERMILPDZ128rmk:
2002 case X86::VPERMILPDZ256rmk:
2003 case X86::VPERMILPDZrmk:
2004 SrcIdx = 3; MaskIdx = 7; ElSize = 64; break;
2005 }
2006
2007 assert(MI->getNumOperands() >= 6 &&
2008 "We should always have at least 6 operands!");
2009
2010 const MachineOperand &MaskOp = MI->getOperand(MaskIdx);
2011 if (auto *C = getConstantFromPool(*MI, MaskOp)) {
2012 unsigned Width = getRegisterWidth(MI->getDesc().OpInfo[0]);
2013 SmallVector<int, 16> Mask;
2014 DecodeVPERMILPMask(C, ElSize, Width, Mask);
2015 if (!Mask.empty())
2016 OutStreamer->AddComment(getShuffleComment(MI, SrcIdx, SrcIdx, Mask));
2017 }
2018 break;
2019 }
2020
2021 case X86::VPERMIL2PDrm:
2022 case X86::VPERMIL2PSrm:
2023 case X86::VPERMIL2PDYrm:
2024 case X86::VPERMIL2PSYrm: {
2025 if (!OutStreamer->isVerboseAsm())
2026 break;
2027 assert(MI->getNumOperands() >= 8 &&
2028 "We should always have at least 8 operands!");
2029
2030 const MachineOperand &CtrlOp = MI->getOperand(MI->getNumOperands() - 1);
2031 if (!CtrlOp.isImm())
2032 break;
2033
2034 unsigned ElSize;
2035 switch (MI->getOpcode()) {
2036 default: llvm_unreachable("Invalid opcode");
2037 case X86::VPERMIL2PSrm: case X86::VPERMIL2PSYrm: ElSize = 32; break;
2038 case X86::VPERMIL2PDrm: case X86::VPERMIL2PDYrm: ElSize = 64; break;
2039 }
2040
2041 const MachineOperand &MaskOp = MI->getOperand(6);
2042 if (auto *C = getConstantFromPool(*MI, MaskOp)) {
2043 unsigned Width = getRegisterWidth(MI->getDesc().OpInfo[0]);
2044 SmallVector<int, 16> Mask;
2045 DecodeVPERMIL2PMask(C, (unsigned)CtrlOp.getImm(), ElSize, Width, Mask);
2046 if (!Mask.empty())
2047 OutStreamer->AddComment(getShuffleComment(MI, 1, 2, Mask));
2048 }
2049 break;
2050 }
2051
2052 case X86::VPPERMrrm: {
2053 if (!OutStreamer->isVerboseAsm())
2054 break;
2055 assert(MI->getNumOperands() >= 7 &&
2056 "We should always have at least 7 operands!");
2057
2058 const MachineOperand &MaskOp = MI->getOperand(6);
2059 if (auto *C = getConstantFromPool(*MI, MaskOp)) {
2060 unsigned Width = getRegisterWidth(MI->getDesc().OpInfo[0]);
2061 SmallVector<int, 16> Mask;
2062 DecodeVPPERMMask(C, Width, Mask);
2063 if (!Mask.empty())
2064 OutStreamer->AddComment(getShuffleComment(MI, 1, 2, Mask));
2065 }
2066 break;
2067 }
2068
2069 case X86::MMX_MOVQ64rm: {
2070 if (!OutStreamer->isVerboseAsm())
2071 break;
2072 if (MI->getNumOperands() <= 4)
2073 break;
2074 if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) {
2075 std::string Comment;
2076 raw_string_ostream CS(Comment);
2077 const MachineOperand &DstOp = MI->getOperand(0);
2078 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = ";
2079 if (auto *CF = dyn_cast<ConstantFP>(C)) {
2080 CS << "0x" << CF->getValueAPF().bitcastToAPInt().toString(16, false);
2081 OutStreamer->AddComment(CS.str());
2082 }
2083 }
2084 break;
2085 }
2086
2087 #define MOV_CASE(Prefix, Suffix) \
2088 case X86::Prefix##MOVAPD##Suffix##rm: \
2089 case X86::Prefix##MOVAPS##Suffix##rm: \
2090 case X86::Prefix##MOVUPD##Suffix##rm: \
2091 case X86::Prefix##MOVUPS##Suffix##rm: \
2092 case X86::Prefix##MOVDQA##Suffix##rm: \
2093 case X86::Prefix##MOVDQU##Suffix##rm:
2094
2095 #define MOV_AVX512_CASE(Suffix) \
2096 case X86::VMOVDQA64##Suffix##rm: \
2097 case X86::VMOVDQA32##Suffix##rm: \
2098 case X86::VMOVDQU64##Suffix##rm: \
2099 case X86::VMOVDQU32##Suffix##rm: \
2100 case X86::VMOVDQU16##Suffix##rm: \
2101 case X86::VMOVDQU8##Suffix##rm: \
2102 case X86::VMOVAPS##Suffix##rm: \
2103 case X86::VMOVAPD##Suffix##rm: \
2104 case X86::VMOVUPS##Suffix##rm: \
2105 case X86::VMOVUPD##Suffix##rm:
2106
2107 #define CASE_ALL_MOV_RM() \
2108 MOV_CASE(, ) /* SSE */ \
2109 MOV_CASE(V, ) /* AVX-128 */ \
2110 MOV_CASE(V, Y) /* AVX-256 */ \
2111 MOV_AVX512_CASE(Z) \
2112 MOV_AVX512_CASE(Z256) \
2113 MOV_AVX512_CASE(Z128)
2114
2115 // For loads from a constant pool to a vector register, print the constant
2116 // loaded.
2117 CASE_ALL_MOV_RM()
2118 case X86::VBROADCASTF128:
2119 case X86::VBROADCASTI128:
2120 case X86::VBROADCASTF32X4Z256rm:
2121 case X86::VBROADCASTF32X4rm:
2122 case X86::VBROADCASTF32X8rm:
2123 case X86::VBROADCASTF64X2Z128rm:
2124 case X86::VBROADCASTF64X2rm:
2125 case X86::VBROADCASTF64X4rm:
2126 case X86::VBROADCASTI32X4Z256rm:
2127 case X86::VBROADCASTI32X4rm:
2128 case X86::VBROADCASTI32X8rm:
2129 case X86::VBROADCASTI64X2Z128rm:
2130 case X86::VBROADCASTI64X2rm:
2131 case X86::VBROADCASTI64X4rm:
2132 if (!OutStreamer->isVerboseAsm())
2133 break;
2134 if (MI->getNumOperands() <= 4)
2135 break;
2136 if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) {
2137 int NumLanes = 1;
2138 // Override NumLanes for the broadcast instructions.
2139 switch (MI->getOpcode()) {
2140 case X86::VBROADCASTF128: NumLanes = 2; break;
2141 case X86::VBROADCASTI128: NumLanes = 2; break;
2142 case X86::VBROADCASTF32X4Z256rm: NumLanes = 2; break;
2143 case X86::VBROADCASTF32X4rm: NumLanes = 4; break;
2144 case X86::VBROADCASTF32X8rm: NumLanes = 2; break;
2145 case X86::VBROADCASTF64X2Z128rm: NumLanes = 2; break;
2146 case X86::VBROADCASTF64X2rm: NumLanes = 4; break;
2147 case X86::VBROADCASTF64X4rm: NumLanes = 2; break;
2148 case X86::VBROADCASTI32X4Z256rm: NumLanes = 2; break;
2149 case X86::VBROADCASTI32X4rm: NumLanes = 4; break;
2150 case X86::VBROADCASTI32X8rm: NumLanes = 2; break;
2151 case X86::VBROADCASTI64X2Z128rm: NumLanes = 2; break;
2152 case X86::VBROADCASTI64X2rm: NumLanes = 4; break;
2153 case X86::VBROADCASTI64X4rm: NumLanes = 2; break;
2154 }
2155
2156 std::string Comment;
2157 raw_string_ostream CS(Comment);
2158 const MachineOperand &DstOp = MI->getOperand(0);
2159 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = ";
2160 if (auto *CDS = dyn_cast<ConstantDataSequential>(C)) {
2161 CS << "[";
2162 for (int l = 0; l != NumLanes; ++l) {
2163 for (int i = 0, NumElements = CDS->getNumElements(); i < NumElements;
2164 ++i) {
2165 if (i != 0 || l != 0)
2166 CS << ",";
2167 if (CDS->getElementType()->isIntegerTy())
2168 printConstant(CDS->getElementAsAPInt(i), CS);
2169 else if (CDS->getElementType()->isHalfTy() ||
2170 CDS->getElementType()->isFloatTy() ||
2171 CDS->getElementType()->isDoubleTy())
2172 printConstant(CDS->getElementAsAPFloat(i), CS);
2173 else
2174 CS << "?";
2175 }
2176 }
2177 CS << "]";
2178 OutStreamer->AddComment(CS.str());
2179 } else if (auto *CV = dyn_cast<ConstantVector>(C)) {
2180 CS << "<";
2181 for (int l = 0; l != NumLanes; ++l) {
2182 for (int i = 0, NumOperands = CV->getNumOperands(); i < NumOperands;
2183 ++i) {
2184 if (i != 0 || l != 0)
2185 CS << ",";
2186 printConstant(CV->getOperand(i), CS);
2187 }
2188 }
2189 CS << ">";
2190 OutStreamer->AddComment(CS.str());
2191 }
2192 }
2193 break;
2194 case X86::MOVDDUPrm:
2195 case X86::VMOVDDUPrm:
2196 case X86::VMOVDDUPZ128rm:
2197 case X86::VBROADCASTSSrm:
2198 case X86::VBROADCASTSSYrm:
2199 case X86::VBROADCASTSSZ128m:
2200 case X86::VBROADCASTSSZ256m:
2201 case X86::VBROADCASTSSZm:
2202 case X86::VBROADCASTSDYrm:
2203 case X86::VBROADCASTSDZ256m:
2204 case X86::VBROADCASTSDZm:
2205 case X86::VPBROADCASTBrm:
2206 case X86::VPBROADCASTBYrm:
2207 case X86::VPBROADCASTBZ128m:
2208 case X86::VPBROADCASTBZ256m:
2209 case X86::VPBROADCASTBZm:
2210 case X86::VPBROADCASTDrm:
2211 case X86::VPBROADCASTDYrm:
2212 case X86::VPBROADCASTDZ128m:
2213 case X86::VPBROADCASTDZ256m:
2214 case X86::VPBROADCASTDZm:
2215 case X86::VPBROADCASTQrm:
2216 case X86::VPBROADCASTQYrm:
2217 case X86::VPBROADCASTQZ128m:
2218 case X86::VPBROADCASTQZ256m:
2219 case X86::VPBROADCASTQZm:
2220 case X86::VPBROADCASTWrm:
2221 case X86::VPBROADCASTWYrm:
2222 case X86::VPBROADCASTWZ128m:
2223 case X86::VPBROADCASTWZ256m:
2224 case X86::VPBROADCASTWZm:
2225 if (!OutStreamer->isVerboseAsm())
2226 break;
2227 if (MI->getNumOperands() <= 4)
2228 break;
2229 if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) {
2230 int NumElts;
2231 switch (MI->getOpcode()) {
2232 default: llvm_unreachable("Invalid opcode");
2233 case X86::MOVDDUPrm: NumElts = 2; break;
2234 case X86::VMOVDDUPrm: NumElts = 2; break;
2235 case X86::VMOVDDUPZ128rm: NumElts = 2; break;
2236 case X86::VBROADCASTSSrm: NumElts = 4; break;
2237 case X86::VBROADCASTSSYrm: NumElts = 8; break;
2238 case X86::VBROADCASTSSZ128m: NumElts = 4; break;
2239 case X86::VBROADCASTSSZ256m: NumElts = 8; break;
2240 case X86::VBROADCASTSSZm: NumElts = 16; break;
2241 case X86::VBROADCASTSDYrm: NumElts = 4; break;
2242 case X86::VBROADCASTSDZ256m: NumElts = 4; break;
2243 case X86::VBROADCASTSDZm: NumElts = 8; break;
2244 case X86::VPBROADCASTBrm: NumElts = 16; break;
2245 case X86::VPBROADCASTBYrm: NumElts = 32; break;
2246 case X86::VPBROADCASTBZ128m: NumElts = 16; break;
2247 case X86::VPBROADCASTBZ256m: NumElts = 32; break;
2248 case X86::VPBROADCASTBZm: NumElts = 64; break;
2249 case X86::VPBROADCASTDrm: NumElts = 4; break;
2250 case X86::VPBROADCASTDYrm: NumElts = 8; break;
2251 case X86::VPBROADCASTDZ128m: NumElts = 4; break;
2252 case X86::VPBROADCASTDZ256m: NumElts = 8; break;
2253 case X86::VPBROADCASTDZm: NumElts = 16; break;
2254 case X86::VPBROADCASTQrm: NumElts = 2; break;
2255 case X86::VPBROADCASTQYrm: NumElts = 4; break;
2256 case X86::VPBROADCASTQZ128m: NumElts = 2; break;
2257 case X86::VPBROADCASTQZ256m: NumElts = 4; break;
2258 case X86::VPBROADCASTQZm: NumElts = 8; break;
2259 case X86::VPBROADCASTWrm: NumElts = 8; break;
2260 case X86::VPBROADCASTWYrm: NumElts = 16; break;
2261 case X86::VPBROADCASTWZ128m: NumElts = 8; break;
2262 case X86::VPBROADCASTWZ256m: NumElts = 16; break;
2263 case X86::VPBROADCASTWZm: NumElts = 32; break;
2264 }
2265
2266 std::string Comment;
2267 raw_string_ostream CS(Comment);
2268 const MachineOperand &DstOp = MI->getOperand(0);
2269 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = ";
2270 CS << "[";
2271 for (int i = 0; i != NumElts; ++i) {
2272 if (i != 0)
2273 CS << ",";
2274 printConstant(C, CS);
2275 }
2276 CS << "]";
2277 OutStreamer->AddComment(CS.str());
2278 }
2279 }
2280
2281 MCInst TmpInst;
2282 MCInstLowering.Lower(MI, TmpInst);
2283
2284 // Stackmap shadows cannot include branch targets, so we can count the bytes
2285 // in a call towards the shadow, but must ensure that the no thread returns
2286 // in to the stackmap shadow. The only way to achieve this is if the call
2287 // is at the end of the shadow.
2288 if (MI->isCall()) {
2289 // Count then size of the call towards the shadow
2290 SMShadowTracker.count(TmpInst, getSubtargetInfo(), CodeEmitter.get());
2291 // Then flush the shadow so that we fill with nops before the call, not
2292 // after it.
2293 SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
2294 // Then emit the call
2295 OutStreamer->EmitInstruction(TmpInst, getSubtargetInfo());
2296 return;
2297 }
2298
2299 EmitAndCountInstruction(TmpInst);
2300 }
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