1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 /// This file implements a TargetTransformInfo analysis pass specific to the
10 /// X86 target machine. It uses the target's detailed information to provide
11 /// more precise answers to certain TTI queries, while letting the target
12 /// independent and default TTI implementations handle the rest.
14 //===----------------------------------------------------------------------===//
15 /// About Cost Model numbers used below it's necessary to say the following:
16 /// the numbers correspond to some "generic" X86 CPU instead of usage of
17 /// concrete CPU model. Usually the numbers correspond to CPU where the feature
18 /// apeared at the first time. For example, if we do Subtarget.hasSSE42() in
19 /// the lookups below the cost is based on Nehalem as that was the first CPU
20 /// to support that feature level and thus has most likely the worst case cost.
21 /// Some examples of other technologies/CPUs:
22 /// SSE 3 - Pentium4 / Athlon64
25 /// AVX - Sandy Bridge
27 /// AVX-512 - Xeon Phi / Skylake
28 /// And some examples of instruction target dependent costs (latency)
29 /// divss sqrtss rsqrtss
31 /// Piledriver 9-24 13-15 5
33 /// Pentium II,III 18 30 2
34 /// Nehalem 7-14 7-18 3
35 /// Haswell 10-13 11 5
36 /// TODO: Develop and implement the target dependent cost model and
37 /// specialize cost numbers for different Cost Model Targets such as throughput,
38 /// code size, latency and uop count.
39 //===----------------------------------------------------------------------===//
41 #include "X86TargetTransformInfo.h"
42 #include "llvm/Analysis/TargetTransformInfo.h"
43 #include "llvm/CodeGen/BasicTTIImpl.h"
44 #include "llvm/CodeGen/CostTable.h"
45 #include "llvm/CodeGen/TargetLowering.h"
46 #include "llvm/IR/IntrinsicInst.h"
47 #include "llvm/Support/Debug.h"
51 #define DEBUG_TYPE "x86tti"
53 extern cl::opt
<bool> ExperimentalVectorWideningLegalization
;
55 //===----------------------------------------------------------------------===//
59 //===----------------------------------------------------------------------===//
61 TargetTransformInfo::PopcntSupportKind
62 X86TTIImpl::getPopcntSupport(unsigned TyWidth
) {
63 assert(isPowerOf2_32(TyWidth
) && "Ty width must be power of 2");
64 // TODO: Currently the __builtin_popcount() implementation using SSE3
65 // instructions is inefficient. Once the problem is fixed, we should
66 // call ST->hasSSE3() instead of ST->hasPOPCNT().
67 return ST
->hasPOPCNT() ? TTI::PSK_FastHardware
: TTI::PSK_Software
;
70 llvm::Optional
<unsigned> X86TTIImpl::getCacheSize(
71 TargetTransformInfo::CacheLevel Level
) const {
73 case TargetTransformInfo::CacheLevel::L1D
:
83 return 32 * 1024; // 32 KByte
84 case TargetTransformInfo::CacheLevel::L2D
:
94 return 256 * 1024; // 256 KByte
97 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel");
100 llvm::Optional
<unsigned> X86TTIImpl::getCacheAssociativity(
101 TargetTransformInfo::CacheLevel Level
) const {
112 case TargetTransformInfo::CacheLevel::L1D
:
114 case TargetTransformInfo::CacheLevel::L2D
:
118 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel");
121 unsigned X86TTIImpl::getNumberOfRegisters(bool Vector
) {
122 if (Vector
&& !ST
->hasSSE1())
126 if (Vector
&& ST
->hasAVX512())
133 unsigned X86TTIImpl::getRegisterBitWidth(bool Vector
) const {
134 unsigned PreferVectorWidth
= ST
->getPreferVectorWidth();
136 if (ST
->hasAVX512() && PreferVectorWidth
>= 512)
138 if (ST
->hasAVX() && PreferVectorWidth
>= 256)
140 if (ST
->hasSSE1() && PreferVectorWidth
>= 128)
151 unsigned X86TTIImpl::getLoadStoreVecRegBitWidth(unsigned) const {
152 return getRegisterBitWidth(true);
155 unsigned X86TTIImpl::getMaxInterleaveFactor(unsigned VF
) {
156 // If the loop will not be vectorized, don't interleave the loop.
157 // Let regular unroll to unroll the loop, which saves the overflow
158 // check and memory check cost.
165 // Sandybridge and Haswell have multiple execution ports and pipelined
173 int X86TTIImpl::getArithmeticInstrCost(
174 unsigned Opcode
, Type
*Ty
,
175 TTI::OperandValueKind Op1Info
, TTI::OperandValueKind Op2Info
,
176 TTI::OperandValueProperties Opd1PropInfo
,
177 TTI::OperandValueProperties Opd2PropInfo
,
178 ArrayRef
<const Value
*> Args
) {
179 // Legalize the type.
180 std::pair
<int, MVT
> LT
= TLI
->getTypeLegalizationCost(DL
, Ty
);
182 int ISD
= TLI
->InstructionOpcodeToISD(Opcode
);
183 assert(ISD
&& "Invalid opcode");
185 static const CostTblEntry GLMCostTable
[] = {
186 { ISD::FDIV
, MVT::f32
, 18 }, // divss
187 { ISD::FDIV
, MVT::v4f32
, 35 }, // divps
188 { ISD::FDIV
, MVT::f64
, 33 }, // divsd
189 { ISD::FDIV
, MVT::v2f64
, 65 }, // divpd
193 if (const auto *Entry
= CostTableLookup(GLMCostTable
, ISD
,
195 return LT
.first
* Entry
->Cost
;
197 static const CostTblEntry SLMCostTable
[] = {
198 { ISD::MUL
, MVT::v4i32
, 11 }, // pmulld
199 { ISD::MUL
, MVT::v8i16
, 2 }, // pmullw
200 { ISD::MUL
, MVT::v16i8
, 14 }, // extend/pmullw/trunc sequence.
201 { ISD::FMUL
, MVT::f64
, 2 }, // mulsd
202 { ISD::FMUL
, MVT::v2f64
, 4 }, // mulpd
203 { ISD::FMUL
, MVT::v4f32
, 2 }, // mulps
204 { ISD::FDIV
, MVT::f32
, 17 }, // divss
205 { ISD::FDIV
, MVT::v4f32
, 39 }, // divps
206 { ISD::FDIV
, MVT::f64
, 32 }, // divsd
207 { ISD::FDIV
, MVT::v2f64
, 69 }, // divpd
208 { ISD::FADD
, MVT::v2f64
, 2 }, // addpd
209 { ISD::FSUB
, MVT::v2f64
, 2 }, // subpd
210 // v2i64/v4i64 mul is custom lowered as a series of long:
211 // multiplies(3), shifts(3) and adds(2)
212 // slm muldq version throughput is 2 and addq throughput 4
213 // thus: 3X2 (muldq throughput) + 3X1 (shift throughput) +
214 // 3X4 (addq throughput) = 17
215 { ISD::MUL
, MVT::v2i64
, 17 },
216 // slm addq\subq throughput is 4
217 { ISD::ADD
, MVT::v2i64
, 4 },
218 { ISD::SUB
, MVT::v2i64
, 4 },
222 if (Args
.size() == 2 && ISD
== ISD::MUL
&& LT
.second
== MVT::v4i32
) {
223 // Check if the operands can be shrinked into a smaller datatype.
224 bool Op1Signed
= false;
225 unsigned Op1MinSize
= BaseT::minRequiredElementSize(Args
[0], Op1Signed
);
226 bool Op2Signed
= false;
227 unsigned Op2MinSize
= BaseT::minRequiredElementSize(Args
[1], Op2Signed
);
229 bool signedMode
= Op1Signed
| Op2Signed
;
230 unsigned OpMinSize
= std::max(Op1MinSize
, Op2MinSize
);
233 return LT
.first
* 3; // pmullw/sext
234 if (!signedMode
&& OpMinSize
<= 8)
235 return LT
.first
* 3; // pmullw/zext
237 return LT
.first
* 5; // pmullw/pmulhw/pshuf
238 if (!signedMode
&& OpMinSize
<= 16)
239 return LT
.first
* 5; // pmullw/pmulhw/pshuf
242 if (const auto *Entry
= CostTableLookup(SLMCostTable
, ISD
,
244 return LT
.first
* Entry
->Cost
;
248 if ((ISD
== ISD::SDIV
|| ISD
== ISD::SREM
|| ISD
== ISD::UDIV
||
250 (Op2Info
== TargetTransformInfo::OK_UniformConstantValue
||
251 Op2Info
== TargetTransformInfo::OK_NonUniformConstantValue
) &&
252 Opd2PropInfo
== TargetTransformInfo::OP_PowerOf2
) {
253 if (ISD
== ISD::SDIV
|| ISD
== ISD::SREM
) {
254 // On X86, vector signed division by constants power-of-two are
255 // normally expanded to the sequence SRA + SRL + ADD + SRA.
256 // The OperandValue properties may not be the same as that of the previous
257 // operation; conservatively assume OP_None.
259 2 * getArithmeticInstrCost(Instruction::AShr
, Ty
, Op1Info
, Op2Info
,
260 TargetTransformInfo::OP_None
,
261 TargetTransformInfo::OP_None
);
262 Cost
+= getArithmeticInstrCost(Instruction::LShr
, Ty
, Op1Info
, Op2Info
,
263 TargetTransformInfo::OP_None
,
264 TargetTransformInfo::OP_None
);
265 Cost
+= getArithmeticInstrCost(Instruction::Add
, Ty
, Op1Info
, Op2Info
,
266 TargetTransformInfo::OP_None
,
267 TargetTransformInfo::OP_None
);
269 if (ISD
== ISD::SREM
) {
270 // For SREM: (X % C) is the equivalent of (X - (X/C)*C)
271 Cost
+= getArithmeticInstrCost(Instruction::Mul
, Ty
, Op1Info
, Op2Info
);
272 Cost
+= getArithmeticInstrCost(Instruction::Sub
, Ty
, Op1Info
, Op2Info
);
278 // Vector unsigned division/remainder will be simplified to shifts/masks.
279 if (ISD
== ISD::UDIV
)
280 return getArithmeticInstrCost(Instruction::LShr
, Ty
, Op1Info
, Op2Info
,
281 TargetTransformInfo::OP_None
,
282 TargetTransformInfo::OP_None
);
284 if (ISD
== ISD::UREM
)
285 return getArithmeticInstrCost(Instruction::And
, Ty
, Op1Info
, Op2Info
,
286 TargetTransformInfo::OP_None
,
287 TargetTransformInfo::OP_None
);
290 static const CostTblEntry AVX512BWUniformConstCostTable
[] = {
291 { ISD::SHL
, MVT::v64i8
, 2 }, // psllw + pand.
292 { ISD::SRL
, MVT::v64i8
, 2 }, // psrlw + pand.
293 { ISD::SRA
, MVT::v64i8
, 4 }, // psrlw, pand, pxor, psubb.
296 if (Op2Info
== TargetTransformInfo::OK_UniformConstantValue
&&
298 if (const auto *Entry
= CostTableLookup(AVX512BWUniformConstCostTable
, ISD
,
300 return LT
.first
* Entry
->Cost
;
303 static const CostTblEntry AVX512UniformConstCostTable
[] = {
304 { ISD::SRA
, MVT::v2i64
, 1 },
305 { ISD::SRA
, MVT::v4i64
, 1 },
306 { ISD::SRA
, MVT::v8i64
, 1 },
309 if (Op2Info
== TargetTransformInfo::OK_UniformConstantValue
&&
311 if (const auto *Entry
= CostTableLookup(AVX512UniformConstCostTable
, ISD
,
313 return LT
.first
* Entry
->Cost
;
316 static const CostTblEntry AVX2UniformConstCostTable
[] = {
317 { ISD::SHL
, MVT::v32i8
, 2 }, // psllw + pand.
318 { ISD::SRL
, MVT::v32i8
, 2 }, // psrlw + pand.
319 { ISD::SRA
, MVT::v32i8
, 4 }, // psrlw, pand, pxor, psubb.
321 { ISD::SRA
, MVT::v4i64
, 4 }, // 2 x psrad + shuffle.
324 if (Op2Info
== TargetTransformInfo::OK_UniformConstantValue
&&
326 if (const auto *Entry
= CostTableLookup(AVX2UniformConstCostTable
, ISD
,
328 return LT
.first
* Entry
->Cost
;
331 static const CostTblEntry SSE2UniformConstCostTable
[] = {
332 { ISD::SHL
, MVT::v16i8
, 2 }, // psllw + pand.
333 { ISD::SRL
, MVT::v16i8
, 2 }, // psrlw + pand.
334 { ISD::SRA
, MVT::v16i8
, 4 }, // psrlw, pand, pxor, psubb.
336 { ISD::SHL
, MVT::v32i8
, 4+2 }, // 2*(psllw + pand) + split.
337 { ISD::SRL
, MVT::v32i8
, 4+2 }, // 2*(psrlw + pand) + split.
338 { ISD::SRA
, MVT::v32i8
, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split.
341 // XOP has faster vXi8 shifts.
342 if (Op2Info
== TargetTransformInfo::OK_UniformConstantValue
&&
343 ST
->hasSSE2() && !ST
->hasXOP()) {
344 if (const auto *Entry
=
345 CostTableLookup(SSE2UniformConstCostTable
, ISD
, LT
.second
))
346 return LT
.first
* Entry
->Cost
;
349 static const CostTblEntry AVX512BWConstCostTable
[] = {
350 { ISD::SDIV
, MVT::v64i8
, 14 }, // 2*ext+2*pmulhw sequence
351 { ISD::SREM
, MVT::v64i8
, 16 }, // 2*ext+2*pmulhw+mul+sub sequence
352 { ISD::UDIV
, MVT::v64i8
, 14 }, // 2*ext+2*pmulhw sequence
353 { ISD::UREM
, MVT::v64i8
, 16 }, // 2*ext+2*pmulhw+mul+sub sequence
354 { ISD::SDIV
, MVT::v32i16
, 6 }, // vpmulhw sequence
355 { ISD::SREM
, MVT::v32i16
, 8 }, // vpmulhw+mul+sub sequence
356 { ISD::UDIV
, MVT::v32i16
, 6 }, // vpmulhuw sequence
357 { ISD::UREM
, MVT::v32i16
, 8 }, // vpmulhuw+mul+sub sequence
360 if ((Op2Info
== TargetTransformInfo::OK_UniformConstantValue
||
361 Op2Info
== TargetTransformInfo::OK_NonUniformConstantValue
) &&
363 if (const auto *Entry
=
364 CostTableLookup(AVX512BWConstCostTable
, ISD
, LT
.second
))
365 return LT
.first
* Entry
->Cost
;
368 static const CostTblEntry AVX512ConstCostTable
[] = {
369 { ISD::SDIV
, MVT::v16i32
, 15 }, // vpmuldq sequence
370 { ISD::SREM
, MVT::v16i32
, 17 }, // vpmuldq+mul+sub sequence
371 { ISD::UDIV
, MVT::v16i32
, 15 }, // vpmuludq sequence
372 { ISD::UREM
, MVT::v16i32
, 17 }, // vpmuludq+mul+sub sequence
375 if ((Op2Info
== TargetTransformInfo::OK_UniformConstantValue
||
376 Op2Info
== TargetTransformInfo::OK_NonUniformConstantValue
) &&
378 if (const auto *Entry
=
379 CostTableLookup(AVX512ConstCostTable
, ISD
, LT
.second
))
380 return LT
.first
* Entry
->Cost
;
383 static const CostTblEntry AVX2ConstCostTable
[] = {
384 { ISD::SDIV
, MVT::v32i8
, 14 }, // 2*ext+2*pmulhw sequence
385 { ISD::SREM
, MVT::v32i8
, 16 }, // 2*ext+2*pmulhw+mul+sub sequence
386 { ISD::UDIV
, MVT::v32i8
, 14 }, // 2*ext+2*pmulhw sequence
387 { ISD::UREM
, MVT::v32i8
, 16 }, // 2*ext+2*pmulhw+mul+sub sequence
388 { ISD::SDIV
, MVT::v16i16
, 6 }, // vpmulhw sequence
389 { ISD::SREM
, MVT::v16i16
, 8 }, // vpmulhw+mul+sub sequence
390 { ISD::UDIV
, MVT::v16i16
, 6 }, // vpmulhuw sequence
391 { ISD::UREM
, MVT::v16i16
, 8 }, // vpmulhuw+mul+sub sequence
392 { ISD::SDIV
, MVT::v8i32
, 15 }, // vpmuldq sequence
393 { ISD::SREM
, MVT::v8i32
, 19 }, // vpmuldq+mul+sub sequence
394 { ISD::UDIV
, MVT::v8i32
, 15 }, // vpmuludq sequence
395 { ISD::UREM
, MVT::v8i32
, 19 }, // vpmuludq+mul+sub sequence
398 if ((Op2Info
== TargetTransformInfo::OK_UniformConstantValue
||
399 Op2Info
== TargetTransformInfo::OK_NonUniformConstantValue
) &&
401 if (const auto *Entry
= CostTableLookup(AVX2ConstCostTable
, ISD
, LT
.second
))
402 return LT
.first
* Entry
->Cost
;
405 static const CostTblEntry SSE2ConstCostTable
[] = {
406 { ISD::SDIV
, MVT::v32i8
, 28+2 }, // 4*ext+4*pmulhw sequence + split.
407 { ISD::SREM
, MVT::v32i8
, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split.
408 { ISD::SDIV
, MVT::v16i8
, 14 }, // 2*ext+2*pmulhw sequence
409 { ISD::SREM
, MVT::v16i8
, 16 }, // 2*ext+2*pmulhw+mul+sub sequence
410 { ISD::UDIV
, MVT::v32i8
, 28+2 }, // 4*ext+4*pmulhw sequence + split.
411 { ISD::UREM
, MVT::v32i8
, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split.
412 { ISD::UDIV
, MVT::v16i8
, 14 }, // 2*ext+2*pmulhw sequence
413 { ISD::UREM
, MVT::v16i8
, 16 }, // 2*ext+2*pmulhw+mul+sub sequence
414 { ISD::SDIV
, MVT::v16i16
, 12+2 }, // 2*pmulhw sequence + split.
415 { ISD::SREM
, MVT::v16i16
, 16+2 }, // 2*pmulhw+mul+sub sequence + split.
416 { ISD::SDIV
, MVT::v8i16
, 6 }, // pmulhw sequence
417 { ISD::SREM
, MVT::v8i16
, 8 }, // pmulhw+mul+sub sequence
418 { ISD::UDIV
, MVT::v16i16
, 12+2 }, // 2*pmulhuw sequence + split.
419 { ISD::UREM
, MVT::v16i16
, 16+2 }, // 2*pmulhuw+mul+sub sequence + split.
420 { ISD::UDIV
, MVT::v8i16
, 6 }, // pmulhuw sequence
421 { ISD::UREM
, MVT::v8i16
, 8 }, // pmulhuw+mul+sub sequence
422 { ISD::SDIV
, MVT::v8i32
, 38+2 }, // 2*pmuludq sequence + split.
423 { ISD::SREM
, MVT::v8i32
, 48+2 }, // 2*pmuludq+mul+sub sequence + split.
424 { ISD::SDIV
, MVT::v4i32
, 19 }, // pmuludq sequence
425 { ISD::SREM
, MVT::v4i32
, 24 }, // pmuludq+mul+sub sequence
426 { ISD::UDIV
, MVT::v8i32
, 30+2 }, // 2*pmuludq sequence + split.
427 { ISD::UREM
, MVT::v8i32
, 40+2 }, // 2*pmuludq+mul+sub sequence + split.
428 { ISD::UDIV
, MVT::v4i32
, 15 }, // pmuludq sequence
429 { ISD::UREM
, MVT::v4i32
, 20 }, // pmuludq+mul+sub sequence
432 if ((Op2Info
== TargetTransformInfo::OK_UniformConstantValue
||
433 Op2Info
== TargetTransformInfo::OK_NonUniformConstantValue
) &&
436 if (ISD
== ISD::SDIV
&& LT
.second
== MVT::v8i32
&& ST
->hasAVX())
437 return LT
.first
* 32;
438 if (ISD
== ISD::SREM
&& LT
.second
== MVT::v8i32
&& ST
->hasAVX())
439 return LT
.first
* 38;
440 if (ISD
== ISD::SDIV
&& LT
.second
== MVT::v4i32
&& ST
->hasSSE41())
441 return LT
.first
* 15;
442 if (ISD
== ISD::SREM
&& LT
.second
== MVT::v4i32
&& ST
->hasSSE41())
443 return LT
.first
* 20;
445 if (const auto *Entry
= CostTableLookup(SSE2ConstCostTable
, ISD
, LT
.second
))
446 return LT
.first
* Entry
->Cost
;
449 static const CostTblEntry AVX2UniformCostTable
[] = {
450 // Uniform splats are cheaper for the following instructions.
451 { ISD::SHL
, MVT::v16i16
, 1 }, // psllw.
452 { ISD::SRL
, MVT::v16i16
, 1 }, // psrlw.
453 { ISD::SRA
, MVT::v16i16
, 1 }, // psraw.
457 ((Op2Info
== TargetTransformInfo::OK_UniformConstantValue
) ||
458 (Op2Info
== TargetTransformInfo::OK_UniformValue
))) {
459 if (const auto *Entry
=
460 CostTableLookup(AVX2UniformCostTable
, ISD
, LT
.second
))
461 return LT
.first
* Entry
->Cost
;
464 static const CostTblEntry SSE2UniformCostTable
[] = {
465 // Uniform splats are cheaper for the following instructions.
466 { ISD::SHL
, MVT::v8i16
, 1 }, // psllw.
467 { ISD::SHL
, MVT::v4i32
, 1 }, // pslld
468 { ISD::SHL
, MVT::v2i64
, 1 }, // psllq.
470 { ISD::SRL
, MVT::v8i16
, 1 }, // psrlw.
471 { ISD::SRL
, MVT::v4i32
, 1 }, // psrld.
472 { ISD::SRL
, MVT::v2i64
, 1 }, // psrlq.
474 { ISD::SRA
, MVT::v8i16
, 1 }, // psraw.
475 { ISD::SRA
, MVT::v4i32
, 1 }, // psrad.
479 ((Op2Info
== TargetTransformInfo::OK_UniformConstantValue
) ||
480 (Op2Info
== TargetTransformInfo::OK_UniformValue
))) {
481 if (const auto *Entry
=
482 CostTableLookup(SSE2UniformCostTable
, ISD
, LT
.second
))
483 return LT
.first
* Entry
->Cost
;
486 static const CostTblEntry AVX512DQCostTable
[] = {
487 { ISD::MUL
, MVT::v2i64
, 1 },
488 { ISD::MUL
, MVT::v4i64
, 1 },
489 { ISD::MUL
, MVT::v8i64
, 1 }
492 // Look for AVX512DQ lowering tricks for custom cases.
494 if (const auto *Entry
= CostTableLookup(AVX512DQCostTable
, ISD
, LT
.second
))
495 return LT
.first
* Entry
->Cost
;
497 static const CostTblEntry AVX512BWCostTable
[] = {
498 { ISD::SHL
, MVT::v8i16
, 1 }, // vpsllvw
499 { ISD::SRL
, MVT::v8i16
, 1 }, // vpsrlvw
500 { ISD::SRA
, MVT::v8i16
, 1 }, // vpsravw
502 { ISD::SHL
, MVT::v16i16
, 1 }, // vpsllvw
503 { ISD::SRL
, MVT::v16i16
, 1 }, // vpsrlvw
504 { ISD::SRA
, MVT::v16i16
, 1 }, // vpsravw
506 { ISD::SHL
, MVT::v32i16
, 1 }, // vpsllvw
507 { ISD::SRL
, MVT::v32i16
, 1 }, // vpsrlvw
508 { ISD::SRA
, MVT::v32i16
, 1 }, // vpsravw
510 { ISD::SHL
, MVT::v64i8
, 11 }, // vpblendvb sequence.
511 { ISD::SRL
, MVT::v64i8
, 11 }, // vpblendvb sequence.
512 { ISD::SRA
, MVT::v64i8
, 24 }, // vpblendvb sequence.
514 { ISD::MUL
, MVT::v64i8
, 11 }, // extend/pmullw/trunc sequence.
515 { ISD::MUL
, MVT::v32i8
, 4 }, // extend/pmullw/trunc sequence.
516 { ISD::MUL
, MVT::v16i8
, 4 }, // extend/pmullw/trunc sequence.
519 // Look for AVX512BW lowering tricks for custom cases.
521 if (const auto *Entry
= CostTableLookup(AVX512BWCostTable
, ISD
, LT
.second
))
522 return LT
.first
* Entry
->Cost
;
524 static const CostTblEntry AVX512CostTable
[] = {
525 { ISD::SHL
, MVT::v16i32
, 1 },
526 { ISD::SRL
, MVT::v16i32
, 1 },
527 { ISD::SRA
, MVT::v16i32
, 1 },
529 { ISD::SHL
, MVT::v8i64
, 1 },
530 { ISD::SRL
, MVT::v8i64
, 1 },
532 { ISD::SRA
, MVT::v2i64
, 1 },
533 { ISD::SRA
, MVT::v4i64
, 1 },
534 { ISD::SRA
, MVT::v8i64
, 1 },
536 { ISD::MUL
, MVT::v32i8
, 13 }, // extend/pmullw/trunc sequence.
537 { ISD::MUL
, MVT::v16i8
, 5 }, // extend/pmullw/trunc sequence.
538 { ISD::MUL
, MVT::v16i32
, 1 }, // pmulld (Skylake from agner.org)
539 { ISD::MUL
, MVT::v8i32
, 1 }, // pmulld (Skylake from agner.org)
540 { ISD::MUL
, MVT::v4i32
, 1 }, // pmulld (Skylake from agner.org)
541 { ISD::MUL
, MVT::v8i64
, 8 }, // 3*pmuludq/3*shift/2*add
543 { ISD::FADD
, MVT::v8f64
, 1 }, // Skylake from http://www.agner.org/
544 { ISD::FSUB
, MVT::v8f64
, 1 }, // Skylake from http://www.agner.org/
545 { ISD::FMUL
, MVT::v8f64
, 1 }, // Skylake from http://www.agner.org/
547 { ISD::FADD
, MVT::v16f32
, 1 }, // Skylake from http://www.agner.org/
548 { ISD::FSUB
, MVT::v16f32
, 1 }, // Skylake from http://www.agner.org/
549 { ISD::FMUL
, MVT::v16f32
, 1 }, // Skylake from http://www.agner.org/
553 if (const auto *Entry
= CostTableLookup(AVX512CostTable
, ISD
, LT
.second
))
554 return LT
.first
* Entry
->Cost
;
556 static const CostTblEntry AVX2ShiftCostTable
[] = {
557 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to
558 // customize them to detect the cases where shift amount is a scalar one.
559 { ISD::SHL
, MVT::v4i32
, 1 },
560 { ISD::SRL
, MVT::v4i32
, 1 },
561 { ISD::SRA
, MVT::v4i32
, 1 },
562 { ISD::SHL
, MVT::v8i32
, 1 },
563 { ISD::SRL
, MVT::v8i32
, 1 },
564 { ISD::SRA
, MVT::v8i32
, 1 },
565 { ISD::SHL
, MVT::v2i64
, 1 },
566 { ISD::SRL
, MVT::v2i64
, 1 },
567 { ISD::SHL
, MVT::v4i64
, 1 },
568 { ISD::SRL
, MVT::v4i64
, 1 },
571 // Look for AVX2 lowering tricks.
573 if (ISD
== ISD::SHL
&& LT
.second
== MVT::v16i16
&&
574 (Op2Info
== TargetTransformInfo::OK_UniformConstantValue
||
575 Op2Info
== TargetTransformInfo::OK_NonUniformConstantValue
))
576 // On AVX2, a packed v16i16 shift left by a constant build_vector
577 // is lowered into a vector multiply (vpmullw).
578 return getArithmeticInstrCost(Instruction::Mul
, Ty
, Op1Info
, Op2Info
,
579 TargetTransformInfo::OP_None
,
580 TargetTransformInfo::OP_None
);
582 if (const auto *Entry
= CostTableLookup(AVX2ShiftCostTable
, ISD
, LT
.second
))
583 return LT
.first
* Entry
->Cost
;
586 static const CostTblEntry XOPShiftCostTable
[] = {
587 // 128bit shifts take 1cy, but right shifts require negation beforehand.
588 { ISD::SHL
, MVT::v16i8
, 1 },
589 { ISD::SRL
, MVT::v16i8
, 2 },
590 { ISD::SRA
, MVT::v16i8
, 2 },
591 { ISD::SHL
, MVT::v8i16
, 1 },
592 { ISD::SRL
, MVT::v8i16
, 2 },
593 { ISD::SRA
, MVT::v8i16
, 2 },
594 { ISD::SHL
, MVT::v4i32
, 1 },
595 { ISD::SRL
, MVT::v4i32
, 2 },
596 { ISD::SRA
, MVT::v4i32
, 2 },
597 { ISD::SHL
, MVT::v2i64
, 1 },
598 { ISD::SRL
, MVT::v2i64
, 2 },
599 { ISD::SRA
, MVT::v2i64
, 2 },
600 // 256bit shifts require splitting if AVX2 didn't catch them above.
601 { ISD::SHL
, MVT::v32i8
, 2+2 },
602 { ISD::SRL
, MVT::v32i8
, 4+2 },
603 { ISD::SRA
, MVT::v32i8
, 4+2 },
604 { ISD::SHL
, MVT::v16i16
, 2+2 },
605 { ISD::SRL
, MVT::v16i16
, 4+2 },
606 { ISD::SRA
, MVT::v16i16
, 4+2 },
607 { ISD::SHL
, MVT::v8i32
, 2+2 },
608 { ISD::SRL
, MVT::v8i32
, 4+2 },
609 { ISD::SRA
, MVT::v8i32
, 4+2 },
610 { ISD::SHL
, MVT::v4i64
, 2+2 },
611 { ISD::SRL
, MVT::v4i64
, 4+2 },
612 { ISD::SRA
, MVT::v4i64
, 4+2 },
615 // Look for XOP lowering tricks.
617 // If the right shift is constant then we'll fold the negation so
618 // it's as cheap as a left shift.
620 if ((ShiftISD
== ISD::SRL
|| ShiftISD
== ISD::SRA
) &&
621 (Op2Info
== TargetTransformInfo::OK_UniformConstantValue
||
622 Op2Info
== TargetTransformInfo::OK_NonUniformConstantValue
))
624 if (const auto *Entry
=
625 CostTableLookup(XOPShiftCostTable
, ShiftISD
, LT
.second
))
626 return LT
.first
* Entry
->Cost
;
629 static const CostTblEntry SSE2UniformShiftCostTable
[] = {
630 // Uniform splats are cheaper for the following instructions.
631 { ISD::SHL
, MVT::v16i16
, 2+2 }, // 2*psllw + split.
632 { ISD::SHL
, MVT::v8i32
, 2+2 }, // 2*pslld + split.
633 { ISD::SHL
, MVT::v4i64
, 2+2 }, // 2*psllq + split.
635 { ISD::SRL
, MVT::v16i16
, 2+2 }, // 2*psrlw + split.
636 { ISD::SRL
, MVT::v8i32
, 2+2 }, // 2*psrld + split.
637 { ISD::SRL
, MVT::v4i64
, 2+2 }, // 2*psrlq + split.
639 { ISD::SRA
, MVT::v16i16
, 2+2 }, // 2*psraw + split.
640 { ISD::SRA
, MVT::v8i32
, 2+2 }, // 2*psrad + split.
641 { ISD::SRA
, MVT::v2i64
, 4 }, // 2*psrad + shuffle.
642 { ISD::SRA
, MVT::v4i64
, 8+2 }, // 2*(2*psrad + shuffle) + split.
646 ((Op2Info
== TargetTransformInfo::OK_UniformConstantValue
) ||
647 (Op2Info
== TargetTransformInfo::OK_UniformValue
))) {
649 // Handle AVX2 uniform v4i64 ISD::SRA, it's not worth a table.
650 if (ISD
== ISD::SRA
&& LT
.second
== MVT::v4i64
&& ST
->hasAVX2())
651 return LT
.first
* 4; // 2*psrad + shuffle.
653 if (const auto *Entry
=
654 CostTableLookup(SSE2UniformShiftCostTable
, ISD
, LT
.second
))
655 return LT
.first
* Entry
->Cost
;
658 if (ISD
== ISD::SHL
&&
659 Op2Info
== TargetTransformInfo::OK_NonUniformConstantValue
) {
661 // Vector shift left by non uniform constant can be lowered
662 // into vector multiply.
663 if (((VT
== MVT::v8i16
|| VT
== MVT::v4i32
) && ST
->hasSSE2()) ||
664 ((VT
== MVT::v16i16
|| VT
== MVT::v8i32
) && ST
->hasAVX()))
668 static const CostTblEntry AVX2CostTable
[] = {
669 { ISD::SHL
, MVT::v32i8
, 11 }, // vpblendvb sequence.
670 { ISD::SHL
, MVT::v16i16
, 10 }, // extend/vpsrlvd/pack sequence.
672 { ISD::SRL
, MVT::v32i8
, 11 }, // vpblendvb sequence.
673 { ISD::SRL
, MVT::v16i16
, 10 }, // extend/vpsrlvd/pack sequence.
675 { ISD::SRA
, MVT::v32i8
, 24 }, // vpblendvb sequence.
676 { ISD::SRA
, MVT::v16i16
, 10 }, // extend/vpsravd/pack sequence.
677 { ISD::SRA
, MVT::v2i64
, 4 }, // srl/xor/sub sequence.
678 { ISD::SRA
, MVT::v4i64
, 4 }, // srl/xor/sub sequence.
680 { ISD::SUB
, MVT::v32i8
, 1 }, // psubb
681 { ISD::ADD
, MVT::v32i8
, 1 }, // paddb
682 { ISD::SUB
, MVT::v16i16
, 1 }, // psubw
683 { ISD::ADD
, MVT::v16i16
, 1 }, // paddw
684 { ISD::SUB
, MVT::v8i32
, 1 }, // psubd
685 { ISD::ADD
, MVT::v8i32
, 1 }, // paddd
686 { ISD::SUB
, MVT::v4i64
, 1 }, // psubq
687 { ISD::ADD
, MVT::v4i64
, 1 }, // paddq
689 { ISD::MUL
, MVT::v32i8
, 17 }, // extend/pmullw/trunc sequence.
690 { ISD::MUL
, MVT::v16i8
, 7 }, // extend/pmullw/trunc sequence.
691 { ISD::MUL
, MVT::v16i16
, 1 }, // pmullw
692 { ISD::MUL
, MVT::v8i32
, 2 }, // pmulld (Haswell from agner.org)
693 { ISD::MUL
, MVT::v4i64
, 8 }, // 3*pmuludq/3*shift/2*add
695 { ISD::FADD
, MVT::v4f64
, 1 }, // Haswell from http://www.agner.org/
696 { ISD::FADD
, MVT::v8f32
, 1 }, // Haswell from http://www.agner.org/
697 { ISD::FSUB
, MVT::v4f64
, 1 }, // Haswell from http://www.agner.org/
698 { ISD::FSUB
, MVT::v8f32
, 1 }, // Haswell from http://www.agner.org/
699 { ISD::FMUL
, MVT::v4f64
, 1 }, // Haswell from http://www.agner.org/
700 { ISD::FMUL
, MVT::v8f32
, 1 }, // Haswell from http://www.agner.org/
702 { ISD::FDIV
, MVT::f32
, 7 }, // Haswell from http://www.agner.org/
703 { ISD::FDIV
, MVT::v4f32
, 7 }, // Haswell from http://www.agner.org/
704 { ISD::FDIV
, MVT::v8f32
, 14 }, // Haswell from http://www.agner.org/
705 { ISD::FDIV
, MVT::f64
, 14 }, // Haswell from http://www.agner.org/
706 { ISD::FDIV
, MVT::v2f64
, 14 }, // Haswell from http://www.agner.org/
707 { ISD::FDIV
, MVT::v4f64
, 28 }, // Haswell from http://www.agner.org/
710 // Look for AVX2 lowering tricks for custom cases.
712 if (const auto *Entry
= CostTableLookup(AVX2CostTable
, ISD
, LT
.second
))
713 return LT
.first
* Entry
->Cost
;
715 static const CostTblEntry AVX1CostTable
[] = {
716 // We don't have to scalarize unsupported ops. We can issue two half-sized
717 // operations and we only need to extract the upper YMM half.
718 // Two ops + 1 extract + 1 insert = 4.
719 { ISD::MUL
, MVT::v16i16
, 4 },
720 { ISD::MUL
, MVT::v8i32
, 4 },
721 { ISD::SUB
, MVT::v32i8
, 4 },
722 { ISD::ADD
, MVT::v32i8
, 4 },
723 { ISD::SUB
, MVT::v16i16
, 4 },
724 { ISD::ADD
, MVT::v16i16
, 4 },
725 { ISD::SUB
, MVT::v8i32
, 4 },
726 { ISD::ADD
, MVT::v8i32
, 4 },
727 { ISD::SUB
, MVT::v4i64
, 4 },
728 { ISD::ADD
, MVT::v4i64
, 4 },
730 // A v4i64 multiply is custom lowered as two split v2i64 vectors that then
731 // are lowered as a series of long multiplies(3), shifts(3) and adds(2)
732 // Because we believe v4i64 to be a legal type, we must also include the
733 // extract+insert in the cost table. Therefore, the cost here is 18
735 { ISD::MUL
, MVT::v4i64
, 18 },
737 { ISD::MUL
, MVT::v32i8
, 26 }, // extend/pmullw/trunc sequence.
739 { ISD::FDIV
, MVT::f32
, 14 }, // SNB from http://www.agner.org/
740 { ISD::FDIV
, MVT::v4f32
, 14 }, // SNB from http://www.agner.org/
741 { ISD::FDIV
, MVT::v8f32
, 28 }, // SNB from http://www.agner.org/
742 { ISD::FDIV
, MVT::f64
, 22 }, // SNB from http://www.agner.org/
743 { ISD::FDIV
, MVT::v2f64
, 22 }, // SNB from http://www.agner.org/
744 { ISD::FDIV
, MVT::v4f64
, 44 }, // SNB from http://www.agner.org/
748 if (const auto *Entry
= CostTableLookup(AVX1CostTable
, ISD
, LT
.second
))
749 return LT
.first
* Entry
->Cost
;
751 static const CostTblEntry SSE42CostTable
[] = {
752 { ISD::FADD
, MVT::f64
, 1 }, // Nehalem from http://www.agner.org/
753 { ISD::FADD
, MVT::f32
, 1 }, // Nehalem from http://www.agner.org/
754 { ISD::FADD
, MVT::v2f64
, 1 }, // Nehalem from http://www.agner.org/
755 { ISD::FADD
, MVT::v4f32
, 1 }, // Nehalem from http://www.agner.org/
757 { ISD::FSUB
, MVT::f64
, 1 }, // Nehalem from http://www.agner.org/
758 { ISD::FSUB
, MVT::f32
, 1 }, // Nehalem from http://www.agner.org/
759 { ISD::FSUB
, MVT::v2f64
, 1 }, // Nehalem from http://www.agner.org/
760 { ISD::FSUB
, MVT::v4f32
, 1 }, // Nehalem from http://www.agner.org/
762 { ISD::FMUL
, MVT::f64
, 1 }, // Nehalem from http://www.agner.org/
763 { ISD::FMUL
, MVT::f32
, 1 }, // Nehalem from http://www.agner.org/
764 { ISD::FMUL
, MVT::v2f64
, 1 }, // Nehalem from http://www.agner.org/
765 { ISD::FMUL
, MVT::v4f32
, 1 }, // Nehalem from http://www.agner.org/
767 { ISD::FDIV
, MVT::f32
, 14 }, // Nehalem from http://www.agner.org/
768 { ISD::FDIV
, MVT::v4f32
, 14 }, // Nehalem from http://www.agner.org/
769 { ISD::FDIV
, MVT::f64
, 22 }, // Nehalem from http://www.agner.org/
770 { ISD::FDIV
, MVT::v2f64
, 22 }, // Nehalem from http://www.agner.org/
774 if (const auto *Entry
= CostTableLookup(SSE42CostTable
, ISD
, LT
.second
))
775 return LT
.first
* Entry
->Cost
;
777 static const CostTblEntry SSE41CostTable
[] = {
778 { ISD::SHL
, MVT::v16i8
, 11 }, // pblendvb sequence.
779 { ISD::SHL
, MVT::v32i8
, 2*11+2 }, // pblendvb sequence + split.
780 { ISD::SHL
, MVT::v8i16
, 14 }, // pblendvb sequence.
781 { ISD::SHL
, MVT::v16i16
, 2*14+2 }, // pblendvb sequence + split.
782 { ISD::SHL
, MVT::v4i32
, 4 }, // pslld/paddd/cvttps2dq/pmulld
783 { ISD::SHL
, MVT::v8i32
, 2*4+2 }, // pslld/paddd/cvttps2dq/pmulld + split
785 { ISD::SRL
, MVT::v16i8
, 12 }, // pblendvb sequence.
786 { ISD::SRL
, MVT::v32i8
, 2*12+2 }, // pblendvb sequence + split.
787 { ISD::SRL
, MVT::v8i16
, 14 }, // pblendvb sequence.
788 { ISD::SRL
, MVT::v16i16
, 2*14+2 }, // pblendvb sequence + split.
789 { ISD::SRL
, MVT::v4i32
, 11 }, // Shift each lane + blend.
790 { ISD::SRL
, MVT::v8i32
, 2*11+2 }, // Shift each lane + blend + split.
792 { ISD::SRA
, MVT::v16i8
, 24 }, // pblendvb sequence.
793 { ISD::SRA
, MVT::v32i8
, 2*24+2 }, // pblendvb sequence + split.
794 { ISD::SRA
, MVT::v8i16
, 14 }, // pblendvb sequence.
795 { ISD::SRA
, MVT::v16i16
, 2*14+2 }, // pblendvb sequence + split.
796 { ISD::SRA
, MVT::v4i32
, 12 }, // Shift each lane + blend.
797 { ISD::SRA
, MVT::v8i32
, 2*12+2 }, // Shift each lane + blend + split.
799 { ISD::MUL
, MVT::v4i32
, 2 } // pmulld (Nehalem from agner.org)
803 if (const auto *Entry
= CostTableLookup(SSE41CostTable
, ISD
, LT
.second
))
804 return LT
.first
* Entry
->Cost
;
806 static const CostTblEntry SSE2CostTable
[] = {
807 // We don't correctly identify costs of casts because they are marked as
809 { ISD::SHL
, MVT::v16i8
, 26 }, // cmpgtb sequence.
810 { ISD::SHL
, MVT::v8i16
, 32 }, // cmpgtb sequence.
811 { ISD::SHL
, MVT::v4i32
, 2*5 }, // We optimized this using mul.
812 { ISD::SHL
, MVT::v2i64
, 4 }, // splat+shuffle sequence.
813 { ISD::SHL
, MVT::v4i64
, 2*4+2 }, // splat+shuffle sequence + split.
815 { ISD::SRL
, MVT::v16i8
, 26 }, // cmpgtb sequence.
816 { ISD::SRL
, MVT::v8i16
, 32 }, // cmpgtb sequence.
817 { ISD::SRL
, MVT::v4i32
, 16 }, // Shift each lane + blend.
818 { ISD::SRL
, MVT::v2i64
, 4 }, // splat+shuffle sequence.
819 { ISD::SRL
, MVT::v4i64
, 2*4+2 }, // splat+shuffle sequence + split.
821 { ISD::SRA
, MVT::v16i8
, 54 }, // unpacked cmpgtb sequence.
822 { ISD::SRA
, MVT::v8i16
, 32 }, // cmpgtb sequence.
823 { ISD::SRA
, MVT::v4i32
, 16 }, // Shift each lane + blend.
824 { ISD::SRA
, MVT::v2i64
, 12 }, // srl/xor/sub sequence.
825 { ISD::SRA
, MVT::v4i64
, 2*12+2 }, // srl/xor/sub sequence+split.
827 { ISD::MUL
, MVT::v16i8
, 12 }, // extend/pmullw/trunc sequence.
828 { ISD::MUL
, MVT::v8i16
, 1 }, // pmullw
829 { ISD::MUL
, MVT::v4i32
, 6 }, // 3*pmuludq/4*shuffle
830 { ISD::MUL
, MVT::v2i64
, 8 }, // 3*pmuludq/3*shift/2*add
832 { ISD::FDIV
, MVT::f32
, 23 }, // Pentium IV from http://www.agner.org/
833 { ISD::FDIV
, MVT::v4f32
, 39 }, // Pentium IV from http://www.agner.org/
834 { ISD::FDIV
, MVT::f64
, 38 }, // Pentium IV from http://www.agner.org/
835 { ISD::FDIV
, MVT::v2f64
, 69 }, // Pentium IV from http://www.agner.org/
837 { ISD::FADD
, MVT::f32
, 2 }, // Pentium IV from http://www.agner.org/
838 { ISD::FADD
, MVT::f64
, 2 }, // Pentium IV from http://www.agner.org/
840 { ISD::FSUB
, MVT::f32
, 2 }, // Pentium IV from http://www.agner.org/
841 { ISD::FSUB
, MVT::f64
, 2 }, // Pentium IV from http://www.agner.org/
845 if (const auto *Entry
= CostTableLookup(SSE2CostTable
, ISD
, LT
.second
))
846 return LT
.first
* Entry
->Cost
;
848 static const CostTblEntry SSE1CostTable
[] = {
849 { ISD::FDIV
, MVT::f32
, 17 }, // Pentium III from http://www.agner.org/
850 { ISD::FDIV
, MVT::v4f32
, 34 }, // Pentium III from http://www.agner.org/
852 { ISD::FADD
, MVT::f32
, 1 }, // Pentium III from http://www.agner.org/
853 { ISD::FADD
, MVT::v4f32
, 2 }, // Pentium III from http://www.agner.org/
855 { ISD::FSUB
, MVT::f32
, 1 }, // Pentium III from http://www.agner.org/
856 { ISD::FSUB
, MVT::v4f32
, 2 }, // Pentium III from http://www.agner.org/
858 { ISD::ADD
, MVT::i8
, 1 }, // Pentium III from http://www.agner.org/
859 { ISD::ADD
, MVT::i16
, 1 }, // Pentium III from http://www.agner.org/
860 { ISD::ADD
, MVT::i32
, 1 }, // Pentium III from http://www.agner.org/
862 { ISD::SUB
, MVT::i8
, 1 }, // Pentium III from http://www.agner.org/
863 { ISD::SUB
, MVT::i16
, 1 }, // Pentium III from http://www.agner.org/
864 { ISD::SUB
, MVT::i32
, 1 }, // Pentium III from http://www.agner.org/
868 if (const auto *Entry
= CostTableLookup(SSE1CostTable
, ISD
, LT
.second
))
869 return LT
.first
* Entry
->Cost
;
871 // It is not a good idea to vectorize division. We have to scalarize it and
872 // in the process we will often end up having to spilling regular
873 // registers. The overhead of division is going to dominate most kernels
874 // anyways so try hard to prevent vectorization of division - it is
875 // generally a bad idea. Assume somewhat arbitrarily that we have to be able
876 // to hide "20 cycles" for each lane.
877 if (LT
.second
.isVector() && (ISD
== ISD::SDIV
|| ISD
== ISD::SREM
||
878 ISD
== ISD::UDIV
|| ISD
== ISD::UREM
)) {
879 int ScalarCost
= getArithmeticInstrCost(
880 Opcode
, Ty
->getScalarType(), Op1Info
, Op2Info
,
881 TargetTransformInfo::OP_None
, TargetTransformInfo::OP_None
);
882 return 20 * LT
.first
* LT
.second
.getVectorNumElements() * ScalarCost
;
885 // Fallback to the default implementation.
886 return BaseT::getArithmeticInstrCost(Opcode
, Ty
, Op1Info
, Op2Info
);
889 int X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind
, Type
*Tp
, int Index
,
891 // 64-bit packed float vectors (v2f32) are widened to type v4f32.
892 // 64-bit packed integer vectors (v2i32) are widened to type v4i32.
893 std::pair
<int, MVT
> LT
= TLI
->getTypeLegalizationCost(DL
, Tp
);
895 // Treat Transpose as 2-op shuffles - there's no difference in lowering.
896 if (Kind
== TTI::SK_Transpose
)
897 Kind
= TTI::SK_PermuteTwoSrc
;
899 // For Broadcasts we are splatting the first element from the first input
900 // register, so only need to reference that input and all the output
901 // registers are the same.
902 if (Kind
== TTI::SK_Broadcast
)
905 // Subvector extractions are free if they start at the beginning of a
906 // vector and cheap if the subvectors are aligned.
907 if (Kind
== TTI::SK_ExtractSubvector
&& LT
.second
.isVector()) {
908 int NumElts
= LT
.second
.getVectorNumElements();
909 if ((Index
% NumElts
) == 0)
911 std::pair
<int, MVT
> SubLT
= TLI
->getTypeLegalizationCost(DL
, SubTp
);
912 if (SubLT
.second
.isVector()) {
913 int NumSubElts
= SubLT
.second
.getVectorNumElements();
914 if ((Index
% NumSubElts
) == 0 && (NumElts
% NumSubElts
) == 0)
916 // Handle some cases for widening legalization. For now we only handle
917 // cases where the original subvector was naturally aligned and evenly
918 // fit in its legalized subvector type.
919 // FIXME: Remove some of the alignment restrictions.
920 // FIXME: We can use permq for 64-bit or larger extracts from 256-bit
922 int OrigSubElts
= SubTp
->getVectorNumElements();
923 if (ExperimentalVectorWideningLegalization
&&
924 NumSubElts
> OrigSubElts
&&
925 (Index
% OrigSubElts
) == 0 && (NumSubElts
% OrigSubElts
) == 0 &&
926 LT
.second
.getVectorElementType() ==
927 SubLT
.second
.getVectorElementType() &&
928 LT
.second
.getVectorElementType().getSizeInBits() ==
929 Tp
->getVectorElementType()->getPrimitiveSizeInBits()) {
930 assert(NumElts
>= NumSubElts
&& NumElts
> OrigSubElts
&&
931 "Unexpected number of elements!");
932 Type
*VecTy
= VectorType::get(Tp
->getVectorElementType(),
933 LT
.second
.getVectorNumElements());
934 Type
*SubTy
= VectorType::get(Tp
->getVectorElementType(),
935 SubLT
.second
.getVectorNumElements());
936 int ExtractIndex
= alignDown((Index
% NumElts
), NumSubElts
);
937 int ExtractCost
= getShuffleCost(TTI::SK_ExtractSubvector
, VecTy
,
938 ExtractIndex
, SubTy
);
940 // If the original size is 32-bits or more, we can use pshufd. Otherwise
941 // if we have SSSE3 we can use pshufb.
942 if (SubTp
->getPrimitiveSizeInBits() >= 32 || ST
->hasSSSE3())
943 return ExtractCost
+ 1; // pshufd or pshufb
945 assert(SubTp
->getPrimitiveSizeInBits() == 16 &&
946 "Unexpected vector size");
948 return ExtractCost
+ 2; // worst case pshufhw + pshufd
953 // We are going to permute multiple sources and the result will be in multiple
954 // destinations. Providing an accurate cost only for splits where the element
955 // type remains the same.
956 if (Kind
== TTI::SK_PermuteSingleSrc
&& LT
.first
!= 1) {
957 MVT LegalVT
= LT
.second
;
958 if (LegalVT
.isVector() &&
959 LegalVT
.getVectorElementType().getSizeInBits() ==
960 Tp
->getVectorElementType()->getPrimitiveSizeInBits() &&
961 LegalVT
.getVectorNumElements() < Tp
->getVectorNumElements()) {
963 unsigned VecTySize
= DL
.getTypeStoreSize(Tp
);
964 unsigned LegalVTSize
= LegalVT
.getStoreSize();
965 // Number of source vectors after legalization:
966 unsigned NumOfSrcs
= (VecTySize
+ LegalVTSize
- 1) / LegalVTSize
;
967 // Number of destination vectors after legalization:
968 unsigned NumOfDests
= LT
.first
;
970 Type
*SingleOpTy
= VectorType::get(Tp
->getVectorElementType(),
971 LegalVT
.getVectorNumElements());
973 unsigned NumOfShuffles
= (NumOfSrcs
- 1) * NumOfDests
;
974 return NumOfShuffles
*
975 getShuffleCost(TTI::SK_PermuteTwoSrc
, SingleOpTy
, 0, nullptr);
978 return BaseT::getShuffleCost(Kind
, Tp
, Index
, SubTp
);
981 // For 2-input shuffles, we must account for splitting the 2 inputs into many.
982 if (Kind
== TTI::SK_PermuteTwoSrc
&& LT
.first
!= 1) {
983 // We assume that source and destination have the same vector type.
984 int NumOfDests
= LT
.first
;
985 int NumOfShufflesPerDest
= LT
.first
* 2 - 1;
986 LT
.first
= NumOfDests
* NumOfShufflesPerDest
;
989 static const CostTblEntry AVX512VBMIShuffleTbl
[] = {
990 {TTI::SK_Reverse
, MVT::v64i8
, 1}, // vpermb
991 {TTI::SK_Reverse
, MVT::v32i8
, 1}, // vpermb
993 {TTI::SK_PermuteSingleSrc
, MVT::v64i8
, 1}, // vpermb
994 {TTI::SK_PermuteSingleSrc
, MVT::v32i8
, 1}, // vpermb
996 {TTI::SK_PermuteTwoSrc
, MVT::v64i8
, 1}, // vpermt2b
997 {TTI::SK_PermuteTwoSrc
, MVT::v32i8
, 1}, // vpermt2b
998 {TTI::SK_PermuteTwoSrc
, MVT::v16i8
, 1} // vpermt2b
1002 if (const auto *Entry
=
1003 CostTableLookup(AVX512VBMIShuffleTbl
, Kind
, LT
.second
))
1004 return LT
.first
* Entry
->Cost
;
1006 static const CostTblEntry AVX512BWShuffleTbl
[] = {
1007 {TTI::SK_Broadcast
, MVT::v32i16
, 1}, // vpbroadcastw
1008 {TTI::SK_Broadcast
, MVT::v64i8
, 1}, // vpbroadcastb
1010 {TTI::SK_Reverse
, MVT::v32i16
, 1}, // vpermw
1011 {TTI::SK_Reverse
, MVT::v16i16
, 1}, // vpermw
1012 {TTI::SK_Reverse
, MVT::v64i8
, 2}, // pshufb + vshufi64x2
1014 {TTI::SK_PermuteSingleSrc
, MVT::v32i16
, 1}, // vpermw
1015 {TTI::SK_PermuteSingleSrc
, MVT::v16i16
, 1}, // vpermw
1016 {TTI::SK_PermuteSingleSrc
, MVT::v8i16
, 1}, // vpermw
1017 {TTI::SK_PermuteSingleSrc
, MVT::v64i8
, 8}, // extend to v32i16
1018 {TTI::SK_PermuteSingleSrc
, MVT::v32i8
, 3}, // vpermw + zext/trunc
1020 {TTI::SK_PermuteTwoSrc
, MVT::v32i16
, 1}, // vpermt2w
1021 {TTI::SK_PermuteTwoSrc
, MVT::v16i16
, 1}, // vpermt2w
1022 {TTI::SK_PermuteTwoSrc
, MVT::v8i16
, 1}, // vpermt2w
1023 {TTI::SK_PermuteTwoSrc
, MVT::v32i8
, 3}, // zext + vpermt2w + trunc
1024 {TTI::SK_PermuteTwoSrc
, MVT::v64i8
, 19}, // 6 * v32i8 + 1
1025 {TTI::SK_PermuteTwoSrc
, MVT::v16i8
, 3} // zext + vpermt2w + trunc
1029 if (const auto *Entry
=
1030 CostTableLookup(AVX512BWShuffleTbl
, Kind
, LT
.second
))
1031 return LT
.first
* Entry
->Cost
;
1033 static const CostTblEntry AVX512ShuffleTbl
[] = {
1034 {TTI::SK_Broadcast
, MVT::v8f64
, 1}, // vbroadcastpd
1035 {TTI::SK_Broadcast
, MVT::v16f32
, 1}, // vbroadcastps
1036 {TTI::SK_Broadcast
, MVT::v8i64
, 1}, // vpbroadcastq
1037 {TTI::SK_Broadcast
, MVT::v16i32
, 1}, // vpbroadcastd
1039 {TTI::SK_Reverse
, MVT::v8f64
, 1}, // vpermpd
1040 {TTI::SK_Reverse
, MVT::v16f32
, 1}, // vpermps
1041 {TTI::SK_Reverse
, MVT::v8i64
, 1}, // vpermq
1042 {TTI::SK_Reverse
, MVT::v16i32
, 1}, // vpermd
1044 {TTI::SK_PermuteSingleSrc
, MVT::v8f64
, 1}, // vpermpd
1045 {TTI::SK_PermuteSingleSrc
, MVT::v4f64
, 1}, // vpermpd
1046 {TTI::SK_PermuteSingleSrc
, MVT::v2f64
, 1}, // vpermpd
1047 {TTI::SK_PermuteSingleSrc
, MVT::v16f32
, 1}, // vpermps
1048 {TTI::SK_PermuteSingleSrc
, MVT::v8f32
, 1}, // vpermps
1049 {TTI::SK_PermuteSingleSrc
, MVT::v4f32
, 1}, // vpermps
1050 {TTI::SK_PermuteSingleSrc
, MVT::v8i64
, 1}, // vpermq
1051 {TTI::SK_PermuteSingleSrc
, MVT::v4i64
, 1}, // vpermq
1052 {TTI::SK_PermuteSingleSrc
, MVT::v2i64
, 1}, // vpermq
1053 {TTI::SK_PermuteSingleSrc
, MVT::v16i32
, 1}, // vpermd
1054 {TTI::SK_PermuteSingleSrc
, MVT::v8i32
, 1}, // vpermd
1055 {TTI::SK_PermuteSingleSrc
, MVT::v4i32
, 1}, // vpermd
1056 {TTI::SK_PermuteSingleSrc
, MVT::v16i8
, 1}, // pshufb
1058 {TTI::SK_PermuteTwoSrc
, MVT::v8f64
, 1}, // vpermt2pd
1059 {TTI::SK_PermuteTwoSrc
, MVT::v16f32
, 1}, // vpermt2ps
1060 {TTI::SK_PermuteTwoSrc
, MVT::v8i64
, 1}, // vpermt2q
1061 {TTI::SK_PermuteTwoSrc
, MVT::v16i32
, 1}, // vpermt2d
1062 {TTI::SK_PermuteTwoSrc
, MVT::v4f64
, 1}, // vpermt2pd
1063 {TTI::SK_PermuteTwoSrc
, MVT::v8f32
, 1}, // vpermt2ps
1064 {TTI::SK_PermuteTwoSrc
, MVT::v4i64
, 1}, // vpermt2q
1065 {TTI::SK_PermuteTwoSrc
, MVT::v8i32
, 1}, // vpermt2d
1066 {TTI::SK_PermuteTwoSrc
, MVT::v2f64
, 1}, // vpermt2pd
1067 {TTI::SK_PermuteTwoSrc
, MVT::v4f32
, 1}, // vpermt2ps
1068 {TTI::SK_PermuteTwoSrc
, MVT::v2i64
, 1}, // vpermt2q
1069 {TTI::SK_PermuteTwoSrc
, MVT::v4i32
, 1} // vpermt2d
1072 if (ST
->hasAVX512())
1073 if (const auto *Entry
= CostTableLookup(AVX512ShuffleTbl
, Kind
, LT
.second
))
1074 return LT
.first
* Entry
->Cost
;
1076 static const CostTblEntry AVX2ShuffleTbl
[] = {
1077 {TTI::SK_Broadcast
, MVT::v4f64
, 1}, // vbroadcastpd
1078 {TTI::SK_Broadcast
, MVT::v8f32
, 1}, // vbroadcastps
1079 {TTI::SK_Broadcast
, MVT::v4i64
, 1}, // vpbroadcastq
1080 {TTI::SK_Broadcast
, MVT::v8i32
, 1}, // vpbroadcastd
1081 {TTI::SK_Broadcast
, MVT::v16i16
, 1}, // vpbroadcastw
1082 {TTI::SK_Broadcast
, MVT::v32i8
, 1}, // vpbroadcastb
1084 {TTI::SK_Reverse
, MVT::v4f64
, 1}, // vpermpd
1085 {TTI::SK_Reverse
, MVT::v8f32
, 1}, // vpermps
1086 {TTI::SK_Reverse
, MVT::v4i64
, 1}, // vpermq
1087 {TTI::SK_Reverse
, MVT::v8i32
, 1}, // vpermd
1088 {TTI::SK_Reverse
, MVT::v16i16
, 2}, // vperm2i128 + pshufb
1089 {TTI::SK_Reverse
, MVT::v32i8
, 2}, // vperm2i128 + pshufb
1091 {TTI::SK_Select
, MVT::v16i16
, 1}, // vpblendvb
1092 {TTI::SK_Select
, MVT::v32i8
, 1}, // vpblendvb
1094 {TTI::SK_PermuteSingleSrc
, MVT::v4f64
, 1}, // vpermpd
1095 {TTI::SK_PermuteSingleSrc
, MVT::v8f32
, 1}, // vpermps
1096 {TTI::SK_PermuteSingleSrc
, MVT::v4i64
, 1}, // vpermq
1097 {TTI::SK_PermuteSingleSrc
, MVT::v8i32
, 1}, // vpermd
1098 {TTI::SK_PermuteSingleSrc
, MVT::v16i16
, 4}, // vperm2i128 + 2*vpshufb
1100 {TTI::SK_PermuteSingleSrc
, MVT::v32i8
, 4}, // vperm2i128 + 2*vpshufb
1103 {TTI::SK_PermuteTwoSrc
, MVT::v4f64
, 3}, // 2*vpermpd + vblendpd
1104 {TTI::SK_PermuteTwoSrc
, MVT::v8f32
, 3}, // 2*vpermps + vblendps
1105 {TTI::SK_PermuteTwoSrc
, MVT::v4i64
, 3}, // 2*vpermq + vpblendd
1106 {TTI::SK_PermuteTwoSrc
, MVT::v8i32
, 3}, // 2*vpermd + vpblendd
1107 {TTI::SK_PermuteTwoSrc
, MVT::v16i16
, 7}, // 2*vperm2i128 + 4*vpshufb
1109 {TTI::SK_PermuteTwoSrc
, MVT::v32i8
, 7}, // 2*vperm2i128 + 4*vpshufb
1114 if (const auto *Entry
= CostTableLookup(AVX2ShuffleTbl
, Kind
, LT
.second
))
1115 return LT
.first
* Entry
->Cost
;
1117 static const CostTblEntry XOPShuffleTbl
[] = {
1118 {TTI::SK_PermuteSingleSrc
, MVT::v4f64
, 2}, // vperm2f128 + vpermil2pd
1119 {TTI::SK_PermuteSingleSrc
, MVT::v8f32
, 2}, // vperm2f128 + vpermil2ps
1120 {TTI::SK_PermuteSingleSrc
, MVT::v4i64
, 2}, // vperm2f128 + vpermil2pd
1121 {TTI::SK_PermuteSingleSrc
, MVT::v8i32
, 2}, // vperm2f128 + vpermil2ps
1122 {TTI::SK_PermuteSingleSrc
, MVT::v16i16
, 4}, // vextractf128 + 2*vpperm
1124 {TTI::SK_PermuteSingleSrc
, MVT::v32i8
, 4}, // vextractf128 + 2*vpperm
1127 {TTI::SK_PermuteTwoSrc
, MVT::v16i16
, 9}, // 2*vextractf128 + 6*vpperm
1129 {TTI::SK_PermuteTwoSrc
, MVT::v8i16
, 1}, // vpperm
1130 {TTI::SK_PermuteTwoSrc
, MVT::v32i8
, 9}, // 2*vextractf128 + 6*vpperm
1132 {TTI::SK_PermuteTwoSrc
, MVT::v16i8
, 1}, // vpperm
1136 if (const auto *Entry
= CostTableLookup(XOPShuffleTbl
, Kind
, LT
.second
))
1137 return LT
.first
* Entry
->Cost
;
1139 static const CostTblEntry AVX1ShuffleTbl
[] = {
1140 {TTI::SK_Broadcast
, MVT::v4f64
, 2}, // vperm2f128 + vpermilpd
1141 {TTI::SK_Broadcast
, MVT::v8f32
, 2}, // vperm2f128 + vpermilps
1142 {TTI::SK_Broadcast
, MVT::v4i64
, 2}, // vperm2f128 + vpermilpd
1143 {TTI::SK_Broadcast
, MVT::v8i32
, 2}, // vperm2f128 + vpermilps
1144 {TTI::SK_Broadcast
, MVT::v16i16
, 3}, // vpshuflw + vpshufd + vinsertf128
1145 {TTI::SK_Broadcast
, MVT::v32i8
, 2}, // vpshufb + vinsertf128
1147 {TTI::SK_Reverse
, MVT::v4f64
, 2}, // vperm2f128 + vpermilpd
1148 {TTI::SK_Reverse
, MVT::v8f32
, 2}, // vperm2f128 + vpermilps
1149 {TTI::SK_Reverse
, MVT::v4i64
, 2}, // vperm2f128 + vpermilpd
1150 {TTI::SK_Reverse
, MVT::v8i32
, 2}, // vperm2f128 + vpermilps
1151 {TTI::SK_Reverse
, MVT::v16i16
, 4}, // vextractf128 + 2*pshufb
1153 {TTI::SK_Reverse
, MVT::v32i8
, 4}, // vextractf128 + 2*pshufb
1156 {TTI::SK_Select
, MVT::v4i64
, 1}, // vblendpd
1157 {TTI::SK_Select
, MVT::v4f64
, 1}, // vblendpd
1158 {TTI::SK_Select
, MVT::v8i32
, 1}, // vblendps
1159 {TTI::SK_Select
, MVT::v8f32
, 1}, // vblendps
1160 {TTI::SK_Select
, MVT::v16i16
, 3}, // vpand + vpandn + vpor
1161 {TTI::SK_Select
, MVT::v32i8
, 3}, // vpand + vpandn + vpor
1163 {TTI::SK_PermuteSingleSrc
, MVT::v4f64
, 2}, // vperm2f128 + vshufpd
1164 {TTI::SK_PermuteSingleSrc
, MVT::v4i64
, 2}, // vperm2f128 + vshufpd
1165 {TTI::SK_PermuteSingleSrc
, MVT::v8f32
, 4}, // 2*vperm2f128 + 2*vshufps
1166 {TTI::SK_PermuteSingleSrc
, MVT::v8i32
, 4}, // 2*vperm2f128 + 2*vshufps
1167 {TTI::SK_PermuteSingleSrc
, MVT::v16i16
, 8}, // vextractf128 + 4*pshufb
1168 // + 2*por + vinsertf128
1169 {TTI::SK_PermuteSingleSrc
, MVT::v32i8
, 8}, // vextractf128 + 4*pshufb
1170 // + 2*por + vinsertf128
1172 {TTI::SK_PermuteTwoSrc
, MVT::v4f64
, 3}, // 2*vperm2f128 + vshufpd
1173 {TTI::SK_PermuteTwoSrc
, MVT::v4i64
, 3}, // 2*vperm2f128 + vshufpd
1174 {TTI::SK_PermuteTwoSrc
, MVT::v8f32
, 4}, // 2*vperm2f128 + 2*vshufps
1175 {TTI::SK_PermuteTwoSrc
, MVT::v8i32
, 4}, // 2*vperm2f128 + 2*vshufps
1176 {TTI::SK_PermuteTwoSrc
, MVT::v16i16
, 15}, // 2*vextractf128 + 8*pshufb
1177 // + 4*por + vinsertf128
1178 {TTI::SK_PermuteTwoSrc
, MVT::v32i8
, 15}, // 2*vextractf128 + 8*pshufb
1179 // + 4*por + vinsertf128
1183 if (const auto *Entry
= CostTableLookup(AVX1ShuffleTbl
, Kind
, LT
.second
))
1184 return LT
.first
* Entry
->Cost
;
1186 static const CostTblEntry SSE41ShuffleTbl
[] = {
1187 {TTI::SK_Select
, MVT::v2i64
, 1}, // pblendw
1188 {TTI::SK_Select
, MVT::v2f64
, 1}, // movsd
1189 {TTI::SK_Select
, MVT::v4i32
, 1}, // pblendw
1190 {TTI::SK_Select
, MVT::v4f32
, 1}, // blendps
1191 {TTI::SK_Select
, MVT::v8i16
, 1}, // pblendw
1192 {TTI::SK_Select
, MVT::v16i8
, 1} // pblendvb
1196 if (const auto *Entry
= CostTableLookup(SSE41ShuffleTbl
, Kind
, LT
.second
))
1197 return LT
.first
* Entry
->Cost
;
1199 static const CostTblEntry SSSE3ShuffleTbl
[] = {
1200 {TTI::SK_Broadcast
, MVT::v8i16
, 1}, // pshufb
1201 {TTI::SK_Broadcast
, MVT::v16i8
, 1}, // pshufb
1203 {TTI::SK_Reverse
, MVT::v8i16
, 1}, // pshufb
1204 {TTI::SK_Reverse
, MVT::v16i8
, 1}, // pshufb
1206 {TTI::SK_Select
, MVT::v8i16
, 3}, // 2*pshufb + por
1207 {TTI::SK_Select
, MVT::v16i8
, 3}, // 2*pshufb + por
1209 {TTI::SK_PermuteSingleSrc
, MVT::v8i16
, 1}, // pshufb
1210 {TTI::SK_PermuteSingleSrc
, MVT::v16i8
, 1}, // pshufb
1212 {TTI::SK_PermuteTwoSrc
, MVT::v8i16
, 3}, // 2*pshufb + por
1213 {TTI::SK_PermuteTwoSrc
, MVT::v16i8
, 3}, // 2*pshufb + por
1217 if (const auto *Entry
= CostTableLookup(SSSE3ShuffleTbl
, Kind
, LT
.second
))
1218 return LT
.first
* Entry
->Cost
;
1220 static const CostTblEntry SSE2ShuffleTbl
[] = {
1221 {TTI::SK_Broadcast
, MVT::v2f64
, 1}, // shufpd
1222 {TTI::SK_Broadcast
, MVT::v2i64
, 1}, // pshufd
1223 {TTI::SK_Broadcast
, MVT::v4i32
, 1}, // pshufd
1224 {TTI::SK_Broadcast
, MVT::v8i16
, 2}, // pshuflw + pshufd
1225 {TTI::SK_Broadcast
, MVT::v16i8
, 3}, // unpck + pshuflw + pshufd
1227 {TTI::SK_Reverse
, MVT::v2f64
, 1}, // shufpd
1228 {TTI::SK_Reverse
, MVT::v2i64
, 1}, // pshufd
1229 {TTI::SK_Reverse
, MVT::v4i32
, 1}, // pshufd
1230 {TTI::SK_Reverse
, MVT::v8i16
, 3}, // pshuflw + pshufhw + pshufd
1231 {TTI::SK_Reverse
, MVT::v16i8
, 9}, // 2*pshuflw + 2*pshufhw
1232 // + 2*pshufd + 2*unpck + packus
1234 {TTI::SK_Select
, MVT::v2i64
, 1}, // movsd
1235 {TTI::SK_Select
, MVT::v2f64
, 1}, // movsd
1236 {TTI::SK_Select
, MVT::v4i32
, 2}, // 2*shufps
1237 {TTI::SK_Select
, MVT::v8i16
, 3}, // pand + pandn + por
1238 {TTI::SK_Select
, MVT::v16i8
, 3}, // pand + pandn + por
1240 {TTI::SK_PermuteSingleSrc
, MVT::v2f64
, 1}, // shufpd
1241 {TTI::SK_PermuteSingleSrc
, MVT::v2i64
, 1}, // pshufd
1242 {TTI::SK_PermuteSingleSrc
, MVT::v4i32
, 1}, // pshufd
1243 {TTI::SK_PermuteSingleSrc
, MVT::v8i16
, 5}, // 2*pshuflw + 2*pshufhw
1245 { TTI::SK_PermuteSingleSrc
, MVT::v16i8
, 10 }, // 2*pshuflw + 2*pshufhw
1246 // + 2*pshufd + 2*unpck + 2*packus
1248 { TTI::SK_PermuteTwoSrc
, MVT::v2f64
, 1 }, // shufpd
1249 { TTI::SK_PermuteTwoSrc
, MVT::v2i64
, 1 }, // shufpd
1250 { TTI::SK_PermuteTwoSrc
, MVT::v4i32
, 2 }, // 2*{unpck,movsd,pshufd}
1251 { TTI::SK_PermuteTwoSrc
, MVT::v8i16
, 8 }, // blend+permute
1252 { TTI::SK_PermuteTwoSrc
, MVT::v16i8
, 13 }, // blend+permute
1256 if (const auto *Entry
= CostTableLookup(SSE2ShuffleTbl
, Kind
, LT
.second
))
1257 return LT
.first
* Entry
->Cost
;
1259 static const CostTblEntry SSE1ShuffleTbl
[] = {
1260 { TTI::SK_Broadcast
, MVT::v4f32
, 1 }, // shufps
1261 { TTI::SK_Reverse
, MVT::v4f32
, 1 }, // shufps
1262 { TTI::SK_Select
, MVT::v4f32
, 2 }, // 2*shufps
1263 { TTI::SK_PermuteSingleSrc
, MVT::v4f32
, 1 }, // shufps
1264 { TTI::SK_PermuteTwoSrc
, MVT::v4f32
, 2 }, // 2*shufps
1268 if (const auto *Entry
= CostTableLookup(SSE1ShuffleTbl
, Kind
, LT
.second
))
1269 return LT
.first
* Entry
->Cost
;
1271 return BaseT::getShuffleCost(Kind
, Tp
, Index
, SubTp
);
1274 int X86TTIImpl::getCastInstrCost(unsigned Opcode
, Type
*Dst
, Type
*Src
,
1275 const Instruction
*I
) {
1276 int ISD
= TLI
->InstructionOpcodeToISD(Opcode
);
1277 assert(ISD
&& "Invalid opcode");
1279 // FIXME: Need a better design of the cost table to handle non-simple types of
1280 // potential massive combinations (elem_num x src_type x dst_type).
1282 static const TypeConversionCostTblEntry AVX512BWConversionTbl
[] {
1283 { ISD::SIGN_EXTEND
, MVT::v32i16
, MVT::v32i8
, 1 },
1284 { ISD::ZERO_EXTEND
, MVT::v32i16
, MVT::v32i8
, 1 },
1286 // Mask sign extend has an instruction.
1287 { ISD::SIGN_EXTEND
, MVT::v8i16
, MVT::v8i1
, 1 },
1288 { ISD::SIGN_EXTEND
, MVT::v16i8
, MVT::v16i1
, 1 },
1289 { ISD::SIGN_EXTEND
, MVT::v16i16
, MVT::v16i1
, 1 },
1290 { ISD::SIGN_EXTEND
, MVT::v32i8
, MVT::v32i1
, 1 },
1291 { ISD::SIGN_EXTEND
, MVT::v32i16
, MVT::v32i1
, 1 },
1292 { ISD::SIGN_EXTEND
, MVT::v64i8
, MVT::v64i1
, 1 },
1294 // Mask zero extend is a load + broadcast.
1295 { ISD::ZERO_EXTEND
, MVT::v8i16
, MVT::v8i1
, 2 },
1296 { ISD::ZERO_EXTEND
, MVT::v16i8
, MVT::v16i1
, 2 },
1297 { ISD::ZERO_EXTEND
, MVT::v16i16
, MVT::v16i1
, 2 },
1298 { ISD::ZERO_EXTEND
, MVT::v32i8
, MVT::v32i1
, 2 },
1299 { ISD::ZERO_EXTEND
, MVT::v32i16
, MVT::v32i1
, 2 },
1300 { ISD::ZERO_EXTEND
, MVT::v64i8
, MVT::v64i1
, 2 },
1303 static const TypeConversionCostTblEntry AVX512DQConversionTbl
[] = {
1304 { ISD::SINT_TO_FP
, MVT::v2f32
, MVT::v2i64
, 1 },
1305 { ISD::SINT_TO_FP
, MVT::v2f64
, MVT::v2i64
, 1 },
1306 { ISD::SINT_TO_FP
, MVT::v4f32
, MVT::v4i64
, 1 },
1307 { ISD::SINT_TO_FP
, MVT::v4f64
, MVT::v4i64
, 1 },
1308 { ISD::SINT_TO_FP
, MVT::v8f32
, MVT::v8i64
, 1 },
1309 { ISD::SINT_TO_FP
, MVT::v8f64
, MVT::v8i64
, 1 },
1311 { ISD::UINT_TO_FP
, MVT::v2f32
, MVT::v2i64
, 1 },
1312 { ISD::UINT_TO_FP
, MVT::v2f64
, MVT::v2i64
, 1 },
1313 { ISD::UINT_TO_FP
, MVT::v4f32
, MVT::v4i64
, 1 },
1314 { ISD::UINT_TO_FP
, MVT::v4f64
, MVT::v4i64
, 1 },
1315 { ISD::UINT_TO_FP
, MVT::v8f32
, MVT::v8i64
, 1 },
1316 { ISD::UINT_TO_FP
, MVT::v8f64
, MVT::v8i64
, 1 },
1318 { ISD::FP_TO_SINT
, MVT::v2i64
, MVT::v2f32
, 1 },
1319 { ISD::FP_TO_SINT
, MVT::v4i64
, MVT::v4f32
, 1 },
1320 { ISD::FP_TO_SINT
, MVT::v8i64
, MVT::v8f32
, 1 },
1321 { ISD::FP_TO_SINT
, MVT::v2i64
, MVT::v2f64
, 1 },
1322 { ISD::FP_TO_SINT
, MVT::v4i64
, MVT::v4f64
, 1 },
1323 { ISD::FP_TO_SINT
, MVT::v8i64
, MVT::v8f64
, 1 },
1325 { ISD::FP_TO_UINT
, MVT::v2i64
, MVT::v2f32
, 1 },
1326 { ISD::FP_TO_UINT
, MVT::v4i64
, MVT::v4f32
, 1 },
1327 { ISD::FP_TO_UINT
, MVT::v8i64
, MVT::v8f32
, 1 },
1328 { ISD::FP_TO_UINT
, MVT::v2i64
, MVT::v2f64
, 1 },
1329 { ISD::FP_TO_UINT
, MVT::v4i64
, MVT::v4f64
, 1 },
1330 { ISD::FP_TO_UINT
, MVT::v8i64
, MVT::v8f64
, 1 },
1333 // TODO: For AVX512DQ + AVX512VL, we also have cheap casts for 128-bit and
1334 // 256-bit wide vectors.
1336 // Used with widening legalization
1337 static const TypeConversionCostTblEntry AVX512FConversionTblWide
[] = {
1338 { ISD::SIGN_EXTEND
, MVT::v8i64
, MVT::v8i8
, 1 },
1339 { ISD::ZERO_EXTEND
, MVT::v8i64
, MVT::v8i8
, 1 },
1342 static const TypeConversionCostTblEntry AVX512FConversionTbl
[] = {
1343 { ISD::FP_EXTEND
, MVT::v8f64
, MVT::v8f32
, 1 },
1344 { ISD::FP_EXTEND
, MVT::v8f64
, MVT::v16f32
, 3 },
1345 { ISD::FP_ROUND
, MVT::v8f32
, MVT::v8f64
, 1 },
1347 { ISD::TRUNCATE
, MVT::v16i8
, MVT::v16i32
, 1 },
1348 { ISD::TRUNCATE
, MVT::v16i16
, MVT::v16i32
, 1 },
1349 { ISD::TRUNCATE
, MVT::v8i16
, MVT::v8i64
, 1 },
1350 { ISD::TRUNCATE
, MVT::v8i32
, MVT::v8i64
, 1 },
1352 // v16i1 -> v16i32 - load + broadcast
1353 { ISD::SIGN_EXTEND
, MVT::v16i32
, MVT::v16i1
, 2 },
1354 { ISD::ZERO_EXTEND
, MVT::v16i32
, MVT::v16i1
, 2 },
1355 { ISD::SIGN_EXTEND
, MVT::v16i32
, MVT::v16i8
, 1 },
1356 { ISD::ZERO_EXTEND
, MVT::v16i32
, MVT::v16i8
, 1 },
1357 { ISD::SIGN_EXTEND
, MVT::v16i32
, MVT::v16i16
, 1 },
1358 { ISD::ZERO_EXTEND
, MVT::v16i32
, MVT::v16i16
, 1 },
1359 { ISD::SIGN_EXTEND
, MVT::v8i64
, MVT::v8i16
, 1 },
1360 { ISD::ZERO_EXTEND
, MVT::v8i64
, MVT::v8i16
, 1 },
1361 { ISD::SIGN_EXTEND
, MVT::v8i64
, MVT::v8i32
, 1 },
1362 { ISD::ZERO_EXTEND
, MVT::v8i64
, MVT::v8i32
, 1 },
1364 { ISD::SINT_TO_FP
, MVT::v8f64
, MVT::v8i1
, 4 },
1365 { ISD::SINT_TO_FP
, MVT::v16f32
, MVT::v16i1
, 3 },
1366 { ISD::SINT_TO_FP
, MVT::v8f64
, MVT::v8i8
, 2 },
1367 { ISD::SINT_TO_FP
, MVT::v16f32
, MVT::v16i8
, 2 },
1368 { ISD::SINT_TO_FP
, MVT::v8f64
, MVT::v8i16
, 2 },
1369 { ISD::SINT_TO_FP
, MVT::v16f32
, MVT::v16i16
, 2 },
1370 { ISD::SINT_TO_FP
, MVT::v16f32
, MVT::v16i32
, 1 },
1371 { ISD::SINT_TO_FP
, MVT::v8f64
, MVT::v8i32
, 1 },
1373 { ISD::UINT_TO_FP
, MVT::v8f64
, MVT::v8i1
, 4 },
1374 { ISD::UINT_TO_FP
, MVT::v16f32
, MVT::v16i1
, 3 },
1375 { ISD::UINT_TO_FP
, MVT::v2f64
, MVT::v2i8
, 2 },
1376 { ISD::UINT_TO_FP
, MVT::v4f64
, MVT::v4i8
, 2 },
1377 { ISD::UINT_TO_FP
, MVT::v8f32
, MVT::v8i8
, 2 },
1378 { ISD::UINT_TO_FP
, MVT::v8f64
, MVT::v8i8
, 2 },
1379 { ISD::UINT_TO_FP
, MVT::v16f32
, MVT::v16i8
, 2 },
1380 { ISD::UINT_TO_FP
, MVT::v2f64
, MVT::v2i16
, 5 },
1381 { ISD::UINT_TO_FP
, MVT::v4f64
, MVT::v4i16
, 2 },
1382 { ISD::UINT_TO_FP
, MVT::v8f32
, MVT::v8i16
, 2 },
1383 { ISD::UINT_TO_FP
, MVT::v8f64
, MVT::v8i16
, 2 },
1384 { ISD::UINT_TO_FP
, MVT::v16f32
, MVT::v16i16
, 2 },
1385 { ISD::UINT_TO_FP
, MVT::v2f32
, MVT::v2i32
, 2 },
1386 { ISD::UINT_TO_FP
, MVT::v2f64
, MVT::v2i32
, 1 },
1387 { ISD::UINT_TO_FP
, MVT::v4f32
, MVT::v4i32
, 1 },
1388 { ISD::UINT_TO_FP
, MVT::v4f64
, MVT::v4i32
, 1 },
1389 { ISD::UINT_TO_FP
, MVT::v8f32
, MVT::v8i32
, 1 },
1390 { ISD::UINT_TO_FP
, MVT::v8f64
, MVT::v8i32
, 1 },
1391 { ISD::UINT_TO_FP
, MVT::v16f32
, MVT::v16i32
, 1 },
1392 { ISD::UINT_TO_FP
, MVT::v2f32
, MVT::v2i64
, 5 },
1393 { ISD::UINT_TO_FP
, MVT::v8f32
, MVT::v8i64
, 26 },
1394 { ISD::UINT_TO_FP
, MVT::v2f64
, MVT::v2i64
, 5 },
1395 { ISD::UINT_TO_FP
, MVT::v4f64
, MVT::v4i64
, 5 },
1396 { ISD::UINT_TO_FP
, MVT::v8f64
, MVT::v8i64
, 5 },
1398 { ISD::UINT_TO_FP
, MVT::f64
, MVT::i64
, 1 },
1400 { ISD::FP_TO_UINT
, MVT::v2i32
, MVT::v2f32
, 1 },
1401 { ISD::FP_TO_UINT
, MVT::v4i32
, MVT::v4f32
, 1 },
1402 { ISD::FP_TO_UINT
, MVT::v4i32
, MVT::v4f64
, 1 },
1403 { ISD::FP_TO_UINT
, MVT::v8i32
, MVT::v8f32
, 1 },
1404 { ISD::FP_TO_UINT
, MVT::v8i16
, MVT::v8f64
, 2 },
1405 { ISD::FP_TO_UINT
, MVT::v8i8
, MVT::v8f64
, 2 },
1406 { ISD::FP_TO_UINT
, MVT::v16i32
, MVT::v16f32
, 1 },
1407 { ISD::FP_TO_UINT
, MVT::v16i16
, MVT::v16f32
, 2 },
1408 { ISD::FP_TO_UINT
, MVT::v16i8
, MVT::v16f32
, 2 },
1411 static const TypeConversionCostTblEntry AVX2ConversionTblWide
[] = {
1412 { ISD::SIGN_EXTEND
, MVT::v4i64
, MVT::v4i8
, 1 },
1413 { ISD::ZERO_EXTEND
, MVT::v4i64
, MVT::v4i8
, 1 },
1414 { ISD::SIGN_EXTEND
, MVT::v8i32
, MVT::v8i8
, 1 },
1415 { ISD::ZERO_EXTEND
, MVT::v8i32
, MVT::v8i8
, 1 },
1416 { ISD::SIGN_EXTEND
, MVT::v4i64
, MVT::v4i16
, 1 },
1417 { ISD::ZERO_EXTEND
, MVT::v4i64
, MVT::v4i16
, 1 },
1420 static const TypeConversionCostTblEntry AVX2ConversionTbl
[] = {
1421 { ISD::SIGN_EXTEND
, MVT::v4i64
, MVT::v4i1
, 3 },
1422 { ISD::ZERO_EXTEND
, MVT::v4i64
, MVT::v4i1
, 3 },
1423 { ISD::SIGN_EXTEND
, MVT::v8i32
, MVT::v8i1
, 3 },
1424 { ISD::ZERO_EXTEND
, MVT::v8i32
, MVT::v8i1
, 3 },
1425 { ISD::SIGN_EXTEND
, MVT::v4i64
, MVT::v4i8
, 3 },
1426 { ISD::ZERO_EXTEND
, MVT::v4i64
, MVT::v4i8
, 3 },
1427 { ISD::SIGN_EXTEND
, MVT::v8i32
, MVT::v8i8
, 3 },
1428 { ISD::ZERO_EXTEND
, MVT::v8i32
, MVT::v8i8
, 3 },
1429 { ISD::SIGN_EXTEND
, MVT::v16i16
, MVT::v16i8
, 1 },
1430 { ISD::ZERO_EXTEND
, MVT::v16i16
, MVT::v16i8
, 1 },
1431 { ISD::SIGN_EXTEND
, MVT::v4i64
, MVT::v4i16
, 3 },
1432 { ISD::ZERO_EXTEND
, MVT::v4i64
, MVT::v4i16
, 3 },
1433 { ISD::SIGN_EXTEND
, MVT::v8i32
, MVT::v8i16
, 1 },
1434 { ISD::ZERO_EXTEND
, MVT::v8i32
, MVT::v8i16
, 1 },
1435 { ISD::SIGN_EXTEND
, MVT::v4i64
, MVT::v4i32
, 1 },
1436 { ISD::ZERO_EXTEND
, MVT::v4i64
, MVT::v4i32
, 1 },
1438 { ISD::TRUNCATE
, MVT::v4i8
, MVT::v4i64
, 2 },
1439 { ISD::TRUNCATE
, MVT::v4i16
, MVT::v4i64
, 2 },
1440 { ISD::TRUNCATE
, MVT::v4i32
, MVT::v4i64
, 2 },
1441 { ISD::TRUNCATE
, MVT::v8i8
, MVT::v8i32
, 2 },
1442 { ISD::TRUNCATE
, MVT::v8i16
, MVT::v8i32
, 2 },
1443 { ISD::TRUNCATE
, MVT::v8i32
, MVT::v8i64
, 4 },
1445 { ISD::FP_EXTEND
, MVT::v8f64
, MVT::v8f32
, 3 },
1446 { ISD::FP_ROUND
, MVT::v8f32
, MVT::v8f64
, 3 },
1448 { ISD::UINT_TO_FP
, MVT::v8f32
, MVT::v8i32
, 8 },
1451 static const TypeConversionCostTblEntry AVXConversionTblWide
[] = {
1452 { ISD::SIGN_EXTEND
, MVT::v4i64
, MVT::v4i8
, 4 },
1453 { ISD::SIGN_EXTEND
, MVT::v8i32
, MVT::v8i8
, 4 },
1454 { ISD::SIGN_EXTEND
, MVT::v4i64
, MVT::v4i16
, 4 },
1457 static const TypeConversionCostTblEntry AVXConversionTbl
[] = {
1458 { ISD::SIGN_EXTEND
, MVT::v4i64
, MVT::v4i1
, 6 },
1459 { ISD::ZERO_EXTEND
, MVT::v4i64
, MVT::v4i1
, 4 },
1460 { ISD::SIGN_EXTEND
, MVT::v8i32
, MVT::v8i1
, 7 },
1461 { ISD::ZERO_EXTEND
, MVT::v8i32
, MVT::v8i1
, 4 },
1462 { ISD::SIGN_EXTEND
, MVT::v4i64
, MVT::v4i8
, 6 },
1463 { ISD::ZERO_EXTEND
, MVT::v4i64
, MVT::v4i8
, 4 },
1464 { ISD::SIGN_EXTEND
, MVT::v8i32
, MVT::v8i8
, 7 },
1465 { ISD::ZERO_EXTEND
, MVT::v8i32
, MVT::v8i8
, 4 },
1466 { ISD::SIGN_EXTEND
, MVT::v16i16
, MVT::v16i8
, 4 },
1467 { ISD::ZERO_EXTEND
, MVT::v16i16
, MVT::v16i8
, 4 },
1468 { ISD::SIGN_EXTEND
, MVT::v4i64
, MVT::v4i16
, 6 },
1469 { ISD::ZERO_EXTEND
, MVT::v4i64
, MVT::v4i16
, 3 },
1470 { ISD::SIGN_EXTEND
, MVT::v8i32
, MVT::v8i16
, 4 },
1471 { ISD::ZERO_EXTEND
, MVT::v8i32
, MVT::v8i16
, 4 },
1472 { ISD::SIGN_EXTEND
, MVT::v4i64
, MVT::v4i32
, 4 },
1473 { ISD::ZERO_EXTEND
, MVT::v4i64
, MVT::v4i32
, 4 },
1475 { ISD::TRUNCATE
, MVT::v16i8
, MVT::v16i16
, 4 },
1476 { ISD::TRUNCATE
, MVT::v8i8
, MVT::v8i32
, 4 },
1477 { ISD::TRUNCATE
, MVT::v8i16
, MVT::v8i32
, 5 },
1478 { ISD::TRUNCATE
, MVT::v4i8
, MVT::v4i64
, 4 },
1479 { ISD::TRUNCATE
, MVT::v4i16
, MVT::v4i64
, 4 },
1480 { ISD::TRUNCATE
, MVT::v4i32
, MVT::v4i64
, 4 },
1481 { ISD::TRUNCATE
, MVT::v8i32
, MVT::v8i64
, 9 },
1483 { ISD::SINT_TO_FP
, MVT::v4f32
, MVT::v4i1
, 3 },
1484 { ISD::SINT_TO_FP
, MVT::v4f64
, MVT::v4i1
, 3 },
1485 { ISD::SINT_TO_FP
, MVT::v8f32
, MVT::v8i1
, 8 },
1486 { ISD::SINT_TO_FP
, MVT::v4f32
, MVT::v4i8
, 3 },
1487 { ISD::SINT_TO_FP
, MVT::v4f64
, MVT::v4i8
, 3 },
1488 { ISD::SINT_TO_FP
, MVT::v8f32
, MVT::v8i8
, 8 },
1489 { ISD::SINT_TO_FP
, MVT::v4f32
, MVT::v4i16
, 3 },
1490 { ISD::SINT_TO_FP
, MVT::v4f64
, MVT::v4i16
, 3 },
1491 { ISD::SINT_TO_FP
, MVT::v8f32
, MVT::v8i16
, 5 },
1492 { ISD::SINT_TO_FP
, MVT::v4f32
, MVT::v4i32
, 1 },
1493 { ISD::SINT_TO_FP
, MVT::v4f64
, MVT::v4i32
, 1 },
1494 { ISD::SINT_TO_FP
, MVT::v8f32
, MVT::v8i32
, 1 },
1496 { ISD::UINT_TO_FP
, MVT::v4f32
, MVT::v4i1
, 7 },
1497 { ISD::UINT_TO_FP
, MVT::v4f64
, MVT::v4i1
, 7 },
1498 { ISD::UINT_TO_FP
, MVT::v8f32
, MVT::v8i1
, 6 },
1499 { ISD::UINT_TO_FP
, MVT::v4f32
, MVT::v4i8
, 2 },
1500 { ISD::UINT_TO_FP
, MVT::v4f64
, MVT::v4i8
, 2 },
1501 { ISD::UINT_TO_FP
, MVT::v8f32
, MVT::v8i8
, 5 },
1502 { ISD::UINT_TO_FP
, MVT::v4f32
, MVT::v4i16
, 2 },
1503 { ISD::UINT_TO_FP
, MVT::v4f64
, MVT::v4i16
, 2 },
1504 { ISD::UINT_TO_FP
, MVT::v8f32
, MVT::v8i16
, 5 },
1505 { ISD::UINT_TO_FP
, MVT::v2f64
, MVT::v2i32
, 6 },
1506 { ISD::UINT_TO_FP
, MVT::v4f32
, MVT::v4i32
, 6 },
1507 { ISD::UINT_TO_FP
, MVT::v4f64
, MVT::v4i32
, 6 },
1508 { ISD::UINT_TO_FP
, MVT::v8f32
, MVT::v8i32
, 9 },
1509 { ISD::UINT_TO_FP
, MVT::v2f64
, MVT::v2i64
, 5 },
1510 { ISD::UINT_TO_FP
, MVT::v4f64
, MVT::v4i64
, 6 },
1511 // The generic code to compute the scalar overhead is currently broken.
1512 // Workaround this limitation by estimating the scalarization overhead
1513 // here. We have roughly 10 instructions per scalar element.
1514 // Multiply that by the vector width.
1515 // FIXME: remove that when PR19268 is fixed.
1516 { ISD::SINT_TO_FP
, MVT::v4f64
, MVT::v4i64
, 13 },
1517 { ISD::SINT_TO_FP
, MVT::v4f64
, MVT::v4i64
, 13 },
1519 { ISD::FP_TO_SINT
, MVT::v4i8
, MVT::v4f32
, 1 },
1520 { ISD::FP_TO_SINT
, MVT::v8i8
, MVT::v8f32
, 7 },
1521 // This node is expanded into scalarized operations but BasicTTI is overly
1522 // optimistic estimating its cost. It computes 3 per element (one
1523 // vector-extract, one scalar conversion and one vector-insert). The
1524 // problem is that the inserts form a read-modify-write chain so latency
1525 // should be factored in too. Inflating the cost per element by 1.
1526 { ISD::FP_TO_UINT
, MVT::v8i32
, MVT::v8f32
, 8*4 },
1527 { ISD::FP_TO_UINT
, MVT::v4i32
, MVT::v4f64
, 4*4 },
1529 { ISD::FP_EXTEND
, MVT::v4f64
, MVT::v4f32
, 1 },
1530 { ISD::FP_ROUND
, MVT::v4f32
, MVT::v4f64
, 1 },
1533 static const TypeConversionCostTblEntry SSE41ConversionTbl
[] = {
1534 { ISD::ZERO_EXTEND
, MVT::v4i64
, MVT::v4i8
, 2 },
1535 { ISD::SIGN_EXTEND
, MVT::v4i64
, MVT::v4i8
, 2 },
1536 { ISD::ZERO_EXTEND
, MVT::v4i64
, MVT::v4i16
, 2 },
1537 { ISD::SIGN_EXTEND
, MVT::v4i64
, MVT::v4i16
, 2 },
1538 { ISD::ZERO_EXTEND
, MVT::v4i64
, MVT::v4i32
, 2 },
1539 { ISD::SIGN_EXTEND
, MVT::v4i64
, MVT::v4i32
, 2 },
1541 { ISD::ZERO_EXTEND
, MVT::v4i16
, MVT::v4i8
, 1 },
1542 { ISD::SIGN_EXTEND
, MVT::v4i16
, MVT::v4i8
, 2 },
1543 { ISD::ZERO_EXTEND
, MVT::v4i32
, MVT::v4i8
, 1 },
1544 { ISD::SIGN_EXTEND
, MVT::v4i32
, MVT::v4i8
, 1 },
1545 { ISD::ZERO_EXTEND
, MVT::v8i16
, MVT::v8i8
, 1 },
1546 { ISD::SIGN_EXTEND
, MVT::v8i16
, MVT::v8i8
, 1 },
1547 { ISD::ZERO_EXTEND
, MVT::v8i32
, MVT::v8i8
, 2 },
1548 { ISD::SIGN_EXTEND
, MVT::v8i32
, MVT::v8i8
, 2 },
1549 { ISD::ZERO_EXTEND
, MVT::v16i16
, MVT::v16i8
, 2 },
1550 { ISD::SIGN_EXTEND
, MVT::v16i16
, MVT::v16i8
, 2 },
1551 { ISD::ZERO_EXTEND
, MVT::v16i32
, MVT::v16i8
, 4 },
1552 { ISD::SIGN_EXTEND
, MVT::v16i32
, MVT::v16i8
, 4 },
1553 { ISD::ZERO_EXTEND
, MVT::v4i32
, MVT::v4i16
, 1 },
1554 { ISD::SIGN_EXTEND
, MVT::v4i32
, MVT::v4i16
, 1 },
1555 { ISD::ZERO_EXTEND
, MVT::v8i32
, MVT::v8i16
, 2 },
1556 { ISD::SIGN_EXTEND
, MVT::v8i32
, MVT::v8i16
, 2 },
1557 { ISD::ZERO_EXTEND
, MVT::v16i32
, MVT::v16i16
, 4 },
1558 { ISD::SIGN_EXTEND
, MVT::v16i32
, MVT::v16i16
, 4 },
1560 { ISD::TRUNCATE
, MVT::v4i8
, MVT::v4i16
, 2 },
1561 { ISD::TRUNCATE
, MVT::v8i8
, MVT::v8i16
, 1 },
1562 { ISD::TRUNCATE
, MVT::v4i8
, MVT::v4i32
, 1 },
1563 { ISD::TRUNCATE
, MVT::v4i16
, MVT::v4i32
, 1 },
1564 { ISD::TRUNCATE
, MVT::v8i8
, MVT::v8i32
, 3 },
1565 { ISD::TRUNCATE
, MVT::v8i16
, MVT::v8i32
, 3 },
1566 { ISD::TRUNCATE
, MVT::v16i16
, MVT::v16i32
, 6 },
1568 { ISD::UINT_TO_FP
, MVT::f64
, MVT::i64
, 4 },
1571 static const TypeConversionCostTblEntry SSE2ConversionTblWide
[] = {
1572 { ISD::SINT_TO_FP
, MVT::v2f64
, MVT::v4i32
, 2*10 },
1573 { ISD::SINT_TO_FP
, MVT::v2f64
, MVT::v2i32
, 2*10 },
1576 static const TypeConversionCostTblEntry SSE2ConversionTbl
[] = {
1577 // These are somewhat magic numbers justified by looking at the output of
1578 // Intel's IACA, running some kernels and making sure when we take
1579 // legalization into account the throughput will be overestimated.
1580 { ISD::SINT_TO_FP
, MVT::v4f32
, MVT::v16i8
, 8 },
1581 { ISD::SINT_TO_FP
, MVT::v2f64
, MVT::v16i8
, 16*10 },
1582 { ISD::SINT_TO_FP
, MVT::v4f32
, MVT::v8i16
, 15 },
1583 { ISD::SINT_TO_FP
, MVT::v2f64
, MVT::v8i16
, 8*10 },
1584 { ISD::SINT_TO_FP
, MVT::v4f32
, MVT::v4i32
, 5 },
1585 { ISD::SINT_TO_FP
, MVT::v2f64
, MVT::v4i32
, 4*10 },
1586 { ISD::SINT_TO_FP
, MVT::v4f32
, MVT::v2i64
, 15 },
1587 { ISD::SINT_TO_FP
, MVT::v2f64
, MVT::v2i64
, 2*10 },
1589 { ISD::UINT_TO_FP
, MVT::v2f64
, MVT::v16i8
, 16*10 },
1590 { ISD::UINT_TO_FP
, MVT::v4f32
, MVT::v16i8
, 8 },
1591 { ISD::UINT_TO_FP
, MVT::v4f32
, MVT::v8i16
, 15 },
1592 { ISD::UINT_TO_FP
, MVT::v2f64
, MVT::v8i16
, 8*10 },
1593 { ISD::UINT_TO_FP
, MVT::v2f64
, MVT::v4i32
, 4*10 },
1594 { ISD::UINT_TO_FP
, MVT::v4f32
, MVT::v4i32
, 8 },
1595 { ISD::UINT_TO_FP
, MVT::v2f64
, MVT::v2i64
, 6 },
1596 { ISD::UINT_TO_FP
, MVT::v4f32
, MVT::v2i64
, 15 },
1598 { ISD::FP_TO_SINT
, MVT::v2i32
, MVT::v2f64
, 3 },
1600 { ISD::UINT_TO_FP
, MVT::f64
, MVT::i64
, 6 },
1602 { ISD::ZERO_EXTEND
, MVT::v4i16
, MVT::v4i8
, 1 },
1603 { ISD::SIGN_EXTEND
, MVT::v4i16
, MVT::v4i8
, 6 },
1604 { ISD::ZERO_EXTEND
, MVT::v4i32
, MVT::v4i8
, 2 },
1605 { ISD::SIGN_EXTEND
, MVT::v4i32
, MVT::v4i8
, 3 },
1606 { ISD::ZERO_EXTEND
, MVT::v4i64
, MVT::v4i8
, 4 },
1607 { ISD::SIGN_EXTEND
, MVT::v4i64
, MVT::v4i8
, 8 },
1608 { ISD::ZERO_EXTEND
, MVT::v8i16
, MVT::v8i8
, 1 },
1609 { ISD::SIGN_EXTEND
, MVT::v8i16
, MVT::v8i8
, 2 },
1610 { ISD::ZERO_EXTEND
, MVT::v8i32
, MVT::v8i8
, 6 },
1611 { ISD::SIGN_EXTEND
, MVT::v8i32
, MVT::v8i8
, 6 },
1612 { ISD::ZERO_EXTEND
, MVT::v16i16
, MVT::v16i8
, 3 },
1613 { ISD::SIGN_EXTEND
, MVT::v16i16
, MVT::v16i8
, 4 },
1614 { ISD::ZERO_EXTEND
, MVT::v16i32
, MVT::v16i8
, 9 },
1615 { ISD::SIGN_EXTEND
, MVT::v16i32
, MVT::v16i8
, 12 },
1616 { ISD::ZERO_EXTEND
, MVT::v4i32
, MVT::v4i16
, 1 },
1617 { ISD::SIGN_EXTEND
, MVT::v4i32
, MVT::v4i16
, 2 },
1618 { ISD::ZERO_EXTEND
, MVT::v4i64
, MVT::v4i16
, 3 },
1619 { ISD::SIGN_EXTEND
, MVT::v4i64
, MVT::v4i16
, 10 },
1620 { ISD::ZERO_EXTEND
, MVT::v8i32
, MVT::v8i16
, 3 },
1621 { ISD::SIGN_EXTEND
, MVT::v8i32
, MVT::v8i16
, 4 },
1622 { ISD::ZERO_EXTEND
, MVT::v16i32
, MVT::v16i16
, 6 },
1623 { ISD::SIGN_EXTEND
, MVT::v16i32
, MVT::v16i16
, 8 },
1624 { ISD::ZERO_EXTEND
, MVT::v4i64
, MVT::v4i32
, 3 },
1625 { ISD::SIGN_EXTEND
, MVT::v4i64
, MVT::v4i32
, 5 },
1627 { ISD::TRUNCATE
, MVT::v4i8
, MVT::v4i16
, 4 },
1628 { ISD::TRUNCATE
, MVT::v8i8
, MVT::v8i16
, 2 },
1629 { ISD::TRUNCATE
, MVT::v16i8
, MVT::v16i16
, 3 },
1630 { ISD::TRUNCATE
, MVT::v4i8
, MVT::v4i32
, 3 },
1631 { ISD::TRUNCATE
, MVT::v4i16
, MVT::v4i32
, 3 },
1632 { ISD::TRUNCATE
, MVT::v8i8
, MVT::v8i32
, 4 },
1633 { ISD::TRUNCATE
, MVT::v16i8
, MVT::v16i32
, 7 },
1634 { ISD::TRUNCATE
, MVT::v8i16
, MVT::v8i32
, 5 },
1635 { ISD::TRUNCATE
, MVT::v16i16
, MVT::v16i32
, 10 },
1638 std::pair
<int, MVT
> LTSrc
= TLI
->getTypeLegalizationCost(DL
, Src
);
1639 std::pair
<int, MVT
> LTDest
= TLI
->getTypeLegalizationCost(DL
, Dst
);
1641 if (ST
->hasSSE2() && !ST
->hasAVX() &&
1642 ExperimentalVectorWideningLegalization
) {
1643 if (const auto *Entry
= ConvertCostTableLookup(SSE2ConversionTblWide
, ISD
,
1644 LTDest
.second
, LTSrc
.second
))
1645 return LTSrc
.first
* Entry
->Cost
;
1648 if (ST
->hasSSE2() && !ST
->hasAVX()) {
1649 if (const auto *Entry
= ConvertCostTableLookup(SSE2ConversionTbl
, ISD
,
1650 LTDest
.second
, LTSrc
.second
))
1651 return LTSrc
.first
* Entry
->Cost
;
1654 EVT SrcTy
= TLI
->getValueType(DL
, Src
);
1655 EVT DstTy
= TLI
->getValueType(DL
, Dst
);
1657 // The function getSimpleVT only handles simple value types.
1658 if (!SrcTy
.isSimple() || !DstTy
.isSimple())
1659 return BaseT::getCastInstrCost(Opcode
, Dst
, Src
);
1661 MVT SimpleSrcTy
= SrcTy
.getSimpleVT();
1662 MVT SimpleDstTy
= DstTy
.getSimpleVT();
1664 // Make sure that neither type is going to be split before using the
1665 // AVX512 tables. This handles -mprefer-vector-width=256
1666 // with -min-legal-vector-width<=256
1667 if (TLI
->getTypeAction(SimpleSrcTy
) != TargetLowering::TypeSplitVector
&&
1668 TLI
->getTypeAction(SimpleDstTy
) != TargetLowering::TypeSplitVector
) {
1670 if (const auto *Entry
= ConvertCostTableLookup(AVX512BWConversionTbl
, ISD
,
1671 SimpleDstTy
, SimpleSrcTy
))
1675 if (const auto *Entry
= ConvertCostTableLookup(AVX512DQConversionTbl
, ISD
,
1676 SimpleDstTy
, SimpleSrcTy
))
1679 if (ST
->hasAVX512() && ExperimentalVectorWideningLegalization
)
1680 if (const auto *Entry
= ConvertCostTableLookup(AVX512FConversionTblWide
, ISD
,
1681 SimpleDstTy
, SimpleSrcTy
))
1684 if (ST
->hasAVX512())
1685 if (const auto *Entry
= ConvertCostTableLookup(AVX512FConversionTbl
, ISD
,
1686 SimpleDstTy
, SimpleSrcTy
))
1690 if (ST
->hasAVX2() && ExperimentalVectorWideningLegalization
) {
1691 if (const auto *Entry
= ConvertCostTableLookup(AVX2ConversionTblWide
, ISD
,
1692 SimpleDstTy
, SimpleSrcTy
))
1696 if (ST
->hasAVX2()) {
1697 if (const auto *Entry
= ConvertCostTableLookup(AVX2ConversionTbl
, ISD
,
1698 SimpleDstTy
, SimpleSrcTy
))
1702 if (ST
->hasAVX() && ExperimentalVectorWideningLegalization
) {
1703 if (const auto *Entry
= ConvertCostTableLookup(AVXConversionTblWide
, ISD
,
1704 SimpleDstTy
, SimpleSrcTy
))
1709 if (const auto *Entry
= ConvertCostTableLookup(AVXConversionTbl
, ISD
,
1710 SimpleDstTy
, SimpleSrcTy
))
1714 if (ST
->hasSSE41()) {
1715 if (const auto *Entry
= ConvertCostTableLookup(SSE41ConversionTbl
, ISD
,
1716 SimpleDstTy
, SimpleSrcTy
))
1720 if (ST
->hasSSE2() && ExperimentalVectorWideningLegalization
) {
1721 if (const auto *Entry
= ConvertCostTableLookup(SSE2ConversionTblWide
, ISD
,
1722 SimpleDstTy
, SimpleSrcTy
))
1726 if (ST
->hasSSE2()) {
1727 if (const auto *Entry
= ConvertCostTableLookup(SSE2ConversionTbl
, ISD
,
1728 SimpleDstTy
, SimpleSrcTy
))
1732 return BaseT::getCastInstrCost(Opcode
, Dst
, Src
, I
);
1735 int X86TTIImpl::getCmpSelInstrCost(unsigned Opcode
, Type
*ValTy
, Type
*CondTy
,
1736 const Instruction
*I
) {
1737 // Legalize the type.
1738 std::pair
<int, MVT
> LT
= TLI
->getTypeLegalizationCost(DL
, ValTy
);
1740 MVT MTy
= LT
.second
;
1742 int ISD
= TLI
->InstructionOpcodeToISD(Opcode
);
1743 assert(ISD
&& "Invalid opcode");
1745 unsigned ExtraCost
= 0;
1746 if (I
&& (Opcode
== Instruction::ICmp
|| Opcode
== Instruction::FCmp
)) {
1747 // Some vector comparison predicates cost extra instructions.
1748 if (MTy
.isVector() &&
1749 !((ST
->hasXOP() && (!ST
->hasAVX2() || MTy
.is128BitVector())) ||
1750 (ST
->hasAVX512() && 32 <= MTy
.getScalarSizeInBits()) ||
1752 switch (cast
<CmpInst
>(I
)->getPredicate()) {
1753 case CmpInst::Predicate::ICMP_NE
:
1754 // xor(cmpeq(x,y),-1)
1757 case CmpInst::Predicate::ICMP_SGE
:
1758 case CmpInst::Predicate::ICMP_SLE
:
1759 // xor(cmpgt(x,y),-1)
1762 case CmpInst::Predicate::ICMP_ULT
:
1763 case CmpInst::Predicate::ICMP_UGT
:
1764 // cmpgt(xor(x,signbit),xor(y,signbit))
1765 // xor(cmpeq(pmaxu(x,y),x),-1)
1768 case CmpInst::Predicate::ICMP_ULE
:
1769 case CmpInst::Predicate::ICMP_UGE
:
1770 if ((ST
->hasSSE41() && MTy
.getScalarSizeInBits() == 32) ||
1771 (ST
->hasSSE2() && MTy
.getScalarSizeInBits() < 32)) {
1772 // cmpeq(psubus(x,y),0)
1773 // cmpeq(pminu(x,y),x)
1776 // xor(cmpgt(xor(x,signbit),xor(y,signbit)),-1)
1786 static const CostTblEntry AVX512BWCostTbl
[] = {
1787 { ISD::SETCC
, MVT::v32i16
, 1 },
1788 { ISD::SETCC
, MVT::v64i8
, 1 },
1790 { ISD::SELECT
, MVT::v32i16
, 1 },
1791 { ISD::SELECT
, MVT::v64i8
, 1 },
1794 static const CostTblEntry AVX512CostTbl
[] = {
1795 { ISD::SETCC
, MVT::v8i64
, 1 },
1796 { ISD::SETCC
, MVT::v16i32
, 1 },
1797 { ISD::SETCC
, MVT::v8f64
, 1 },
1798 { ISD::SETCC
, MVT::v16f32
, 1 },
1800 { ISD::SELECT
, MVT::v8i64
, 1 },
1801 { ISD::SELECT
, MVT::v16i32
, 1 },
1802 { ISD::SELECT
, MVT::v8f64
, 1 },
1803 { ISD::SELECT
, MVT::v16f32
, 1 },
1806 static const CostTblEntry AVX2CostTbl
[] = {
1807 { ISD::SETCC
, MVT::v4i64
, 1 },
1808 { ISD::SETCC
, MVT::v8i32
, 1 },
1809 { ISD::SETCC
, MVT::v16i16
, 1 },
1810 { ISD::SETCC
, MVT::v32i8
, 1 },
1812 { ISD::SELECT
, MVT::v4i64
, 1 }, // pblendvb
1813 { ISD::SELECT
, MVT::v8i32
, 1 }, // pblendvb
1814 { ISD::SELECT
, MVT::v16i16
, 1 }, // pblendvb
1815 { ISD::SELECT
, MVT::v32i8
, 1 }, // pblendvb
1818 static const CostTblEntry AVX1CostTbl
[] = {
1819 { ISD::SETCC
, MVT::v4f64
, 1 },
1820 { ISD::SETCC
, MVT::v8f32
, 1 },
1821 // AVX1 does not support 8-wide integer compare.
1822 { ISD::SETCC
, MVT::v4i64
, 4 },
1823 { ISD::SETCC
, MVT::v8i32
, 4 },
1824 { ISD::SETCC
, MVT::v16i16
, 4 },
1825 { ISD::SETCC
, MVT::v32i8
, 4 },
1827 { ISD::SELECT
, MVT::v4f64
, 1 }, // vblendvpd
1828 { ISD::SELECT
, MVT::v8f32
, 1 }, // vblendvps
1829 { ISD::SELECT
, MVT::v4i64
, 1 }, // vblendvpd
1830 { ISD::SELECT
, MVT::v8i32
, 1 }, // vblendvps
1831 { ISD::SELECT
, MVT::v16i16
, 3 }, // vandps + vandnps + vorps
1832 { ISD::SELECT
, MVT::v32i8
, 3 }, // vandps + vandnps + vorps
1835 static const CostTblEntry SSE42CostTbl
[] = {
1836 { ISD::SETCC
, MVT::v2f64
, 1 },
1837 { ISD::SETCC
, MVT::v4f32
, 1 },
1838 { ISD::SETCC
, MVT::v2i64
, 1 },
1841 static const CostTblEntry SSE41CostTbl
[] = {
1842 { ISD::SELECT
, MVT::v2f64
, 1 }, // blendvpd
1843 { ISD::SELECT
, MVT::v4f32
, 1 }, // blendvps
1844 { ISD::SELECT
, MVT::v2i64
, 1 }, // pblendvb
1845 { ISD::SELECT
, MVT::v4i32
, 1 }, // pblendvb
1846 { ISD::SELECT
, MVT::v8i16
, 1 }, // pblendvb
1847 { ISD::SELECT
, MVT::v16i8
, 1 }, // pblendvb
1850 static const CostTblEntry SSE2CostTbl
[] = {
1851 { ISD::SETCC
, MVT::v2f64
, 2 },
1852 { ISD::SETCC
, MVT::f64
, 1 },
1853 { ISD::SETCC
, MVT::v2i64
, 8 },
1854 { ISD::SETCC
, MVT::v4i32
, 1 },
1855 { ISD::SETCC
, MVT::v8i16
, 1 },
1856 { ISD::SETCC
, MVT::v16i8
, 1 },
1858 { ISD::SELECT
, MVT::v2f64
, 3 }, // andpd + andnpd + orpd
1859 { ISD::SELECT
, MVT::v2i64
, 3 }, // pand + pandn + por
1860 { ISD::SELECT
, MVT::v4i32
, 3 }, // pand + pandn + por
1861 { ISD::SELECT
, MVT::v8i16
, 3 }, // pand + pandn + por
1862 { ISD::SELECT
, MVT::v16i8
, 3 }, // pand + pandn + por
1865 static const CostTblEntry SSE1CostTbl
[] = {
1866 { ISD::SETCC
, MVT::v4f32
, 2 },
1867 { ISD::SETCC
, MVT::f32
, 1 },
1869 { ISD::SELECT
, MVT::v4f32
, 3 }, // andps + andnps + orps
1873 if (const auto *Entry
= CostTableLookup(AVX512BWCostTbl
, ISD
, MTy
))
1874 return LT
.first
* (ExtraCost
+ Entry
->Cost
);
1876 if (ST
->hasAVX512())
1877 if (const auto *Entry
= CostTableLookup(AVX512CostTbl
, ISD
, MTy
))
1878 return LT
.first
* (ExtraCost
+ Entry
->Cost
);
1881 if (const auto *Entry
= CostTableLookup(AVX2CostTbl
, ISD
, MTy
))
1882 return LT
.first
* (ExtraCost
+ Entry
->Cost
);
1885 if (const auto *Entry
= CostTableLookup(AVX1CostTbl
, ISD
, MTy
))
1886 return LT
.first
* (ExtraCost
+ Entry
->Cost
);
1889 if (const auto *Entry
= CostTableLookup(SSE42CostTbl
, ISD
, MTy
))
1890 return LT
.first
* (ExtraCost
+ Entry
->Cost
);
1893 if (const auto *Entry
= CostTableLookup(SSE41CostTbl
, ISD
, MTy
))
1894 return LT
.first
* (ExtraCost
+ Entry
->Cost
);
1897 if (const auto *Entry
= CostTableLookup(SSE2CostTbl
, ISD
, MTy
))
1898 return LT
.first
* (ExtraCost
+ Entry
->Cost
);
1901 if (const auto *Entry
= CostTableLookup(SSE1CostTbl
, ISD
, MTy
))
1902 return LT
.first
* (ExtraCost
+ Entry
->Cost
);
1904 return BaseT::getCmpSelInstrCost(Opcode
, ValTy
, CondTy
, I
);
1907 unsigned X86TTIImpl::getAtomicMemIntrinsicMaxElementSize() const { return 16; }
1909 int X86TTIImpl::getIntrinsicInstrCost(Intrinsic::ID IID
, Type
*RetTy
,
1910 ArrayRef
<Type
*> Tys
, FastMathFlags FMF
,
1911 unsigned ScalarizationCostPassed
) {
1912 // Costs should match the codegen from:
1913 // BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll
1914 // BSWAP: llvm\test\CodeGen\X86\bswap-vector.ll
1915 // CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll
1916 // CTPOP: llvm\test\CodeGen\X86\vector-popcnt-*.ll
1917 // CTTZ: llvm\test\CodeGen\X86\vector-tzcnt-*.ll
1918 static const CostTblEntry AVX512CDCostTbl
[] = {
1919 { ISD::CTLZ
, MVT::v8i64
, 1 },
1920 { ISD::CTLZ
, MVT::v16i32
, 1 },
1921 { ISD::CTLZ
, MVT::v32i16
, 8 },
1922 { ISD::CTLZ
, MVT::v64i8
, 20 },
1923 { ISD::CTLZ
, MVT::v4i64
, 1 },
1924 { ISD::CTLZ
, MVT::v8i32
, 1 },
1925 { ISD::CTLZ
, MVT::v16i16
, 4 },
1926 { ISD::CTLZ
, MVT::v32i8
, 10 },
1927 { ISD::CTLZ
, MVT::v2i64
, 1 },
1928 { ISD::CTLZ
, MVT::v4i32
, 1 },
1929 { ISD::CTLZ
, MVT::v8i16
, 4 },
1930 { ISD::CTLZ
, MVT::v16i8
, 4 },
1932 static const CostTblEntry AVX512BWCostTbl
[] = {
1933 { ISD::BITREVERSE
, MVT::v8i64
, 5 },
1934 { ISD::BITREVERSE
, MVT::v16i32
, 5 },
1935 { ISD::BITREVERSE
, MVT::v32i16
, 5 },
1936 { ISD::BITREVERSE
, MVT::v64i8
, 5 },
1937 { ISD::CTLZ
, MVT::v8i64
, 23 },
1938 { ISD::CTLZ
, MVT::v16i32
, 22 },
1939 { ISD::CTLZ
, MVT::v32i16
, 18 },
1940 { ISD::CTLZ
, MVT::v64i8
, 17 },
1941 { ISD::CTPOP
, MVT::v8i64
, 7 },
1942 { ISD::CTPOP
, MVT::v16i32
, 11 },
1943 { ISD::CTPOP
, MVT::v32i16
, 9 },
1944 { ISD::CTPOP
, MVT::v64i8
, 6 },
1945 { ISD::CTTZ
, MVT::v8i64
, 10 },
1946 { ISD::CTTZ
, MVT::v16i32
, 14 },
1947 { ISD::CTTZ
, MVT::v32i16
, 12 },
1948 { ISD::CTTZ
, MVT::v64i8
, 9 },
1949 { ISD::SADDSAT
, MVT::v32i16
, 1 },
1950 { ISD::SADDSAT
, MVT::v64i8
, 1 },
1951 { ISD::SSUBSAT
, MVT::v32i16
, 1 },
1952 { ISD::SSUBSAT
, MVT::v64i8
, 1 },
1953 { ISD::UADDSAT
, MVT::v32i16
, 1 },
1954 { ISD::UADDSAT
, MVT::v64i8
, 1 },
1955 { ISD::USUBSAT
, MVT::v32i16
, 1 },
1956 { ISD::USUBSAT
, MVT::v64i8
, 1 },
1958 static const CostTblEntry AVX512CostTbl
[] = {
1959 { ISD::BITREVERSE
, MVT::v8i64
, 36 },
1960 { ISD::BITREVERSE
, MVT::v16i32
, 24 },
1961 { ISD::CTLZ
, MVT::v8i64
, 29 },
1962 { ISD::CTLZ
, MVT::v16i32
, 35 },
1963 { ISD::CTPOP
, MVT::v8i64
, 16 },
1964 { ISD::CTPOP
, MVT::v16i32
, 24 },
1965 { ISD::CTTZ
, MVT::v8i64
, 20 },
1966 { ISD::CTTZ
, MVT::v16i32
, 28 },
1967 { ISD::USUBSAT
, MVT::v16i32
, 2 }, // pmaxud + psubd
1968 { ISD::USUBSAT
, MVT::v2i64
, 2 }, // pmaxuq + psubq
1969 { ISD::USUBSAT
, MVT::v4i64
, 2 }, // pmaxuq + psubq
1970 { ISD::USUBSAT
, MVT::v8i64
, 2 }, // pmaxuq + psubq
1971 { ISD::UADDSAT
, MVT::v16i32
, 3 }, // not + pminud + paddd
1972 { ISD::UADDSAT
, MVT::v2i64
, 3 }, // not + pminuq + paddq
1973 { ISD::UADDSAT
, MVT::v4i64
, 3 }, // not + pminuq + paddq
1974 { ISD::UADDSAT
, MVT::v8i64
, 3 }, // not + pminuq + paddq
1976 static const CostTblEntry XOPCostTbl
[] = {
1977 { ISD::BITREVERSE
, MVT::v4i64
, 4 },
1978 { ISD::BITREVERSE
, MVT::v8i32
, 4 },
1979 { ISD::BITREVERSE
, MVT::v16i16
, 4 },
1980 { ISD::BITREVERSE
, MVT::v32i8
, 4 },
1981 { ISD::BITREVERSE
, MVT::v2i64
, 1 },
1982 { ISD::BITREVERSE
, MVT::v4i32
, 1 },
1983 { ISD::BITREVERSE
, MVT::v8i16
, 1 },
1984 { ISD::BITREVERSE
, MVT::v16i8
, 1 },
1985 { ISD::BITREVERSE
, MVT::i64
, 3 },
1986 { ISD::BITREVERSE
, MVT::i32
, 3 },
1987 { ISD::BITREVERSE
, MVT::i16
, 3 },
1988 { ISD::BITREVERSE
, MVT::i8
, 3 }
1990 static const CostTblEntry AVX2CostTbl
[] = {
1991 { ISD::BITREVERSE
, MVT::v4i64
, 5 },
1992 { ISD::BITREVERSE
, MVT::v8i32
, 5 },
1993 { ISD::BITREVERSE
, MVT::v16i16
, 5 },
1994 { ISD::BITREVERSE
, MVT::v32i8
, 5 },
1995 { ISD::BSWAP
, MVT::v4i64
, 1 },
1996 { ISD::BSWAP
, MVT::v8i32
, 1 },
1997 { ISD::BSWAP
, MVT::v16i16
, 1 },
1998 { ISD::CTLZ
, MVT::v4i64
, 23 },
1999 { ISD::CTLZ
, MVT::v8i32
, 18 },
2000 { ISD::CTLZ
, MVT::v16i16
, 14 },
2001 { ISD::CTLZ
, MVT::v32i8
, 9 },
2002 { ISD::CTPOP
, MVT::v4i64
, 7 },
2003 { ISD::CTPOP
, MVT::v8i32
, 11 },
2004 { ISD::CTPOP
, MVT::v16i16
, 9 },
2005 { ISD::CTPOP
, MVT::v32i8
, 6 },
2006 { ISD::CTTZ
, MVT::v4i64
, 10 },
2007 { ISD::CTTZ
, MVT::v8i32
, 14 },
2008 { ISD::CTTZ
, MVT::v16i16
, 12 },
2009 { ISD::CTTZ
, MVT::v32i8
, 9 },
2010 { ISD::SADDSAT
, MVT::v16i16
, 1 },
2011 { ISD::SADDSAT
, MVT::v32i8
, 1 },
2012 { ISD::SSUBSAT
, MVT::v16i16
, 1 },
2013 { ISD::SSUBSAT
, MVT::v32i8
, 1 },
2014 { ISD::UADDSAT
, MVT::v16i16
, 1 },
2015 { ISD::UADDSAT
, MVT::v32i8
, 1 },
2016 { ISD::UADDSAT
, MVT::v8i32
, 3 }, // not + pminud + paddd
2017 { ISD::USUBSAT
, MVT::v16i16
, 1 },
2018 { ISD::USUBSAT
, MVT::v32i8
, 1 },
2019 { ISD::USUBSAT
, MVT::v8i32
, 2 }, // pmaxud + psubd
2020 { ISD::FSQRT
, MVT::f32
, 7 }, // Haswell from http://www.agner.org/
2021 { ISD::FSQRT
, MVT::v4f32
, 7 }, // Haswell from http://www.agner.org/
2022 { ISD::FSQRT
, MVT::v8f32
, 14 }, // Haswell from http://www.agner.org/
2023 { ISD::FSQRT
, MVT::f64
, 14 }, // Haswell from http://www.agner.org/
2024 { ISD::FSQRT
, MVT::v2f64
, 14 }, // Haswell from http://www.agner.org/
2025 { ISD::FSQRT
, MVT::v4f64
, 28 }, // Haswell from http://www.agner.org/
2027 static const CostTblEntry AVX1CostTbl
[] = {
2028 { ISD::BITREVERSE
, MVT::v4i64
, 12 }, // 2 x 128-bit Op + extract/insert
2029 { ISD::BITREVERSE
, MVT::v8i32
, 12 }, // 2 x 128-bit Op + extract/insert
2030 { ISD::BITREVERSE
, MVT::v16i16
, 12 }, // 2 x 128-bit Op + extract/insert
2031 { ISD::BITREVERSE
, MVT::v32i8
, 12 }, // 2 x 128-bit Op + extract/insert
2032 { ISD::BSWAP
, MVT::v4i64
, 4 },
2033 { ISD::BSWAP
, MVT::v8i32
, 4 },
2034 { ISD::BSWAP
, MVT::v16i16
, 4 },
2035 { ISD::CTLZ
, MVT::v4i64
, 48 }, // 2 x 128-bit Op + extract/insert
2036 { ISD::CTLZ
, MVT::v8i32
, 38 }, // 2 x 128-bit Op + extract/insert
2037 { ISD::CTLZ
, MVT::v16i16
, 30 }, // 2 x 128-bit Op + extract/insert
2038 { ISD::CTLZ
, MVT::v32i8
, 20 }, // 2 x 128-bit Op + extract/insert
2039 { ISD::CTPOP
, MVT::v4i64
, 16 }, // 2 x 128-bit Op + extract/insert
2040 { ISD::CTPOP
, MVT::v8i32
, 24 }, // 2 x 128-bit Op + extract/insert
2041 { ISD::CTPOP
, MVT::v16i16
, 20 }, // 2 x 128-bit Op + extract/insert
2042 { ISD::CTPOP
, MVT::v32i8
, 14 }, // 2 x 128-bit Op + extract/insert
2043 { ISD::CTTZ
, MVT::v4i64
, 22 }, // 2 x 128-bit Op + extract/insert
2044 { ISD::CTTZ
, MVT::v8i32
, 30 }, // 2 x 128-bit Op + extract/insert
2045 { ISD::CTTZ
, MVT::v16i16
, 26 }, // 2 x 128-bit Op + extract/insert
2046 { ISD::CTTZ
, MVT::v32i8
, 20 }, // 2 x 128-bit Op + extract/insert
2047 { ISD::SADDSAT
, MVT::v16i16
, 4 }, // 2 x 128-bit Op + extract/insert
2048 { ISD::SADDSAT
, MVT::v32i8
, 4 }, // 2 x 128-bit Op + extract/insert
2049 { ISD::SSUBSAT
, MVT::v16i16
, 4 }, // 2 x 128-bit Op + extract/insert
2050 { ISD::SSUBSAT
, MVT::v32i8
, 4 }, // 2 x 128-bit Op + extract/insert
2051 { ISD::UADDSAT
, MVT::v16i16
, 4 }, // 2 x 128-bit Op + extract/insert
2052 { ISD::UADDSAT
, MVT::v32i8
, 4 }, // 2 x 128-bit Op + extract/insert
2053 { ISD::UADDSAT
, MVT::v8i32
, 8 }, // 2 x 128-bit Op + extract/insert
2054 { ISD::USUBSAT
, MVT::v16i16
, 4 }, // 2 x 128-bit Op + extract/insert
2055 { ISD::USUBSAT
, MVT::v32i8
, 4 }, // 2 x 128-bit Op + extract/insert
2056 { ISD::USUBSAT
, MVT::v8i32
, 6 }, // 2 x 128-bit Op + extract/insert
2057 { ISD::FSQRT
, MVT::f32
, 14 }, // SNB from http://www.agner.org/
2058 { ISD::FSQRT
, MVT::v4f32
, 14 }, // SNB from http://www.agner.org/
2059 { ISD::FSQRT
, MVT::v8f32
, 28 }, // SNB from http://www.agner.org/
2060 { ISD::FSQRT
, MVT::f64
, 21 }, // SNB from http://www.agner.org/
2061 { ISD::FSQRT
, MVT::v2f64
, 21 }, // SNB from http://www.agner.org/
2062 { ISD::FSQRT
, MVT::v4f64
, 43 }, // SNB from http://www.agner.org/
2064 static const CostTblEntry GLMCostTbl
[] = {
2065 { ISD::FSQRT
, MVT::f32
, 19 }, // sqrtss
2066 { ISD::FSQRT
, MVT::v4f32
, 37 }, // sqrtps
2067 { ISD::FSQRT
, MVT::f64
, 34 }, // sqrtsd
2068 { ISD::FSQRT
, MVT::v2f64
, 67 }, // sqrtpd
2070 static const CostTblEntry SLMCostTbl
[] = {
2071 { ISD::FSQRT
, MVT::f32
, 20 }, // sqrtss
2072 { ISD::FSQRT
, MVT::v4f32
, 40 }, // sqrtps
2073 { ISD::FSQRT
, MVT::f64
, 35 }, // sqrtsd
2074 { ISD::FSQRT
, MVT::v2f64
, 70 }, // sqrtpd
2076 static const CostTblEntry SSE42CostTbl
[] = {
2077 { ISD::USUBSAT
, MVT::v4i32
, 2 }, // pmaxud + psubd
2078 { ISD::UADDSAT
, MVT::v4i32
, 3 }, // not + pminud + paddd
2079 { ISD::FSQRT
, MVT::f32
, 18 }, // Nehalem from http://www.agner.org/
2080 { ISD::FSQRT
, MVT::v4f32
, 18 }, // Nehalem from http://www.agner.org/
2082 static const CostTblEntry SSSE3CostTbl
[] = {
2083 { ISD::BITREVERSE
, MVT::v2i64
, 5 },
2084 { ISD::BITREVERSE
, MVT::v4i32
, 5 },
2085 { ISD::BITREVERSE
, MVT::v8i16
, 5 },
2086 { ISD::BITREVERSE
, MVT::v16i8
, 5 },
2087 { ISD::BSWAP
, MVT::v2i64
, 1 },
2088 { ISD::BSWAP
, MVT::v4i32
, 1 },
2089 { ISD::BSWAP
, MVT::v8i16
, 1 },
2090 { ISD::CTLZ
, MVT::v2i64
, 23 },
2091 { ISD::CTLZ
, MVT::v4i32
, 18 },
2092 { ISD::CTLZ
, MVT::v8i16
, 14 },
2093 { ISD::CTLZ
, MVT::v16i8
, 9 },
2094 { ISD::CTPOP
, MVT::v2i64
, 7 },
2095 { ISD::CTPOP
, MVT::v4i32
, 11 },
2096 { ISD::CTPOP
, MVT::v8i16
, 9 },
2097 { ISD::CTPOP
, MVT::v16i8
, 6 },
2098 { ISD::CTTZ
, MVT::v2i64
, 10 },
2099 { ISD::CTTZ
, MVT::v4i32
, 14 },
2100 { ISD::CTTZ
, MVT::v8i16
, 12 },
2101 { ISD::CTTZ
, MVT::v16i8
, 9 }
2103 static const CostTblEntry SSE2CostTbl
[] = {
2104 { ISD::BITREVERSE
, MVT::v2i64
, 29 },
2105 { ISD::BITREVERSE
, MVT::v4i32
, 27 },
2106 { ISD::BITREVERSE
, MVT::v8i16
, 27 },
2107 { ISD::BITREVERSE
, MVT::v16i8
, 20 },
2108 { ISD::BSWAP
, MVT::v2i64
, 7 },
2109 { ISD::BSWAP
, MVT::v4i32
, 7 },
2110 { ISD::BSWAP
, MVT::v8i16
, 7 },
2111 { ISD::CTLZ
, MVT::v2i64
, 25 },
2112 { ISD::CTLZ
, MVT::v4i32
, 26 },
2113 { ISD::CTLZ
, MVT::v8i16
, 20 },
2114 { ISD::CTLZ
, MVT::v16i8
, 17 },
2115 { ISD::CTPOP
, MVT::v2i64
, 12 },
2116 { ISD::CTPOP
, MVT::v4i32
, 15 },
2117 { ISD::CTPOP
, MVT::v8i16
, 13 },
2118 { ISD::CTPOP
, MVT::v16i8
, 10 },
2119 { ISD::CTTZ
, MVT::v2i64
, 14 },
2120 { ISD::CTTZ
, MVT::v4i32
, 18 },
2121 { ISD::CTTZ
, MVT::v8i16
, 16 },
2122 { ISD::CTTZ
, MVT::v16i8
, 13 },
2123 { ISD::SADDSAT
, MVT::v8i16
, 1 },
2124 { ISD::SADDSAT
, MVT::v16i8
, 1 },
2125 { ISD::SSUBSAT
, MVT::v8i16
, 1 },
2126 { ISD::SSUBSAT
, MVT::v16i8
, 1 },
2127 { ISD::UADDSAT
, MVT::v8i16
, 1 },
2128 { ISD::UADDSAT
, MVT::v16i8
, 1 },
2129 { ISD::USUBSAT
, MVT::v8i16
, 1 },
2130 { ISD::USUBSAT
, MVT::v16i8
, 1 },
2131 { ISD::FSQRT
, MVT::f64
, 32 }, // Nehalem from http://www.agner.org/
2132 { ISD::FSQRT
, MVT::v2f64
, 32 }, // Nehalem from http://www.agner.org/
2134 static const CostTblEntry SSE1CostTbl
[] = {
2135 { ISD::FSQRT
, MVT::f32
, 28 }, // Pentium III from http://www.agner.org/
2136 { ISD::FSQRT
, MVT::v4f32
, 56 }, // Pentium III from http://www.agner.org/
2138 static const CostTblEntry X64CostTbl
[] = { // 64-bit targets
2139 { ISD::BITREVERSE
, MVT::i64
, 14 },
2140 { ISD::SADDO
, MVT::i64
, 1 },
2141 { ISD::UADDO
, MVT::i64
, 1 },
2143 static const CostTblEntry X86CostTbl
[] = { // 32 or 64-bit targets
2144 { ISD::BITREVERSE
, MVT::i32
, 14 },
2145 { ISD::BITREVERSE
, MVT::i16
, 14 },
2146 { ISD::BITREVERSE
, MVT::i8
, 11 },
2147 { ISD::SADDO
, MVT::i32
, 1 },
2148 { ISD::SADDO
, MVT::i16
, 1 },
2149 { ISD::SADDO
, MVT::i8
, 1 },
2150 { ISD::UADDO
, MVT::i32
, 1 },
2151 { ISD::UADDO
, MVT::i16
, 1 },
2152 { ISD::UADDO
, MVT::i8
, 1 },
2156 unsigned ISD
= ISD::DELETED_NODE
;
2160 case Intrinsic::bitreverse
:
2161 ISD
= ISD::BITREVERSE
;
2163 case Intrinsic::bswap
:
2166 case Intrinsic::ctlz
:
2169 case Intrinsic::ctpop
:
2172 case Intrinsic::cttz
:
2175 case Intrinsic::sadd_sat
:
2178 case Intrinsic::ssub_sat
:
2181 case Intrinsic::uadd_sat
:
2184 case Intrinsic::usub_sat
:
2187 case Intrinsic::sqrt
:
2190 case Intrinsic::sadd_with_overflow
:
2191 case Intrinsic::ssub_with_overflow
:
2192 // SSUBO has same costs so don't duplicate.
2194 OpTy
= RetTy
->getContainedType(0);
2196 case Intrinsic::uadd_with_overflow
:
2197 case Intrinsic::usub_with_overflow
:
2198 // USUBO has same costs so don't duplicate.
2200 OpTy
= RetTy
->getContainedType(0);
2204 if (ISD
!= ISD::DELETED_NODE
) {
2205 // Legalize the type.
2206 std::pair
<int, MVT
> LT
= TLI
->getTypeLegalizationCost(DL
, OpTy
);
2207 MVT MTy
= LT
.second
;
2209 // Attempt to lookup cost.
2211 if (const auto *Entry
= CostTableLookup(GLMCostTbl
, ISD
, MTy
))
2212 return LT
.first
* Entry
->Cost
;
2215 if (const auto *Entry
= CostTableLookup(SLMCostTbl
, ISD
, MTy
))
2216 return LT
.first
* Entry
->Cost
;
2219 if (const auto *Entry
= CostTableLookup(AVX512CDCostTbl
, ISD
, MTy
))
2220 return LT
.first
* Entry
->Cost
;
2223 if (const auto *Entry
= CostTableLookup(AVX512BWCostTbl
, ISD
, MTy
))
2224 return LT
.first
* Entry
->Cost
;
2226 if (ST
->hasAVX512())
2227 if (const auto *Entry
= CostTableLookup(AVX512CostTbl
, ISD
, MTy
))
2228 return LT
.first
* Entry
->Cost
;
2231 if (const auto *Entry
= CostTableLookup(XOPCostTbl
, ISD
, MTy
))
2232 return LT
.first
* Entry
->Cost
;
2235 if (const auto *Entry
= CostTableLookup(AVX2CostTbl
, ISD
, MTy
))
2236 return LT
.first
* Entry
->Cost
;
2239 if (const auto *Entry
= CostTableLookup(AVX1CostTbl
, ISD
, MTy
))
2240 return LT
.first
* Entry
->Cost
;
2243 if (const auto *Entry
= CostTableLookup(SSE42CostTbl
, ISD
, MTy
))
2244 return LT
.first
* Entry
->Cost
;
2247 if (const auto *Entry
= CostTableLookup(SSSE3CostTbl
, ISD
, MTy
))
2248 return LT
.first
* Entry
->Cost
;
2251 if (const auto *Entry
= CostTableLookup(SSE2CostTbl
, ISD
, MTy
))
2252 return LT
.first
* Entry
->Cost
;
2255 if (const auto *Entry
= CostTableLookup(SSE1CostTbl
, ISD
, MTy
))
2256 return LT
.first
* Entry
->Cost
;
2259 if (const auto *Entry
= CostTableLookup(X64CostTbl
, ISD
, MTy
))
2260 return LT
.first
* Entry
->Cost
;
2262 if (const auto *Entry
= CostTableLookup(X86CostTbl
, ISD
, MTy
))
2263 return LT
.first
* Entry
->Cost
;
2266 return BaseT::getIntrinsicInstrCost(IID
, RetTy
, Tys
, FMF
, ScalarizationCostPassed
);
2269 int X86TTIImpl::getIntrinsicInstrCost(Intrinsic::ID IID
, Type
*RetTy
,
2270 ArrayRef
<Value
*> Args
, FastMathFlags FMF
,
2272 static const CostTblEntry AVX512CostTbl
[] = {
2273 { ISD::ROTL
, MVT::v8i64
, 1 },
2274 { ISD::ROTL
, MVT::v4i64
, 1 },
2275 { ISD::ROTL
, MVT::v2i64
, 1 },
2276 { ISD::ROTL
, MVT::v16i32
, 1 },
2277 { ISD::ROTL
, MVT::v8i32
, 1 },
2278 { ISD::ROTL
, MVT::v4i32
, 1 },
2279 { ISD::ROTR
, MVT::v8i64
, 1 },
2280 { ISD::ROTR
, MVT::v4i64
, 1 },
2281 { ISD::ROTR
, MVT::v2i64
, 1 },
2282 { ISD::ROTR
, MVT::v16i32
, 1 },
2283 { ISD::ROTR
, MVT::v8i32
, 1 },
2284 { ISD::ROTR
, MVT::v4i32
, 1 }
2286 // XOP: ROTL = VPROT(X,Y), ROTR = VPROT(X,SUB(0,Y))
2287 static const CostTblEntry XOPCostTbl
[] = {
2288 { ISD::ROTL
, MVT::v4i64
, 4 },
2289 { ISD::ROTL
, MVT::v8i32
, 4 },
2290 { ISD::ROTL
, MVT::v16i16
, 4 },
2291 { ISD::ROTL
, MVT::v32i8
, 4 },
2292 { ISD::ROTL
, MVT::v2i64
, 1 },
2293 { ISD::ROTL
, MVT::v4i32
, 1 },
2294 { ISD::ROTL
, MVT::v8i16
, 1 },
2295 { ISD::ROTL
, MVT::v16i8
, 1 },
2296 { ISD::ROTR
, MVT::v4i64
, 6 },
2297 { ISD::ROTR
, MVT::v8i32
, 6 },
2298 { ISD::ROTR
, MVT::v16i16
, 6 },
2299 { ISD::ROTR
, MVT::v32i8
, 6 },
2300 { ISD::ROTR
, MVT::v2i64
, 2 },
2301 { ISD::ROTR
, MVT::v4i32
, 2 },
2302 { ISD::ROTR
, MVT::v8i16
, 2 },
2303 { ISD::ROTR
, MVT::v16i8
, 2 }
2305 static const CostTblEntry X64CostTbl
[] = { // 64-bit targets
2306 { ISD::ROTL
, MVT::i64
, 1 },
2307 { ISD::ROTR
, MVT::i64
, 1 },
2308 { ISD::FSHL
, MVT::i64
, 4 }
2310 static const CostTblEntry X86CostTbl
[] = { // 32 or 64-bit targets
2311 { ISD::ROTL
, MVT::i32
, 1 },
2312 { ISD::ROTL
, MVT::i16
, 1 },
2313 { ISD::ROTL
, MVT::i8
, 1 },
2314 { ISD::ROTR
, MVT::i32
, 1 },
2315 { ISD::ROTR
, MVT::i16
, 1 },
2316 { ISD::ROTR
, MVT::i8
, 1 },
2317 { ISD::FSHL
, MVT::i32
, 4 },
2318 { ISD::FSHL
, MVT::i16
, 4 },
2319 { ISD::FSHL
, MVT::i8
, 4 }
2322 unsigned ISD
= ISD::DELETED_NODE
;
2326 case Intrinsic::fshl
:
2328 if (Args
[0] == Args
[1])
2331 case Intrinsic::fshr
:
2332 // FSHR has same costs so don't duplicate.
2334 if (Args
[0] == Args
[1])
2339 if (ISD
!= ISD::DELETED_NODE
) {
2340 // Legalize the type.
2341 std::pair
<int, MVT
> LT
= TLI
->getTypeLegalizationCost(DL
, RetTy
);
2342 MVT MTy
= LT
.second
;
2344 // Attempt to lookup cost.
2345 if (ST
->hasAVX512())
2346 if (const auto *Entry
= CostTableLookup(AVX512CostTbl
, ISD
, MTy
))
2347 return LT
.first
* Entry
->Cost
;
2350 if (const auto *Entry
= CostTableLookup(XOPCostTbl
, ISD
, MTy
))
2351 return LT
.first
* Entry
->Cost
;
2354 if (const auto *Entry
= CostTableLookup(X64CostTbl
, ISD
, MTy
))
2355 return LT
.first
* Entry
->Cost
;
2357 if (const auto *Entry
= CostTableLookup(X86CostTbl
, ISD
, MTy
))
2358 return LT
.first
* Entry
->Cost
;
2361 return BaseT::getIntrinsicInstrCost(IID
, RetTy
, Args
, FMF
, VF
);
2364 int X86TTIImpl::getVectorInstrCost(unsigned Opcode
, Type
*Val
, unsigned Index
) {
2365 assert(Val
->isVectorTy() && "This must be a vector type");
2367 Type
*ScalarType
= Val
->getScalarType();
2370 // Legalize the type.
2371 std::pair
<int, MVT
> LT
= TLI
->getTypeLegalizationCost(DL
, Val
);
2373 // This type is legalized to a scalar type.
2374 if (!LT
.second
.isVector())
2377 // The type may be split. Normalize the index to the new type.
2378 unsigned Width
= LT
.second
.getVectorNumElements();
2379 Index
= Index
% Width
;
2381 // Floating point scalars are already located in index #0.
2382 if (ScalarType
->isFloatingPointTy() && Index
== 0)
2386 // Add to the base cost if we know that the extracted element of a vector is
2387 // destined to be moved to and used in the integer register file.
2388 int RegisterFileMoveCost
= 0;
2389 if (Opcode
== Instruction::ExtractElement
&& ScalarType
->isPointerTy())
2390 RegisterFileMoveCost
= 1;
2392 return BaseT::getVectorInstrCost(Opcode
, Val
, Index
) + RegisterFileMoveCost
;
2395 int X86TTIImpl::getMemoryOpCost(unsigned Opcode
, Type
*Src
, unsigned Alignment
,
2396 unsigned AddressSpace
, const Instruction
*I
) {
2397 // Handle non-power-of-two vectors such as <3 x float>
2398 if (VectorType
*VTy
= dyn_cast
<VectorType
>(Src
)) {
2399 unsigned NumElem
= VTy
->getVectorNumElements();
2401 // Handle a few common cases:
2403 if (NumElem
== 3 && VTy
->getScalarSizeInBits() == 32)
2404 // Cost = 64 bit store + extract + 32 bit store.
2408 if (NumElem
== 3 && VTy
->getScalarSizeInBits() == 64)
2409 // Cost = 128 bit store + unpack + 64 bit store.
2412 // Assume that all other non-power-of-two numbers are scalarized.
2413 if (!isPowerOf2_32(NumElem
)) {
2414 int Cost
= BaseT::getMemoryOpCost(Opcode
, VTy
->getScalarType(), Alignment
,
2416 int SplitCost
= getScalarizationOverhead(Src
, Opcode
== Instruction::Load
,
2417 Opcode
== Instruction::Store
);
2418 return NumElem
* Cost
+ SplitCost
;
2422 // Legalize the type.
2423 std::pair
<int, MVT
> LT
= TLI
->getTypeLegalizationCost(DL
, Src
);
2424 assert((Opcode
== Instruction::Load
|| Opcode
== Instruction::Store
) &&
2427 // Each load/store unit costs 1.
2428 int Cost
= LT
.first
* 1;
2430 // This isn't exactly right. We're using slow unaligned 32-byte accesses as a
2431 // proxy for a double-pumped AVX memory interface such as on Sandybridge.
2432 if (LT
.second
.getStoreSize() == 32 && ST
->isUnalignedMem32Slow())
2438 int X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode
, Type
*SrcTy
,
2440 unsigned AddressSpace
) {
2441 bool IsLoad
= (Instruction::Load
== Opcode
);
2442 bool IsStore
= (Instruction::Store
== Opcode
);
2444 VectorType
*SrcVTy
= dyn_cast
<VectorType
>(SrcTy
);
2446 // To calculate scalar take the regular cost, without mask
2447 return getMemoryOpCost(Opcode
, SrcTy
, Alignment
, AddressSpace
);
2449 unsigned NumElem
= SrcVTy
->getVectorNumElements();
2450 VectorType
*MaskTy
=
2451 VectorType::get(Type::getInt8Ty(SrcVTy
->getContext()), NumElem
);
2452 if ((IsLoad
&& !isLegalMaskedLoad(SrcVTy
)) ||
2453 (IsStore
&& !isLegalMaskedStore(SrcVTy
)) || !isPowerOf2_32(NumElem
)) {
2455 int MaskSplitCost
= getScalarizationOverhead(MaskTy
, false, true);
2456 int ScalarCompareCost
= getCmpSelInstrCost(
2457 Instruction::ICmp
, Type::getInt8Ty(SrcVTy
->getContext()), nullptr);
2458 int BranchCost
= getCFInstrCost(Instruction::Br
);
2459 int MaskCmpCost
= NumElem
* (BranchCost
+ ScalarCompareCost
);
2461 int ValueSplitCost
= getScalarizationOverhead(SrcVTy
, IsLoad
, IsStore
);
2463 NumElem
* BaseT::getMemoryOpCost(Opcode
, SrcVTy
->getScalarType(),
2464 Alignment
, AddressSpace
);
2465 return MemopCost
+ ValueSplitCost
+ MaskSplitCost
+ MaskCmpCost
;
2468 // Legalize the type.
2469 std::pair
<int, MVT
> LT
= TLI
->getTypeLegalizationCost(DL
, SrcVTy
);
2470 auto VT
= TLI
->getValueType(DL
, SrcVTy
);
2472 if (VT
.isSimple() && LT
.second
!= VT
.getSimpleVT() &&
2473 LT
.second
.getVectorNumElements() == NumElem
)
2474 // Promotion requires expand/truncate for data and a shuffle for mask.
2475 Cost
+= getShuffleCost(TTI::SK_PermuteTwoSrc
, SrcVTy
, 0, nullptr) +
2476 getShuffleCost(TTI::SK_PermuteTwoSrc
, MaskTy
, 0, nullptr);
2478 else if (LT
.second
.getVectorNumElements() > NumElem
) {
2479 VectorType
*NewMaskTy
= VectorType::get(MaskTy
->getVectorElementType(),
2480 LT
.second
.getVectorNumElements());
2481 // Expanding requires fill mask with zeroes
2482 Cost
+= getShuffleCost(TTI::SK_InsertSubvector
, NewMaskTy
, 0, MaskTy
);
2485 // Pre-AVX512 - each maskmov load costs 2 + store costs ~8.
2486 if (!ST
->hasAVX512())
2487 return Cost
+ LT
.first
* (IsLoad
? 2 : 8);
2489 // AVX-512 masked load/store is cheapper
2490 return Cost
+ LT
.first
;
2493 int X86TTIImpl::getAddressComputationCost(Type
*Ty
, ScalarEvolution
*SE
,
2495 // Address computations in vectorized code with non-consecutive addresses will
2496 // likely result in more instructions compared to scalar code where the
2497 // computation can more often be merged into the index mode. The resulting
2498 // extra micro-ops can significantly decrease throughput.
2499 const unsigned NumVectorInstToHideOverhead
= 10;
2501 // Cost modeling of Strided Access Computation is hidden by the indexing
2502 // modes of X86 regardless of the stride value. We dont believe that there
2503 // is a difference between constant strided access in gerenal and constant
2504 // strided value which is less than or equal to 64.
2505 // Even in the case of (loop invariant) stride whose value is not known at
2506 // compile time, the address computation will not incur more than one extra
2508 if (Ty
->isVectorTy() && SE
) {
2509 if (!BaseT::isStridedAccess(Ptr
))
2510 return NumVectorInstToHideOverhead
;
2511 if (!BaseT::getConstantStrideStep(SE
, Ptr
))
2515 return BaseT::getAddressComputationCost(Ty
, SE
, Ptr
);
2518 int X86TTIImpl::getArithmeticReductionCost(unsigned Opcode
, Type
*ValTy
,
2520 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput
2521 // and make it as the cost.
2523 static const CostTblEntry SSE42CostTblPairWise
[] = {
2524 { ISD::FADD
, MVT::v2f64
, 2 },
2525 { ISD::FADD
, MVT::v4f32
, 4 },
2526 { ISD::ADD
, MVT::v2i64
, 2 }, // The data reported by the IACA tool is "1.6".
2527 { ISD::ADD
, MVT::v2i32
, 2 }, // FIXME: chosen to be less than v4i32.
2528 { ISD::ADD
, MVT::v4i32
, 3 }, // The data reported by the IACA tool is "3.5".
2529 { ISD::ADD
, MVT::v2i16
, 3 }, // FIXME: chosen to be less than v4i16
2530 { ISD::ADD
, MVT::v4i16
, 4 }, // FIXME: chosen to be less than v8i16
2531 { ISD::ADD
, MVT::v8i16
, 5 },
2534 static const CostTblEntry AVX1CostTblPairWise
[] = {
2535 { ISD::FADD
, MVT::v4f32
, 4 },
2536 { ISD::FADD
, MVT::v4f64
, 5 },
2537 { ISD::FADD
, MVT::v8f32
, 7 },
2538 { ISD::ADD
, MVT::v2i64
, 1 }, // The data reported by the IACA tool is "1.5".
2539 { ISD::ADD
, MVT::v2i32
, 2 }, // FIXME: chosen to be less than v4i32
2540 { ISD::ADD
, MVT::v4i32
, 3 }, // The data reported by the IACA tool is "3.5".
2541 { ISD::ADD
, MVT::v4i64
, 5 }, // The data reported by the IACA tool is "4.8".
2542 { ISD::ADD
, MVT::v2i16
, 3 }, // FIXME: chosen to be less than v4i16
2543 { ISD::ADD
, MVT::v4i16
, 4 }, // FIXME: chosen to be less than v8i16
2544 { ISD::ADD
, MVT::v8i16
, 5 },
2545 { ISD::ADD
, MVT::v8i32
, 5 },
2548 static const CostTblEntry SSE42CostTblNoPairWise
[] = {
2549 { ISD::FADD
, MVT::v2f64
, 2 },
2550 { ISD::FADD
, MVT::v4f32
, 4 },
2551 { ISD::ADD
, MVT::v2i64
, 2 }, // The data reported by the IACA tool is "1.6".
2552 { ISD::ADD
, MVT::v2i32
, 2 }, // FIXME: chosen to be less than v4i32
2553 { ISD::ADD
, MVT::v4i32
, 3 }, // The data reported by the IACA tool is "3.3".
2554 { ISD::ADD
, MVT::v2i16
, 2 }, // The data reported by the IACA tool is "4.3".
2555 { ISD::ADD
, MVT::v4i16
, 3 }, // The data reported by the IACA tool is "4.3".
2556 { ISD::ADD
, MVT::v8i16
, 4 }, // The data reported by the IACA tool is "4.3".
2559 static const CostTblEntry AVX1CostTblNoPairWise
[] = {
2560 { ISD::FADD
, MVT::v4f32
, 3 },
2561 { ISD::FADD
, MVT::v4f64
, 3 },
2562 { ISD::FADD
, MVT::v8f32
, 4 },
2563 { ISD::ADD
, MVT::v2i64
, 1 }, // The data reported by the IACA tool is "1.5".
2564 { ISD::ADD
, MVT::v2i32
, 2 }, // FIXME: chosen to be less than v4i32
2565 { ISD::ADD
, MVT::v4i32
, 3 }, // The data reported by the IACA tool is "2.8".
2566 { ISD::ADD
, MVT::v4i64
, 3 },
2567 { ISD::ADD
, MVT::v2i16
, 2 }, // The data reported by the IACA tool is "4.3".
2568 { ISD::ADD
, MVT::v4i16
, 3 }, // The data reported by the IACA tool is "4.3".
2569 { ISD::ADD
, MVT::v8i16
, 4 },
2570 { ISD::ADD
, MVT::v8i32
, 5 },
2573 int ISD
= TLI
->InstructionOpcodeToISD(Opcode
);
2574 assert(ISD
&& "Invalid opcode");
2576 // Before legalizing the type, give a chance to look up illegal narrow types
2578 // FIXME: Is there a better way to do this?
2579 EVT VT
= TLI
->getValueType(DL
, ValTy
);
2580 if (VT
.isSimple() && ExperimentalVectorWideningLegalization
) {
2581 MVT MTy
= VT
.getSimpleVT();
2584 if (const auto *Entry
= CostTableLookup(AVX1CostTblPairWise
, ISD
, MTy
))
2588 if (const auto *Entry
= CostTableLookup(SSE42CostTblPairWise
, ISD
, MTy
))
2592 if (const auto *Entry
= CostTableLookup(AVX1CostTblNoPairWise
, ISD
, MTy
))
2596 if (const auto *Entry
= CostTableLookup(SSE42CostTblNoPairWise
, ISD
, MTy
))
2601 std::pair
<int, MVT
> LT
= TLI
->getTypeLegalizationCost(DL
, ValTy
);
2603 MVT MTy
= LT
.second
;
2607 if (const auto *Entry
= CostTableLookup(AVX1CostTblPairWise
, ISD
, MTy
))
2608 return LT
.first
* Entry
->Cost
;
2611 if (const auto *Entry
= CostTableLookup(SSE42CostTblPairWise
, ISD
, MTy
))
2612 return LT
.first
* Entry
->Cost
;
2615 if (const auto *Entry
= CostTableLookup(AVX1CostTblNoPairWise
, ISD
, MTy
))
2616 return LT
.first
* Entry
->Cost
;
2619 if (const auto *Entry
= CostTableLookup(SSE42CostTblNoPairWise
, ISD
, MTy
))
2620 return LT
.first
* Entry
->Cost
;
2623 static const CostTblEntry AVX2BoolReduction
[] = {
2624 { ISD::AND
, MVT::v16i16
, 2 }, // vpmovmskb + cmp
2625 { ISD::AND
, MVT::v32i8
, 2 }, // vpmovmskb + cmp
2626 { ISD::OR
, MVT::v16i16
, 2 }, // vpmovmskb + cmp
2627 { ISD::OR
, MVT::v32i8
, 2 }, // vpmovmskb + cmp
2630 static const CostTblEntry AVX1BoolReduction
[] = {
2631 { ISD::AND
, MVT::v4i64
, 2 }, // vmovmskpd + cmp
2632 { ISD::AND
, MVT::v8i32
, 2 }, // vmovmskps + cmp
2633 { ISD::AND
, MVT::v16i16
, 4 }, // vextractf128 + vpand + vpmovmskb + cmp
2634 { ISD::AND
, MVT::v32i8
, 4 }, // vextractf128 + vpand + vpmovmskb + cmp
2635 { ISD::OR
, MVT::v4i64
, 2 }, // vmovmskpd + cmp
2636 { ISD::OR
, MVT::v8i32
, 2 }, // vmovmskps + cmp
2637 { ISD::OR
, MVT::v16i16
, 4 }, // vextractf128 + vpor + vpmovmskb + cmp
2638 { ISD::OR
, MVT::v32i8
, 4 }, // vextractf128 + vpor + vpmovmskb + cmp
2641 static const CostTblEntry SSE2BoolReduction
[] = {
2642 { ISD::AND
, MVT::v2i64
, 2 }, // movmskpd + cmp
2643 { ISD::AND
, MVT::v4i32
, 2 }, // movmskps + cmp
2644 { ISD::AND
, MVT::v8i16
, 2 }, // pmovmskb + cmp
2645 { ISD::AND
, MVT::v16i8
, 2 }, // pmovmskb + cmp
2646 { ISD::OR
, MVT::v2i64
, 2 }, // movmskpd + cmp
2647 { ISD::OR
, MVT::v4i32
, 2 }, // movmskps + cmp
2648 { ISD::OR
, MVT::v8i16
, 2 }, // pmovmskb + cmp
2649 { ISD::OR
, MVT::v16i8
, 2 }, // pmovmskb + cmp
2652 // Handle bool allof/anyof patterns.
2653 if (ValTy
->getVectorElementType()->isIntegerTy(1)) {
2655 if (const auto *Entry
= CostTableLookup(AVX2BoolReduction
, ISD
, MTy
))
2656 return LT
.first
* Entry
->Cost
;
2658 if (const auto *Entry
= CostTableLookup(AVX1BoolReduction
, ISD
, MTy
))
2659 return LT
.first
* Entry
->Cost
;
2661 if (const auto *Entry
= CostTableLookup(SSE2BoolReduction
, ISD
, MTy
))
2662 return LT
.first
* Entry
->Cost
;
2665 return BaseT::getArithmeticReductionCost(Opcode
, ValTy
, IsPairwise
);
2668 int X86TTIImpl::getMinMaxReductionCost(Type
*ValTy
, Type
*CondTy
,
2669 bool IsPairwise
, bool IsUnsigned
) {
2670 std::pair
<int, MVT
> LT
= TLI
->getTypeLegalizationCost(DL
, ValTy
);
2672 MVT MTy
= LT
.second
;
2675 if (ValTy
->isIntOrIntVectorTy()) {
2676 ISD
= IsUnsigned
? ISD::UMIN
: ISD::SMIN
;
2678 assert(ValTy
->isFPOrFPVectorTy() &&
2679 "Expected float point or integer vector type.");
2683 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput
2684 // and make it as the cost.
2686 static const CostTblEntry SSE1CostTblPairWise
[] = {
2687 {ISD::FMINNUM
, MVT::v4f32
, 4},
2690 static const CostTblEntry SSE2CostTblPairWise
[] = {
2691 {ISD::FMINNUM
, MVT::v2f64
, 3},
2692 {ISD::SMIN
, MVT::v2i64
, 6},
2693 {ISD::UMIN
, MVT::v2i64
, 8},
2694 {ISD::SMIN
, MVT::v4i32
, 6},
2695 {ISD::UMIN
, MVT::v4i32
, 8},
2696 {ISD::SMIN
, MVT::v8i16
, 4},
2697 {ISD::UMIN
, MVT::v8i16
, 6},
2698 {ISD::SMIN
, MVT::v16i8
, 8},
2699 {ISD::UMIN
, MVT::v16i8
, 6},
2702 static const CostTblEntry SSE41CostTblPairWise
[] = {
2703 {ISD::FMINNUM
, MVT::v4f32
, 2},
2704 {ISD::SMIN
, MVT::v2i64
, 9},
2705 {ISD::UMIN
, MVT::v2i64
,10},
2706 {ISD::SMIN
, MVT::v4i32
, 1}, // The data reported by the IACA is "1.5"
2707 {ISD::UMIN
, MVT::v4i32
, 2}, // The data reported by the IACA is "1.8"
2708 {ISD::SMIN
, MVT::v8i16
, 2},
2709 {ISD::UMIN
, MVT::v8i16
, 2},
2710 {ISD::SMIN
, MVT::v16i8
, 3},
2711 {ISD::UMIN
, MVT::v16i8
, 3},
2714 static const CostTblEntry SSE42CostTblPairWise
[] = {
2715 {ISD::SMIN
, MVT::v2i64
, 7}, // The data reported by the IACA is "6.8"
2716 {ISD::UMIN
, MVT::v2i64
, 8}, // The data reported by the IACA is "8.6"
2719 static const CostTblEntry AVX1CostTblPairWise
[] = {
2720 {ISD::FMINNUM
, MVT::v4f32
, 1},
2721 {ISD::FMINNUM
, MVT::v4f64
, 1},
2722 {ISD::FMINNUM
, MVT::v8f32
, 2},
2723 {ISD::SMIN
, MVT::v2i64
, 3},
2724 {ISD::UMIN
, MVT::v2i64
, 3},
2725 {ISD::SMIN
, MVT::v4i32
, 1},
2726 {ISD::UMIN
, MVT::v4i32
, 1},
2727 {ISD::SMIN
, MVT::v8i16
, 1},
2728 {ISD::UMIN
, MVT::v8i16
, 1},
2729 {ISD::SMIN
, MVT::v16i8
, 2},
2730 {ISD::UMIN
, MVT::v16i8
, 2},
2731 {ISD::SMIN
, MVT::v4i64
, 7},
2732 {ISD::UMIN
, MVT::v4i64
, 7},
2733 {ISD::SMIN
, MVT::v8i32
, 3},
2734 {ISD::UMIN
, MVT::v8i32
, 3},
2735 {ISD::SMIN
, MVT::v16i16
, 3},
2736 {ISD::UMIN
, MVT::v16i16
, 3},
2737 {ISD::SMIN
, MVT::v32i8
, 3},
2738 {ISD::UMIN
, MVT::v32i8
, 3},
2741 static const CostTblEntry AVX2CostTblPairWise
[] = {
2742 {ISD::SMIN
, MVT::v4i64
, 2},
2743 {ISD::UMIN
, MVT::v4i64
, 2},
2744 {ISD::SMIN
, MVT::v8i32
, 1},
2745 {ISD::UMIN
, MVT::v8i32
, 1},
2746 {ISD::SMIN
, MVT::v16i16
, 1},
2747 {ISD::UMIN
, MVT::v16i16
, 1},
2748 {ISD::SMIN
, MVT::v32i8
, 2},
2749 {ISD::UMIN
, MVT::v32i8
, 2},
2752 static const CostTblEntry AVX512CostTblPairWise
[] = {
2753 {ISD::FMINNUM
, MVT::v8f64
, 1},
2754 {ISD::FMINNUM
, MVT::v16f32
, 2},
2755 {ISD::SMIN
, MVT::v8i64
, 2},
2756 {ISD::UMIN
, MVT::v8i64
, 2},
2757 {ISD::SMIN
, MVT::v16i32
, 1},
2758 {ISD::UMIN
, MVT::v16i32
, 1},
2761 static const CostTblEntry SSE1CostTblNoPairWise
[] = {
2762 {ISD::FMINNUM
, MVT::v4f32
, 4},
2765 static const CostTblEntry SSE2CostTblNoPairWise
[] = {
2766 {ISD::FMINNUM
, MVT::v2f64
, 3},
2767 {ISD::SMIN
, MVT::v2i64
, 6},
2768 {ISD::UMIN
, MVT::v2i64
, 8},
2769 {ISD::SMIN
, MVT::v4i32
, 6},
2770 {ISD::UMIN
, MVT::v4i32
, 8},
2771 {ISD::SMIN
, MVT::v8i16
, 4},
2772 {ISD::UMIN
, MVT::v8i16
, 6},
2773 {ISD::SMIN
, MVT::v16i8
, 8},
2774 {ISD::UMIN
, MVT::v16i8
, 6},
2777 static const CostTblEntry SSE41CostTblNoPairWise
[] = {
2778 {ISD::FMINNUM
, MVT::v4f32
, 3},
2779 {ISD::SMIN
, MVT::v2i64
, 9},
2780 {ISD::UMIN
, MVT::v2i64
,11},
2781 {ISD::SMIN
, MVT::v4i32
, 1}, // The data reported by the IACA is "1.5"
2782 {ISD::UMIN
, MVT::v4i32
, 2}, // The data reported by the IACA is "1.8"
2783 {ISD::SMIN
, MVT::v8i16
, 1}, // The data reported by the IACA is "1.5"
2784 {ISD::UMIN
, MVT::v8i16
, 2}, // The data reported by the IACA is "1.8"
2785 {ISD::SMIN
, MVT::v16i8
, 3},
2786 {ISD::UMIN
, MVT::v16i8
, 3},
2789 static const CostTblEntry SSE42CostTblNoPairWise
[] = {
2790 {ISD::SMIN
, MVT::v2i64
, 7}, // The data reported by the IACA is "6.8"
2791 {ISD::UMIN
, MVT::v2i64
, 9}, // The data reported by the IACA is "8.6"
2794 static const CostTblEntry AVX1CostTblNoPairWise
[] = {
2795 {ISD::FMINNUM
, MVT::v4f32
, 1},
2796 {ISD::FMINNUM
, MVT::v4f64
, 1},
2797 {ISD::FMINNUM
, MVT::v8f32
, 1},
2798 {ISD::SMIN
, MVT::v2i64
, 3},
2799 {ISD::UMIN
, MVT::v2i64
, 3},
2800 {ISD::SMIN
, MVT::v4i32
, 1},
2801 {ISD::UMIN
, MVT::v4i32
, 1},
2802 {ISD::SMIN
, MVT::v8i16
, 1},
2803 {ISD::UMIN
, MVT::v8i16
, 1},
2804 {ISD::SMIN
, MVT::v16i8
, 2},
2805 {ISD::UMIN
, MVT::v16i8
, 2},
2806 {ISD::SMIN
, MVT::v4i64
, 7},
2807 {ISD::UMIN
, MVT::v4i64
, 7},
2808 {ISD::SMIN
, MVT::v8i32
, 2},
2809 {ISD::UMIN
, MVT::v8i32
, 2},
2810 {ISD::SMIN
, MVT::v16i16
, 2},
2811 {ISD::UMIN
, MVT::v16i16
, 2},
2812 {ISD::SMIN
, MVT::v32i8
, 2},
2813 {ISD::UMIN
, MVT::v32i8
, 2},
2816 static const CostTblEntry AVX2CostTblNoPairWise
[] = {
2817 {ISD::SMIN
, MVT::v4i64
, 1},
2818 {ISD::UMIN
, MVT::v4i64
, 1},
2819 {ISD::SMIN
, MVT::v8i32
, 1},
2820 {ISD::UMIN
, MVT::v8i32
, 1},
2821 {ISD::SMIN
, MVT::v16i16
, 1},
2822 {ISD::UMIN
, MVT::v16i16
, 1},
2823 {ISD::SMIN
, MVT::v32i8
, 1},
2824 {ISD::UMIN
, MVT::v32i8
, 1},
2827 static const CostTblEntry AVX512CostTblNoPairWise
[] = {
2828 {ISD::FMINNUM
, MVT::v8f64
, 1},
2829 {ISD::FMINNUM
, MVT::v16f32
, 2},
2830 {ISD::SMIN
, MVT::v8i64
, 1},
2831 {ISD::UMIN
, MVT::v8i64
, 1},
2832 {ISD::SMIN
, MVT::v16i32
, 1},
2833 {ISD::UMIN
, MVT::v16i32
, 1},
2837 if (ST
->hasAVX512())
2838 if (const auto *Entry
= CostTableLookup(AVX512CostTblPairWise
, ISD
, MTy
))
2839 return LT
.first
* Entry
->Cost
;
2842 if (const auto *Entry
= CostTableLookup(AVX2CostTblPairWise
, ISD
, MTy
))
2843 return LT
.first
* Entry
->Cost
;
2846 if (const auto *Entry
= CostTableLookup(AVX1CostTblPairWise
, ISD
, MTy
))
2847 return LT
.first
* Entry
->Cost
;
2850 if (const auto *Entry
= CostTableLookup(SSE42CostTblPairWise
, ISD
, MTy
))
2851 return LT
.first
* Entry
->Cost
;
2854 if (const auto *Entry
= CostTableLookup(SSE41CostTblPairWise
, ISD
, MTy
))
2855 return LT
.first
* Entry
->Cost
;
2858 if (const auto *Entry
= CostTableLookup(SSE2CostTblPairWise
, ISD
, MTy
))
2859 return LT
.first
* Entry
->Cost
;
2862 if (const auto *Entry
= CostTableLookup(SSE1CostTblPairWise
, ISD
, MTy
))
2863 return LT
.first
* Entry
->Cost
;
2865 if (ST
->hasAVX512())
2866 if (const auto *Entry
=
2867 CostTableLookup(AVX512CostTblNoPairWise
, ISD
, MTy
))
2868 return LT
.first
* Entry
->Cost
;
2871 if (const auto *Entry
= CostTableLookup(AVX2CostTblNoPairWise
, ISD
, MTy
))
2872 return LT
.first
* Entry
->Cost
;
2875 if (const auto *Entry
= CostTableLookup(AVX1CostTblNoPairWise
, ISD
, MTy
))
2876 return LT
.first
* Entry
->Cost
;
2879 if (const auto *Entry
= CostTableLookup(SSE42CostTblNoPairWise
, ISD
, MTy
))
2880 return LT
.first
* Entry
->Cost
;
2883 if (const auto *Entry
= CostTableLookup(SSE41CostTblNoPairWise
, ISD
, MTy
))
2884 return LT
.first
* Entry
->Cost
;
2887 if (const auto *Entry
= CostTableLookup(SSE2CostTblNoPairWise
, ISD
, MTy
))
2888 return LT
.first
* Entry
->Cost
;
2891 if (const auto *Entry
= CostTableLookup(SSE1CostTblNoPairWise
, ISD
, MTy
))
2892 return LT
.first
* Entry
->Cost
;
2895 return BaseT::getMinMaxReductionCost(ValTy
, CondTy
, IsPairwise
, IsUnsigned
);
2898 /// Calculate the cost of materializing a 64-bit value. This helper
2899 /// method might only calculate a fraction of a larger immediate. Therefore it
2900 /// is valid to return a cost of ZERO.
2901 int X86TTIImpl::getIntImmCost(int64_t Val
) {
2903 return TTI::TCC_Free
;
2906 return TTI::TCC_Basic
;
2908 return 2 * TTI::TCC_Basic
;
2911 int X86TTIImpl::getIntImmCost(const APInt
&Imm
, Type
*Ty
) {
2912 assert(Ty
->isIntegerTy());
2914 unsigned BitSize
= Ty
->getPrimitiveSizeInBits();
2918 // Never hoist constants larger than 128bit, because this might lead to
2919 // incorrect code generation or assertions in codegen.
2920 // Fixme: Create a cost model for types larger than i128 once the codegen
2921 // issues have been fixed.
2923 return TTI::TCC_Free
;
2926 return TTI::TCC_Free
;
2928 // Sign-extend all constants to a multiple of 64-bit.
2930 if (BitSize
% 64 != 0)
2931 ImmVal
= Imm
.sext(alignTo(BitSize
, 64));
2933 // Split the constant into 64-bit chunks and calculate the cost for each
2936 for (unsigned ShiftVal
= 0; ShiftVal
< BitSize
; ShiftVal
+= 64) {
2937 APInt Tmp
= ImmVal
.ashr(ShiftVal
).sextOrTrunc(64);
2938 int64_t Val
= Tmp
.getSExtValue();
2939 Cost
+= getIntImmCost(Val
);
2941 // We need at least one instruction to materialize the constant.
2942 return std::max(1, Cost
);
2945 int X86TTIImpl::getIntImmCost(unsigned Opcode
, unsigned Idx
, const APInt
&Imm
,
2947 assert(Ty
->isIntegerTy());
2949 unsigned BitSize
= Ty
->getPrimitiveSizeInBits();
2950 // There is no cost model for constants with a bit size of 0. Return TCC_Free
2951 // here, so that constant hoisting will ignore this constant.
2953 return TTI::TCC_Free
;
2955 unsigned ImmIdx
= ~0U;
2958 return TTI::TCC_Free
;
2959 case Instruction::GetElementPtr
:
2960 // Always hoist the base address of a GetElementPtr. This prevents the
2961 // creation of new constants for every base constant that gets constant
2962 // folded with the offset.
2964 return 2 * TTI::TCC_Basic
;
2965 return TTI::TCC_Free
;
2966 case Instruction::Store
:
2969 case Instruction::ICmp
:
2970 // This is an imperfect hack to prevent constant hoisting of
2971 // compares that might be trying to check if a 64-bit value fits in
2972 // 32-bits. The backend can optimize these cases using a right shift by 32.
2973 // Ideally we would check the compare predicate here. There also other
2974 // similar immediates the backend can use shifts for.
2975 if (Idx
== 1 && Imm
.getBitWidth() == 64) {
2976 uint64_t ImmVal
= Imm
.getZExtValue();
2977 if (ImmVal
== 0x100000000ULL
|| ImmVal
== 0xffffffff)
2978 return TTI::TCC_Free
;
2982 case Instruction::And
:
2983 // We support 64-bit ANDs with immediates with 32-bits of leading zeroes
2984 // by using a 32-bit operation with implicit zero extension. Detect such
2985 // immediates here as the normal path expects bit 31 to be sign extended.
2986 if (Idx
== 1 && Imm
.getBitWidth() == 64 && isUInt
<32>(Imm
.getZExtValue()))
2987 return TTI::TCC_Free
;
2990 case Instruction::Add
:
2991 case Instruction::Sub
:
2992 // For add/sub, we can use the opposite instruction for INT32_MIN.
2993 if (Idx
== 1 && Imm
.getBitWidth() == 64 && Imm
.getZExtValue() == 0x80000000)
2994 return TTI::TCC_Free
;
2997 case Instruction::UDiv
:
2998 case Instruction::SDiv
:
2999 case Instruction::URem
:
3000 case Instruction::SRem
:
3001 // Division by constant is typically expanded later into a different
3002 // instruction sequence. This completely changes the constants.
3003 // Report them as "free" to stop ConstantHoist from marking them as opaque.
3004 return TTI::TCC_Free
;
3005 case Instruction::Mul
:
3006 case Instruction::Or
:
3007 case Instruction::Xor
:
3010 // Always return TCC_Free for the shift value of a shift instruction.
3011 case Instruction::Shl
:
3012 case Instruction::LShr
:
3013 case Instruction::AShr
:
3015 return TTI::TCC_Free
;
3017 case Instruction::Trunc
:
3018 case Instruction::ZExt
:
3019 case Instruction::SExt
:
3020 case Instruction::IntToPtr
:
3021 case Instruction::PtrToInt
:
3022 case Instruction::BitCast
:
3023 case Instruction::PHI
:
3024 case Instruction::Call
:
3025 case Instruction::Select
:
3026 case Instruction::Ret
:
3027 case Instruction::Load
:
3031 if (Idx
== ImmIdx
) {
3032 int NumConstants
= divideCeil(BitSize
, 64);
3033 int Cost
= X86TTIImpl::getIntImmCost(Imm
, Ty
);
3034 return (Cost
<= NumConstants
* TTI::TCC_Basic
)
3035 ? static_cast<int>(TTI::TCC_Free
)
3039 return X86TTIImpl::getIntImmCost(Imm
, Ty
);
3042 int X86TTIImpl::getIntImmCost(Intrinsic::ID IID
, unsigned Idx
, const APInt
&Imm
,
3044 assert(Ty
->isIntegerTy());
3046 unsigned BitSize
= Ty
->getPrimitiveSizeInBits();
3047 // There is no cost model for constants with a bit size of 0. Return TCC_Free
3048 // here, so that constant hoisting will ignore this constant.
3050 return TTI::TCC_Free
;
3054 return TTI::TCC_Free
;
3055 case Intrinsic::sadd_with_overflow
:
3056 case Intrinsic::uadd_with_overflow
:
3057 case Intrinsic::ssub_with_overflow
:
3058 case Intrinsic::usub_with_overflow
:
3059 case Intrinsic::smul_with_overflow
:
3060 case Intrinsic::umul_with_overflow
:
3061 if ((Idx
== 1) && Imm
.getBitWidth() <= 64 && isInt
<32>(Imm
.getSExtValue()))
3062 return TTI::TCC_Free
;
3064 case Intrinsic::experimental_stackmap
:
3065 if ((Idx
< 2) || (Imm
.getBitWidth() <= 64 && isInt
<64>(Imm
.getSExtValue())))
3066 return TTI::TCC_Free
;
3068 case Intrinsic::experimental_patchpoint_void
:
3069 case Intrinsic::experimental_patchpoint_i64
:
3070 if ((Idx
< 4) || (Imm
.getBitWidth() <= 64 && isInt
<64>(Imm
.getSExtValue())))
3071 return TTI::TCC_Free
;
3074 return X86TTIImpl::getIntImmCost(Imm
, Ty
);
3077 unsigned X86TTIImpl::getUserCost(const User
*U
,
3078 ArrayRef
<const Value
*> Operands
) {
3079 if (isa
<StoreInst
>(U
)) {
3080 Value
*Ptr
= U
->getOperand(1);
3081 // Store instruction with index and scale costs 2 Uops.
3082 // Check the preceding GEP to identify non-const indices.
3083 if (auto GEP
= dyn_cast
<GetElementPtrInst
>(Ptr
)) {
3084 if (!all_of(GEP
->indices(), [](Value
*V
) { return isa
<Constant
>(V
); }))
3085 return TTI::TCC_Basic
* 2;
3087 return TTI::TCC_Basic
;
3089 return BaseT::getUserCost(U
, Operands
);
3092 // Return an average cost of Gather / Scatter instruction, maybe improved later
3093 int X86TTIImpl::getGSVectorCost(unsigned Opcode
, Type
*SrcVTy
, Value
*Ptr
,
3094 unsigned Alignment
, unsigned AddressSpace
) {
3096 assert(isa
<VectorType
>(SrcVTy
) && "Unexpected type in getGSVectorCost");
3097 unsigned VF
= SrcVTy
->getVectorNumElements();
3099 // Try to reduce index size from 64 bit (default for GEP)
3100 // to 32. It is essential for VF 16. If the index can't be reduced to 32, the
3101 // operation will use 16 x 64 indices which do not fit in a zmm and needs
3102 // to split. Also check that the base pointer is the same for all lanes,
3103 // and that there's at most one variable index.
3104 auto getIndexSizeInBits
= [](Value
*Ptr
, const DataLayout
& DL
) {
3105 unsigned IndexSize
= DL
.getPointerSizeInBits();
3106 GetElementPtrInst
*GEP
= dyn_cast
<GetElementPtrInst
>(Ptr
);
3107 if (IndexSize
< 64 || !GEP
)
3110 unsigned NumOfVarIndices
= 0;
3111 Value
*Ptrs
= GEP
->getPointerOperand();
3112 if (Ptrs
->getType()->isVectorTy() && !getSplatValue(Ptrs
))
3114 for (unsigned i
= 1; i
< GEP
->getNumOperands(); ++i
) {
3115 if (isa
<Constant
>(GEP
->getOperand(i
)))
3117 Type
*IndxTy
= GEP
->getOperand(i
)->getType();
3118 if (IndxTy
->isVectorTy())
3119 IndxTy
= IndxTy
->getVectorElementType();
3120 if ((IndxTy
->getPrimitiveSizeInBits() == 64 &&
3121 !isa
<SExtInst
>(GEP
->getOperand(i
))) ||
3122 ++NumOfVarIndices
> 1)
3123 return IndexSize
; // 64
3125 return (unsigned)32;
3129 // Trying to reduce IndexSize to 32 bits for vector 16.
3130 // By default the IndexSize is equal to pointer size.
3131 unsigned IndexSize
= (ST
->hasAVX512() && VF
>= 16)
3132 ? getIndexSizeInBits(Ptr
, DL
)
3133 : DL
.getPointerSizeInBits();
3135 Type
*IndexVTy
= VectorType::get(IntegerType::get(SrcVTy
->getContext(),
3137 std::pair
<int, MVT
> IdxsLT
= TLI
->getTypeLegalizationCost(DL
, IndexVTy
);
3138 std::pair
<int, MVT
> SrcLT
= TLI
->getTypeLegalizationCost(DL
, SrcVTy
);
3139 int SplitFactor
= std::max(IdxsLT
.first
, SrcLT
.first
);
3140 if (SplitFactor
> 1) {
3141 // Handle splitting of vector of pointers
3142 Type
*SplitSrcTy
= VectorType::get(SrcVTy
->getScalarType(), VF
/ SplitFactor
);
3143 return SplitFactor
* getGSVectorCost(Opcode
, SplitSrcTy
, Ptr
, Alignment
,
3147 // The gather / scatter cost is given by Intel architects. It is a rough
3148 // number since we are looking at one instruction in a time.
3149 const int GSOverhead
= (Opcode
== Instruction::Load
)
3150 ? ST
->getGatherOverhead()
3151 : ST
->getScatterOverhead();
3152 return GSOverhead
+ VF
* getMemoryOpCost(Opcode
, SrcVTy
->getScalarType(),
3153 Alignment
, AddressSpace
);
3156 /// Return the cost of full scalarization of gather / scatter operation.
3158 /// Opcode - Load or Store instruction.
3159 /// SrcVTy - The type of the data vector that should be gathered or scattered.
3160 /// VariableMask - The mask is non-constant at compile time.
3161 /// Alignment - Alignment for one element.
3162 /// AddressSpace - pointer[s] address space.
3164 int X86TTIImpl::getGSScalarCost(unsigned Opcode
, Type
*SrcVTy
,
3165 bool VariableMask
, unsigned Alignment
,
3166 unsigned AddressSpace
) {
3167 unsigned VF
= SrcVTy
->getVectorNumElements();
3169 int MaskUnpackCost
= 0;
3171 VectorType
*MaskTy
=
3172 VectorType::get(Type::getInt1Ty(SrcVTy
->getContext()), VF
);
3173 MaskUnpackCost
= getScalarizationOverhead(MaskTy
, false, true);
3174 int ScalarCompareCost
=
3175 getCmpSelInstrCost(Instruction::ICmp
, Type::getInt1Ty(SrcVTy
->getContext()),
3177 int BranchCost
= getCFInstrCost(Instruction::Br
);
3178 MaskUnpackCost
+= VF
* (BranchCost
+ ScalarCompareCost
);
3181 // The cost of the scalar loads/stores.
3182 int MemoryOpCost
= VF
* getMemoryOpCost(Opcode
, SrcVTy
->getScalarType(),
3183 Alignment
, AddressSpace
);
3185 int InsertExtractCost
= 0;
3186 if (Opcode
== Instruction::Load
)
3187 for (unsigned i
= 0; i
< VF
; ++i
)
3188 // Add the cost of inserting each scalar load into the vector
3189 InsertExtractCost
+=
3190 getVectorInstrCost(Instruction::InsertElement
, SrcVTy
, i
);
3192 for (unsigned i
= 0; i
< VF
; ++i
)
3193 // Add the cost of extracting each element out of the data vector
3194 InsertExtractCost
+=
3195 getVectorInstrCost(Instruction::ExtractElement
, SrcVTy
, i
);
3197 return MemoryOpCost
+ MaskUnpackCost
+ InsertExtractCost
;
3200 /// Calculate the cost of Gather / Scatter operation
3201 int X86TTIImpl::getGatherScatterOpCost(unsigned Opcode
, Type
*SrcVTy
,
3202 Value
*Ptr
, bool VariableMask
,
3203 unsigned Alignment
) {
3204 assert(SrcVTy
->isVectorTy() && "Unexpected data type for Gather/Scatter");
3205 unsigned VF
= SrcVTy
->getVectorNumElements();
3206 PointerType
*PtrTy
= dyn_cast
<PointerType
>(Ptr
->getType());
3207 if (!PtrTy
&& Ptr
->getType()->isVectorTy())
3208 PtrTy
= dyn_cast
<PointerType
>(Ptr
->getType()->getVectorElementType());
3209 assert(PtrTy
&& "Unexpected type for Ptr argument");
3210 unsigned AddressSpace
= PtrTy
->getAddressSpace();
3212 bool Scalarize
= false;
3213 if ((Opcode
== Instruction::Load
&& !isLegalMaskedGather(SrcVTy
)) ||
3214 (Opcode
== Instruction::Store
&& !isLegalMaskedScatter(SrcVTy
)))
3216 // Gather / Scatter for vector 2 is not profitable on KNL / SKX
3217 // Vector-4 of gather/scatter instruction does not exist on KNL.
3218 // We can extend it to 8 elements, but zeroing upper bits of
3219 // the mask vector will add more instructions. Right now we give the scalar
3220 // cost of vector-4 for KNL. TODO: Check, maybe the gather/scatter instruction
3221 // is better in the VariableMask case.
3222 if (ST
->hasAVX512() && (VF
== 2 || (VF
== 4 && !ST
->hasVLX())))
3226 return getGSScalarCost(Opcode
, SrcVTy
, VariableMask
, Alignment
,
3229 return getGSVectorCost(Opcode
, SrcVTy
, Ptr
, Alignment
, AddressSpace
);
3232 bool X86TTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost
&C1
,
3233 TargetTransformInfo::LSRCost
&C2
) {
3234 // X86 specific here are "instruction number 1st priority".
3235 return std::tie(C1
.Insns
, C1
.NumRegs
, C1
.AddRecCost
,
3236 C1
.NumIVMuls
, C1
.NumBaseAdds
,
3237 C1
.ScaleCost
, C1
.ImmCost
, C1
.SetupCost
) <
3238 std::tie(C2
.Insns
, C2
.NumRegs
, C2
.AddRecCost
,
3239 C2
.NumIVMuls
, C2
.NumBaseAdds
,
3240 C2
.ScaleCost
, C2
.ImmCost
, C2
.SetupCost
);
3243 bool X86TTIImpl::canMacroFuseCmp() {
3244 return ST
->hasMacroFusion() || ST
->hasBranchFusion();
3247 bool X86TTIImpl::isLegalMaskedLoad(Type
*DataTy
) {
3251 // The backend can't handle a single element vector.
3252 if (isa
<VectorType
>(DataTy
) && DataTy
->getVectorNumElements() == 1)
3254 Type
*ScalarTy
= DataTy
->getScalarType();
3256 if (ScalarTy
->isPointerTy())
3259 if (ScalarTy
->isFloatTy() || ScalarTy
->isDoubleTy())
3262 if (!ScalarTy
->isIntegerTy())
3265 unsigned IntWidth
= ScalarTy
->getIntegerBitWidth();
3266 return IntWidth
== 32 || IntWidth
== 64 ||
3267 ((IntWidth
== 8 || IntWidth
== 16) && ST
->hasBWI());
3270 bool X86TTIImpl::isLegalMaskedStore(Type
*DataType
) {
3271 return isLegalMaskedLoad(DataType
);
3274 bool X86TTIImpl::isLegalNTLoad(Type
*DataType
, unsigned Alignment
) {
3275 unsigned DataSize
= DL
.getTypeStoreSize(DataType
);
3276 // The only supported nontemporal loads are for aligned vectors of 16 or 32
3277 // bytes. Note that 32-byte nontemporal vector loads are supported by AVX2
3278 // (the equivalent stores only require AVX).
3279 if (Alignment
>= DataSize
&& (DataSize
== 16 || DataSize
== 32))
3280 return DataSize
== 16 ? ST
->hasSSE1() : ST
->hasAVX2();
3285 bool X86TTIImpl::isLegalNTStore(Type
*DataType
, unsigned Alignment
) {
3286 unsigned DataSize
= DL
.getTypeStoreSize(DataType
);
3288 // SSE4A supports nontemporal stores of float and double at arbitrary
3290 if (ST
->hasSSE4A() && (DataType
->isFloatTy() || DataType
->isDoubleTy()))
3293 // Besides the SSE4A subtarget exception above, only aligned stores are
3294 // available nontemporaly on any other subtarget. And only stores with a size
3295 // of 4..32 bytes (powers of 2, only) are permitted.
3296 if (Alignment
< DataSize
|| DataSize
< 4 || DataSize
> 32 ||
3297 !isPowerOf2_32(DataSize
))
3300 // 32-byte vector nontemporal stores are supported by AVX (the equivalent
3301 // loads require AVX2).
3303 return ST
->hasAVX();
3304 else if (DataSize
== 16)
3305 return ST
->hasSSE1();
3309 bool X86TTIImpl::isLegalMaskedExpandLoad(Type
*DataTy
) {
3310 if (!isa
<VectorType
>(DataTy
))
3313 if (!ST
->hasAVX512())
3316 // The backend can't handle a single element vector.
3317 if (DataTy
->getVectorNumElements() == 1)
3320 Type
*ScalarTy
= DataTy
->getVectorElementType();
3322 if (ScalarTy
->isFloatTy() || ScalarTy
->isDoubleTy())
3325 if (!ScalarTy
->isIntegerTy())
3328 unsigned IntWidth
= ScalarTy
->getIntegerBitWidth();
3329 return IntWidth
== 32 || IntWidth
== 64 ||
3330 ((IntWidth
== 8 || IntWidth
== 16) && ST
->hasVBMI2());
3333 bool X86TTIImpl::isLegalMaskedCompressStore(Type
*DataTy
) {
3334 return isLegalMaskedExpandLoad(DataTy
);
3337 bool X86TTIImpl::isLegalMaskedGather(Type
*DataTy
) {
3338 // Some CPUs have better gather performance than others.
3339 // TODO: Remove the explicit ST->hasAVX512()?, That would mean we would only
3340 // enable gather with a -march.
3341 if (!(ST
->hasAVX512() || (ST
->hasFastGather() && ST
->hasAVX2())))
3344 // This function is called now in two cases: from the Loop Vectorizer
3345 // and from the Scalarizer.
3346 // When the Loop Vectorizer asks about legality of the feature,
3347 // the vectorization factor is not calculated yet. The Loop Vectorizer
3348 // sends a scalar type and the decision is based on the width of the
3350 // Later on, the cost model will estimate usage this intrinsic based on
3352 // The Scalarizer asks again about legality. It sends a vector type.
3353 // In this case we can reject non-power-of-2 vectors.
3354 // We also reject single element vectors as the type legalizer can't
3356 if (isa
<VectorType
>(DataTy
)) {
3357 unsigned NumElts
= DataTy
->getVectorNumElements();
3358 if (NumElts
== 1 || !isPowerOf2_32(NumElts
))
3361 Type
*ScalarTy
= DataTy
->getScalarType();
3362 if (ScalarTy
->isPointerTy())
3365 if (ScalarTy
->isFloatTy() || ScalarTy
->isDoubleTy())
3368 if (!ScalarTy
->isIntegerTy())
3371 unsigned IntWidth
= ScalarTy
->getIntegerBitWidth();
3372 return IntWidth
== 32 || IntWidth
== 64;
3375 bool X86TTIImpl::isLegalMaskedScatter(Type
*DataType
) {
3376 // AVX2 doesn't support scatter
3377 if (!ST
->hasAVX512())
3379 return isLegalMaskedGather(DataType
);
3382 bool X86TTIImpl::hasDivRemOp(Type
*DataType
, bool IsSigned
) {
3383 EVT VT
= TLI
->getValueType(DL
, DataType
);
3384 return TLI
->isOperationLegal(IsSigned
? ISD::SDIVREM
: ISD::UDIVREM
, VT
);
3387 bool X86TTIImpl::isFCmpOrdCheaperThanFCmpZero(Type
*Ty
) {
3391 bool X86TTIImpl::areInlineCompatible(const Function
*Caller
,
3392 const Function
*Callee
) const {
3393 const TargetMachine
&TM
= getTLI()->getTargetMachine();
3395 // Work this as a subsetting of subtarget features.
3396 const FeatureBitset
&CallerBits
=
3397 TM
.getSubtargetImpl(*Caller
)->getFeatureBits();
3398 const FeatureBitset
&CalleeBits
=
3399 TM
.getSubtargetImpl(*Callee
)->getFeatureBits();
3401 FeatureBitset RealCallerBits
= CallerBits
& ~InlineFeatureIgnoreList
;
3402 FeatureBitset RealCalleeBits
= CalleeBits
& ~InlineFeatureIgnoreList
;
3403 return (RealCallerBits
& RealCalleeBits
) == RealCalleeBits
;
3406 bool X86TTIImpl::areFunctionArgsABICompatible(
3407 const Function
*Caller
, const Function
*Callee
,
3408 SmallPtrSetImpl
<Argument
*> &Args
) const {
3409 if (!BaseT::areFunctionArgsABICompatible(Caller
, Callee
, Args
))
3412 // If we get here, we know the target features match. If one function
3413 // considers 512-bit vectors legal and the other does not, consider them
3415 // FIXME Look at the arguments and only consider 512 bit or larger vectors?
3416 const TargetMachine
&TM
= getTLI()->getTargetMachine();
3418 return TM
.getSubtarget
<X86Subtarget
>(*Caller
).useAVX512Regs() ==
3419 TM
.getSubtarget
<X86Subtarget
>(*Callee
).useAVX512Regs();
3422 X86TTIImpl::TTI::MemCmpExpansionOptions
3423 X86TTIImpl::enableMemCmpExpansion(bool OptSize
, bool IsZeroCmp
) const {
3424 TTI::MemCmpExpansionOptions Options
;
3425 Options
.MaxNumLoads
= TLI
->getMaxExpandSizeMemcmp(OptSize
);
3426 Options
.NumLoadsPerBlock
= 2;
3428 // Only enable vector loads for equality comparison. Right now the vector
3429 // version is not as fast for three way compare (see #33329).
3430 // TODO: enable AVX512 when the DAG is ready.
3431 // if (ST->hasAVX512()) Options.LoadSizes.push_back(64);
3432 const unsigned PreferredWidth
= ST
->getPreferVectorWidth();
3433 if (PreferredWidth
>= 256 && ST
->hasAVX2()) Options
.LoadSizes
.push_back(32);
3434 if (PreferredWidth
>= 128 && ST
->hasSSE2()) Options
.LoadSizes
.push_back(16);
3435 // All GPR and vector loads can be unaligned. SIMD compare requires integer
3436 // vectors (SSE2/AVX2).
3437 Options
.AllowOverlappingLoads
= true;
3439 if (ST
->is64Bit()) {
3440 Options
.LoadSizes
.push_back(8);
3442 Options
.LoadSizes
.push_back(4);
3443 Options
.LoadSizes
.push_back(2);
3444 Options
.LoadSizes
.push_back(1);
3448 bool X86TTIImpl::enableInterleavedAccessVectorization() {
3449 // TODO: We expect this to be beneficial regardless of arch,
3450 // but there are currently some unexplained performance artifacts on Atom.
3451 // As a temporary solution, disable on Atom.
3452 return !(ST
->isAtom());
3455 // Get estimation for interleaved load/store operations for AVX2.
3456 // \p Factor is the interleaved-access factor (stride) - number of
3457 // (interleaved) elements in the group.
3458 // \p Indices contains the indices for a strided load: when the
3459 // interleaved load has gaps they indicate which elements are used.
3460 // If Indices is empty (or if the number of indices is equal to the size
3461 // of the interleaved-access as given in \p Factor) the access has no gaps.
3463 // As opposed to AVX-512, AVX2 does not have generic shuffles that allow
3464 // computing the cost using a generic formula as a function of generic
3465 // shuffles. We therefore use a lookup table instead, filled according to
3466 // the instruction sequences that codegen currently generates.
3467 int X86TTIImpl::getInterleavedMemoryOpCostAVX2(unsigned Opcode
, Type
*VecTy
,
3469 ArrayRef
<unsigned> Indices
,
3471 unsigned AddressSpace
,
3472 bool UseMaskForCond
,
3473 bool UseMaskForGaps
) {
3475 if (UseMaskForCond
|| UseMaskForGaps
)
3476 return BaseT::getInterleavedMemoryOpCost(Opcode
, VecTy
, Factor
, Indices
,
3477 Alignment
, AddressSpace
,
3478 UseMaskForCond
, UseMaskForGaps
);
3480 // We currently Support only fully-interleaved groups, with no gaps.
3481 // TODO: Support also strided loads (interleaved-groups with gaps).
3482 if (Indices
.size() && Indices
.size() != Factor
)
3483 return BaseT::getInterleavedMemoryOpCost(Opcode
, VecTy
, Factor
, Indices
,
3484 Alignment
, AddressSpace
);
3486 // VecTy for interleave memop is <VF*Factor x Elt>.
3487 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have
3488 // VecTy = <12 x i32>.
3489 MVT LegalVT
= getTLI()->getTypeLegalizationCost(DL
, VecTy
).second
;
3491 // This function can be called with VecTy=<6xi128>, Factor=3, in which case
3492 // the VF=2, while v2i128 is an unsupported MVT vector type
3493 // (see MachineValueType.h::getVectorVT()).
3494 if (!LegalVT
.isVector())
3495 return BaseT::getInterleavedMemoryOpCost(Opcode
, VecTy
, Factor
, Indices
,
3496 Alignment
, AddressSpace
);
3498 unsigned VF
= VecTy
->getVectorNumElements() / Factor
;
3499 Type
*ScalarTy
= VecTy
->getVectorElementType();
3501 // Calculate the number of memory operations (NumOfMemOps), required
3502 // for load/store the VecTy.
3503 unsigned VecTySize
= DL
.getTypeStoreSize(VecTy
);
3504 unsigned LegalVTSize
= LegalVT
.getStoreSize();
3505 unsigned NumOfMemOps
= (VecTySize
+ LegalVTSize
- 1) / LegalVTSize
;
3507 // Get the cost of one memory operation.
3508 Type
*SingleMemOpTy
= VectorType::get(VecTy
->getVectorElementType(),
3509 LegalVT
.getVectorNumElements());
3510 unsigned MemOpCost
=
3511 getMemoryOpCost(Opcode
, SingleMemOpTy
, Alignment
, AddressSpace
);
3513 VectorType
*VT
= VectorType::get(ScalarTy
, VF
);
3514 EVT ETy
= TLI
->getValueType(DL
, VT
);
3515 if (!ETy
.isSimple())
3516 return BaseT::getInterleavedMemoryOpCost(Opcode
, VecTy
, Factor
, Indices
,
3517 Alignment
, AddressSpace
);
3519 // TODO: Complete for other data-types and strides.
3520 // Each combination of Stride, ElementTy and VF results in a different
3521 // sequence; The cost tables are therefore accessed with:
3522 // Factor (stride) and VectorType=VFxElemType.
3523 // The Cost accounts only for the shuffle sequence;
3524 // The cost of the loads/stores is accounted for separately.
3526 static const CostTblEntry AVX2InterleavedLoadTbl
[] = {
3527 { 2, MVT::v4i64
, 6 }, //(load 8i64 and) deinterleave into 2 x 4i64
3528 { 2, MVT::v4f64
, 6 }, //(load 8f64 and) deinterleave into 2 x 4f64
3530 { 3, MVT::v2i8
, 10 }, //(load 6i8 and) deinterleave into 3 x 2i8
3531 { 3, MVT::v4i8
, 4 }, //(load 12i8 and) deinterleave into 3 x 4i8
3532 { 3, MVT::v8i8
, 9 }, //(load 24i8 and) deinterleave into 3 x 8i8
3533 { 3, MVT::v16i8
, 11}, //(load 48i8 and) deinterleave into 3 x 16i8
3534 { 3, MVT::v32i8
, 13}, //(load 96i8 and) deinterleave into 3 x 32i8
3535 { 3, MVT::v8f32
, 17 }, //(load 24f32 and)deinterleave into 3 x 8f32
3537 { 4, MVT::v2i8
, 12 }, //(load 8i8 and) deinterleave into 4 x 2i8
3538 { 4, MVT::v4i8
, 4 }, //(load 16i8 and) deinterleave into 4 x 4i8
3539 { 4, MVT::v8i8
, 20 }, //(load 32i8 and) deinterleave into 4 x 8i8
3540 { 4, MVT::v16i8
, 39 }, //(load 64i8 and) deinterleave into 4 x 16i8
3541 { 4, MVT::v32i8
, 80 }, //(load 128i8 and) deinterleave into 4 x 32i8
3543 { 8, MVT::v8f32
, 40 } //(load 64f32 and)deinterleave into 8 x 8f32
3546 static const CostTblEntry AVX2InterleavedStoreTbl
[] = {
3547 { 2, MVT::v4i64
, 6 }, //interleave into 2 x 4i64 into 8i64 (and store)
3548 { 2, MVT::v4f64
, 6 }, //interleave into 2 x 4f64 into 8f64 (and store)
3550 { 3, MVT::v2i8
, 7 }, //interleave 3 x 2i8 into 6i8 (and store)
3551 { 3, MVT::v4i8
, 8 }, //interleave 3 x 4i8 into 12i8 (and store)
3552 { 3, MVT::v8i8
, 11 }, //interleave 3 x 8i8 into 24i8 (and store)
3553 { 3, MVT::v16i8
, 11 }, //interleave 3 x 16i8 into 48i8 (and store)
3554 { 3, MVT::v32i8
, 13 }, //interleave 3 x 32i8 into 96i8 (and store)
3556 { 4, MVT::v2i8
, 12 }, //interleave 4 x 2i8 into 8i8 (and store)
3557 { 4, MVT::v4i8
, 9 }, //interleave 4 x 4i8 into 16i8 (and store)
3558 { 4, MVT::v8i8
, 10 }, //interleave 4 x 8i8 into 32i8 (and store)
3559 { 4, MVT::v16i8
, 10 }, //interleave 4 x 16i8 into 64i8 (and store)
3560 { 4, MVT::v32i8
, 12 } //interleave 4 x 32i8 into 128i8 (and store)
3563 if (Opcode
== Instruction::Load
) {
3564 if (const auto *Entry
=
3565 CostTableLookup(AVX2InterleavedLoadTbl
, Factor
, ETy
.getSimpleVT()))
3566 return NumOfMemOps
* MemOpCost
+ Entry
->Cost
;
3568 assert(Opcode
== Instruction::Store
&&
3569 "Expected Store Instruction at this point");
3570 if (const auto *Entry
=
3571 CostTableLookup(AVX2InterleavedStoreTbl
, Factor
, ETy
.getSimpleVT()))
3572 return NumOfMemOps
* MemOpCost
+ Entry
->Cost
;
3575 return BaseT::getInterleavedMemoryOpCost(Opcode
, VecTy
, Factor
, Indices
,
3576 Alignment
, AddressSpace
);
3579 // Get estimation for interleaved load/store operations and strided load.
3580 // \p Indices contains indices for strided load.
3581 // \p Factor - the factor of interleaving.
3582 // AVX-512 provides 3-src shuffles that significantly reduces the cost.
3583 int X86TTIImpl::getInterleavedMemoryOpCostAVX512(unsigned Opcode
, Type
*VecTy
,
3585 ArrayRef
<unsigned> Indices
,
3587 unsigned AddressSpace
,
3588 bool UseMaskForCond
,
3589 bool UseMaskForGaps
) {
3591 if (UseMaskForCond
|| UseMaskForGaps
)
3592 return BaseT::getInterleavedMemoryOpCost(Opcode
, VecTy
, Factor
, Indices
,
3593 Alignment
, AddressSpace
,
3594 UseMaskForCond
, UseMaskForGaps
);
3596 // VecTy for interleave memop is <VF*Factor x Elt>.
3597 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have
3598 // VecTy = <12 x i32>.
3600 // Calculate the number of memory operations (NumOfMemOps), required
3601 // for load/store the VecTy.
3602 MVT LegalVT
= getTLI()->getTypeLegalizationCost(DL
, VecTy
).second
;
3603 unsigned VecTySize
= DL
.getTypeStoreSize(VecTy
);
3604 unsigned LegalVTSize
= LegalVT
.getStoreSize();
3605 unsigned NumOfMemOps
= (VecTySize
+ LegalVTSize
- 1) / LegalVTSize
;
3607 // Get the cost of one memory operation.
3608 Type
*SingleMemOpTy
= VectorType::get(VecTy
->getVectorElementType(),
3609 LegalVT
.getVectorNumElements());
3610 unsigned MemOpCost
=
3611 getMemoryOpCost(Opcode
, SingleMemOpTy
, Alignment
, AddressSpace
);
3613 unsigned VF
= VecTy
->getVectorNumElements() / Factor
;
3614 MVT VT
= MVT::getVectorVT(MVT::getVT(VecTy
->getScalarType()), VF
);
3616 if (Opcode
== Instruction::Load
) {
3617 // The tables (AVX512InterleavedLoadTbl and AVX512InterleavedStoreTbl)
3618 // contain the cost of the optimized shuffle sequence that the
3619 // X86InterleavedAccess pass will generate.
3620 // The cost of loads and stores are computed separately from the table.
3622 // X86InterleavedAccess support only the following interleaved-access group.
3623 static const CostTblEntry AVX512InterleavedLoadTbl
[] = {
3624 {3, MVT::v16i8
, 12}, //(load 48i8 and) deinterleave into 3 x 16i8
3625 {3, MVT::v32i8
, 14}, //(load 96i8 and) deinterleave into 3 x 32i8
3626 {3, MVT::v64i8
, 22}, //(load 96i8 and) deinterleave into 3 x 32i8
3629 if (const auto *Entry
=
3630 CostTableLookup(AVX512InterleavedLoadTbl
, Factor
, VT
))
3631 return NumOfMemOps
* MemOpCost
+ Entry
->Cost
;
3632 //If an entry does not exist, fallback to the default implementation.
3634 // Kind of shuffle depends on number of loaded values.
3635 // If we load the entire data in one register, we can use a 1-src shuffle.
3636 // Otherwise, we'll merge 2 sources in each operation.
3637 TTI::ShuffleKind ShuffleKind
=
3638 (NumOfMemOps
> 1) ? TTI::SK_PermuteTwoSrc
: TTI::SK_PermuteSingleSrc
;
3640 unsigned ShuffleCost
=
3641 getShuffleCost(ShuffleKind
, SingleMemOpTy
, 0, nullptr);
3643 unsigned NumOfLoadsInInterleaveGrp
=
3644 Indices
.size() ? Indices
.size() : Factor
;
3645 Type
*ResultTy
= VectorType::get(VecTy
->getVectorElementType(),
3646 VecTy
->getVectorNumElements() / Factor
);
3647 unsigned NumOfResults
=
3648 getTLI()->getTypeLegalizationCost(DL
, ResultTy
).first
*
3649 NumOfLoadsInInterleaveGrp
;
3651 // About a half of the loads may be folded in shuffles when we have only
3652 // one result. If we have more than one result, we do not fold loads at all.
3653 unsigned NumOfUnfoldedLoads
=
3654 NumOfResults
> 1 ? NumOfMemOps
: NumOfMemOps
/ 2;
3656 // Get a number of shuffle operations per result.
3657 unsigned NumOfShufflesPerResult
=
3658 std::max((unsigned)1, (unsigned)(NumOfMemOps
- 1));
3660 // The SK_MergeTwoSrc shuffle clobbers one of src operands.
3661 // When we have more than one destination, we need additional instructions
3663 unsigned NumOfMoves
= 0;
3664 if (NumOfResults
> 1 && ShuffleKind
== TTI::SK_PermuteTwoSrc
)
3665 NumOfMoves
= NumOfResults
* NumOfShufflesPerResult
/ 2;
3667 int Cost
= NumOfResults
* NumOfShufflesPerResult
* ShuffleCost
+
3668 NumOfUnfoldedLoads
* MemOpCost
+ NumOfMoves
;
3674 assert(Opcode
== Instruction::Store
&&
3675 "Expected Store Instruction at this point");
3676 // X86InterleavedAccess support only the following interleaved-access group.
3677 static const CostTblEntry AVX512InterleavedStoreTbl
[] = {
3678 {3, MVT::v16i8
, 12}, // interleave 3 x 16i8 into 48i8 (and store)
3679 {3, MVT::v32i8
, 14}, // interleave 3 x 32i8 into 96i8 (and store)
3680 {3, MVT::v64i8
, 26}, // interleave 3 x 64i8 into 96i8 (and store)
3682 {4, MVT::v8i8
, 10}, // interleave 4 x 8i8 into 32i8 (and store)
3683 {4, MVT::v16i8
, 11}, // interleave 4 x 16i8 into 64i8 (and store)
3684 {4, MVT::v32i8
, 14}, // interleave 4 x 32i8 into 128i8 (and store)
3685 {4, MVT::v64i8
, 24} // interleave 4 x 32i8 into 256i8 (and store)
3688 if (const auto *Entry
=
3689 CostTableLookup(AVX512InterleavedStoreTbl
, Factor
, VT
))
3690 return NumOfMemOps
* MemOpCost
+ Entry
->Cost
;
3691 //If an entry does not exist, fallback to the default implementation.
3693 // There is no strided stores meanwhile. And store can't be folded in
3695 unsigned NumOfSources
= Factor
; // The number of values to be merged.
3696 unsigned ShuffleCost
=
3697 getShuffleCost(TTI::SK_PermuteTwoSrc
, SingleMemOpTy
, 0, nullptr);
3698 unsigned NumOfShufflesPerStore
= NumOfSources
- 1;
3700 // The SK_MergeTwoSrc shuffle clobbers one of src operands.
3701 // We need additional instructions to keep sources.
3702 unsigned NumOfMoves
= NumOfMemOps
* NumOfShufflesPerStore
/ 2;
3703 int Cost
= NumOfMemOps
* (MemOpCost
+ NumOfShufflesPerStore
* ShuffleCost
) +
3708 int X86TTIImpl::getInterleavedMemoryOpCost(unsigned Opcode
, Type
*VecTy
,
3710 ArrayRef
<unsigned> Indices
,
3712 unsigned AddressSpace
,
3713 bool UseMaskForCond
,
3714 bool UseMaskForGaps
) {
3715 auto isSupportedOnAVX512
= [](Type
*VecTy
, bool HasBW
) {
3716 Type
*EltTy
= VecTy
->getVectorElementType();
3717 if (EltTy
->isFloatTy() || EltTy
->isDoubleTy() || EltTy
->isIntegerTy(64) ||
3718 EltTy
->isIntegerTy(32) || EltTy
->isPointerTy())
3720 if (EltTy
->isIntegerTy(16) || EltTy
->isIntegerTy(8))
3724 if (ST
->hasAVX512() && isSupportedOnAVX512(VecTy
, ST
->hasBWI()))
3725 return getInterleavedMemoryOpCostAVX512(Opcode
, VecTy
, Factor
, Indices
,
3726 Alignment
, AddressSpace
,
3727 UseMaskForCond
, UseMaskForGaps
);
3729 return getInterleavedMemoryOpCostAVX2(Opcode
, VecTy
, Factor
, Indices
,
3730 Alignment
, AddressSpace
,
3731 UseMaskForCond
, UseMaskForGaps
);
3733 return BaseT::getInterleavedMemoryOpCost(Opcode
, VecTy
, Factor
, Indices
,
3734 Alignment
, AddressSpace
,
3735 UseMaskForCond
, UseMaskForGaps
);