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[ARM] Rejig MVE load store tests. NFC
[llvm-core.git] / lib / CodeGen / TargetLoweringBase.cpp
blob9b28c1a6c4501b599e5e4cb5c7e8a492285ebbcb
1 //===- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements the TargetLoweringBase class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "llvm/ADT/BitVector.h"
14 #include "llvm/ADT/STLExtras.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringExtras.h"
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/ADT/Twine.h"
20 #include "llvm/CodeGen/Analysis.h"
21 #include "llvm/CodeGen/ISDOpcodes.h"
22 #include "llvm/CodeGen/MachineBasicBlock.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstr.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineMemOperand.h"
28 #include "llvm/CodeGen/MachineOperand.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/RuntimeLibcalls.h"
31 #include "llvm/CodeGen/StackMaps.h"
32 #include "llvm/CodeGen/TargetLowering.h"
33 #include "llvm/CodeGen/TargetOpcodes.h"
34 #include "llvm/CodeGen/TargetRegisterInfo.h"
35 #include "llvm/CodeGen/ValueTypes.h"
36 #include "llvm/IR/Attributes.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/DataLayout.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalValue.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/IRBuilder.h"
44 #include "llvm/IR/Module.h"
45 #include "llvm/IR/Type.h"
46 #include "llvm/Support/BranchProbability.h"
47 #include "llvm/Support/Casting.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Compiler.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MachineValueType.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Target/TargetMachine.h"
54 #include <algorithm>
55 #include <cassert>
56 #include <cstddef>
57 #include <cstdint>
58 #include <cstring>
59 #include <iterator>
60 #include <string>
61 #include <tuple>
62 #include <utility>
63
64 using namespace llvm;
65
66 static cl::opt<bool> JumpIsExpensiveOverride(
67 "jump-is-expensive", cl::init(false),
68 cl::desc("Do not create extra branches to split comparison logic."),
69 cl::Hidden);
70
71 static cl::opt<unsigned> MinimumJumpTableEntries
72 ("min-jump-table-entries", cl::init(4), cl::Hidden,
73 cl::desc("Set minimum number of entries to use a jump table."));
74
75 static cl::opt<unsigned> MaximumJumpTableSize
76 ("max-jump-table-size", cl::init(UINT_MAX), cl::Hidden,
77 cl::desc("Set maximum size of jump tables."));
78
79 /// Minimum jump table density for normal functions.
80 static cl::opt<unsigned>
81 JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden,
82 cl::desc("Minimum density for building a jump table in "
83 "a normal function"));
84
85 /// Minimum jump table density for -Os or -Oz functions.
86 static cl::opt<unsigned> OptsizeJumpTableDensity(
87 "optsize-jump-table-density", cl::init(40), cl::Hidden,
88 cl::desc("Minimum density for building a jump table in "
89 "an optsize function"));
90
91 static bool darwinHasSinCos(const Triple &TT) {
92 assert(TT.isOSDarwin() && "should be called with darwin triple");
93 // Don't bother with 32 bit x86.
94 if (TT.getArch() == Triple::x86)
95 return false;
96 // Macos < 10.9 has no sincos_stret.
97 if (TT.isMacOSX())
98 return !TT.isMacOSXVersionLT(10, 9) && TT.isArch64Bit();
99 // iOS < 7.0 has no sincos_stret.
100 if (TT.isiOS())
101 return !TT.isOSVersionLT(7, 0);
102 // Any other darwin such as WatchOS/TvOS is new enough.
103 return true;
104 }
105
106 // Although this default value is arbitrary, it is not random. It is assumed
107 // that a condition that evaluates the same way by a higher percentage than this
108 // is best represented as control flow. Therefore, the default value N should be
109 // set such that the win from N% correct executions is greater than the loss
110 // from (100 - N)% mispredicted executions for the majority of intended targets.
111 static cl::opt<int> MinPercentageForPredictableBranch(
112 "min-predictable-branch", cl::init(99),
113 cl::desc("Minimum percentage (0-100) that a condition must be either true "
114 "or false to assume that the condition is predictable"),
115 cl::Hidden);
116
117 void TargetLoweringBase::InitLibcalls(const Triple &TT) {
118 #define HANDLE_LIBCALL(code, name) \
119 setLibcallName(RTLIB::code, name);
120 #include "llvm/IR/RuntimeLibcalls.def"
121 #undef HANDLE_LIBCALL
122 // Initialize calling conventions to their default.
123 for (int LC = 0; LC < RTLIB::UNKNOWN_LIBCALL; ++LC)
124 setLibcallCallingConv((RTLIB::Libcall)LC, CallingConv::C);
125
126 // For IEEE quad-precision libcall names, PPC uses "kf" instead of "tf".
127 if (TT.getArch() == Triple::ppc || TT.isPPC64()) {
128 setLibcallName(RTLIB::ADD_F128, "__addkf3");
129 setLibcallName(RTLIB::SUB_F128, "__subkf3");
130 setLibcallName(RTLIB::MUL_F128, "__mulkf3");
131 setLibcallName(RTLIB::DIV_F128, "__divkf3");
132 setLibcallName(RTLIB::FPEXT_F32_F128, "__extendsfkf2");
133 setLibcallName(RTLIB::FPEXT_F64_F128, "__extenddfkf2");
134 setLibcallName(RTLIB::FPROUND_F128_F32, "__trunckfsf2");
135 setLibcallName(RTLIB::FPROUND_F128_F64, "__trunckfdf2");
136 setLibcallName(RTLIB::FPTOSINT_F128_I32, "__fixkfsi");
137 setLibcallName(RTLIB::FPTOSINT_F128_I64, "__fixkfdi");
138 setLibcallName(RTLIB::FPTOUINT_F128_I32, "__fixunskfsi");
139 setLibcallName(RTLIB::FPTOUINT_F128_I64, "__fixunskfdi");
140 setLibcallName(RTLIB::SINTTOFP_I32_F128, "__floatsikf");
141 setLibcallName(RTLIB::SINTTOFP_I64_F128, "__floatdikf");
142 setLibcallName(RTLIB::UINTTOFP_I32_F128, "__floatunsikf");
143 setLibcallName(RTLIB::UINTTOFP_I64_F128, "__floatundikf");
144 setLibcallName(RTLIB::OEQ_F128, "__eqkf2");
145 setLibcallName(RTLIB::UNE_F128, "__nekf2");
146 setLibcallName(RTLIB::OGE_F128, "__gekf2");
147 setLibcallName(RTLIB::OLT_F128, "__ltkf2");
148 setLibcallName(RTLIB::OLE_F128, "__lekf2");
149 setLibcallName(RTLIB::OGT_F128, "__gtkf2");
150 setLibcallName(RTLIB::UO_F128, "__unordkf2");
151 setLibcallName(RTLIB::O_F128, "__unordkf2");
152 }
153
154 // A few names are different on particular architectures or environments.
155 if (TT.isOSDarwin()) {
156 // For f16/f32 conversions, Darwin uses the standard naming scheme, instead
157 // of the gnueabi-style __gnu_*_ieee.
158 // FIXME: What about other targets?
159 setLibcallName(RTLIB::FPEXT_F16_F32, "__extendhfsf2");
160 setLibcallName(RTLIB::FPROUND_F32_F16, "__truncsfhf2");
161
162 // Some darwins have an optimized __bzero/bzero function.
163 switch (TT.getArch()) {
164 case Triple::x86:
165 case Triple::x86_64:
166 if (TT.isMacOSX() && !TT.isMacOSXVersionLT(10, 6))
167 setLibcallName(RTLIB::BZERO, "__bzero");
168 break;
169 case Triple::aarch64:
170 setLibcallName(RTLIB::BZERO, "bzero");
171 break;
172 default:
173 break;
174 }
175
176 if (darwinHasSinCos(TT)) {
177 setLibcallName(RTLIB::SINCOS_STRET_F32, "__sincosf_stret");
178 setLibcallName(RTLIB::SINCOS_STRET_F64, "__sincos_stret");
179 if (TT.isWatchABI()) {
180 setLibcallCallingConv(RTLIB::SINCOS_STRET_F32,
181 CallingConv::ARM_AAPCS_VFP);
182 setLibcallCallingConv(RTLIB::SINCOS_STRET_F64,
183 CallingConv::ARM_AAPCS_VFP);
184 }
185 }
186 } else {
187 setLibcallName(RTLIB::FPEXT_F16_F32, "__gnu_h2f_ieee");
188 setLibcallName(RTLIB::FPROUND_F32_F16, "__gnu_f2h_ieee");
189 }
190
191 if (TT.isGNUEnvironment() || TT.isOSFuchsia() ||
192 (TT.isAndroid() && !TT.isAndroidVersionLT(9))) {
193 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
194 setLibcallName(RTLIB::SINCOS_F64, "sincos");
195 setLibcallName(RTLIB::SINCOS_F80, "sincosl");
196 setLibcallName(RTLIB::SINCOS_F128, "sincosl");
197 setLibcallName(RTLIB::SINCOS_PPCF128, "sincosl");
198 }
199
200 if (TT.isOSOpenBSD()) {
201 setLibcallName(RTLIB::STACKPROTECTOR_CHECK_FAIL, nullptr);
202 }
203 }
204
205 /// getFPEXT - Return the FPEXT_*_* value for the given types, or
206 /// UNKNOWN_LIBCALL if there is none.
207 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
208 if (OpVT == MVT::f16) {
209 if (RetVT == MVT::f32)
210 return FPEXT_F16_F32;
211 } else if (OpVT == MVT::f32) {
212 if (RetVT == MVT::f64)
213 return FPEXT_F32_F64;
214 if (RetVT == MVT::f128)
215 return FPEXT_F32_F128;
216 if (RetVT == MVT::ppcf128)
217 return FPEXT_F32_PPCF128;
218 } else if (OpVT == MVT::f64) {
219 if (RetVT == MVT::f128)
220 return FPEXT_F64_F128;
221 else if (RetVT == MVT::ppcf128)
222 return FPEXT_F64_PPCF128;
223 } else if (OpVT == MVT::f80) {
224 if (RetVT == MVT::f128)
225 return FPEXT_F80_F128;
226 }
227
228 return UNKNOWN_LIBCALL;
229 }
230
231 /// getFPROUND - Return the FPROUND_*_* value for the given types, or
232 /// UNKNOWN_LIBCALL if there is none.
233 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
234 if (RetVT == MVT::f16) {
235 if (OpVT == MVT::f32)
236 return FPROUND_F32_F16;
237 if (OpVT == MVT::f64)
238 return FPROUND_F64_F16;
239 if (OpVT == MVT::f80)
240 return FPROUND_F80_F16;
241 if (OpVT == MVT::f128)
242 return FPROUND_F128_F16;
243 if (OpVT == MVT::ppcf128)
244 return FPROUND_PPCF128_F16;
245 } else if (RetVT == MVT::f32) {
246 if (OpVT == MVT::f64)
247 return FPROUND_F64_F32;
248 if (OpVT == MVT::f80)
249 return FPROUND_F80_F32;
250 if (OpVT == MVT::f128)
251 return FPROUND_F128_F32;
252 if (OpVT == MVT::ppcf128)
253 return FPROUND_PPCF128_F32;
254 } else if (RetVT == MVT::f64) {
255 if (OpVT == MVT::f80)
256 return FPROUND_F80_F64;
257 if (OpVT == MVT::f128)
258 return FPROUND_F128_F64;
259 if (OpVT == MVT::ppcf128)
260 return FPROUND_PPCF128_F64;
261 } else if (RetVT == MVT::f80) {
262 if (OpVT == MVT::f128)
263 return FPROUND_F128_F80;
264 }
265
266 return UNKNOWN_LIBCALL;
267 }
268
269 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
270 /// UNKNOWN_LIBCALL if there is none.
271 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
272 if (OpVT == MVT::f32) {
273 if (RetVT == MVT::i32)
274 return FPTOSINT_F32_I32;
275 if (RetVT == MVT::i64)
276 return FPTOSINT_F32_I64;
277 if (RetVT == MVT::i128)
278 return FPTOSINT_F32_I128;
279 } else if (OpVT == MVT::f64) {
280 if (RetVT == MVT::i32)
281 return FPTOSINT_F64_I32;
282 if (RetVT == MVT::i64)
283 return FPTOSINT_F64_I64;
284 if (RetVT == MVT::i128)
285 return FPTOSINT_F64_I128;
286 } else if (OpVT == MVT::f80) {
287 if (RetVT == MVT::i32)
288 return FPTOSINT_F80_I32;
289 if (RetVT == MVT::i64)
290 return FPTOSINT_F80_I64;
291 if (RetVT == MVT::i128)
292 return FPTOSINT_F80_I128;
293 } else if (OpVT == MVT::f128) {
294 if (RetVT == MVT::i32)
295 return FPTOSINT_F128_I32;
296 if (RetVT == MVT::i64)
297 return FPTOSINT_F128_I64;
298 if (RetVT == MVT::i128)
299 return FPTOSINT_F128_I128;
300 } else if (OpVT == MVT::ppcf128) {
301 if (RetVT == MVT::i32)
302 return FPTOSINT_PPCF128_I32;
303 if (RetVT == MVT::i64)
304 return FPTOSINT_PPCF128_I64;
305 if (RetVT == MVT::i128)
306 return FPTOSINT_PPCF128_I128;
307 }
308 return UNKNOWN_LIBCALL;
309 }
310
311 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
312 /// UNKNOWN_LIBCALL if there is none.
313 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
314 if (OpVT == MVT::f32) {
315 if (RetVT == MVT::i32)
316 return FPTOUINT_F32_I32;
317 if (RetVT == MVT::i64)
318 return FPTOUINT_F32_I64;
319 if (RetVT == MVT::i128)
320 return FPTOUINT_F32_I128;
321 } else if (OpVT == MVT::f64) {
322 if (RetVT == MVT::i32)
323 return FPTOUINT_F64_I32;
324 if (RetVT == MVT::i64)
325 return FPTOUINT_F64_I64;
326 if (RetVT == MVT::i128)
327 return FPTOUINT_F64_I128;
328 } else if (OpVT == MVT::f80) {
329 if (RetVT == MVT::i32)
330 return FPTOUINT_F80_I32;
331 if (RetVT == MVT::i64)
332 return FPTOUINT_F80_I64;
333 if (RetVT == MVT::i128)
334 return FPTOUINT_F80_I128;
335 } else if (OpVT == MVT::f128) {
336 if (RetVT == MVT::i32)
337 return FPTOUINT_F128_I32;
338 if (RetVT == MVT::i64)
339 return FPTOUINT_F128_I64;
340 if (RetVT == MVT::i128)
341 return FPTOUINT_F128_I128;
342 } else if (OpVT == MVT::ppcf128) {
343 if (RetVT == MVT::i32)
344 return FPTOUINT_PPCF128_I32;
345 if (RetVT == MVT::i64)
346 return FPTOUINT_PPCF128_I64;
347 if (RetVT == MVT::i128)
348 return FPTOUINT_PPCF128_I128;
349 }
350 return UNKNOWN_LIBCALL;
351 }
352
353 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
354 /// UNKNOWN_LIBCALL if there is none.
355 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
356 if (OpVT == MVT::i32) {
357 if (RetVT == MVT::f32)
358 return SINTTOFP_I32_F32;
359 if (RetVT == MVT::f64)
360 return SINTTOFP_I32_F64;
361 if (RetVT == MVT::f80)
362 return SINTTOFP_I32_F80;
363 if (RetVT == MVT::f128)
364 return SINTTOFP_I32_F128;
365 if (RetVT == MVT::ppcf128)
366 return SINTTOFP_I32_PPCF128;
367 } else if (OpVT == MVT::i64) {
368 if (RetVT == MVT::f32)
369 return SINTTOFP_I64_F32;
370 if (RetVT == MVT::f64)
371 return SINTTOFP_I64_F64;
372 if (RetVT == MVT::f80)
373 return SINTTOFP_I64_F80;
374 if (RetVT == MVT::f128)
375 return SINTTOFP_I64_F128;
376 if (RetVT == MVT::ppcf128)
377 return SINTTOFP_I64_PPCF128;
378 } else if (OpVT == MVT::i128) {
379 if (RetVT == MVT::f32)
380 return SINTTOFP_I128_F32;
381 if (RetVT == MVT::f64)
382 return SINTTOFP_I128_F64;
383 if (RetVT == MVT::f80)
384 return SINTTOFP_I128_F80;
385 if (RetVT == MVT::f128)
386 return SINTTOFP_I128_F128;
387 if (RetVT == MVT::ppcf128)
388 return SINTTOFP_I128_PPCF128;
389 }
390 return UNKNOWN_LIBCALL;
391 }
392
393 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
394 /// UNKNOWN_LIBCALL if there is none.
395 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
396 if (OpVT == MVT::i32) {
397 if (RetVT == MVT::f32)
398 return UINTTOFP_I32_F32;
399 if (RetVT == MVT::f64)
400 return UINTTOFP_I32_F64;
401 if (RetVT == MVT::f80)
402 return UINTTOFP_I32_F80;
403 if (RetVT == MVT::f128)
404 return UINTTOFP_I32_F128;
405 if (RetVT == MVT::ppcf128)
406 return UINTTOFP_I32_PPCF128;
407 } else if (OpVT == MVT::i64) {
408 if (RetVT == MVT::f32)
409 return UINTTOFP_I64_F32;
410 if (RetVT == MVT::f64)
411 return UINTTOFP_I64_F64;
412 if (RetVT == MVT::f80)
413 return UINTTOFP_I64_F80;
414 if (RetVT == MVT::f128)
415 return UINTTOFP_I64_F128;
416 if (RetVT == MVT::ppcf128)
417 return UINTTOFP_I64_PPCF128;
418 } else if (OpVT == MVT::i128) {
419 if (RetVT == MVT::f32)
420 return UINTTOFP_I128_F32;
421 if (RetVT == MVT::f64)
422 return UINTTOFP_I128_F64;
423 if (RetVT == MVT::f80)
424 return UINTTOFP_I128_F80;
425 if (RetVT == MVT::f128)
426 return UINTTOFP_I128_F128;
427 if (RetVT == MVT::ppcf128)
428 return UINTTOFP_I128_PPCF128;
429 }
430 return UNKNOWN_LIBCALL;
431 }
432
433 RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) {
434 #define OP_TO_LIBCALL(Name, Enum) \
435 case Name: \
436 switch (VT.SimpleTy) { \
437 default: \
438 return UNKNOWN_LIBCALL; \
439 case MVT::i8: \
440 return Enum##_1; \
441 case MVT::i16: \
442 return Enum##_2; \
443 case MVT::i32: \
444 return Enum##_4; \
445 case MVT::i64: \
446 return Enum##_8; \
447 case MVT::i128: \
448 return Enum##_16; \
449 }
450
451 switch (Opc) {
452 OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET)
453 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP)
454 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD)
455 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB)
456 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND)
457 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR)
458 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR)
459 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND)
460 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX)
461 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX)
462 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN)
463 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN)
464 }
465
466 #undef OP_TO_LIBCALL
467
468 return UNKNOWN_LIBCALL;
469 }
470
471 RTLIB::Libcall RTLIB::getMEMCPY_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) {
472 switch (ElementSize) {
473 case 1:
474 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_1;
475 case 2:
476 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_2;
477 case 4:
478 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_4;
479 case 8:
480 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_8;
481 case 16:
482 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_16;
483 default:
484 return UNKNOWN_LIBCALL;
485 }
486 }
487
488 RTLIB::Libcall RTLIB::getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) {
489 switch (ElementSize) {
490 case 1:
491 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_1;
492 case 2:
493 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_2;
494 case 4:
495 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_4;
496 case 8:
497 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_8;
498 case 16:
499 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_16;
500 default:
501 return UNKNOWN_LIBCALL;
502 }
503 }
504
505 RTLIB::Libcall RTLIB::getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) {
506 switch (ElementSize) {
507 case 1:
508 return MEMSET_ELEMENT_UNORDERED_ATOMIC_1;
509 case 2:
510 return MEMSET_ELEMENT_UNORDERED_ATOMIC_2;
511 case 4:
512 return MEMSET_ELEMENT_UNORDERED_ATOMIC_4;
513 case 8:
514 return MEMSET_ELEMENT_UNORDERED_ATOMIC_8;
515 case 16:
516 return MEMSET_ELEMENT_UNORDERED_ATOMIC_16;
517 default:
518 return UNKNOWN_LIBCALL;
519 }
520 }
521
522 /// InitCmpLibcallCCs - Set default comparison libcall CC.
523 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
524 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
525 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
526 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
527 CCs[RTLIB::OEQ_F128] = ISD::SETEQ;
528 CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ;
529 CCs[RTLIB::UNE_F32] = ISD::SETNE;
530 CCs[RTLIB::UNE_F64] = ISD::SETNE;
531 CCs[RTLIB::UNE_F128] = ISD::SETNE;
532 CCs[RTLIB::UNE_PPCF128] = ISD::SETNE;
533 CCs[RTLIB::OGE_F32] = ISD::SETGE;
534 CCs[RTLIB::OGE_F64] = ISD::SETGE;
535 CCs[RTLIB::OGE_F128] = ISD::SETGE;
536 CCs[RTLIB::OGE_PPCF128] = ISD::SETGE;
537 CCs[RTLIB::OLT_F32] = ISD::SETLT;
538 CCs[RTLIB::OLT_F64] = ISD::SETLT;
539 CCs[RTLIB::OLT_F128] = ISD::SETLT;
540 CCs[RTLIB::OLT_PPCF128] = ISD::SETLT;
541 CCs[RTLIB::OLE_F32] = ISD::SETLE;
542 CCs[RTLIB::OLE_F64] = ISD::SETLE;
543 CCs[RTLIB::OLE_F128] = ISD::SETLE;
544 CCs[RTLIB::OLE_PPCF128] = ISD::SETLE;
545 CCs[RTLIB::OGT_F32] = ISD::SETGT;
546 CCs[RTLIB::OGT_F64] = ISD::SETGT;
547 CCs[RTLIB::OGT_F128] = ISD::SETGT;
548 CCs[RTLIB::OGT_PPCF128] = ISD::SETGT;
549 CCs[RTLIB::UO_F32] = ISD::SETNE;
550 CCs[RTLIB::UO_F64] = ISD::SETNE;
551 CCs[RTLIB::UO_F128] = ISD::SETNE;
552 CCs[RTLIB::UO_PPCF128] = ISD::SETNE;
553 CCs[RTLIB::O_F32] = ISD::SETEQ;
554 CCs[RTLIB::O_F64] = ISD::SETEQ;
555 CCs[RTLIB::O_F128] = ISD::SETEQ;
556 CCs[RTLIB::O_PPCF128] = ISD::SETEQ;
557 }
558
559 /// NOTE: The TargetMachine owns TLOF.
560 TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm) : TM(tm) {
561 initActions();
562
563 // Perform these initializations only once.
564 MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove =
565 MaxLoadsPerMemcmp = 8;
566 MaxGluedStoresPerMemcpy = 0;
567 MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize =
568 MaxStoresPerMemmoveOptSize = MaxLoadsPerMemcmpOptSize = 4;
569 UseUnderscoreSetJmp = false;
570 UseUnderscoreLongJmp = false;
571 HasMultipleConditionRegisters = false;
572 HasExtractBitsInsn = false;
573 JumpIsExpensive = JumpIsExpensiveOverride;
574 PredictableSelectIsExpensive = false;
575 EnableExtLdPromotion = false;
576 StackPointerRegisterToSaveRestore = 0;
577 BooleanContents = UndefinedBooleanContent;
578 BooleanFloatContents = UndefinedBooleanContent;
579 BooleanVectorContents = UndefinedBooleanContent;
580 SchedPreferenceInfo = Sched::ILP;
581 JumpBufSize = 0;
582 JumpBufAlignment = 0;
583 MinFunctionAlignment = 0;
584 PrefFunctionAlignment = 0;
585 PrefLoopAlignment = 0;
586 GatherAllAliasesMaxDepth = 18;
587 MinStackArgumentAlignment = 1;
588 // TODO: the default will be switched to 0 in the next commit, along
589 // with the Target-specific changes necessary.
590 MaxAtomicSizeInBitsSupported = 1024;
591
592 MinCmpXchgSizeInBits = 0;
593 SupportsUnalignedAtomics = false;
594
595 std::fill(std::begin(LibcallRoutineNames), std::end(LibcallRoutineNames), nullptr);
596
597 InitLibcalls(TM.getTargetTriple());
598 InitCmpLibcallCCs(CmpLibcallCCs);
599 }
600
601 void TargetLoweringBase::initActions() {
602 // All operations default to being supported.
603 memset(OpActions, 0, sizeof(OpActions));
604 memset(LoadExtActions, 0, sizeof(LoadExtActions));
605 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
606 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
607 memset(CondCodeActions, 0, sizeof(CondCodeActions));
608 std::fill(std::begin(RegClassForVT), std::end(RegClassForVT), nullptr);
609 std::fill(std::begin(TargetDAGCombineArray),
610 std::end(TargetDAGCombineArray), 0);
611
612 for (MVT VT : MVT::fp_valuetypes()) {
613 MVT IntVT = MVT::getIntegerVT(VT.getSizeInBits());
614 if (IntVT.isValid()) {
615 setOperationAction(ISD::ATOMIC_SWAP, VT, Promote);
616 AddPromotedToType(ISD::ATOMIC_SWAP, VT, IntVT);
617 }
618 }
619
620 // Set default actions for various operations.
621 for (MVT VT : MVT::all_valuetypes()) {
622 // Default all indexed load / store to expand.
623 for (unsigned IM = (unsigned)ISD::PRE_INC;
624 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
625 setIndexedLoadAction(IM, VT, Expand);
626 setIndexedStoreAction(IM, VT, Expand);
627 }
628
629 // Most backends expect to see the node which just returns the value loaded.
630 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Expand);
631
632 // These operations default to expand.
633 setOperationAction(ISD::FGETSIGN, VT, Expand);
634 setOperationAction(ISD::CONCAT_VECTORS, VT, Expand);
635 setOperationAction(ISD::FMINNUM, VT, Expand);
636 setOperationAction(ISD::FMAXNUM, VT, Expand);
637 setOperationAction(ISD::FMINNUM_IEEE, VT, Expand);
638 setOperationAction(ISD::FMAXNUM_IEEE, VT, Expand);
639 setOperationAction(ISD::FMINIMUM, VT, Expand);
640 setOperationAction(ISD::FMAXIMUM, VT, Expand);
641 setOperationAction(ISD::FMAD, VT, Expand);
642 setOperationAction(ISD::SMIN, VT, Expand);
643 setOperationAction(ISD::SMAX, VT, Expand);
644 setOperationAction(ISD::UMIN, VT, Expand);
645 setOperationAction(ISD::UMAX, VT, Expand);
646 setOperationAction(ISD::ABS, VT, Expand);
647 setOperationAction(ISD::FSHL, VT, Expand);
648 setOperationAction(ISD::FSHR, VT, Expand);
649 setOperationAction(ISD::SADDSAT, VT, Expand);
650 setOperationAction(ISD::UADDSAT, VT, Expand);
651 setOperationAction(ISD::SSUBSAT, VT, Expand);
652 setOperationAction(ISD::USUBSAT, VT, Expand);
653 setOperationAction(ISD::SMULFIX, VT, Expand);
654 setOperationAction(ISD::SMULFIXSAT, VT, Expand);
655 setOperationAction(ISD::UMULFIX, VT, Expand);
656
657 // Overflow operations default to expand
658 setOperationAction(ISD::SADDO, VT, Expand);
659 setOperationAction(ISD::SSUBO, VT, Expand);
660 setOperationAction(ISD::UADDO, VT, Expand);
661 setOperationAction(ISD::USUBO, VT, Expand);
662 setOperationAction(ISD::SMULO, VT, Expand);
663 setOperationAction(ISD::UMULO, VT, Expand);
664
665 // ADDCARRY operations default to expand
666 setOperationAction(ISD::ADDCARRY, VT, Expand);
667 setOperationAction(ISD::SUBCARRY, VT, Expand);
668 setOperationAction(ISD::SETCCCARRY, VT, Expand);
669
670 // ADDC/ADDE/SUBC/SUBE default to expand.
671 setOperationAction(ISD::ADDC, VT, Expand);
672 setOperationAction(ISD::ADDE, VT, Expand);
673 setOperationAction(ISD::SUBC, VT, Expand);
674 setOperationAction(ISD::SUBE, VT, Expand);
675
676 // These default to Expand so they will be expanded to CTLZ/CTTZ by default.
677 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
678 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
679
680 setOperationAction(ISD::BITREVERSE, VT, Expand);
681
682 // These library functions default to expand.
683 setOperationAction(ISD::FROUND, VT, Expand);
684 setOperationAction(ISD::FPOWI, VT, Expand);
685
686 // These operations default to expand for vector types.
687 if (VT.isVector()) {
688 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
689 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, VT, Expand);
690 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Expand);
691 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Expand);
692 }
693
694 // Constrained floating-point operations default to expand.
695 setOperationAction(ISD::STRICT_FADD, VT, Expand);
696 setOperationAction(ISD::STRICT_FSUB, VT, Expand);
697 setOperationAction(ISD::STRICT_FMUL, VT, Expand);
698 setOperationAction(ISD::STRICT_FDIV, VT, Expand);
699 setOperationAction(ISD::STRICT_FREM, VT, Expand);
700 setOperationAction(ISD::STRICT_FMA, VT, Expand);
701 setOperationAction(ISD::STRICT_FSQRT, VT, Expand);
702 setOperationAction(ISD::STRICT_FPOW, VT, Expand);
703 setOperationAction(ISD::STRICT_FPOWI, VT, Expand);
704 setOperationAction(ISD::STRICT_FSIN, VT, Expand);
705 setOperationAction(ISD::STRICT_FCOS, VT, Expand);
706 setOperationAction(ISD::STRICT_FEXP, VT, Expand);
707 setOperationAction(ISD::STRICT_FEXP2, VT, Expand);
708 setOperationAction(ISD::STRICT_FLOG, VT, Expand);
709 setOperationAction(ISD::STRICT_FLOG10, VT, Expand);
710 setOperationAction(ISD::STRICT_FLOG2, VT, Expand);
711 setOperationAction(ISD::STRICT_FRINT, VT, Expand);
712 setOperationAction(ISD::STRICT_FNEARBYINT, VT, Expand);
713 setOperationAction(ISD::STRICT_FCEIL, VT, Expand);
714 setOperationAction(ISD::STRICT_FFLOOR, VT, Expand);
715 setOperationAction(ISD::STRICT_FROUND, VT, Expand);
716 setOperationAction(ISD::STRICT_FTRUNC, VT, Expand);
717 setOperationAction(ISD::STRICT_FMAXNUM, VT, Expand);
718 setOperationAction(ISD::STRICT_FMINNUM, VT, Expand);
719 setOperationAction(ISD::STRICT_FP_ROUND, VT, Expand);
720 setOperationAction(ISD::STRICT_FP_EXTEND, VT, Expand);
721
722 // For most targets @llvm.get.dynamic.area.offset just returns 0.
723 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, VT, Expand);
724
725 // Vector reduction default to expand.
726 setOperationAction(ISD::VECREDUCE_FADD, VT, Expand);
727 setOperationAction(ISD::VECREDUCE_FMUL, VT, Expand);
728 setOperationAction(ISD::VECREDUCE_ADD, VT, Expand);
729 setOperationAction(ISD::VECREDUCE_MUL, VT, Expand);
730 setOperationAction(ISD::VECREDUCE_AND, VT, Expand);
731 setOperationAction(ISD::VECREDUCE_OR, VT, Expand);
732 setOperationAction(ISD::VECREDUCE_XOR, VT, Expand);
733 setOperationAction(ISD::VECREDUCE_SMAX, VT, Expand);
734 setOperationAction(ISD::VECREDUCE_SMIN, VT, Expand);
735 setOperationAction(ISD::VECREDUCE_UMAX, VT, Expand);
736 setOperationAction(ISD::VECREDUCE_UMIN, VT, Expand);
737 setOperationAction(ISD::VECREDUCE_FMAX, VT, Expand);
738 setOperationAction(ISD::VECREDUCE_FMIN, VT, Expand);
739 }
740
741 // Most targets ignore the @llvm.prefetch intrinsic.
742 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
743
744 // Most targets also ignore the @llvm.readcyclecounter intrinsic.
745 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Expand);
746
747 // ConstantFP nodes default to expand. Targets can either change this to
748 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
749 // to optimize expansions for certain constants.
750 setOperationAction(ISD::ConstantFP, MVT::f16, Expand);
751 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
752 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
753 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
754 setOperationAction(ISD::ConstantFP, MVT::f128, Expand);
755
756 // These library functions default to expand.
757 for (MVT VT : {MVT::f32, MVT::f64, MVT::f128}) {
758 setOperationAction(ISD::FCBRT, VT, Expand);
759 setOperationAction(ISD::FLOG , VT, Expand);
760 setOperationAction(ISD::FLOG2, VT, Expand);
761 setOperationAction(ISD::FLOG10, VT, Expand);
762 setOperationAction(ISD::FEXP , VT, Expand);
763 setOperationAction(ISD::FEXP2, VT, Expand);
764 setOperationAction(ISD::FFLOOR, VT, Expand);
765 setOperationAction(ISD::FNEARBYINT, VT, Expand);
766 setOperationAction(ISD::FCEIL, VT, Expand);
767 setOperationAction(ISD::FRINT, VT, Expand);
768 setOperationAction(ISD::FTRUNC, VT, Expand);
769 setOperationAction(ISD::FROUND, VT, Expand);
770 setOperationAction(ISD::LROUND, VT, Expand);
771 setOperationAction(ISD::LLROUND, VT, Expand);
772 setOperationAction(ISD::LRINT, VT, Expand);
773 setOperationAction(ISD::LLRINT, VT, Expand);
774 }
775
776 // Default ISD::TRAP to expand (which turns it into abort).
777 setOperationAction(ISD::TRAP, MVT::Other, Expand);
778
779 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
780 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
781 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand);
782 }
783
784 MVT TargetLoweringBase::getScalarShiftAmountTy(const DataLayout &DL,
785 EVT) const {
786 return MVT::getIntegerVT(DL.getPointerSizeInBits(0));
787 }
788
789 EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy, const DataLayout &DL,
790 bool LegalTypes) const {
791 assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
792 if (LHSTy.isVector())
793 return LHSTy;
794 return LegalTypes ? getScalarShiftAmountTy(DL, LHSTy)
795 : getPointerTy(DL);
796 }
797
798 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
799 assert(isTypeLegal(VT));
800 switch (Op) {
801 default:
802 return false;
803 case ISD::SDIV:
804 case ISD::UDIV:
805 case ISD::SREM:
806 case ISD::UREM:
807 return true;
808 }
809 }
810
811 void TargetLoweringBase::setJumpIsExpensive(bool isExpensive) {
812 // If the command-line option was specified, ignore this request.
813 if (!JumpIsExpensiveOverride.getNumOccurrences())
814 JumpIsExpensive = isExpensive;
815 }
816
817 TargetLoweringBase::LegalizeKind
818 TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const {
819 // If this is a simple type, use the ComputeRegisterProp mechanism.
820 if (VT.isSimple()) {
821 MVT SVT = VT.getSimpleVT();
822 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));
823 MVT NVT = TransformToType[SVT.SimpleTy];
824 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT);
825
826 assert((LA == TypeLegal || LA == TypeSoftenFloat ||
827 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger) &&
828 "Promote may not follow Expand or Promote");
829
830 if (LA == TypeSplitVector)
831 return LegalizeKind(LA,
832 EVT::getVectorVT(Context, SVT.getVectorElementType(),
833 SVT.getVectorNumElements() / 2));
834 if (LA == TypeScalarizeVector)
835 return LegalizeKind(LA, SVT.getVectorElementType());
836 return LegalizeKind(LA, NVT);
837 }
838
839 // Handle Extended Scalar Types.
840 if (!VT.isVector()) {
841 assert(VT.isInteger() && "Float types must be simple");
842 unsigned BitSize = VT.getSizeInBits();
843 // First promote to a power-of-two size, then expand if necessary.
844 if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
845 EVT NVT = VT.getRoundIntegerType(Context);
846 assert(NVT != VT && "Unable to round integer VT");
847 LegalizeKind NextStep = getTypeConversion(Context, NVT);
848 // Avoid multi-step promotion.
849 if (NextStep.first == TypePromoteInteger)
850 return NextStep;
851 // Return rounded integer type.
852 return LegalizeKind(TypePromoteInteger, NVT);
853 }
854
855 return LegalizeKind(TypeExpandInteger,
856 EVT::getIntegerVT(Context, VT.getSizeInBits() / 2));
857 }
858
859 // Handle vector types.
860 unsigned NumElts = VT.getVectorNumElements();
861 EVT EltVT = VT.getVectorElementType();
862
863 // Vectors with only one element are always scalarized.
864 if (NumElts == 1)
865 return LegalizeKind(TypeScalarizeVector, EltVT);
866
867 // Try to widen vector elements until the element type is a power of two and
868 // promote it to a legal type later on, for example:
869 // <3 x i8> -> <4 x i8> -> <4 x i32>
870 if (EltVT.isInteger()) {
871 // Vectors with a number of elements that is not a power of two are always
872 // widened, for example <3 x i8> -> <4 x i8>.
873 if (!VT.isPow2VectorType()) {
874 NumElts = (unsigned)NextPowerOf2(NumElts);
875 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
876 return LegalizeKind(TypeWidenVector, NVT);
877 }
878
879 // Examine the element type.
880 LegalizeKind LK = getTypeConversion(Context, EltVT);
881
882 // If type is to be expanded, split the vector.
883 // <4 x i140> -> <2 x i140>
884 if (LK.first == TypeExpandInteger)
885 return LegalizeKind(TypeSplitVector,
886 EVT::getVectorVT(Context, EltVT, NumElts / 2));
887
888 // Promote the integer element types until a legal vector type is found
889 // or until the element integer type is too big. If a legal type was not
890 // found, fallback to the usual mechanism of widening/splitting the
891 // vector.
892 EVT OldEltVT = EltVT;
893 while (true) {
894 // Increase the bitwidth of the element to the next pow-of-two
895 // (which is greater than 8 bits).
896 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits())
897 .getRoundIntegerType(Context);
898
899 // Stop trying when getting a non-simple element type.
900 // Note that vector elements may be greater than legal vector element
901 // types. Example: X86 XMM registers hold 64bit element on 32bit
902 // systems.
903 if (!EltVT.isSimple())
904 break;
905
906 // Build a new vector type and check if it is legal.
907 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
908 // Found a legal promoted vector type.
909 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
910 return LegalizeKind(TypePromoteInteger,
911 EVT::getVectorVT(Context, EltVT, NumElts));
912 }
913
914 // Reset the type to the unexpanded type if we did not find a legal vector
915 // type with a promoted vector element type.
916 EltVT = OldEltVT;
917 }
918
919 // Try to widen the vector until a legal type is found.
920 // If there is no wider legal type, split the vector.
921 while (true) {
922 // Round up to the next power of 2.
923 NumElts = (unsigned)NextPowerOf2(NumElts);
924
925 // If there is no simple vector type with this many elements then there
926 // cannot be a larger legal vector type. Note that this assumes that
927 // there are no skipped intermediate vector types in the simple types.
928 if (!EltVT.isSimple())
929 break;
930 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
931 if (LargerVector == MVT())
932 break;
933
934 // If this type is legal then widen the vector.
935 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
936 return LegalizeKind(TypeWidenVector, LargerVector);
937 }
938
939 // Widen odd vectors to next power of two.
940 if (!VT.isPow2VectorType()) {
941 EVT NVT = VT.getPow2VectorType(Context);
942 return LegalizeKind(TypeWidenVector, NVT);
943 }
944
945 // Vectors with illegal element types are expanded.
946 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2);
947 return LegalizeKind(TypeSplitVector, NVT);
948 }
949
950 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
951 unsigned &NumIntermediates,
952 MVT &RegisterVT,
953 TargetLoweringBase *TLI) {
954 // Figure out the right, legal destination reg to copy into.
955 unsigned NumElts = VT.getVectorNumElements();
956 MVT EltTy = VT.getVectorElementType();
957
958 unsigned NumVectorRegs = 1;
959
960 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
961 // could break down into LHS/RHS like LegalizeDAG does.
962 if (!isPowerOf2_32(NumElts)) {
963 NumVectorRegs = NumElts;
964 NumElts = 1;
965 }
966
967 // Divide the input until we get to a supported size. This will always
968 // end with a scalar if the target doesn't support vectors.
969 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
970 NumElts >>= 1;
971 NumVectorRegs <<= 1;
972 }
973
974 NumIntermediates = NumVectorRegs;
975
976 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
977 if (!TLI->isTypeLegal(NewVT))
978 NewVT = EltTy;
979 IntermediateVT = NewVT;
980
981 unsigned NewVTSize = NewVT.getSizeInBits();
982
983 // Convert sizes such as i33 to i64.
984 if (!isPowerOf2_32(NewVTSize))
985 NewVTSize = NextPowerOf2(NewVTSize);
986
987 MVT DestVT = TLI->getRegisterType(NewVT);
988 RegisterVT = DestVT;
989 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
990 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
991
992 // Otherwise, promotion or legal types use the same number of registers as
993 // the vector decimated to the appropriate level.
994 return NumVectorRegs;
995 }
996
997 /// isLegalRC - Return true if the value types that can be represented by the
998 /// specified register class are all legal.
999 bool TargetLoweringBase::isLegalRC(const TargetRegisterInfo &TRI,
1000 const TargetRegisterClass &RC) const {
1001 for (auto I = TRI.legalclasstypes_begin(RC); *I != MVT::Other; ++I)
1002 if (isTypeLegal(*I))
1003 return true;
1004 return false;
1005 }
1006
1007 /// Replace/modify any TargetFrameIndex operands with a targte-dependent
1008 /// sequence of memory operands that is recognized by PrologEpilogInserter.
1009 MachineBasicBlock *
1010 TargetLoweringBase::emitPatchPoint(MachineInstr &InitialMI,
1011 MachineBasicBlock *MBB) const {
1012 MachineInstr *MI = &InitialMI;
1013 MachineFunction &MF = *MI->getMF();
1014 MachineFrameInfo &MFI = MF.getFrameInfo();
1015
1016 // We're handling multiple types of operands here:
1017 // PATCHPOINT MetaArgs - live-in, read only, direct
1018 // STATEPOINT Deopt Spill - live-through, read only, indirect
1019 // STATEPOINT Deopt Alloca - live-through, read only, direct
1020 // (We're currently conservative and mark the deopt slots read/write in
1021 // practice.)
1022 // STATEPOINT GC Spill - live-through, read/write, indirect
1023 // STATEPOINT GC Alloca - live-through, read/write, direct
1024 // The live-in vs live-through is handled already (the live through ones are
1025 // all stack slots), but we need to handle the different type of stackmap
1026 // operands and memory effects here.
1027
1028 // MI changes inside this loop as we grow operands.
1029 for(unsigned OperIdx = 0; OperIdx != MI->getNumOperands(); ++OperIdx) {
1030 MachineOperand &MO = MI->getOperand(OperIdx);
1031 if (!MO.isFI())
1032 continue;
1033
1034 // foldMemoryOperand builds a new MI after replacing a single FI operand
1035 // with the canonical set of five x86 addressing-mode operands.
1036 int FI = MO.getIndex();
1037 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc());
1038
1039 // Copy operands before the frame-index.
1040 for (unsigned i = 0; i < OperIdx; ++i)
1041 MIB.add(MI->getOperand(i));
1042 // Add frame index operands recognized by stackmaps.cpp
1043 if (MFI.isStatepointSpillSlotObjectIndex(FI)) {
1044 // indirect-mem-ref tag, size, #FI, offset.
1045 // Used for spills inserted by StatepointLowering. This codepath is not
1046 // used for patchpoints/stackmaps at all, for these spilling is done via
1047 // foldMemoryOperand callback only.
1048 assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity");
1049 MIB.addImm(StackMaps::IndirectMemRefOp);
1050 MIB.addImm(MFI.getObjectSize(FI));
1051 MIB.add(MI->getOperand(OperIdx));
1052 MIB.addImm(0);
1053 } else {
1054 // direct-mem-ref tag, #FI, offset.
1055 // Used by patchpoint, and direct alloca arguments to statepoints
1056 MIB.addImm(StackMaps::DirectMemRefOp);
1057 MIB.add(MI->getOperand(OperIdx));
1058 MIB.addImm(0);
1059 }
1060 // Copy the operands after the frame index.
1061 for (unsigned i = OperIdx + 1; i != MI->getNumOperands(); ++i)
1062 MIB.add(MI->getOperand(i));
1063
1064 // Inherit previous memory operands.
1065 MIB.cloneMemRefs(*MI);
1066 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
1067
1068 // Add a new memory operand for this FI.
1069 assert(MFI.getObjectOffset(FI) != -1);
1070
1071 // Note: STATEPOINT MMOs are added during SelectionDAG. STACKMAP, and
1072 // PATCHPOINT should be updated to do the same. (TODO)
1073 if (MI->getOpcode() != TargetOpcode::STATEPOINT) {
1074 auto Flags = MachineMemOperand::MOLoad;
1075 MachineMemOperand *MMO = MF.getMachineMemOperand(
1076 MachinePointerInfo::getFixedStack(MF, FI), Flags,
1077 MF.getDataLayout().getPointerSize(), MFI.getObjectAlignment(FI));
1078 MIB->addMemOperand(MF, MMO);
1079 }
1080
1081 // Replace the instruction and update the operand index.
1082 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
1083 OperIdx += (MIB->getNumOperands() - MI->getNumOperands()) - 1;
1084 MI->eraseFromParent();
1085 MI = MIB;
1086 }
1087 return MBB;
1088 }
1089
1090 MachineBasicBlock *
1091 TargetLoweringBase::emitXRayCustomEvent(MachineInstr &MI,
1092 MachineBasicBlock *MBB) const {
1093 assert(MI.getOpcode() == TargetOpcode::PATCHABLE_EVENT_CALL &&
1094 "Called emitXRayCustomEvent on the wrong MI!");
1095 auto &MF = *MI.getMF();
1096 auto MIB = BuildMI(MF, MI.getDebugLoc(), MI.getDesc());
1097 for (unsigned OpIdx = 0; OpIdx != MI.getNumOperands(); ++OpIdx)
1098 MIB.add(MI.getOperand(OpIdx));
1099
1100 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
1101 MI.eraseFromParent();
1102 return MBB;
1103 }
1104
1105 MachineBasicBlock *
1106 TargetLoweringBase::emitXRayTypedEvent(MachineInstr &MI,
1107 MachineBasicBlock *MBB) const {
1108 assert(MI.getOpcode() == TargetOpcode::PATCHABLE_TYPED_EVENT_CALL &&
1109 "Called emitXRayTypedEvent on the wrong MI!");
1110 auto &MF = *MI.getMF();
1111 auto MIB = BuildMI(MF, MI.getDebugLoc(), MI.getDesc());
1112 for (unsigned OpIdx = 0; OpIdx != MI.getNumOperands(); ++OpIdx)
1113 MIB.add(MI.getOperand(OpIdx));
1114
1115 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
1116 MI.eraseFromParent();
1117 return MBB;
1118 }
1119
1120 /// findRepresentativeClass - Return the largest legal super-reg register class
1121 /// of the register class for the specified type and its associated "cost".
1122 // This function is in TargetLowering because it uses RegClassForVT which would
1123 // need to be moved to TargetRegisterInfo and would necessitate moving
1124 // isTypeLegal over as well - a massive change that would just require
1125 // TargetLowering having a TargetRegisterInfo class member that it would use.
1126 std::pair<const TargetRegisterClass *, uint8_t>
1127 TargetLoweringBase::findRepresentativeClass(const TargetRegisterInfo *TRI,
1128 MVT VT) const {
1129 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
1130 if (!RC)
1131 return std::make_pair(RC, 0);
1132
1133 // Compute the set of all super-register classes.
1134 BitVector SuperRegRC(TRI->getNumRegClasses());
1135 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
1136 SuperRegRC.setBitsInMask(RCI.getMask());
1137
1138 // Find the first legal register class with the largest spill size.
1139 const TargetRegisterClass *BestRC = RC;
1140 for (unsigned i : SuperRegRC.set_bits()) {
1141 const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
1142 // We want the largest possible spill size.
1143 if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC))
1144 continue;
1145 if (!isLegalRC(*TRI, *SuperRC))
1146 continue;
1147 BestRC = SuperRC;
1148 }
1149 return std::make_pair(BestRC, 1);
1150 }
1151
1152 /// computeRegisterProperties - Once all of the register classes are added,
1153 /// this allows us to compute derived properties we expose.
1154 void TargetLoweringBase::computeRegisterProperties(
1155 const TargetRegisterInfo *TRI) {
1156 static_assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE,
1157 "Too many value types for ValueTypeActions to hold!");
1158
1159 // Everything defaults to needing one register.
1160 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1161 NumRegistersForVT[i] = 1;
1162 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
1163 }
1164 // ...except isVoid, which doesn't need any registers.
1165 NumRegistersForVT[MVT::isVoid] = 0;
1166
1167 // Find the largest integer register class.
1168 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
1169 for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg)
1170 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
1171
1172 // Every integer value type larger than this largest register takes twice as
1173 // many registers to represent as the previous ValueType.
1174 for (unsigned ExpandedReg = LargestIntReg + 1;
1175 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1176 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1177 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
1178 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
1179 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg,
1180 TypeExpandInteger);
1181 }
1182
1183 // Inspect all of the ValueType's smaller than the largest integer
1184 // register to see which ones need promotion.
1185 unsigned LegalIntReg = LargestIntReg;
1186 for (unsigned IntReg = LargestIntReg - 1;
1187 IntReg >= (unsigned)MVT::i1; --IntReg) {
1188 MVT IVT = (MVT::SimpleValueType)IntReg;
1189 if (isTypeLegal(IVT)) {
1190 LegalIntReg = IntReg;
1191 } else {
1192 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
1193 (MVT::SimpleValueType)LegalIntReg;
1194 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
1195 }
1196 }
1197
1198 // ppcf128 type is really two f64's.
1199 if (!isTypeLegal(MVT::ppcf128)) {
1200 if (isTypeLegal(MVT::f64)) {
1201 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
1202 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
1203 TransformToType[MVT::ppcf128] = MVT::f64;
1204 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
1205 } else {
1206 NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128];
1207 RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128];
1208 TransformToType[MVT::ppcf128] = MVT::i128;
1209 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeSoftenFloat);
1210 }
1211 }
1212
1213 // Decide how to handle f128. If the target does not have native f128 support,
1214 // expand it to i128 and we will be generating soft float library calls.
1215 if (!isTypeLegal(MVT::f128)) {
1216 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
1217 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
1218 TransformToType[MVT::f128] = MVT::i128;
1219 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);
1220 }
1221
1222 // Decide how to handle f64. If the target does not have native f64 support,
1223 // expand it to i64 and we will be generating soft float library calls.
1224 if (!isTypeLegal(MVT::f64)) {
1225 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
1226 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
1227 TransformToType[MVT::f64] = MVT::i64;
1228 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
1229 }
1230
1231 // Decide how to handle f32. If the target does not have native f32 support,
1232 // expand it to i32 and we will be generating soft float library calls.
1233 if (!isTypeLegal(MVT::f32)) {
1234 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
1235 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
1236 TransformToType[MVT::f32] = MVT::i32;
1237 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
1238 }
1239
1240 // Decide how to handle f16. If the target does not have native f16 support,
1241 // promote it to f32, because there are no f16 library calls (except for
1242 // conversions).
1243 if (!isTypeLegal(MVT::f16)) {
1244 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32];
1245 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32];
1246 TransformToType[MVT::f16] = MVT::f32;
1247 ValueTypeActions.setTypeAction(MVT::f16, TypePromoteFloat);
1248 }
1249
1250 // Loop over all of the vector value types to see which need transformations.
1251 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1252 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1253 MVT VT = (MVT::SimpleValueType) i;
1254 if (isTypeLegal(VT))
1255 continue;
1256
1257 MVT EltVT = VT.getVectorElementType();
1258 unsigned NElts = VT.getVectorNumElements();
1259 bool IsLegalWiderType = false;
1260 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT);
1261 switch (PreferredAction) {
1262 case TypePromoteInteger:
1263 // Try to promote the elements of integer vectors. If no legal
1264 // promotion was found, fall through to the widen-vector method.
1265 for (unsigned nVT = i + 1; nVT <= MVT::LAST_INTEGER_VECTOR_VALUETYPE; ++nVT) {
1266 MVT SVT = (MVT::SimpleValueType) nVT;
1267 // Promote vectors of integers to vectors with the same number
1268 // of elements, with a wider element type.
1269 if (SVT.getScalarSizeInBits() > EltVT.getSizeInBits() &&
1270 SVT.getVectorNumElements() == NElts && isTypeLegal(SVT)) {
1271 TransformToType[i] = SVT;
1272 RegisterTypeForVT[i] = SVT;
1273 NumRegistersForVT[i] = 1;
1274 ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
1275 IsLegalWiderType = true;
1276 break;
1277 }
1278 }
1279 if (IsLegalWiderType)
1280 break;
1281 LLVM_FALLTHROUGH;
1282
1283 case TypeWidenVector:
1284 // Try to widen the vector.
1285 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1286 MVT SVT = (MVT::SimpleValueType) nVT;
1287 if (SVT.getVectorElementType() == EltVT
1288 && SVT.getVectorNumElements() > NElts && isTypeLegal(SVT)) {
1289 TransformToType[i] = SVT;
1290 RegisterTypeForVT[i] = SVT;
1291 NumRegistersForVT[i] = 1;
1292 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1293 IsLegalWiderType = true;
1294 break;
1295 }
1296 }
1297 if (IsLegalWiderType)
1298 break;
1299 LLVM_FALLTHROUGH;
1300
1301 case TypeSplitVector:
1302 case TypeScalarizeVector: {
1303 MVT IntermediateVT;
1304 MVT RegisterVT;
1305 unsigned NumIntermediates;
1306 NumRegistersForVT[i] = getVectorTypeBreakdownMVT(VT, IntermediateVT,
1307 NumIntermediates, RegisterVT, this);
1308 RegisterTypeForVT[i] = RegisterVT;
1309
1310 MVT NVT = VT.getPow2VectorType();
1311 if (NVT == VT) {
1312 // Type is already a power of 2. The default action is to split.
1313 TransformToType[i] = MVT::Other;
1314 if (PreferredAction == TypeScalarizeVector)
1315 ValueTypeActions.setTypeAction(VT, TypeScalarizeVector);
1316 else if (PreferredAction == TypeSplitVector)
1317 ValueTypeActions.setTypeAction(VT, TypeSplitVector);
1318 else
1319 // Set type action according to the number of elements.
1320 ValueTypeActions.setTypeAction(VT, NElts == 1 ? TypeScalarizeVector
1321 : TypeSplitVector);
1322 } else {
1323 TransformToType[i] = NVT;
1324 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1325 }
1326 break;
1327 }
1328 default:
1329 llvm_unreachable("Unknown vector legalization action!");
1330 }
1331 }
1332
1333 // Determine the 'representative' register class for each value type.
1334 // An representative register class is the largest (meaning one which is
1335 // not a sub-register class / subreg register class) legal register class for
1336 // a group of value types. For example, on i386, i8, i16, and i32
1337 // representative would be GR32; while on x86_64 it's GR64.
1338 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1339 const TargetRegisterClass* RRC;
1340 uint8_t Cost;
1341 std::tie(RRC, Cost) = findRepresentativeClass(TRI, (MVT::SimpleValueType)i);
1342 RepRegClassForVT[i] = RRC;
1343 RepRegClassCostForVT[i] = Cost;
1344 }
1345 }
1346
1347 EVT TargetLoweringBase::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1348 EVT VT) const {
1349 assert(!VT.isVector() && "No default SetCC type for vectors!");
1350 return getPointerTy(DL).SimpleTy;
1351 }
1352
1353 MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType() const {
1354 return MVT::i32; // return the default value
1355 }
1356
1357 /// getVectorTypeBreakdown - Vector types are broken down into some number of
1358 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1359 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1360 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
1361 ///
1362 /// This method returns the number of registers needed, and the VT for each
1363 /// register. It also returns the VT and quantity of the intermediate values
1364 /// before they are promoted/expanded.
1365 unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
1366 EVT &IntermediateVT,
1367 unsigned &NumIntermediates,
1368 MVT &RegisterVT) const {
1369 unsigned NumElts = VT.getVectorNumElements();
1370
1371 // If there is a wider vector type with the same element type as this one,
1372 // or a promoted vector type that has the same number of elements which
1373 // are wider, then we should convert to that legal vector type.
1374 // This handles things like <2 x float> -> <4 x float> and
1375 // <4 x i1> -> <4 x i32>.
1376 LegalizeTypeAction TA = getTypeAction(Context, VT);
1377 if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) {
1378 EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1379 if (isTypeLegal(RegisterEVT)) {
1380 IntermediateVT = RegisterEVT;
1381 RegisterVT = RegisterEVT.getSimpleVT();
1382 NumIntermediates = 1;
1383 return 1;
1384 }
1385 }
1386
1387 // Figure out the right, legal destination reg to copy into.
1388 EVT EltTy = VT.getVectorElementType();
1389
1390 unsigned NumVectorRegs = 1;
1391
1392 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
1393 // could break down into LHS/RHS like LegalizeDAG does.
1394 if (!isPowerOf2_32(NumElts)) {
1395 NumVectorRegs = NumElts;
1396 NumElts = 1;
1397 }
1398
1399 // Divide the input until we get to a supported size. This will always
1400 // end with a scalar if the target doesn't support vectors.
1401 while (NumElts > 1 && !isTypeLegal(
1402 EVT::getVectorVT(Context, EltTy, NumElts))) {
1403 NumElts >>= 1;
1404 NumVectorRegs <<= 1;
1405 }
1406
1407 NumIntermediates = NumVectorRegs;
1408
1409 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
1410 if (!isTypeLegal(NewVT))
1411 NewVT = EltTy;
1412 IntermediateVT = NewVT;
1413
1414 MVT DestVT = getRegisterType(Context, NewVT);
1415 RegisterVT = DestVT;
1416 unsigned NewVTSize = NewVT.getSizeInBits();
1417
1418 // Convert sizes such as i33 to i64.
1419 if (!isPowerOf2_32(NewVTSize))
1420 NewVTSize = NextPowerOf2(NewVTSize);
1421
1422 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1423 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1424
1425 // Otherwise, promotion or legal types use the same number of registers as
1426 // the vector decimated to the appropriate level.
1427 return NumVectorRegs;
1428 }
1429
1430 /// Get the EVTs and ArgFlags collections that represent the legalized return
1431 /// type of the given function. This does not require a DAG or a return value,
1432 /// and is suitable for use before any DAGs for the function are constructed.
1433 /// TODO: Move this out of TargetLowering.cpp.
1434 void llvm::GetReturnInfo(CallingConv::ID CC, Type *ReturnType,
1435 AttributeList attr,
1436 SmallVectorImpl<ISD::OutputArg> &Outs,
1437 const TargetLowering &TLI, const DataLayout &DL) {
1438 SmallVector<EVT, 4> ValueVTs;
1439 ComputeValueVTs(TLI, DL, ReturnType, ValueVTs);
1440 unsigned NumValues = ValueVTs.size();
1441 if (NumValues == 0) return;
1442
1443 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1444 EVT VT = ValueVTs[j];
1445 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1446
1447 if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt))
1448 ExtendKind = ISD::SIGN_EXTEND;
1449 else if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt))
1450 ExtendKind = ISD::ZERO_EXTEND;
1451
1452 // FIXME: C calling convention requires the return type to be promoted to
1453 // at least 32-bit. But this is not necessary for non-C calling
1454 // conventions. The frontend should mark functions whose return values
1455 // require promoting with signext or zeroext attributes.
1456 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1457 MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1458 if (VT.bitsLT(MinVT))
1459 VT = MinVT;
1460 }
1461
1462 unsigned NumParts =
1463 TLI.getNumRegistersForCallingConv(ReturnType->getContext(), CC, VT);
1464 MVT PartVT =
1465 TLI.getRegisterTypeForCallingConv(ReturnType->getContext(), CC, VT);
1466
1467 // 'inreg' on function refers to return value
1468 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1469 if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::InReg))
1470 Flags.setInReg();
1471
1472 // Propagate extension type if any
1473 if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt))
1474 Flags.setSExt();
1475 else if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt))
1476 Flags.setZExt();
1477
1478 for (unsigned i = 0; i < NumParts; ++i)
1479 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isfixed=*/true, 0, 0));
1480 }
1481 }
1482
1483 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1484 /// function arguments in the caller parameter area. This is the actual
1485 /// alignment, not its logarithm.
1486 unsigned TargetLoweringBase::getByValTypeAlignment(Type *Ty,
1487 const DataLayout &DL) const {
1488 return DL.getABITypeAlignment(Ty);
1489 }
1490
1491 bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context,
1492 const DataLayout &DL, EVT VT,
1493 unsigned AddrSpace,
1494 unsigned Alignment,
1495 MachineMemOperand::Flags Flags,
1496 bool *Fast) const {
1497 // Check if the specified alignment is sufficient based on the data layout.
1498 // TODO: While using the data layout works in practice, a better solution
1499 // would be to implement this check directly (make this a virtual function).
1500 // For example, the ABI alignment may change based on software platform while
1501 // this function should only be affected by hardware implementation.
1502 Type *Ty = VT.getTypeForEVT(Context);
1503 if (Alignment >= DL.getABITypeAlignment(Ty)) {
1504 // Assume that an access that meets the ABI-specified alignment is fast.
1505 if (Fast != nullptr)
1506 *Fast = true;
1507 return true;
1508 }
1509
1510 // This is a misaligned access.
1511 return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Flags, Fast);
1512 }
1513
1514 bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context,
1515 const DataLayout &DL, EVT VT,
1516 const MachineMemOperand &MMO,
1517 bool *Fast) const {
1518 return allowsMemoryAccess(Context, DL, VT, MMO.getAddrSpace(),
1519 MMO.getAlignment(), MMO.getFlags(), Fast);
1520 }
1521
1522 BranchProbability TargetLoweringBase::getPredictableBranchThreshold() const {
1523 return BranchProbability(MinPercentageForPredictableBranch, 100);
1524 }
1525
1526 //===----------------------------------------------------------------------===//
1527 // TargetTransformInfo Helpers
1528 //===----------------------------------------------------------------------===//
1529
1530 int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const {
1531 enum InstructionOpcodes {
1532 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1533 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1534 #include "llvm/IR/Instruction.def"
1535 };
1536 switch (static_cast<InstructionOpcodes>(Opcode)) {
1537 case Ret: return 0;
1538 case Br: return 0;
1539 case Switch: return 0;
1540 case IndirectBr: return 0;
1541 case Invoke: return 0;
1542 case CallBr: return 0;
1543 case Resume: return 0;
1544 case Unreachable: return 0;
1545 case CleanupRet: return 0;
1546 case CatchRet: return 0;
1547 case CatchPad: return 0;
1548 case CatchSwitch: return 0;
1549 case CleanupPad: return 0;
1550 case FNeg: return ISD::FNEG;
1551 case Add: return ISD::ADD;
1552 case FAdd: return ISD::FADD;
1553 case Sub: return ISD::SUB;
1554 case FSub: return ISD::FSUB;
1555 case Mul: return ISD::MUL;
1556 case FMul: return ISD::FMUL;
1557 case UDiv: return ISD::UDIV;
1558 case SDiv: return ISD::SDIV;
1559 case FDiv: return ISD::FDIV;
1560 case URem: return ISD::UREM;
1561 case SRem: return ISD::SREM;
1562 case FRem: return ISD::FREM;
1563 case Shl: return ISD::SHL;
1564 case LShr: return ISD::SRL;
1565 case AShr: return ISD::SRA;
1566 case And: return ISD::AND;
1567 case Or: return ISD::OR;
1568 case Xor: return ISD::XOR;
1569 case Alloca: return 0;
1570 case Load: return ISD::LOAD;
1571 case Store: return ISD::STORE;
1572 case GetElementPtr: return 0;
1573 case Fence: return 0;
1574 case AtomicCmpXchg: return 0;
1575 case AtomicRMW: return 0;
1576 case Trunc: return ISD::TRUNCATE;
1577 case ZExt: return ISD::ZERO_EXTEND;
1578 case SExt: return ISD::SIGN_EXTEND;
1579 case FPToUI: return ISD::FP_TO_UINT;
1580 case FPToSI: return ISD::FP_TO_SINT;
1581 case UIToFP: return ISD::UINT_TO_FP;
1582 case SIToFP: return ISD::SINT_TO_FP;
1583 case FPTrunc: return ISD::FP_ROUND;
1584 case FPExt: return ISD::FP_EXTEND;
1585 case PtrToInt: return ISD::BITCAST;
1586 case IntToPtr: return ISD::BITCAST;
1587 case BitCast: return ISD::BITCAST;
1588 case AddrSpaceCast: return ISD::ADDRSPACECAST;
1589 case ICmp: return ISD::SETCC;
1590 case FCmp: return ISD::SETCC;
1591 case PHI: return 0;
1592 case Call: return 0;
1593 case Select: return ISD::SELECT;
1594 case UserOp1: return 0;
1595 case UserOp2: return 0;
1596 case VAArg: return 0;
1597 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
1598 case InsertElement: return ISD::INSERT_VECTOR_ELT;
1599 case ShuffleVector: return ISD::VECTOR_SHUFFLE;
1600 case ExtractValue: return ISD::MERGE_VALUES;
1601 case InsertValue: return ISD::MERGE_VALUES;
1602 case LandingPad: return 0;
1603 }
1604
1605 llvm_unreachable("Unknown instruction type encountered!");
1606 }
1607
1608 std::pair<int, MVT>
1609 TargetLoweringBase::getTypeLegalizationCost(const DataLayout &DL,
1610 Type *Ty) const {
1611 LLVMContext &C = Ty->getContext();
1612 EVT MTy = getValueType(DL, Ty);
1613
1614 int Cost = 1;
1615 // We keep legalizing the type until we find a legal kind. We assume that
1616 // the only operation that costs anything is the split. After splitting
1617 // we need to handle two types.
1618 while (true) {
1619 LegalizeKind LK = getTypeConversion(C, MTy);
1620
1621 if (LK.first == TypeLegal)
1622 return std::make_pair(Cost, MTy.getSimpleVT());
1623
1624 if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger)
1625 Cost *= 2;
1626
1627 // Do not loop with f128 type.
1628 if (MTy == LK.second)
1629 return std::make_pair(Cost, MTy.getSimpleVT());
1630
1631 // Keep legalizing the type.
1632 MTy = LK.second;
1633 }
1634 }
1635
1636 Value *TargetLoweringBase::getDefaultSafeStackPointerLocation(IRBuilder<> &IRB,
1637 bool UseTLS) const {
1638 // compiler-rt provides a variable with a magic name. Targets that do not
1639 // link with compiler-rt may also provide such a variable.
1640 Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1641 const char *UnsafeStackPtrVar = "__safestack_unsafe_stack_ptr";
1642 auto UnsafeStackPtr =
1643 dyn_cast_or_null<GlobalVariable>(M->getNamedValue(UnsafeStackPtrVar));
1644
1645 Type *StackPtrTy = Type::getInt8PtrTy(M->getContext());
1646
1647 if (!UnsafeStackPtr) {
1648 auto TLSModel = UseTLS ?
1649 GlobalValue::InitialExecTLSModel :
1650 GlobalValue::NotThreadLocal;
1651 // The global variable is not defined yet, define it ourselves.
1652 // We use the initial-exec TLS model because we do not support the
1653 // variable living anywhere other than in the main executable.
1654 UnsafeStackPtr = new GlobalVariable(
1655 *M, StackPtrTy, false, GlobalValue::ExternalLinkage, nullptr,
1656 UnsafeStackPtrVar, nullptr, TLSModel);
1657 } else {
1658 // The variable exists, check its type and attributes.
1659 if (UnsafeStackPtr->getValueType() != StackPtrTy)
1660 report_fatal_error(Twine(UnsafeStackPtrVar) + " must have void* type");
1661 if (UseTLS != UnsafeStackPtr->isThreadLocal())
1662 report_fatal_error(Twine(UnsafeStackPtrVar) + " must " +
1663 (UseTLS ? "" : "not ") + "be thread-local");
1664 }
1665 return UnsafeStackPtr;
1666 }
1667
1668 Value *TargetLoweringBase::getSafeStackPointerLocation(IRBuilder<> &IRB) const {
1669 if (!TM.getTargetTriple().isAndroid())
1670 return getDefaultSafeStackPointerLocation(IRB, true);
1671
1672 // Android provides a libc function to retrieve the address of the current
1673 // thread's unsafe stack pointer.
1674 Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1675 Type *StackPtrTy = Type::getInt8PtrTy(M->getContext());
1676 FunctionCallee Fn = M->getOrInsertFunction("__safestack_pointer_address",
1677 StackPtrTy->getPointerTo(0));
1678 return IRB.CreateCall(Fn);
1679 }
1680
1681 //===----------------------------------------------------------------------===//
1682 // Loop Strength Reduction hooks
1683 //===----------------------------------------------------------------------===//
1684
1685 /// isLegalAddressingMode - Return true if the addressing mode represented
1686 /// by AM is legal for this target, for a load/store of the specified type.
1687 bool TargetLoweringBase::isLegalAddressingMode(const DataLayout &DL,
1688 const AddrMode &AM, Type *Ty,
1689 unsigned AS, Instruction *I) const {
1690 // The default implementation of this implements a conservative RISCy, r+r and
1691 // r+i addr mode.
1692
1693 // Allows a sign-extended 16-bit immediate field.
1694 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
1695 return false;
1696
1697 // No global is ever allowed as a base.
1698 if (AM.BaseGV)
1699 return false;
1700
1701 // Only support r+r,
1702 switch (AM.Scale) {
1703 case 0: // "r+i" or just "i", depending on HasBaseReg.
1704 break;
1705 case 1:
1706 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
1707 return false;
1708 // Otherwise we have r+r or r+i.
1709 break;
1710 case 2:
1711 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
1712 return false;
1713 // Allow 2*r as r+r.
1714 break;
1715 default: // Don't allow n * r
1716 return false;
1717 }
1718
1719 return true;
1720 }
1721
1722 //===----------------------------------------------------------------------===//
1723 // Stack Protector
1724 //===----------------------------------------------------------------------===//
1725
1726 // For OpenBSD return its special guard variable. Otherwise return nullptr,
1727 // so that SelectionDAG handle SSP.
1728 Value *TargetLoweringBase::getIRStackGuard(IRBuilder<> &IRB) const {
1729 if (getTargetMachine().getTargetTriple().isOSOpenBSD()) {
1730 Module &M = *IRB.GetInsertBlock()->getParent()->getParent();
1731 PointerType *PtrTy = Type::getInt8PtrTy(M.getContext());
1732 return M.getOrInsertGlobal("__guard_local", PtrTy);
1733 }
1734 return nullptr;
1735 }
1736
1737 // Currently only support "standard" __stack_chk_guard.
1738 // TODO: add LOAD_STACK_GUARD support.
1739 void TargetLoweringBase::insertSSPDeclarations(Module &M) const {
1740 if (!M.getNamedValue("__stack_chk_guard"))
1741 new GlobalVariable(M, Type::getInt8PtrTy(M.getContext()), false,
1742 GlobalVariable::ExternalLinkage,
1743 nullptr, "__stack_chk_guard");
1744 }
1745
1746 // Currently only support "standard" __stack_chk_guard.
1747 // TODO: add LOAD_STACK_GUARD support.
1748 Value *TargetLoweringBase::getSDagStackGuard(const Module &M) const {
1749 return M.getNamedValue("__stack_chk_guard");
1750 }
1751
1752 Function *TargetLoweringBase::getSSPStackGuardCheck(const Module &M) const {
1753 return nullptr;
1754 }
1755
1756 unsigned TargetLoweringBase::getMinimumJumpTableEntries() const {
1757 return MinimumJumpTableEntries;
1758 }
1759
1760 void TargetLoweringBase::setMinimumJumpTableEntries(unsigned Val) {
1761 MinimumJumpTableEntries = Val;
1762 }
1763
1764 unsigned TargetLoweringBase::getMinimumJumpTableDensity(bool OptForSize) const {
1765 return OptForSize ? OptsizeJumpTableDensity : JumpTableDensity;
1766 }
1767
1768 unsigned TargetLoweringBase::getMaximumJumpTableSize() const {
1769 return MaximumJumpTableSize;
1770 }
1771
1772 void TargetLoweringBase::setMaximumJumpTableSize(unsigned Val) {
1773 MaximumJumpTableSize = Val;
1774 }
1775
1776 //===----------------------------------------------------------------------===//
1777 // Reciprocal Estimates
1778 //===----------------------------------------------------------------------===//
1779
1780 /// Get the reciprocal estimate attribute string for a function that will
1781 /// override the target defaults.
1782 static StringRef getRecipEstimateForFunc(MachineFunction &MF) {
1783 const Function &F = MF.getFunction();
1784 return F.getFnAttribute("reciprocal-estimates").getValueAsString();
1785 }
1786
1787 /// Construct a string for the given reciprocal operation of the given type.
1788 /// This string should match the corresponding option to the front-end's
1789 /// "-mrecip" flag assuming those strings have been passed through in an
1790 /// attribute string. For example, "vec-divf" for a division of a vXf32.
1791 static std::string getReciprocalOpName(bool IsSqrt, EVT VT) {
1792 std::string Name = VT.isVector() ? "vec-" : "";
1793
1794 Name += IsSqrt ? "sqrt" : "div";
1795
1796 // TODO: Handle "half" or other float types?
1797 if (VT.getScalarType() == MVT::f64) {
1798 Name += "d";
1799 } else {
1800 assert(VT.getScalarType() == MVT::f32 &&
1801 "Unexpected FP type for reciprocal estimate");
1802 Name += "f";
1803 }
1804
1805 return Name;
1806 }
1807
1808 /// Return the character position and value (a single numeric character) of a
1809 /// customized refinement operation in the input string if it exists. Return
1810 /// false if there is no customized refinement step count.
1811 static bool parseRefinementStep(StringRef In, size_t &Position,
1812 uint8_t &Value) {
1813 const char RefStepToken = ':';
1814 Position = In.find(RefStepToken);
1815 if (Position == StringRef::npos)
1816 return false;
1817
1818 StringRef RefStepString = In.substr(Position + 1);
1819 // Allow exactly one numeric character for the additional refinement
1820 // step parameter.
1821 if (RefStepString.size() == 1) {
1822 char RefStepChar = RefStepString[0];
1823 if (RefStepChar >= '0' && RefStepChar <= '9') {
1824 Value = RefStepChar - '0';
1825 return true;
1826 }
1827 }
1828 report_fatal_error("Invalid refinement step for -recip.");
1829 }
1830
1831 /// For the input attribute string, return one of the ReciprocalEstimate enum
1832 /// status values (enabled, disabled, or not specified) for this operation on
1833 /// the specified data type.
1834 static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override) {
1835 if (Override.empty())
1836 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1837
1838 SmallVector<StringRef, 4> OverrideVector;
1839 Override.split(OverrideVector, ',');
1840 unsigned NumArgs = OverrideVector.size();
1841
1842 // Check if "all", "none", or "default" was specified.
1843 if (NumArgs == 1) {
1844 // Look for an optional setting of the number of refinement steps needed
1845 // for this type of reciprocal operation.
1846 size_t RefPos;
1847 uint8_t RefSteps;
1848 if (parseRefinementStep(Override, RefPos, RefSteps)) {
1849 // Split the string for further processing.
1850 Override = Override.substr(0, RefPos);
1851 }
1852
1853 // All reciprocal types are enabled.
1854 if (Override == "all")
1855 return TargetLoweringBase::ReciprocalEstimate::Enabled;
1856
1857 // All reciprocal types are disabled.
1858 if (Override == "none")
1859 return TargetLoweringBase::ReciprocalEstimate::Disabled;
1860
1861 // Target defaults for enablement are used.
1862 if (Override == "default")
1863 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1864 }
1865
1866 // The attribute string may omit the size suffix ('f'/'d').
1867 std::string VTName = getReciprocalOpName(IsSqrt, VT);
1868 std::string VTNameNoSize = VTName;
1869 VTNameNoSize.pop_back();
1870 static const char DisabledPrefix = '!';
1871
1872 for (StringRef RecipType : OverrideVector) {
1873 size_t RefPos;
1874 uint8_t RefSteps;
1875 if (parseRefinementStep(RecipType, RefPos, RefSteps))
1876 RecipType = RecipType.substr(0, RefPos);
1877
1878 // Ignore the disablement token for string matching.
1879 bool IsDisabled = RecipType[0] == DisabledPrefix;
1880 if (IsDisabled)
1881 RecipType = RecipType.substr(1);
1882
1883 if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize))
1884 return IsDisabled ? TargetLoweringBase::ReciprocalEstimate::Disabled
1885 : TargetLoweringBase::ReciprocalEstimate::Enabled;
1886 }
1887
1888 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1889 }
1890
1891 /// For the input attribute string, return the customized refinement step count
1892 /// for this operation on the specified data type. If the step count does not
1893 /// exist, return the ReciprocalEstimate enum value for unspecified.
1894 static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override) {
1895 if (Override.empty())
1896 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1897
1898 SmallVector<StringRef, 4> OverrideVector;
1899 Override.split(OverrideVector, ',');
1900 unsigned NumArgs = OverrideVector.size();
1901
1902 // Check if "all", "default", or "none" was specified.
1903 if (NumArgs == 1) {
1904 // Look for an optional setting of the number of refinement steps needed
1905 // for this type of reciprocal operation.
1906 size_t RefPos;
1907 uint8_t RefSteps;
1908 if (!parseRefinementStep(Override, RefPos, RefSteps))
1909 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1910
1911 // Split the string for further processing.
1912 Override = Override.substr(0, RefPos);
1913 assert(Override != "none" &&
1914 "Disabled reciprocals, but specifed refinement steps?");
1915
1916 // If this is a general override, return the specified number of steps.
1917 if (Override == "all" || Override == "default")
1918 return RefSteps;
1919 }
1920
1921 // The attribute string may omit the size suffix ('f'/'d').
1922 std::string VTName = getReciprocalOpName(IsSqrt, VT);
1923 std::string VTNameNoSize = VTName;
1924 VTNameNoSize.pop_back();
1925
1926 for (StringRef RecipType : OverrideVector) {
1927 size_t RefPos;
1928 uint8_t RefSteps;
1929 if (!parseRefinementStep(RecipType, RefPos, RefSteps))
1930 continue;
1931
1932 RecipType = RecipType.substr(0, RefPos);
1933 if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize))
1934 return RefSteps;
1935 }
1936
1937 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1938 }
1939
1940 int TargetLoweringBase::getRecipEstimateSqrtEnabled(EVT VT,
1941 MachineFunction &MF) const {
1942 return getOpEnabled(true, VT, getRecipEstimateForFunc(MF));
1943 }
1944
1945 int TargetLoweringBase::getRecipEstimateDivEnabled(EVT VT,
1946 MachineFunction &MF) const {
1947 return getOpEnabled(false, VT, getRecipEstimateForFunc(MF));
1948 }
1949
1950 int TargetLoweringBase::getSqrtRefinementSteps(EVT VT,
1951 MachineFunction &MF) const {
1952 return getOpRefinementSteps(true, VT, getRecipEstimateForFunc(MF));
1953 }
1954
1955 int TargetLoweringBase::getDivRefinementSteps(EVT VT,
1956 MachineFunction &MF) const {
1957 return getOpRefinementSteps(false, VT, getRecipEstimateForFunc(MF));
1958 }
1959
1960 void TargetLoweringBase::finalizeLowering(MachineFunction &MF) const {
1961 MF.getRegInfo().freezeReservedRegs(MF);
1962 }
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