lib/Target/RISCV/Utils/RISCVBaseInfo.h

   1 //===-- RISCVBaseInfo.h - Top level definitions for RISCV MC ----*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file contains small standalone enum definitions for the RISCV target
  10 // useful for the compiler back-end and the MC libraries.
  11 //
  12 //===----------------------------------------------------------------------===//
  13 #ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
  14 #define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
  15
  16 #include "MCTargetDesc/RISCVMCTargetDesc.h"
  17 #include "llvm/ADT/StringRef.h"
  18 #include "llvm/ADT/StringSwitch.h"
  19 #include "llvm/MC/SubtargetFeature.h"
  20
  21 namespace llvm {
  22
  23 // RISCVII - This namespace holds all of the target specific flags that
  24 // instruction info tracks. All definitions must match RISCVInstrFormats.td.
  25 namespace RISCVII {
  26 enum {
  27   InstFormatPseudo = 0,
  28   InstFormatR = 1,
  29   InstFormatR4 = 2,
  30   InstFormatI = 3,
  31   InstFormatS = 4,
  32   InstFormatB = 5,
  33   InstFormatU = 6,
  34   InstFormatJ = 7,
  35   InstFormatCR = 8,
  36   InstFormatCI = 9,
  37   InstFormatCSS = 10,
  38   InstFormatCIW = 11,
  39   InstFormatCL = 12,
  40   InstFormatCS = 13,
  41   InstFormatCA = 14,
  42   InstFormatCB = 15,
  43   InstFormatCJ = 16,
  44   InstFormatOther = 17,
  45
  46   InstFormatMask = 31
  47 };
  48
  49 enum {
  50   MO_None,
  51   MO_CALL,
  52   MO_PLT,
  53   MO_LO,
  54   MO_HI,
  55   MO_PCREL_LO,
  56   MO_PCREL_HI,
  57   MO_GOT_HI,
  58   MO_TPREL_LO,
  59   MO_TPREL_HI,
  60   MO_TPREL_ADD,
  61   MO_TLS_GOT_HI,
  62   MO_TLS_GD_HI,
  63 };
  64 } // namespace RISCVII
  65
  66 // Describes the predecessor/successor bits used in the FENCE instruction.
  67 namespace RISCVFenceField {
  68 enum FenceField {
  69   I = 8,
  70   O = 4,
  71   R = 2,
  72   W = 1
  73 };
  74 }
  75
  76 // Describes the supported floating point rounding mode encodings.
  77 namespace RISCVFPRndMode {
  78 enum RoundingMode {
  79   RNE = 0,
  80   RTZ = 1,
  81   RDN = 2,
  82   RUP = 3,
  83   RMM = 4,
  84   DYN = 7,
  85   Invalid
  86 };
  87
  88 inline static StringRef roundingModeToString(RoundingMode RndMode) {
  89   switch (RndMode) {
  90   default:
  91     llvm_unreachable("Unknown floating point rounding mode");
  92   case RISCVFPRndMode::RNE:
  93     return "rne";
  94   case RISCVFPRndMode::RTZ:
  95     return "rtz";
  96   case RISCVFPRndMode::RDN:
  97     return "rdn";
  98   case RISCVFPRndMode::RUP:
  99     return "rup";
 100   case RISCVFPRndMode::RMM:
 101     return "rmm";
 102   case RISCVFPRndMode::DYN:
 103     return "dyn";
 104   }
 105 }
 106
 107 inline static RoundingMode stringToRoundingMode(StringRef Str) {
 108   return StringSwitch<RoundingMode>(Str)
 109       .Case("rne", RISCVFPRndMode::RNE)
 110       .Case("rtz", RISCVFPRndMode::RTZ)
 111       .Case("rdn", RISCVFPRndMode::RDN)
 112       .Case("rup", RISCVFPRndMode::RUP)
 113       .Case("rmm", RISCVFPRndMode::RMM)
 114       .Case("dyn", RISCVFPRndMode::DYN)
 115       .Default(RISCVFPRndMode::Invalid);
 116 }
 117
 118 inline static bool isValidRoundingMode(unsigned Mode) {
 119   switch (Mode) {
 120   default:
 121     return false;
 122   case RISCVFPRndMode::RNE:
 123   case RISCVFPRndMode::RTZ:
 124   case RISCVFPRndMode::RDN:
 125   case RISCVFPRndMode::RUP:
 126   case RISCVFPRndMode::RMM:
 127   case RISCVFPRndMode::DYN:
 128     return true;
 129   }
 130 }
 131 } // namespace RISCVFPRndMode
 132
 133 namespace RISCVSysReg {
 134 struct SysReg {
 135   const char *Name;
 136   unsigned Encoding;
 137   // FIXME: add these additional fields when needed.
 138   // Privilege Access: Read, Write, Read-Only.
 139   // unsigned ReadWrite;
 140   // Privilege Mode: User, System or Machine.
 141   // unsigned Mode;
 142   // Check field name.
 143   // unsigned Extra;
 144   // Register number without the privilege bits.
 145   // unsigned Number;
 146   FeatureBitset FeaturesRequired;
 147   bool isRV32Only;
 148
 149   bool haveRequiredFeatures(FeatureBitset ActiveFeatures) const {
 150     // Not in 32-bit mode.
 151     if (isRV32Only && ActiveFeatures[RISCV::Feature64Bit])
 152       return false;
 153     // No required feature associated with the system register.
 154     if (FeaturesRequired.none())
 155       return true;
 156     return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
 157   }
 158 };
 159
 160 #define GET_SysRegsList_DECL
 161 #include "RISCVGenSystemOperands.inc"
 162 } // end namespace RISCVSysReg
 163
 164 namespace RISCVABI {
 165
 166 enum ABI {
 167   ABI_ILP32,
 168   ABI_ILP32F,
 169   ABI_ILP32D,
 170   ABI_ILP32E,
 171   ABI_LP64,
 172   ABI_LP64F,
 173   ABI_LP64D,
 174   ABI_Unknown
 175 };
 176
 177 // Returns the target ABI, or else a StringError if the requested ABIName is
 178 // not supported for the given TT and FeatureBits combination.
 179 ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits,
 180                      StringRef ABIName);
 181
 182 } // namespace RISCVABI
 183
 184 namespace RISCVFeatures {
 185
 186 // Validates if the given combination of features are valid for the target
 187 // triple. Exits with report_fatal_error if not.
 188 void validate(const Triple &TT, const FeatureBitset &FeatureBits);
 189
 190 } // namespace RISCVFeatures
 191
 192 } // namespace llvm
 193
 194 #endif