lib/Target/X86/X86FloatingPoint.cpp

   1 //===-- X86FloatingPoint.cpp - Floating point Reg -> Stack converter ------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines the pass which converts floating point instructions from
  10 // pseudo registers into register stack instructions.  This pass uses live
  11 // variable information to indicate where the FPn registers are used and their
  12 // lifetimes.
  13 //
  14 // The x87 hardware tracks liveness of the stack registers, so it is necessary
  15 // to implement exact liveness tracking between basic blocks. The CFG edges are
  16 // partitioned into bundles where the same FP registers must be live in
  17 // identical stack positions. Instructions are inserted at the end of each basic
  18 // block to rearrange the live registers to match the outgoing bundle.
  19 //
  20 // This approach avoids splitting critical edges at the potential cost of more
  21 // live register shuffling instructions when critical edges are present.
  22 //
  23 //===----------------------------------------------------------------------===//
  24
  25 #include "X86.h"
  26 #include "X86InstrInfo.h"
  27 #include "llvm/ADT/DepthFirstIterator.h"
  28 #include "llvm/ADT/STLExtras.h"
  29 #include "llvm/ADT/SmallPtrSet.h"
  30 #include "llvm/ADT/SmallSet.h"
  31 #include "llvm/ADT/SmallVector.h"
  32 #include "llvm/ADT/Statistic.h"
  33 #include "llvm/CodeGen/EdgeBundles.h"
  34 #include "llvm/CodeGen/LivePhysRegs.h"
  35 #include "llvm/CodeGen/MachineFunctionPass.h"
  36 #include "llvm/CodeGen/MachineInstrBuilder.h"
  37 #include "llvm/CodeGen/MachineRegisterInfo.h"
  38 #include "llvm/CodeGen/Passes.h"
  39 #include "llvm/CodeGen/TargetInstrInfo.h"
  40 #include "llvm/CodeGen/TargetSubtargetInfo.h"
  41 #include "llvm/Config/llvm-config.h"
  42 #include "llvm/IR/InlineAsm.h"
  43 #include "llvm/Support/Debug.h"
  44 #include "llvm/Support/ErrorHandling.h"
  45 #include "llvm/Support/raw_ostream.h"
  46 #include "llvm/Target/TargetMachine.h"
  47 #include <algorithm>
  48 #include <bitset>
  49 using namespace llvm;
  50
  51 #define DEBUG_TYPE "x86-codegen"
  52
  53 STATISTIC(NumFXCH, "Number of fxch instructions inserted");
  54 STATISTIC(NumFP  , "Number of floating point instructions");
  55
  56 namespace {
  57   const unsigned ScratchFPReg = 7;
  58
  59   struct FPS : public MachineFunctionPass {
  60     static char ID;
  61     FPS() : MachineFunctionPass(ID) {
  62       // This is really only to keep valgrind quiet.
  63       // The logic in isLive() is too much for it.
  64       memset(Stack, 0, sizeof(Stack));
  65       memset(RegMap, 0, sizeof(RegMap));
  66     }
  67
  68     void getAnalysisUsage(AnalysisUsage &AU) const override {
  69       AU.setPreservesCFG();
  70       AU.addRequired<EdgeBundles>();
  71       AU.addPreservedID(MachineLoopInfoID);
  72       AU.addPreservedID(MachineDominatorsID);
  73       MachineFunctionPass::getAnalysisUsage(AU);
  74     }
  75
  76     bool runOnMachineFunction(MachineFunction &MF) override;
  77
  78     MachineFunctionProperties getRequiredProperties() const override {
  79       return MachineFunctionProperties().set(
  80           MachineFunctionProperties::Property::NoVRegs);
  81     }
  82
  83     StringRef getPassName() const override { return "X86 FP Stackifier"; }
  84
  85   private:
  86     const TargetInstrInfo *TII; // Machine instruction info.
  87
  88     // Two CFG edges are related if they leave the same block, or enter the same
  89     // block. The transitive closure of an edge under this relation is a
  90     // LiveBundle. It represents a set of CFG edges where the live FP stack
  91     // registers must be allocated identically in the x87 stack.
  92     //
  93     // A LiveBundle is usually all the edges leaving a block, or all the edges
  94     // entering a block, but it can contain more edges if critical edges are
  95     // present.
  96     //
  97     // The set of live FP registers in a LiveBundle is calculated by bundleCFG,
  98     // but the exact mapping of FP registers to stack slots is fixed later.
  99     struct LiveBundle {
 100       // Bit mask of live FP registers. Bit 0 = FP0, bit 1 = FP1, &c.
 101       unsigned Mask;
 102
 103       // Number of pre-assigned live registers in FixStack. This is 0 when the
 104       // stack order has not yet been fixed.
 105       unsigned FixCount;
 106
 107       // Assigned stack order for live-in registers.
 108       // FixStack[i] == getStackEntry(i) for all i < FixCount.
 109       unsigned char FixStack[8];
 110
 111       LiveBundle() : Mask(0), FixCount(0) {}
 112
 113       // Have the live registers been assigned a stack order yet?
 114       bool isFixed() const { return !Mask || FixCount; }
 115     };
 116
 117     // Numbered LiveBundle structs. LiveBundles[0] is used for all CFG edges
 118     // with no live FP registers.
 119     SmallVector<LiveBundle, 8> LiveBundles;
 120
 121     // The edge bundle analysis provides indices into the LiveBundles vector.
 122     EdgeBundles *Bundles;
 123
 124     // Return a bitmask of FP registers in block's live-in list.
 125     static unsigned calcLiveInMask(MachineBasicBlock *MBB, bool RemoveFPs) {
 126       unsigned Mask = 0;
 127       for (MachineBasicBlock::livein_iterator I = MBB->livein_begin();
 128            I != MBB->livein_end(); ) {
 129         MCPhysReg Reg = I->PhysReg;
 130         static_assert(X86::FP6 - X86::FP0 == 6, "sequential regnums");
 131         if (Reg >= X86::FP0 && Reg <= X86::FP6) {
 132           Mask |= 1 << (Reg - X86::FP0);
 133           if (RemoveFPs) {
 134             I = MBB->removeLiveIn(I);
 135             continue;
 136           }
 137         }
 138         ++I;
 139       }
 140       return Mask;
 141     }
 142
 143     // Partition all the CFG edges into LiveBundles.
 144     void bundleCFGRecomputeKillFlags(MachineFunction &MF);
 145
 146     MachineBasicBlock *MBB;     // Current basic block
 147
 148     // The hardware keeps track of how many FP registers are live, so we have
 149     // to model that exactly. Usually, each live register corresponds to an
 150     // FP<n> register, but when dealing with calls, returns, and inline
 151     // assembly, it is sometimes necessary to have live scratch registers.
 152     unsigned Stack[8];          // FP<n> Registers in each stack slot...
 153     unsigned StackTop;          // The current top of the FP stack.
 154
 155     enum {
 156       NumFPRegs = 8             // Including scratch pseudo-registers.
 157     };
 158
 159     // For each live FP<n> register, point to its Stack[] entry.
 160     // The first entries correspond to FP0-FP6, the rest are scratch registers
 161     // used when we need slightly different live registers than what the
 162     // register allocator thinks.
 163     unsigned RegMap[NumFPRegs];
 164
 165     // Set up our stack model to match the incoming registers to MBB.
 166     void setupBlockStack();
 167
 168     // Shuffle live registers to match the expectations of successor blocks.
 169     void finishBlockStack();
 170
 171 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
 172     void dumpStack() const {
 173       dbgs() << "Stack contents:";
 174       for (unsigned i = 0; i != StackTop; ++i) {
 175         dbgs() << " FP" << Stack[i];
 176         assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!");
 177       }
 178     }
 179 #endif
 180
 181     /// getSlot - Return the stack slot number a particular register number is
 182     /// in.
 183     unsigned getSlot(unsigned RegNo) const {
 184       assert(RegNo < NumFPRegs && "Regno out of range!");
 185       return RegMap[RegNo];
 186     }
 187
 188     /// isLive - Is RegNo currently live in the stack?
 189     bool isLive(unsigned RegNo) const {
 190       unsigned Slot = getSlot(RegNo);
 191       return Slot < StackTop && Stack[Slot] == RegNo;
 192     }
 193
 194     /// getStackEntry - Return the X86::FP<n> register in register ST(i).
 195     unsigned getStackEntry(unsigned STi) const {
 196       if (STi >= StackTop)
 197         report_fatal_error("Access past stack top!");
 198       return Stack[StackTop-1-STi];
 199     }
 200
 201     /// getSTReg - Return the X86::ST(i) register which contains the specified
 202     /// FP<RegNo> register.
 203     unsigned getSTReg(unsigned RegNo) const {
 204       return StackTop - 1 - getSlot(RegNo) + X86::ST0;
 205     }
 206
 207     // pushReg - Push the specified FP<n> register onto the stack.
 208     void pushReg(unsigned Reg) {
 209       assert(Reg < NumFPRegs && "Register number out of range!");
 210       if (StackTop >= 8)
 211         report_fatal_error("Stack overflow!");
 212       Stack[StackTop] = Reg;
 213       RegMap[Reg] = StackTop++;
 214     }
 215
 216     // popReg - Pop a register from the stack.
 217     void popReg() {
 218       if (StackTop == 0)
 219         report_fatal_error("Cannot pop empty stack!");
 220       RegMap[Stack[--StackTop]] = ~0;     // Update state
 221     }
 222
 223     bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; }
 224     void moveToTop(unsigned RegNo, MachineBasicBlock::iterator I) {
 225       DebugLoc dl = I == MBB->end() ? DebugLoc() : I->getDebugLoc();
 226       if (isAtTop(RegNo)) return;
 227
 228       unsigned STReg = getSTReg(RegNo);
 229       unsigned RegOnTop = getStackEntry(0);
 230
 231       // Swap the slots the regs are in.
 232       std::swap(RegMap[RegNo], RegMap[RegOnTop]);
 233
 234       // Swap stack slot contents.
 235       if (RegMap[RegOnTop] >= StackTop)
 236         report_fatal_error("Access past stack top!");
 237       std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
 238
 239       // Emit an fxch to update the runtime processors version of the state.
 240       BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg);
 241       ++NumFXCH;
 242     }
 243
 244     void duplicateToTop(unsigned RegNo, unsigned AsReg,
 245                         MachineBasicBlock::iterator I) {
 246       DebugLoc dl = I == MBB->end() ? DebugLoc() : I->getDebugLoc();
 247       unsigned STReg = getSTReg(RegNo);
 248       pushReg(AsReg);   // New register on top of stack
 249
 250       BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg);
 251     }
 252
 253     /// popStackAfter - Pop the current value off of the top of the FP stack
 254     /// after the specified instruction.
 255     void popStackAfter(MachineBasicBlock::iterator &I);
 256
 257     /// freeStackSlotAfter - Free the specified register from the register
 258     /// stack, so that it is no longer in a register.  If the register is
 259     /// currently at the top of the stack, we just pop the current instruction,
 260     /// otherwise we store the current top-of-stack into the specified slot,
 261     /// then pop the top of stack.
 262     void freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned Reg);
 263
 264     /// freeStackSlotBefore - Just the pop, no folding. Return the inserted
 265     /// instruction.
 266     MachineBasicBlock::iterator
 267     freeStackSlotBefore(MachineBasicBlock::iterator I, unsigned FPRegNo);
 268
 269     /// Adjust the live registers to be the set in Mask.
 270     void adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I);
 271
 272     /// Shuffle the top FixCount stack entries such that FP reg FixStack[0] is
 273     /// st(0), FP reg FixStack[1] is st(1) etc.
 274     void shuffleStackTop(const unsigned char *FixStack, unsigned FixCount,
 275                          MachineBasicBlock::iterator I);
 276
 277     bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB);
 278
 279     void handleCall(MachineBasicBlock::iterator &I);
 280     void handleReturn(MachineBasicBlock::iterator &I);
 281     void handleZeroArgFP(MachineBasicBlock::iterator &I);
 282     void handleOneArgFP(MachineBasicBlock::iterator &I);
 283     void handleOneArgFPRW(MachineBasicBlock::iterator &I);
 284     void handleTwoArgFP(MachineBasicBlock::iterator &I);
 285     void handleCompareFP(MachineBasicBlock::iterator &I);
 286     void handleCondMovFP(MachineBasicBlock::iterator &I);
 287     void handleSpecialFP(MachineBasicBlock::iterator &I);
 288
 289     // Check if a COPY instruction is using FP registers.
 290     static bool isFPCopy(MachineInstr &MI) {
 291       Register DstReg = MI.getOperand(0).getReg();
 292       Register SrcReg = MI.getOperand(1).getReg();
 293
 294       return X86::RFP80RegClass.contains(DstReg) ||
 295         X86::RFP80RegClass.contains(SrcReg);
 296     }
 297
 298     void setKillFlags(MachineBasicBlock &MBB) const;
 299   };
 300 }
 301
 302 char FPS::ID = 0;
 303
 304 INITIALIZE_PASS_BEGIN(FPS, DEBUG_TYPE, "X86 FP Stackifier",
 305                       false, false)
 306 INITIALIZE_PASS_DEPENDENCY(EdgeBundles)
 307 INITIALIZE_PASS_END(FPS, DEBUG_TYPE, "X86 FP Stackifier",
 308                     false, false)
 309
 310 FunctionPass *llvm::createX86FloatingPointStackifierPass() { return new FPS(); }
 311
 312 /// getFPReg - Return the X86::FPx register number for the specified operand.
 313 /// For example, this returns 3 for X86::FP3.
 314 static unsigned getFPReg(const MachineOperand &MO) {
 315   assert(MO.isReg() && "Expected an FP register!");
 316   Register Reg = MO.getReg();
 317   assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!");
 318   return Reg - X86::FP0;
 319 }
 320
 321 /// runOnMachineFunction - Loop over all of the basic blocks, transforming FP
 322 /// register references into FP stack references.
 323 ///
 324 bool FPS::runOnMachineFunction(MachineFunction &MF) {
 325   // We only need to run this pass if there are any FP registers used in this
 326   // function.  If it is all integer, there is nothing for us to do!
 327   bool FPIsUsed = false;
 328
 329   static_assert(X86::FP6 == X86::FP0+6, "Register enums aren't sorted right!");
 330   const MachineRegisterInfo &MRI = MF.getRegInfo();
 331   for (unsigned i = 0; i <= 6; ++i)
 332     if (!MRI.reg_nodbg_empty(X86::FP0 + i)) {
 333       FPIsUsed = true;
 334       break;
 335     }
 336
 337   // Early exit.
 338   if (!FPIsUsed) return false;
 339
 340   Bundles = &getAnalysis<EdgeBundles>();
 341   TII = MF.getSubtarget().getInstrInfo();
 342
 343   // Prepare cross-MBB liveness.
 344   bundleCFGRecomputeKillFlags(MF);
 345
 346   StackTop = 0;
 347
 348   // Process the function in depth first order so that we process at least one
 349   // of the predecessors for every reachable block in the function.
 350   df_iterator_default_set<MachineBasicBlock*> Processed;
 351   MachineBasicBlock *Entry = &MF.front();
 352
 353   LiveBundle &Bundle =
 354     LiveBundles[Bundles->getBundle(Entry->getNumber(), false)];
 355
 356   // In regcall convention, some FP registers may not be passed through
 357   // the stack, so they will need to be assigned to the stack first
 358   if ((Entry->getParent()->getFunction().getCallingConv() ==
 359     CallingConv::X86_RegCall) && (Bundle.Mask && !Bundle.FixCount)) {
 360     // In the register calling convention, up to one FP argument could be
 361     // saved in the first FP register.
 362     // If bundle.mask is non-zero and Bundle.FixCount is zero, it means
 363     // that the FP registers contain arguments.
 364     // The actual value is passed in FP0.
 365     // Here we fix the stack and mark FP0 as pre-assigned register.
 366     assert((Bundle.Mask & 0xFE) == 0 &&
 367       "Only FP0 could be passed as an argument");
 368     Bundle.FixCount = 1;
 369     Bundle.FixStack[0] = 0;
 370   }
 371
 372   bool Changed = false;
 373   for (MachineBasicBlock *BB : depth_first_ext(Entry, Processed))
 374     Changed |= processBasicBlock(MF, *BB);
 375
 376   // Process any unreachable blocks in arbitrary order now.
 377   if (MF.size() != Processed.size())
 378     for (MachineBasicBlock &BB : MF)
 379       if (Processed.insert(&BB).second)
 380         Changed |= processBasicBlock(MF, BB);
 381
 382   LiveBundles.clear();
 383
 384   return Changed;
 385 }
 386
 387 /// bundleCFG - Scan all the basic blocks to determine consistent live-in and
 388 /// live-out sets for the FP registers. Consistent means that the set of
 389 /// registers live-out from a block is identical to the live-in set of all
 390 /// successors. This is not enforced by the normal live-in lists since
 391 /// registers may be implicitly defined, or not used by all successors.
 392 void FPS::bundleCFGRecomputeKillFlags(MachineFunction &MF) {
 393   assert(LiveBundles.empty() && "Stale data in LiveBundles");
 394   LiveBundles.resize(Bundles->getNumBundles());
 395
 396   // Gather the actual live-in masks for all MBBs.
 397   for (MachineBasicBlock &MBB : MF) {
 398     setKillFlags(MBB);
 399
 400     const unsigned Mask = calcLiveInMask(&MBB, false);
 401     if (!Mask)
 402       continue;
 403     // Update MBB ingoing bundle mask.
 404     LiveBundles[Bundles->getBundle(MBB.getNumber(), false)].Mask |= Mask;
 405   }
 406 }
 407
 408 /// processBasicBlock - Loop over all of the instructions in the basic block,
 409 /// transforming FP instructions into their stack form.
 410 ///
 411 bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
 412   bool Changed = false;
 413   MBB = &BB;
 414
 415   setupBlockStack();
 416
 417   for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
 418     MachineInstr &MI = *I;
 419     uint64_t Flags = MI.getDesc().TSFlags;
 420
 421     unsigned FPInstClass = Flags & X86II::FPTypeMask;
 422     if (MI.isInlineAsm())
 423       FPInstClass = X86II::SpecialFP;
 424
 425     if (MI.isCopy() && isFPCopy(MI))
 426       FPInstClass = X86II::SpecialFP;
 427
 428     if (MI.isImplicitDef() &&
 429         X86::RFP80RegClass.contains(MI.getOperand(0).getReg()))
 430       FPInstClass = X86II::SpecialFP;
 431
 432     if (MI.isCall())
 433       FPInstClass = X86II::SpecialFP;
 434
 435     if (FPInstClass == X86II::NotFP)
 436       continue;  // Efficiently ignore non-fp insts!
 437
 438     MachineInstr *PrevMI = nullptr;
 439     if (I != BB.begin())
 440       PrevMI = &*std::prev(I);
 441
 442     ++NumFP;  // Keep track of # of pseudo instrs
 443     LLVM_DEBUG(dbgs() << "\nFPInst:\t" << MI);
 444
 445     // Get dead variables list now because the MI pointer may be deleted as part
 446     // of processing!
 447     SmallVector<unsigned, 8> DeadRegs;
 448     for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
 449       const MachineOperand &MO = MI.getOperand(i);
 450       if (MO.isReg() && MO.isDead())
 451         DeadRegs.push_back(MO.getReg());
 452     }
 453
 454     switch (FPInstClass) {
 455     case X86II::ZeroArgFP:  handleZeroArgFP(I); break;
 456     case X86II::OneArgFP:   handleOneArgFP(I);  break;  // fstp ST(0)
 457     case X86II::OneArgFPRW: handleOneArgFPRW(I); break; // ST(0) = fsqrt(ST(0))
 458     case X86II::TwoArgFP:   handleTwoArgFP(I);  break;
 459     case X86II::CompareFP:  handleCompareFP(I); break;
 460     case X86II::CondMovFP:  handleCondMovFP(I); break;
 461     case X86II::SpecialFP:  handleSpecialFP(I); break;
 462     default: llvm_unreachable("Unknown FP Type!");
 463     }
 464
 465     // Check to see if any of the values defined by this instruction are dead
 466     // after definition.  If so, pop them.
 467     for (unsigned i = 0, e = DeadRegs.size(); i != e; ++i) {
 468       unsigned Reg = DeadRegs[i];
 469       // Check if Reg is live on the stack. An inline-asm register operand that
 470       // is in the clobber list and marked dead might not be live on the stack.
 471       static_assert(X86::FP7 - X86::FP0 == 7, "sequential FP regnumbers");
 472       if (Reg >= X86::FP0 && Reg <= X86::FP6 && isLive(Reg-X86::FP0)) {
 473         LLVM_DEBUG(dbgs() << "Register FP#" << Reg - X86::FP0 << " is dead!\n");
 474         freeStackSlotAfter(I, Reg-X86::FP0);
 475       }
 476     }
 477
 478     // Print out all of the instructions expanded to if -debug
 479     LLVM_DEBUG({
 480       MachineBasicBlock::iterator PrevI = PrevMI;
 481       if (I == PrevI) {
 482         dbgs() << "Just deleted pseudo instruction\n";
 483       } else {
 484         MachineBasicBlock::iterator Start = I;
 485         // Rewind to first instruction newly inserted.
 486         while (Start != BB.begin() && std::prev(Start) != PrevI)
 487           --Start;
 488         dbgs() << "Inserted instructions:\n\t";
 489         Start->print(dbgs());
 490         while (++Start != std::next(I)) {
 491         }
 492       }
 493       dumpStack();
 494     });
 495     (void)PrevMI;
 496
 497     Changed = true;
 498   }
 499
 500   finishBlockStack();
 501
 502   return Changed;
 503 }
 504
 505 /// setupBlockStack - Use the live bundles to set up our model of the stack
 506 /// to match predecessors' live out stack.
 507 void FPS::setupBlockStack() {
 508   LLVM_DEBUG(dbgs() << "\nSetting up live-ins for " << printMBBReference(*MBB)
 509                     << " derived from " << MBB->getName() << ".\n");
 510   StackTop = 0;
 511   // Get the live-in bundle for MBB.
 512   const LiveBundle &Bundle =
 513     LiveBundles[Bundles->getBundle(MBB->getNumber(), false)];
 514
 515   if (!Bundle.Mask) {
 516     LLVM_DEBUG(dbgs() << "Block has no FP live-ins.\n");
 517     return;
 518   }
 519
 520   // Depth-first iteration should ensure that we always have an assigned stack.
 521   assert(Bundle.isFixed() && "Reached block before any predecessors");
 522
 523   // Push the fixed live-in registers.
 524   for (unsigned i = Bundle.FixCount; i > 0; --i) {
 525     LLVM_DEBUG(dbgs() << "Live-in st(" << (i - 1) << "): %fp"
 526                       << unsigned(Bundle.FixStack[i - 1]) << '\n');
 527     pushReg(Bundle.FixStack[i-1]);
 528   }
 529
 530   // Kill off unwanted live-ins. This can happen with a critical edge.
 531   // FIXME: We could keep these live registers around as zombies. They may need
 532   // to be revived at the end of a short block. It might save a few instrs.
 533   unsigned Mask = calcLiveInMask(MBB, /*RemoveFPs=*/true);
 534   adjustLiveRegs(Mask, MBB->begin());
 535   LLVM_DEBUG(MBB->dump());
 536 }
 537
 538 /// finishBlockStack - Revive live-outs that are implicitly defined out of
 539 /// MBB. Shuffle live registers to match the expected fixed stack of any
 540 /// predecessors, and ensure that all predecessors are expecting the same
 541 /// stack.
 542 void FPS::finishBlockStack() {
 543   // The RET handling below takes care of return blocks for us.
 544   if (MBB->succ_empty())
 545     return;
 546
 547   LLVM_DEBUG(dbgs() << "Setting up live-outs for " << printMBBReference(*MBB)
 548                     << " derived from " << MBB->getName() << ".\n");
 549
 550   // Get MBB's live-out bundle.
 551   unsigned BundleIdx = Bundles->getBundle(MBB->getNumber(), true);
 552   LiveBundle &Bundle = LiveBundles[BundleIdx];
 553
 554   // We may need to kill and define some registers to match successors.
 555   // FIXME: This can probably be combined with the shuffle below.
 556   MachineBasicBlock::iterator Term = MBB->getFirstTerminator();
 557   adjustLiveRegs(Bundle.Mask, Term);
 558
 559   if (!Bundle.Mask) {
 560     LLVM_DEBUG(dbgs() << "No live-outs.\n");
 561     return;
 562   }
 563
 564   // Has the stack order been fixed yet?
 565   LLVM_DEBUG(dbgs() << "LB#" << BundleIdx << ": ");
 566   if (Bundle.isFixed()) {
 567     LLVM_DEBUG(dbgs() << "Shuffling stack to match.\n");
 568     shuffleStackTop(Bundle.FixStack, Bundle.FixCount, Term);
 569   } else {
 570     // Not fixed yet, we get to choose.
 571     LLVM_DEBUG(dbgs() << "Fixing stack order now.\n");
 572     Bundle.FixCount = StackTop;
 573     for (unsigned i = 0; i < StackTop; ++i)
 574       Bundle.FixStack[i] = getStackEntry(i);
 575   }
 576 }
 577
 578
 579 //===----------------------------------------------------------------------===//
 580 // Efficient Lookup Table Support
 581 //===----------------------------------------------------------------------===//
 582
 583 namespace {
 584   struct TableEntry {
 585     uint16_t from;
 586     uint16_t to;
 587     bool operator<(const TableEntry &TE) const { return from < TE.from; }
 588     friend bool operator<(const TableEntry &TE, unsigned V) {
 589       return TE.from < V;
 590     }
 591     friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned V,
 592                                                 const TableEntry &TE) {
 593       return V < TE.from;
 594     }
 595   };
 596 }
 597
 598 static int Lookup(ArrayRef<TableEntry> Table, unsigned Opcode) {
 599   const TableEntry *I = llvm::lower_bound(Table, Opcode);
 600   if (I != Table.end() && I->from == Opcode)
 601     return I->to;
 602   return -1;
 603 }
 604
 605 #ifdef NDEBUG
 606 #define ASSERT_SORTED(TABLE)
 607 #else
 608 #define ASSERT_SORTED(TABLE)                                                   \
 609   {                                                                            \
 610     static std::atomic<bool> TABLE##Checked(false);                            \
 611     if (!TABLE##Checked.load(std::memory_order_relaxed)) {                     \
 612       assert(std::is_sorted(std::begin(TABLE), std::end(TABLE)) &&             \
 613              "All lookup tables must be sorted for efficient access!");        \
 614       TABLE##Checked.store(true, std::memory_order_relaxed);                   \
 615     }                                                                          \
 616   }
 617 #endif
 618
 619 //===----------------------------------------------------------------------===//
 620 // Register File -> Register Stack Mapping Methods
 621 //===----------------------------------------------------------------------===//
 622
 623 // OpcodeTable - Sorted map of register instructions to their stack version.
 624 // The first element is an register file pseudo instruction, the second is the
 625 // concrete X86 instruction which uses the register stack.
 626 //
 627 static const TableEntry OpcodeTable[] = {
 628   { X86::ABS_Fp32     , X86::ABS_F     },
 629   { X86::ABS_Fp64     , X86::ABS_F     },
 630   { X86::ABS_Fp80     , X86::ABS_F     },
 631   { X86::ADD_Fp32m    , X86::ADD_F32m  },
 632   { X86::ADD_Fp64m    , X86::ADD_F64m  },
 633   { X86::ADD_Fp64m32  , X86::ADD_F32m  },
 634   { X86::ADD_Fp80m32  , X86::ADD_F32m  },
 635   { X86::ADD_Fp80m64  , X86::ADD_F64m  },
 636   { X86::ADD_FpI16m32 , X86::ADD_FI16m },
 637   { X86::ADD_FpI16m64 , X86::ADD_FI16m },
 638   { X86::ADD_FpI16m80 , X86::ADD_FI16m },
 639   { X86::ADD_FpI32m32 , X86::ADD_FI32m },
 640   { X86::ADD_FpI32m64 , X86::ADD_FI32m },
 641   { X86::ADD_FpI32m80 , X86::ADD_FI32m },
 642   { X86::CHS_Fp32     , X86::CHS_F     },
 643   { X86::CHS_Fp64     , X86::CHS_F     },
 644   { X86::CHS_Fp80     , X86::CHS_F     },
 645   { X86::CMOVBE_Fp32  , X86::CMOVBE_F  },
 646   { X86::CMOVBE_Fp64  , X86::CMOVBE_F  },
 647   { X86::CMOVBE_Fp80  , X86::CMOVBE_F  },
 648   { X86::CMOVB_Fp32   , X86::CMOVB_F   },
 649   { X86::CMOVB_Fp64   , X86::CMOVB_F  },
 650   { X86::CMOVB_Fp80   , X86::CMOVB_F  },
 651   { X86::CMOVE_Fp32   , X86::CMOVE_F  },
 652   { X86::CMOVE_Fp64   , X86::CMOVE_F   },
 653   { X86::CMOVE_Fp80   , X86::CMOVE_F   },
 654   { X86::CMOVNBE_Fp32 , X86::CMOVNBE_F },
 655   { X86::CMOVNBE_Fp64 , X86::CMOVNBE_F },
 656   { X86::CMOVNBE_Fp80 , X86::CMOVNBE_F },
 657   { X86::CMOVNB_Fp32  , X86::CMOVNB_F  },
 658   { X86::CMOVNB_Fp64  , X86::CMOVNB_F  },
 659   { X86::CMOVNB_Fp80  , X86::CMOVNB_F  },
 660   { X86::CMOVNE_Fp32  , X86::CMOVNE_F  },
 661   { X86::CMOVNE_Fp64  , X86::CMOVNE_F  },
 662   { X86::CMOVNE_Fp80  , X86::CMOVNE_F  },
 663   { X86::CMOVNP_Fp32  , X86::CMOVNP_F  },
 664   { X86::CMOVNP_Fp64  , X86::CMOVNP_F  },
 665   { X86::CMOVNP_Fp80  , X86::CMOVNP_F  },
 666   { X86::CMOVP_Fp32   , X86::CMOVP_F   },
 667   { X86::CMOVP_Fp64   , X86::CMOVP_F   },
 668   { X86::CMOVP_Fp80   , X86::CMOVP_F   },
 669   { X86::COS_Fp32     , X86::COS_F     },
 670   { X86::COS_Fp64     , X86::COS_F     },
 671   { X86::COS_Fp80     , X86::COS_F     },
 672   { X86::DIVR_Fp32m   , X86::DIVR_F32m },
 673   { X86::DIVR_Fp64m   , X86::DIVR_F64m },
 674   { X86::DIVR_Fp64m32 , X86::DIVR_F32m },
 675   { X86::DIVR_Fp80m32 , X86::DIVR_F32m },
 676   { X86::DIVR_Fp80m64 , X86::DIVR_F64m },
 677   { X86::DIVR_FpI16m32, X86::DIVR_FI16m},
 678   { X86::DIVR_FpI16m64, X86::DIVR_FI16m},
 679   { X86::DIVR_FpI16m80, X86::DIVR_FI16m},
 680   { X86::DIVR_FpI32m32, X86::DIVR_FI32m},
 681   { X86::DIVR_FpI32m64, X86::DIVR_FI32m},
 682   { X86::DIVR_FpI32m80, X86::DIVR_FI32m},
 683   { X86::DIV_Fp32m    , X86::DIV_F32m  },
 684   { X86::DIV_Fp64m    , X86::DIV_F64m  },
 685   { X86::DIV_Fp64m32  , X86::DIV_F32m  },
 686   { X86::DIV_Fp80m32  , X86::DIV_F32m  },
 687   { X86::DIV_Fp80m64  , X86::DIV_F64m  },
 688   { X86::DIV_FpI16m32 , X86::DIV_FI16m },
 689   { X86::DIV_FpI16m64 , X86::DIV_FI16m },
 690   { X86::DIV_FpI16m80 , X86::DIV_FI16m },
 691   { X86::DIV_FpI32m32 , X86::DIV_FI32m },
 692   { X86::DIV_FpI32m64 , X86::DIV_FI32m },
 693   { X86::DIV_FpI32m80 , X86::DIV_FI32m },
 694   { X86::ILD_Fp16m32  , X86::ILD_F16m  },
 695   { X86::ILD_Fp16m64  , X86::ILD_F16m  },
 696   { X86::ILD_Fp16m80  , X86::ILD_F16m  },
 697   { X86::ILD_Fp32m32  , X86::ILD_F32m  },
 698   { X86::ILD_Fp32m64  , X86::ILD_F32m  },
 699   { X86::ILD_Fp32m80  , X86::ILD_F32m  },
 700   { X86::ILD_Fp64m32  , X86::ILD_F64m  },
 701   { X86::ILD_Fp64m64  , X86::ILD_F64m  },
 702   { X86::ILD_Fp64m80  , X86::ILD_F64m  },
 703   { X86::ISTT_Fp16m32 , X86::ISTT_FP16m},
 704   { X86::ISTT_Fp16m64 , X86::ISTT_FP16m},
 705   { X86::ISTT_Fp16m80 , X86::ISTT_FP16m},
 706   { X86::ISTT_Fp32m32 , X86::ISTT_FP32m},
 707   { X86::ISTT_Fp32m64 , X86::ISTT_FP32m},
 708   { X86::ISTT_Fp32m80 , X86::ISTT_FP32m},
 709   { X86::ISTT_Fp64m32 , X86::ISTT_FP64m},
 710   { X86::ISTT_Fp64m64 , X86::ISTT_FP64m},
 711   { X86::ISTT_Fp64m80 , X86::ISTT_FP64m},
 712   { X86::IST_Fp16m32  , X86::IST_F16m  },
 713   { X86::IST_Fp16m64  , X86::IST_F16m  },
 714   { X86::IST_Fp16m80  , X86::IST_F16m  },
 715   { X86::IST_Fp32m32  , X86::IST_F32m  },
 716   { X86::IST_Fp32m64  , X86::IST_F32m  },
 717   { X86::IST_Fp32m80  , X86::IST_F32m  },
 718   { X86::IST_Fp64m32  , X86::IST_FP64m },
 719   { X86::IST_Fp64m64  , X86::IST_FP64m },
 720   { X86::IST_Fp64m80  , X86::IST_FP64m },
 721   { X86::LD_Fp032     , X86::LD_F0     },
 722   { X86::LD_Fp064     , X86::LD_F0     },
 723   { X86::LD_Fp080     , X86::LD_F0     },
 724   { X86::LD_Fp132     , X86::LD_F1     },
 725   { X86::LD_Fp164     , X86::LD_F1     },
 726   { X86::LD_Fp180     , X86::LD_F1     },
 727   { X86::LD_Fp32m     , X86::LD_F32m   },
 728   { X86::LD_Fp32m64   , X86::LD_F32m   },
 729   { X86::LD_Fp32m80   , X86::LD_F32m   },
 730   { X86::LD_Fp64m     , X86::LD_F64m   },
 731   { X86::LD_Fp64m80   , X86::LD_F64m   },
 732   { X86::LD_Fp80m     , X86::LD_F80m   },
 733   { X86::MUL_Fp32m    , X86::MUL_F32m  },
 734   { X86::MUL_Fp64m    , X86::MUL_F64m  },
 735   { X86::MUL_Fp64m32  , X86::MUL_F32m  },
 736   { X86::MUL_Fp80m32  , X86::MUL_F32m  },
 737   { X86::MUL_Fp80m64  , X86::MUL_F64m  },
 738   { X86::MUL_FpI16m32 , X86::MUL_FI16m },
 739   { X86::MUL_FpI16m64 , X86::MUL_FI16m },
 740   { X86::MUL_FpI16m80 , X86::MUL_FI16m },
 741   { X86::MUL_FpI32m32 , X86::MUL_FI32m },
 742   { X86::MUL_FpI32m64 , X86::MUL_FI32m },
 743   { X86::MUL_FpI32m80 , X86::MUL_FI32m },
 744   { X86::SIN_Fp32     , X86::SIN_F     },
 745   { X86::SIN_Fp64     , X86::SIN_F     },
 746   { X86::SIN_Fp80     , X86::SIN_F     },
 747   { X86::SQRT_Fp32    , X86::SQRT_F    },
 748   { X86::SQRT_Fp64    , X86::SQRT_F    },
 749   { X86::SQRT_Fp80    , X86::SQRT_F    },
 750   { X86::ST_Fp32m     , X86::ST_F32m   },
 751   { X86::ST_Fp64m     , X86::ST_F64m   },
 752   { X86::ST_Fp64m32   , X86::ST_F32m   },
 753   { X86::ST_Fp80m32   , X86::ST_F32m   },
 754   { X86::ST_Fp80m64   , X86::ST_F64m   },
 755   { X86::ST_FpP80m    , X86::ST_FP80m  },
 756   { X86::SUBR_Fp32m   , X86::SUBR_F32m },
 757   { X86::SUBR_Fp64m   , X86::SUBR_F64m },
 758   { X86::SUBR_Fp64m32 , X86::SUBR_F32m },
 759   { X86::SUBR_Fp80m32 , X86::SUBR_F32m },
 760   { X86::SUBR_Fp80m64 , X86::SUBR_F64m },
 761   { X86::SUBR_FpI16m32, X86::SUBR_FI16m},
 762   { X86::SUBR_FpI16m64, X86::SUBR_FI16m},
 763   { X86::SUBR_FpI16m80, X86::SUBR_FI16m},
 764   { X86::SUBR_FpI32m32, X86::SUBR_FI32m},
 765   { X86::SUBR_FpI32m64, X86::SUBR_FI32m},
 766   { X86::SUBR_FpI32m80, X86::SUBR_FI32m},
 767   { X86::SUB_Fp32m    , X86::SUB_F32m  },
 768   { X86::SUB_Fp64m    , X86::SUB_F64m  },
 769   { X86::SUB_Fp64m32  , X86::SUB_F32m  },
 770   { X86::SUB_Fp80m32  , X86::SUB_F32m  },
 771   { X86::SUB_Fp80m64  , X86::SUB_F64m  },
 772   { X86::SUB_FpI16m32 , X86::SUB_FI16m },
 773   { X86::SUB_FpI16m64 , X86::SUB_FI16m },
 774   { X86::SUB_FpI16m80 , X86::SUB_FI16m },
 775   { X86::SUB_FpI32m32 , X86::SUB_FI32m },
 776   { X86::SUB_FpI32m64 , X86::SUB_FI32m },
 777   { X86::SUB_FpI32m80 , X86::SUB_FI32m },
 778   { X86::TST_Fp32     , X86::TST_F     },
 779   { X86::TST_Fp64     , X86::TST_F     },
 780   { X86::TST_Fp80     , X86::TST_F     },
 781   { X86::UCOM_FpIr32  , X86::UCOM_FIr  },
 782   { X86::UCOM_FpIr64  , X86::UCOM_FIr  },
 783   { X86::UCOM_FpIr80  , X86::UCOM_FIr  },
 784   { X86::UCOM_Fpr32   , X86::UCOM_Fr   },
 785   { X86::UCOM_Fpr64   , X86::UCOM_Fr   },
 786   { X86::UCOM_Fpr80   , X86::UCOM_Fr   },
 787 };
 788
 789 static unsigned getConcreteOpcode(unsigned Opcode) {
 790   ASSERT_SORTED(OpcodeTable);
 791   int Opc = Lookup(OpcodeTable, Opcode);
 792   assert(Opc != -1 && "FP Stack instruction not in OpcodeTable!");
 793   return Opc;
 794 }
 795
 796 //===----------------------------------------------------------------------===//
 797 // Helper Methods
 798 //===----------------------------------------------------------------------===//
 799
 800 // PopTable - Sorted map of instructions to their popping version.  The first
 801 // element is an instruction, the second is the version which pops.
 802 //
 803 static const TableEntry PopTable[] = {
 804   { X86::ADD_FrST0 , X86::ADD_FPrST0  },
 805
 806   { X86::DIVR_FrST0, X86::DIVR_FPrST0 },
 807   { X86::DIV_FrST0 , X86::DIV_FPrST0  },
 808
 809   { X86::IST_F16m  , X86::IST_FP16m   },
 810   { X86::IST_F32m  , X86::IST_FP32m   },
 811
 812   { X86::MUL_FrST0 , X86::MUL_FPrST0  },
 813
 814   { X86::ST_F32m   , X86::ST_FP32m    },
 815   { X86::ST_F64m   , X86::ST_FP64m    },
 816   { X86::ST_Frr    , X86::ST_FPrr     },
 817
 818   { X86::SUBR_FrST0, X86::SUBR_FPrST0 },
 819   { X86::SUB_FrST0 , X86::SUB_FPrST0  },
 820
 821   { X86::UCOM_FIr  , X86::UCOM_FIPr   },
 822
 823   { X86::UCOM_FPr  , X86::UCOM_FPPr   },
 824   { X86::UCOM_Fr   , X86::UCOM_FPr    },
 825 };
 826
 827 /// popStackAfter - Pop the current value off of the top of the FP stack after
 828 /// the specified instruction.  This attempts to be sneaky and combine the pop
 829 /// into the instruction itself if possible.  The iterator is left pointing to
 830 /// the last instruction, be it a new pop instruction inserted, or the old
 831 /// instruction if it was modified in place.
 832 ///
 833 void FPS::popStackAfter(MachineBasicBlock::iterator &I) {
 834   MachineInstr &MI = *I;
 835   const DebugLoc &dl = MI.getDebugLoc();
 836   ASSERT_SORTED(PopTable);
 837
 838   popReg();
 839
 840   // Check to see if there is a popping version of this instruction...
 841   int Opcode = Lookup(PopTable, I->getOpcode());
 842   if (Opcode != -1) {
 843     I->setDesc(TII->get(Opcode));
 844     if (Opcode == X86::UCOM_FPPr)
 845       I->RemoveOperand(0);
 846   } else {    // Insert an explicit pop
 847     I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(X86::ST0);
 848   }
 849 }
 850
 851 /// freeStackSlotAfter - Free the specified register from the register stack, so
 852 /// that it is no longer in a register.  If the register is currently at the top
 853 /// of the stack, we just pop the current instruction, otherwise we store the
 854 /// current top-of-stack into the specified slot, then pop the top of stack.
 855 void FPS::freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned FPRegNo) {
 856   if (getStackEntry(0) == FPRegNo) {  // already at the top of stack? easy.
 857     popStackAfter(I);
 858     return;
 859   }
 860
 861   // Otherwise, store the top of stack into the dead slot, killing the operand
 862   // without having to add in an explicit xchg then pop.
 863   //
 864   I = freeStackSlotBefore(++I, FPRegNo);
 865 }
 866
 867 /// freeStackSlotBefore - Free the specified register without trying any
 868 /// folding.
 869 MachineBasicBlock::iterator
 870 FPS::freeStackSlotBefore(MachineBasicBlock::iterator I, unsigned FPRegNo) {
 871   unsigned STReg    = getSTReg(FPRegNo);
 872   unsigned OldSlot  = getSlot(FPRegNo);
 873   unsigned TopReg   = Stack[StackTop-1];
 874   Stack[OldSlot]    = TopReg;
 875   RegMap[TopReg]    = OldSlot;
 876   RegMap[FPRegNo]   = ~0;
 877   Stack[--StackTop] = ~0;
 878   return BuildMI(*MBB, I, DebugLoc(), TII->get(X86::ST_FPrr))
 879       .addReg(STReg)
 880       .getInstr();
 881 }
 882
 883 /// adjustLiveRegs - Kill and revive registers such that exactly the FP
 884 /// registers with a bit in Mask are live.
 885 void FPS::adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I) {
 886   unsigned Defs = Mask;
 887   unsigned Kills = 0;
 888   for (unsigned i = 0; i < StackTop; ++i) {
 889     unsigned RegNo = Stack[i];
 890     if (!(Defs & (1 << RegNo)))
 891       // This register is live, but we don't want it.
 892       Kills |= (1 << RegNo);
 893     else
 894       // We don't need to imp-def this live register.
 895       Defs &= ~(1 << RegNo);
 896   }
 897   assert((Kills & Defs) == 0 && "Register needs killing and def'ing?");
 898
 899   // Produce implicit-defs for free by using killed registers.
 900   while (Kills && Defs) {
 901     unsigned KReg = countTrailingZeros(Kills);
 902     unsigned DReg = countTrailingZeros(Defs);
 903     LLVM_DEBUG(dbgs() << "Renaming %fp" << KReg << " as imp %fp" << DReg
 904                       << "\n");
 905     std::swap(Stack[getSlot(KReg)], Stack[getSlot(DReg)]);
 906     std::swap(RegMap[KReg], RegMap[DReg]);
 907     Kills &= ~(1 << KReg);
 908     Defs &= ~(1 << DReg);
 909   }
 910
 911   // Kill registers by popping.
 912   if (Kills && I != MBB->begin()) {
 913     MachineBasicBlock::iterator I2 = std::prev(I);
 914     while (StackTop) {
 915       unsigned KReg = getStackEntry(0);
 916       if (!(Kills & (1 << KReg)))
 917         break;
 918       LLVM_DEBUG(dbgs() << "Popping %fp" << KReg << "\n");
 919       popStackAfter(I2);
 920       Kills &= ~(1 << KReg);
 921     }
 922   }
 923
 924   // Manually kill the rest.
 925   while (Kills) {
 926     unsigned KReg = countTrailingZeros(Kills);
 927     LLVM_DEBUG(dbgs() << "Killing %fp" << KReg << "\n");
 928     freeStackSlotBefore(I, KReg);
 929     Kills &= ~(1 << KReg);
 930   }
 931
 932   // Load zeros for all the imp-defs.
 933   while(Defs) {
 934     unsigned DReg = countTrailingZeros(Defs);
 935     LLVM_DEBUG(dbgs() << "Defining %fp" << DReg << " as 0\n");
 936     BuildMI(*MBB, I, DebugLoc(), TII->get(X86::LD_F0));
 937     pushReg(DReg);
 938     Defs &= ~(1 << DReg);
 939   }
 940
 941   // Now we should have the correct registers live.
 942   LLVM_DEBUG(dumpStack());
 943   assert(StackTop == countPopulation(Mask) && "Live count mismatch");
 944 }
 945
 946 /// shuffleStackTop - emit fxch instructions before I to shuffle the top
 947 /// FixCount entries into the order given by FixStack.
 948 /// FIXME: Is there a better algorithm than insertion sort?
 949 void FPS::shuffleStackTop(const unsigned char *FixStack,
 950                           unsigned FixCount,
 951                           MachineBasicBlock::iterator I) {
 952   // Move items into place, starting from the desired stack bottom.
 953   while (FixCount--) {
 954     // Old register at position FixCount.
 955     unsigned OldReg = getStackEntry(FixCount);
 956     // Desired register at position FixCount.
 957     unsigned Reg = FixStack[FixCount];
 958     if (Reg == OldReg)
 959       continue;
 960     // (Reg st0) (OldReg st0) = (Reg OldReg st0)
 961     moveToTop(Reg, I);
 962     if (FixCount > 0)
 963       moveToTop(OldReg, I);
 964   }
 965   LLVM_DEBUG(dumpStack());
 966 }
 967
 968
 969 //===----------------------------------------------------------------------===//
 970 // Instruction transformation implementation
 971 //===----------------------------------------------------------------------===//
 972
 973 void FPS::handleCall(MachineBasicBlock::iterator &I) {
 974   unsigned STReturns = 0;
 975   const MachineFunction* MF = I->getParent()->getParent();
 976
 977   for (const auto &MO : I->operands()) {
 978     if (!MO.isReg())
 979       continue;
 980
 981     unsigned R = MO.getReg() - X86::FP0;
 982
 983     if (R < 8) {
 984       if (MF->getFunction().getCallingConv() != CallingConv::X86_RegCall) {
 985         assert(MO.isDef() && MO.isImplicit());
 986       }
 987
 988       STReturns |= 1 << R;
 989     }
 990   }
 991
 992   unsigned N = countTrailingOnes(STReturns);
 993
 994   // FP registers used for function return must be consecutive starting at
 995   // FP0
 996   assert(STReturns == 0 || (isMask_32(STReturns) && N <= 2));
 997
 998   // Reset the FP Stack - It is required because of possible leftovers from
 999   // passed arguments. The caller should assume that the FP stack is
1000   // returned empty (unless the callee returns values on FP stack).
1001   while (StackTop > 0)
1002     popReg();
1003
1004   for (unsigned I = 0; I < N; ++I)
1005     pushReg(N - I - 1);
1006 }
1007
1008 /// If RET has an FP register use operand, pass the first one in ST(0) and
1009 /// the second one in ST(1).
1010 void FPS::handleReturn(MachineBasicBlock::iterator &I) {
1011   MachineInstr &MI = *I;
1012
1013   // Find the register operands.
1014   unsigned FirstFPRegOp = ~0U, SecondFPRegOp = ~0U;
1015   unsigned LiveMask = 0;
1016
1017   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1018     MachineOperand &Op = MI.getOperand(i);
1019     if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1020       continue;
1021     // FP Register uses must be kills unless there are two uses of the same
1022     // register, in which case only one will be a kill.
1023     assert(Op.isUse() &&
1024            (Op.isKill() ||                    // Marked kill.
1025             getFPReg(Op) == FirstFPRegOp ||   // Second instance.
1026             MI.killsRegister(Op.getReg())) && // Later use is marked kill.
1027            "Ret only defs operands, and values aren't live beyond it");
1028
1029     if (FirstFPRegOp == ~0U)
1030       FirstFPRegOp = getFPReg(Op);
1031     else {
1032       assert(SecondFPRegOp == ~0U && "More than two fp operands!");
1033       SecondFPRegOp = getFPReg(Op);
1034     }
1035     LiveMask |= (1 << getFPReg(Op));
1036
1037     // Remove the operand so that later passes don't see it.
1038     MI.RemoveOperand(i);
1039     --i;
1040     --e;
1041   }
1042
1043   // We may have been carrying spurious live-ins, so make sure only the
1044   // returned registers are left live.
1045   adjustLiveRegs(LiveMask, MI);
1046   if (!LiveMask) return;  // Quick check to see if any are possible.
1047
1048   // There are only four possibilities here:
1049   // 1) we are returning a single FP value.  In this case, it has to be in
1050   //    ST(0) already, so just declare success by removing the value from the
1051   //    FP Stack.
1052   if (SecondFPRegOp == ~0U) {
1053     // Assert that the top of stack contains the right FP register.
1054     assert(StackTop == 1 && FirstFPRegOp == getStackEntry(0) &&
1055            "Top of stack not the right register for RET!");
1056
1057     // Ok, everything is good, mark the value as not being on the stack
1058     // anymore so that our assertion about the stack being empty at end of
1059     // block doesn't fire.
1060     StackTop = 0;
1061     return;
1062   }
1063
1064   // Otherwise, we are returning two values:
1065   // 2) If returning the same value for both, we only have one thing in the FP
1066   //    stack.  Consider:  RET FP1, FP1
1067   if (StackTop == 1) {
1068     assert(FirstFPRegOp == SecondFPRegOp && FirstFPRegOp == getStackEntry(0)&&
1069            "Stack misconfiguration for RET!");
1070
1071     // Duplicate the TOS so that we return it twice.  Just pick some other FPx
1072     // register to hold it.
1073     unsigned NewReg = ScratchFPReg;
1074     duplicateToTop(FirstFPRegOp, NewReg, MI);
1075     FirstFPRegOp = NewReg;
1076   }
1077
1078   /// Okay we know we have two different FPx operands now:
1079   assert(StackTop == 2 && "Must have two values live!");
1080
1081   /// 3) If SecondFPRegOp is currently in ST(0) and FirstFPRegOp is currently
1082   ///    in ST(1).  In this case, emit an fxch.
1083   if (getStackEntry(0) == SecondFPRegOp) {
1084     assert(getStackEntry(1) == FirstFPRegOp && "Unknown regs live");
1085     moveToTop(FirstFPRegOp, MI);
1086   }
1087
1088   /// 4) Finally, FirstFPRegOp must be in ST(0) and SecondFPRegOp must be in
1089   /// ST(1).  Just remove both from our understanding of the stack and return.
1090   assert(getStackEntry(0) == FirstFPRegOp && "Unknown regs live");
1091   assert(getStackEntry(1) == SecondFPRegOp && "Unknown regs live");
1092   StackTop = 0;
1093 }
1094
1095 /// handleZeroArgFP - ST(0) = fld0    ST(0) = flds <mem>
1096 ///
1097 void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) {
1098   MachineInstr &MI = *I;
1099   unsigned DestReg = getFPReg(MI.getOperand(0));
1100
1101   // Change from the pseudo instruction to the concrete instruction.
1102   MI.RemoveOperand(0); // Remove the explicit ST(0) operand
1103   MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode())));
1104   MI.addOperand(
1105       MachineOperand::CreateReg(X86::ST0, /*isDef*/ true, /*isImp*/ true));
1106
1107   // Result gets pushed on the stack.
1108   pushReg(DestReg);
1109 }
1110
1111 /// handleOneArgFP - fst <mem>, ST(0)
1112 ///
1113 void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
1114   MachineInstr &MI = *I;
1115   unsigned NumOps = MI.getDesc().getNumOperands();
1116   assert((NumOps == X86::AddrNumOperands + 1 || NumOps == 1) &&
1117          "Can only handle fst* & ftst instructions!");
1118
1119   // Is this the last use of the source register?
1120   unsigned Reg = getFPReg(MI.getOperand(NumOps - 1));
1121   bool KillsSrc = MI.killsRegister(X86::FP0 + Reg);
1122
1123   // FISTP64m is strange because there isn't a non-popping versions.
1124   // If we have one _and_ we don't want to pop the operand, duplicate the value
1125   // on the stack instead of moving it.  This ensure that popping the value is
1126   // always ok.
1127   // Ditto FISTTP16m, FISTTP32m, FISTTP64m, ST_FpP80m.
1128   //
1129   if (!KillsSrc && (MI.getOpcode() == X86::IST_Fp64m32 ||
1130                     MI.getOpcode() == X86::ISTT_Fp16m32 ||
1131                     MI.getOpcode() == X86::ISTT_Fp32m32 ||
1132                     MI.getOpcode() == X86::ISTT_Fp64m32 ||
1133                     MI.getOpcode() == X86::IST_Fp64m64 ||
1134                     MI.getOpcode() == X86::ISTT_Fp16m64 ||
1135                     MI.getOpcode() == X86::ISTT_Fp32m64 ||
1136                     MI.getOpcode() == X86::ISTT_Fp64m64 ||
1137                     MI.getOpcode() == X86::IST_Fp64m80 ||
1138                     MI.getOpcode() == X86::ISTT_Fp16m80 ||
1139                     MI.getOpcode() == X86::ISTT_Fp32m80 ||
1140                     MI.getOpcode() == X86::ISTT_Fp64m80 ||
1141                     MI.getOpcode() == X86::ST_FpP80m)) {
1142     duplicateToTop(Reg, ScratchFPReg, I);
1143   } else {
1144     moveToTop(Reg, I);            // Move to the top of the stack...
1145   }
1146
1147   // Convert from the pseudo instruction to the concrete instruction.
1148   MI.RemoveOperand(NumOps - 1); // Remove explicit ST(0) operand
1149   MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode())));
1150   MI.addOperand(
1151       MachineOperand::CreateReg(X86::ST0, /*isDef*/ false, /*isImp*/ true));
1152
1153   if (MI.getOpcode() == X86::IST_FP64m || MI.getOpcode() == X86::ISTT_FP16m ||
1154       MI.getOpcode() == X86::ISTT_FP32m || MI.getOpcode() == X86::ISTT_FP64m ||
1155       MI.getOpcode() == X86::ST_FP80m) {
1156     if (StackTop == 0)
1157       report_fatal_error("Stack empty??");
1158     --StackTop;
1159   } else if (KillsSrc) { // Last use of operand?
1160     popStackAfter(I);
1161   }
1162 }
1163
1164
1165 /// handleOneArgFPRW: Handle instructions that read from the top of stack and
1166 /// replace the value with a newly computed value.  These instructions may have
1167 /// non-fp operands after their FP operands.
1168 ///
1169 ///  Examples:
1170 ///     R1 = fchs R2
1171 ///     R1 = fadd R2, [mem]
1172 ///
1173 void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
1174   MachineInstr &MI = *I;
1175 #ifndef NDEBUG
1176   unsigned NumOps = MI.getDesc().getNumOperands();
1177   assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!");
1178 #endif
1179
1180   // Is this the last use of the source register?
1181   unsigned Reg = getFPReg(MI.getOperand(1));
1182   bool KillsSrc = MI.killsRegister(X86::FP0 + Reg);
1183
1184   if (KillsSrc) {
1185     // If this is the last use of the source register, just make sure it's on
1186     // the top of the stack.
1187     moveToTop(Reg, I);
1188     if (StackTop == 0)
1189       report_fatal_error("Stack cannot be empty!");
1190     --StackTop;
1191     pushReg(getFPReg(MI.getOperand(0)));
1192   } else {
1193     // If this is not the last use of the source register, _copy_ it to the top
1194     // of the stack.
1195     duplicateToTop(Reg, getFPReg(MI.getOperand(0)), I);
1196   }
1197
1198   // Change from the pseudo instruction to the concrete instruction.
1199   MI.RemoveOperand(1); // Drop the source operand.
1200   MI.RemoveOperand(0); // Drop the destination operand.
1201   MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode())));
1202 }
1203
1204
1205 //===----------------------------------------------------------------------===//
1206 // Define tables of various ways to map pseudo instructions
1207 //
1208
1209 // ForwardST0Table - Map: A = B op C  into: ST(0) = ST(0) op ST(i)
1210 static const TableEntry ForwardST0Table[] = {
1211   { X86::ADD_Fp32  , X86::ADD_FST0r },
1212   { X86::ADD_Fp64  , X86::ADD_FST0r },
1213   { X86::ADD_Fp80  , X86::ADD_FST0r },
1214   { X86::DIV_Fp32  , X86::DIV_FST0r },
1215   { X86::DIV_Fp64  , X86::DIV_FST0r },
1216   { X86::DIV_Fp80  , X86::DIV_FST0r },
1217   { X86::MUL_Fp32  , X86::MUL_FST0r },
1218   { X86::MUL_Fp64  , X86::MUL_FST0r },
1219   { X86::MUL_Fp80  , X86::MUL_FST0r },
1220   { X86::SUB_Fp32  , X86::SUB_FST0r },
1221   { X86::SUB_Fp64  , X86::SUB_FST0r },
1222   { X86::SUB_Fp80  , X86::SUB_FST0r },
1223 };
1224
1225 // ReverseST0Table - Map: A = B op C  into: ST(0) = ST(i) op ST(0)
1226 static const TableEntry ReverseST0Table[] = {
1227   { X86::ADD_Fp32  , X86::ADD_FST0r  },   // commutative
1228   { X86::ADD_Fp64  , X86::ADD_FST0r  },   // commutative
1229   { X86::ADD_Fp80  , X86::ADD_FST0r  },   // commutative
1230   { X86::DIV_Fp32  , X86::DIVR_FST0r },
1231   { X86::DIV_Fp64  , X86::DIVR_FST0r },
1232   { X86::DIV_Fp80  , X86::DIVR_FST0r },
1233   { X86::MUL_Fp32  , X86::MUL_FST0r  },   // commutative
1234   { X86::MUL_Fp64  , X86::MUL_FST0r  },   // commutative
1235   { X86::MUL_Fp80  , X86::MUL_FST0r  },   // commutative
1236   { X86::SUB_Fp32  , X86::SUBR_FST0r },
1237   { X86::SUB_Fp64  , X86::SUBR_FST0r },
1238   { X86::SUB_Fp80  , X86::SUBR_FST0r },
1239 };
1240
1241 // ForwardSTiTable - Map: A = B op C  into: ST(i) = ST(0) op ST(i)
1242 static const TableEntry ForwardSTiTable[] = {
1243   { X86::ADD_Fp32  , X86::ADD_FrST0  },   // commutative
1244   { X86::ADD_Fp64  , X86::ADD_FrST0  },   // commutative
1245   { X86::ADD_Fp80  , X86::ADD_FrST0  },   // commutative
1246   { X86::DIV_Fp32  , X86::DIVR_FrST0 },
1247   { X86::DIV_Fp64  , X86::DIVR_FrST0 },
1248   { X86::DIV_Fp80  , X86::DIVR_FrST0 },
1249   { X86::MUL_Fp32  , X86::MUL_FrST0  },   // commutative
1250   { X86::MUL_Fp64  , X86::MUL_FrST0  },   // commutative
1251   { X86::MUL_Fp80  , X86::MUL_FrST0  },   // commutative
1252   { X86::SUB_Fp32  , X86::SUBR_FrST0 },
1253   { X86::SUB_Fp64  , X86::SUBR_FrST0 },
1254   { X86::SUB_Fp80  , X86::SUBR_FrST0 },
1255 };
1256
1257 // ReverseSTiTable - Map: A = B op C  into: ST(i) = ST(i) op ST(0)
1258 static const TableEntry ReverseSTiTable[] = {
1259   { X86::ADD_Fp32  , X86::ADD_FrST0 },
1260   { X86::ADD_Fp64  , X86::ADD_FrST0 },
1261   { X86::ADD_Fp80  , X86::ADD_FrST0 },
1262   { X86::DIV_Fp32  , X86::DIV_FrST0 },
1263   { X86::DIV_Fp64  , X86::DIV_FrST0 },
1264   { X86::DIV_Fp80  , X86::DIV_FrST0 },
1265   { X86::MUL_Fp32  , X86::MUL_FrST0 },
1266   { X86::MUL_Fp64  , X86::MUL_FrST0 },
1267   { X86::MUL_Fp80  , X86::MUL_FrST0 },
1268   { X86::SUB_Fp32  , X86::SUB_FrST0 },
1269   { X86::SUB_Fp64  , X86::SUB_FrST0 },
1270   { X86::SUB_Fp80  , X86::SUB_FrST0 },
1271 };
1272
1273
1274 /// handleTwoArgFP - Handle instructions like FADD and friends which are virtual
1275 /// instructions which need to be simplified and possibly transformed.
1276 ///
1277 /// Result: ST(0) = fsub  ST(0), ST(i)
1278 ///         ST(i) = fsub  ST(0), ST(i)
1279 ///         ST(0) = fsubr ST(0), ST(i)
1280 ///         ST(i) = fsubr ST(0), ST(i)
1281 ///
1282 void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) {
1283   ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
1284   ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
1285   MachineInstr &MI = *I;
1286
1287   unsigned NumOperands = MI.getDesc().getNumOperands();
1288   assert(NumOperands == 3 && "Illegal TwoArgFP instruction!");
1289   unsigned Dest = getFPReg(MI.getOperand(0));
1290   unsigned Op0 = getFPReg(MI.getOperand(NumOperands - 2));
1291   unsigned Op1 = getFPReg(MI.getOperand(NumOperands - 1));
1292   bool KillsOp0 = MI.killsRegister(X86::FP0 + Op0);
1293   bool KillsOp1 = MI.killsRegister(X86::FP0 + Op1);
1294   DebugLoc dl = MI.getDebugLoc();
1295
1296   unsigned TOS = getStackEntry(0);
1297
1298   // One of our operands must be on the top of the stack.  If neither is yet, we
1299   // need to move one.
1300   if (Op0 != TOS && Op1 != TOS) {   // No operand at TOS?
1301     // We can choose to move either operand to the top of the stack.  If one of
1302     // the operands is killed by this instruction, we want that one so that we
1303     // can update right on top of the old version.
1304     if (KillsOp0) {
1305       moveToTop(Op0, I);         // Move dead operand to TOS.
1306       TOS = Op0;
1307     } else if (KillsOp1) {
1308       moveToTop(Op1, I);
1309       TOS = Op1;
1310     } else {
1311       // All of the operands are live after this instruction executes, so we
1312       // cannot update on top of any operand.  Because of this, we must
1313       // duplicate one of the stack elements to the top.  It doesn't matter
1314       // which one we pick.
1315       //
1316       duplicateToTop(Op0, Dest, I);
1317       Op0 = TOS = Dest;
1318       KillsOp0 = true;
1319     }
1320   } else if (!KillsOp0 && !KillsOp1) {
1321     // If we DO have one of our operands at the top of the stack, but we don't
1322     // have a dead operand, we must duplicate one of the operands to a new slot
1323     // on the stack.
1324     duplicateToTop(Op0, Dest, I);
1325     Op0 = TOS = Dest;
1326     KillsOp0 = true;
1327   }
1328
1329   // Now we know that one of our operands is on the top of the stack, and at
1330   // least one of our operands is killed by this instruction.
1331   assert((TOS == Op0 || TOS == Op1) && (KillsOp0 || KillsOp1) &&
1332          "Stack conditions not set up right!");
1333
1334   // We decide which form to use based on what is on the top of the stack, and
1335   // which operand is killed by this instruction.
1336   ArrayRef<TableEntry> InstTable;
1337   bool isForward = TOS == Op0;
1338   bool updateST0 = (TOS == Op0 && !KillsOp1) || (TOS == Op1 && !KillsOp0);
1339   if (updateST0) {
1340     if (isForward)
1341       InstTable = ForwardST0Table;
1342     else
1343       InstTable = ReverseST0Table;
1344   } else {
1345     if (isForward)
1346       InstTable = ForwardSTiTable;
1347     else
1348       InstTable = ReverseSTiTable;
1349   }
1350
1351   int Opcode = Lookup(InstTable, MI.getOpcode());
1352   assert(Opcode != -1 && "Unknown TwoArgFP pseudo instruction!");
1353
1354   // NotTOS - The register which is not on the top of stack...
1355   unsigned NotTOS = (TOS == Op0) ? Op1 : Op0;
1356
1357   // Replace the old instruction with a new instruction
1358   MBB->remove(&*I++);
1359   I = BuildMI(*MBB, I, dl, TII->get(Opcode)).addReg(getSTReg(NotTOS));
1360
1361   // If both operands are killed, pop one off of the stack in addition to
1362   // overwriting the other one.
1363   if (KillsOp0 && KillsOp1 && Op0 != Op1) {
1364     assert(!updateST0 && "Should have updated other operand!");
1365     popStackAfter(I);   // Pop the top of stack
1366   }
1367
1368   // Update stack information so that we know the destination register is now on
1369   // the stack.
1370   unsigned UpdatedSlot = getSlot(updateST0 ? TOS : NotTOS);
1371   assert(UpdatedSlot < StackTop && Dest < 7);
1372   Stack[UpdatedSlot]   = Dest;
1373   RegMap[Dest]         = UpdatedSlot;
1374   MBB->getParent()->DeleteMachineInstr(&MI); // Remove the old instruction
1375 }
1376
1377 /// handleCompareFP - Handle FUCOM and FUCOMI instructions, which have two FP
1378 /// register arguments and no explicit destinations.
1379 ///
1380 void FPS::handleCompareFP(MachineBasicBlock::iterator &I) {
1381   MachineInstr &MI = *I;
1382
1383   unsigned NumOperands = MI.getDesc().getNumOperands();
1384   assert(NumOperands == 2 && "Illegal FUCOM* instruction!");
1385   unsigned Op0 = getFPReg(MI.getOperand(NumOperands - 2));
1386   unsigned Op1 = getFPReg(MI.getOperand(NumOperands - 1));
1387   bool KillsOp0 = MI.killsRegister(X86::FP0 + Op0);
1388   bool KillsOp1 = MI.killsRegister(X86::FP0 + Op1);
1389
1390   // Make sure the first operand is on the top of stack, the other one can be
1391   // anywhere.
1392   moveToTop(Op0, I);
1393
1394   // Change from the pseudo instruction to the concrete instruction.
1395   MI.getOperand(0).setReg(getSTReg(Op1));
1396   MI.RemoveOperand(1);
1397   MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode())));
1398
1399   // If any of the operands are killed by this instruction, free them.
1400   if (KillsOp0) freeStackSlotAfter(I, Op0);
1401   if (KillsOp1 && Op0 != Op1) freeStackSlotAfter(I, Op1);
1402 }
1403
1404 /// handleCondMovFP - Handle two address conditional move instructions.  These
1405 /// instructions move a st(i) register to st(0) iff a condition is true.  These
1406 /// instructions require that the first operand is at the top of the stack, but
1407 /// otherwise don't modify the stack at all.
1408 void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) {
1409   MachineInstr &MI = *I;
1410
1411   unsigned Op0 = getFPReg(MI.getOperand(0));
1412   unsigned Op1 = getFPReg(MI.getOperand(2));
1413   bool KillsOp1 = MI.killsRegister(X86::FP0 + Op1);
1414
1415   // The first operand *must* be on the top of the stack.
1416   moveToTop(Op0, I);
1417
1418   // Change the second operand to the stack register that the operand is in.
1419   // Change from the pseudo instruction to the concrete instruction.
1420   MI.RemoveOperand(0);
1421   MI.RemoveOperand(1);
1422   MI.getOperand(0).setReg(getSTReg(Op1));
1423   MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode())));
1424
1425   // If we kill the second operand, make sure to pop it from the stack.
1426   if (Op0 != Op1 && KillsOp1) {
1427     // Get this value off of the register stack.
1428     freeStackSlotAfter(I, Op1);
1429   }
1430 }
1431
1432
1433 /// handleSpecialFP - Handle special instructions which behave unlike other
1434 /// floating point instructions.  This is primarily intended for use by pseudo
1435 /// instructions.
1436 ///
1437 void FPS::handleSpecialFP(MachineBasicBlock::iterator &Inst) {
1438   MachineInstr &MI = *Inst;
1439
1440   if (MI.isCall()) {
1441     handleCall(Inst);
1442     return;
1443   }
1444
1445   if (MI.isReturn()) {
1446     handleReturn(Inst);
1447     return;
1448   }
1449
1450   switch (MI.getOpcode()) {
1451   default: llvm_unreachable("Unknown SpecialFP instruction!");
1452   case TargetOpcode::COPY: {
1453     // We handle three kinds of copies: FP <- FP, FP <- ST, and ST <- FP.
1454     const MachineOperand &MO1 = MI.getOperand(1);
1455     const MachineOperand &MO0 = MI.getOperand(0);
1456     bool KillsSrc = MI.killsRegister(MO1.getReg());
1457
1458     // FP <- FP copy.
1459     unsigned DstFP = getFPReg(MO0);
1460     unsigned SrcFP = getFPReg(MO1);
1461     assert(isLive(SrcFP) && "Cannot copy dead register");
1462     if (KillsSrc) {
1463       // If the input operand is killed, we can just change the owner of the
1464       // incoming stack slot into the result.
1465       unsigned Slot = getSlot(SrcFP);
1466       Stack[Slot] = DstFP;
1467       RegMap[DstFP] = Slot;
1468     } else {
1469       // For COPY we just duplicate the specified value to a new stack slot.
1470       // This could be made better, but would require substantial changes.
1471       duplicateToTop(SrcFP, DstFP, Inst);
1472     }
1473     break;
1474   }
1475
1476   case TargetOpcode::IMPLICIT_DEF: {
1477     // All FP registers must be explicitly defined, so load a 0 instead.
1478     unsigned Reg = MI.getOperand(0).getReg() - X86::FP0;
1479     LLVM_DEBUG(dbgs() << "Emitting LD_F0 for implicit FP" << Reg << '\n');
1480     BuildMI(*MBB, Inst, MI.getDebugLoc(), TII->get(X86::LD_F0));
1481     pushReg(Reg);
1482     break;
1483   }
1484
1485   case TargetOpcode::INLINEASM:
1486   case TargetOpcode::INLINEASM_BR: {
1487     // The inline asm MachineInstr currently only *uses* FP registers for the
1488     // 'f' constraint.  These should be turned into the current ST(x) register
1489     // in the machine instr.
1490     //
1491     // There are special rules for x87 inline assembly. The compiler must know
1492     // exactly how many registers are popped and pushed implicitly by the asm.
1493     // Otherwise it is not possible to restore the stack state after the inline
1494     // asm.
1495     //
1496     // There are 3 kinds of input operands:
1497     //
1498     // 1. Popped inputs. These must appear at the stack top in ST0-STn. A
1499     //    popped input operand must be in a fixed stack slot, and it is either
1500     //    tied to an output operand, or in the clobber list. The MI has ST use
1501     //    and def operands for these inputs.
1502     //
1503     // 2. Fixed inputs. These inputs appear in fixed stack slots, but are
1504     //    preserved by the inline asm. The fixed stack slots must be STn-STm
1505     //    following the popped inputs. A fixed input operand cannot be tied to
1506     //    an output or appear in the clobber list. The MI has ST use operands
1507     //    and no defs for these inputs.
1508     //
1509     // 3. Preserved inputs. These inputs use the "f" constraint which is
1510     //    represented as an FP register. The inline asm won't change these
1511     //    stack slots.
1512     //
1513     // Outputs must be in ST registers, FP outputs are not allowed. Clobbered
1514     // registers do not count as output operands. The inline asm changes the
1515     // stack as if it popped all the popped inputs and then pushed all the
1516     // output operands.
1517
1518     // Scan the assembly for ST registers used, defined and clobbered. We can
1519     // only tell clobbers from defs by looking at the asm descriptor.
1520     unsigned STUses = 0, STDefs = 0, STClobbers = 0, STDeadDefs = 0;
1521     unsigned NumOps = 0;
1522     SmallSet<unsigned, 1> FRegIdx;
1523     unsigned RCID;
1524
1525     for (unsigned i = InlineAsm::MIOp_FirstOperand, e = MI.getNumOperands();
1526          i != e && MI.getOperand(i).isImm(); i += 1 + NumOps) {
1527       unsigned Flags = MI.getOperand(i).getImm();
1528
1529       NumOps = InlineAsm::getNumOperandRegisters(Flags);
1530       if (NumOps != 1)
1531         continue;
1532       const MachineOperand &MO = MI.getOperand(i + 1);
1533       if (!MO.isReg())
1534         continue;
1535       unsigned STReg = MO.getReg() - X86::FP0;
1536       if (STReg >= 8)
1537         continue;
1538
1539       // If the flag has a register class constraint, this must be an operand
1540       // with constraint "f". Record its index and continue.
1541       if (InlineAsm::hasRegClassConstraint(Flags, RCID)) {
1542         FRegIdx.insert(i + 1);
1543         continue;
1544       }
1545
1546       switch (InlineAsm::getKind(Flags)) {
1547       case InlineAsm::Kind_RegUse:
1548         STUses |= (1u << STReg);
1549         break;
1550       case InlineAsm::Kind_RegDef:
1551       case InlineAsm::Kind_RegDefEarlyClobber:
1552         STDefs |= (1u << STReg);
1553         if (MO.isDead())
1554           STDeadDefs |= (1u << STReg);
1555         break;
1556       case InlineAsm::Kind_Clobber:
1557         STClobbers |= (1u << STReg);
1558         break;
1559       default:
1560         break;
1561       }
1562     }
1563
1564     if (STUses && !isMask_32(STUses))
1565       MI.emitError("fixed input regs must be last on the x87 stack");
1566     unsigned NumSTUses = countTrailingOnes(STUses);
1567
1568     // Defs must be contiguous from the stack top. ST0-STn.
1569     if (STDefs && !isMask_32(STDefs)) {
1570       MI.emitError("output regs must be last on the x87 stack");
1571       STDefs = NextPowerOf2(STDefs) - 1;
1572     }
1573     unsigned NumSTDefs = countTrailingOnes(STDefs);
1574
1575     // So must the clobbered stack slots. ST0-STm, m >= n.
1576     if (STClobbers && !isMask_32(STDefs | STClobbers))
1577       MI.emitError("clobbers must be last on the x87 stack");
1578
1579     // Popped inputs are the ones that are also clobbered or defined.
1580     unsigned STPopped = STUses & (STDefs | STClobbers);
1581     if (STPopped && !isMask_32(STPopped))
1582       MI.emitError("implicitly popped regs must be last on the x87 stack");
1583     unsigned NumSTPopped = countTrailingOnes(STPopped);
1584
1585     LLVM_DEBUG(dbgs() << "Asm uses " << NumSTUses << " fixed regs, pops "
1586                       << NumSTPopped << ", and defines " << NumSTDefs
1587                       << " regs.\n");
1588
1589 #ifndef NDEBUG
1590     // If any input operand uses constraint "f", all output register
1591     // constraints must be early-clobber defs.
1592     for (unsigned I = 0, E = MI.getNumOperands(); I < E; ++I)
1593       if (FRegIdx.count(I)) {
1594         assert((1 << getFPReg(MI.getOperand(I)) & STDefs) == 0 &&
1595                "Operands with constraint \"f\" cannot overlap with defs");
1596       }
1597 #endif
1598
1599     // Collect all FP registers (register operands with constraints "t", "u",
1600     // and "f") to kill afer the instruction.
1601     unsigned FPKills = ((1u << NumFPRegs) - 1) & ~0xff;
1602     for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1603       MachineOperand &Op = MI.getOperand(i);
1604       if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1605         continue;
1606       unsigned FPReg = getFPReg(Op);
1607
1608       // If we kill this operand, make sure to pop it from the stack after the
1609       // asm.  We just remember it for now, and pop them all off at the end in
1610       // a batch.
1611       if (Op.isUse() && Op.isKill())
1612         FPKills |= 1U << FPReg;
1613     }
1614
1615     // Do not include registers that are implicitly popped by defs/clobbers.
1616     FPKills &= ~(STDefs | STClobbers);
1617
1618     // Now we can rearrange the live registers to match what was requested.
1619     unsigned char STUsesArray[8];
1620
1621     for (unsigned I = 0; I < NumSTUses; ++I)
1622       STUsesArray[I] = I;
1623
1624     shuffleStackTop(STUsesArray, NumSTUses, Inst);
1625     LLVM_DEBUG({
1626       dbgs() << "Before asm: ";
1627       dumpStack();
1628     });
1629
1630     // With the stack layout fixed, rewrite the FP registers.
1631     for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1632       MachineOperand &Op = MI.getOperand(i);
1633       if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1634         continue;
1635
1636       unsigned FPReg = getFPReg(Op);
1637
1638       if (FRegIdx.count(i))
1639         // Operand with constraint "f".
1640         Op.setReg(getSTReg(FPReg));
1641       else
1642         // Operand with a single register class constraint ("t" or "u").
1643         Op.setReg(X86::ST0 + FPReg);
1644     }
1645
1646     // Simulate the inline asm popping its inputs and pushing its outputs.
1647     StackTop -= NumSTPopped;
1648
1649     for (unsigned i = 0; i < NumSTDefs; ++i)
1650       pushReg(NumSTDefs - i - 1);
1651
1652     // If this asm kills any FP registers (is the last use of them) we must
1653     // explicitly emit pop instructions for them.  Do this now after the asm has
1654     // executed so that the ST(x) numbers are not off (which would happen if we
1655     // did this inline with operand rewriting).
1656     //
1657     // Note: this might be a non-optimal pop sequence.  We might be able to do
1658     // better by trying to pop in stack order or something.
1659     while (FPKills) {
1660       unsigned FPReg = countTrailingZeros(FPKills);
1661       if (isLive(FPReg))
1662         freeStackSlotAfter(Inst, FPReg);
1663       FPKills &= ~(1U << FPReg);
1664     }
1665
1666     // Don't delete the inline asm!
1667     return;
1668   }
1669   }
1670
1671   Inst = MBB->erase(Inst);  // Remove the pseudo instruction
1672
1673   // We want to leave I pointing to the previous instruction, but what if we
1674   // just erased the first instruction?
1675   if (Inst == MBB->begin()) {
1676     LLVM_DEBUG(dbgs() << "Inserting dummy KILL\n");
1677     Inst = BuildMI(*MBB, Inst, DebugLoc(), TII->get(TargetOpcode::KILL));
1678   } else
1679     --Inst;
1680 }
1681
1682 void FPS::setKillFlags(MachineBasicBlock &MBB) const {
1683   const TargetRegisterInfo &TRI =
1684       *MBB.getParent()->getSubtarget().getRegisterInfo();
1685   LivePhysRegs LPR(TRI);
1686
1687   LPR.addLiveOuts(MBB);
1688
1689   for (MachineBasicBlock::reverse_iterator I = MBB.rbegin(), E = MBB.rend();
1690        I != E; ++I) {
1691     if (I->isDebugInstr())
1692       continue;
1693
1694     std::bitset<8> Defs;
1695     SmallVector<MachineOperand *, 2> Uses;
1696     MachineInstr &MI = *I;
1697
1698     for (auto &MO : I->operands()) {
1699       if (!MO.isReg())
1700         continue;
1701
1702       unsigned Reg = MO.getReg() - X86::FP0;
1703
1704       if (Reg >= 8)
1705         continue;
1706
1707       if (MO.isDef()) {
1708         Defs.set(Reg);
1709         if (!LPR.contains(MO.getReg()))
1710           MO.setIsDead();
1711       } else
1712         Uses.push_back(&MO);
1713     }
1714
1715     for (auto *MO : Uses)
1716       if (Defs.test(getFPReg(*MO)) || !LPR.contains(MO->getReg()))
1717         MO->setIsKill();
1718
1719     LPR.stepBackward(MI);
1720   }
1721 }