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[Alignment][NFC] Remove unneeded llvm:: scoping on Align types
[llvm-core.git] / lib / Target / X86 / X86TargetTransformInfo.cpp
blobebbf6d0702e8ad54d80944d40f7dce61182f5fb8
1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements a TargetTransformInfo analysis pass specific to the
10 /// X86 target machine. It uses the target's detailed information to provide
11 /// more precise answers to certain TTI queries, while letting the target
12 /// independent and default TTI implementations handle the rest.
13 ///
14 //===----------------------------------------------------------------------===//
15 /// About Cost Model numbers used below it's necessary to say the following:
16 /// the numbers correspond to some "generic" X86 CPU instead of usage of
17 /// concrete CPU model. Usually the numbers correspond to CPU where the feature
18 /// apeared at the first time. For example, if we do Subtarget.hasSSE42() in
19 /// the lookups below the cost is based on Nehalem as that was the first CPU
20 /// to support that feature level and thus has most likely the worst case cost.
21 /// Some examples of other technologies/CPUs:
22 /// SSE 3 - Pentium4 / Athlon64
23 /// SSE 4.1 - Penryn
24 /// SSE 4.2 - Nehalem
25 /// AVX - Sandy Bridge
26 /// AVX2 - Haswell
27 /// AVX-512 - Xeon Phi / Skylake
28 /// And some examples of instruction target dependent costs (latency)
29 /// divss sqrtss rsqrtss
30 /// AMD K7 11-16 19 3
31 /// Piledriver 9-24 13-15 5
32 /// Jaguar 14 16 2
33 /// Pentium II,III 18 30 2
34 /// Nehalem 7-14 7-18 3
35 /// Haswell 10-13 11 5
36 /// TODO: Develop and implement the target dependent cost model and
37 /// specialize cost numbers for different Cost Model Targets such as throughput,
38 /// code size, latency and uop count.
39 //===----------------------------------------------------------------------===//
40
41 #include "X86TargetTransformInfo.h"
42 #include "llvm/Analysis/TargetTransformInfo.h"
43 #include "llvm/CodeGen/BasicTTIImpl.h"
44 #include "llvm/CodeGen/CostTable.h"
45 #include "llvm/CodeGen/TargetLowering.h"
46 #include "llvm/IR/IntrinsicInst.h"
47 #include "llvm/Support/Debug.h"
48
49 using namespace llvm;
50
51 #define DEBUG_TYPE "x86tti"
52
53 extern cl::opt<bool> ExperimentalVectorWideningLegalization;
54
55 //===----------------------------------------------------------------------===//
56 //
57 // X86 cost model.
58 //
59 //===----------------------------------------------------------------------===//
60
61 TargetTransformInfo::PopcntSupportKind
62 X86TTIImpl::getPopcntSupport(unsigned TyWidth) {
63 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
64 // TODO: Currently the __builtin_popcount() implementation using SSE3
65 // instructions is inefficient. Once the problem is fixed, we should
66 // call ST->hasSSE3() instead of ST->hasPOPCNT().
67 return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software;
68 }
69
70 llvm::Optional<unsigned> X86TTIImpl::getCacheSize(
71 TargetTransformInfo::CacheLevel Level) const {
72 switch (Level) {
73 case TargetTransformInfo::CacheLevel::L1D:
74 // - Penryn
75 // - Nehalem
76 // - Westmere
77 // - Sandy Bridge
78 // - Ivy Bridge
79 // - Haswell
80 // - Broadwell
81 // - Skylake
82 // - Kabylake
83 return 32 * 1024; // 32 KByte
84 case TargetTransformInfo::CacheLevel::L2D:
85 // - Penryn
86 // - Nehalem
87 // - Westmere
88 // - Sandy Bridge
89 // - Ivy Bridge
90 // - Haswell
91 // - Broadwell
92 // - Skylake
93 // - Kabylake
94 return 256 * 1024; // 256 KByte
95 }
96
97 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel");
98 }
99
100 llvm::Optional<unsigned> X86TTIImpl::getCacheAssociativity(
101 TargetTransformInfo::CacheLevel Level) const {
102 // - Penryn
103 // - Nehalem
104 // - Westmere
105 // - Sandy Bridge
106 // - Ivy Bridge
107 // - Haswell
108 // - Broadwell
109 // - Skylake
110 // - Kabylake
111 switch (Level) {
112 case TargetTransformInfo::CacheLevel::L1D:
113 LLVM_FALLTHROUGH;
114 case TargetTransformInfo::CacheLevel::L2D:
115 return 8;
116 }
117
118 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel");
119 }
120
121 unsigned X86TTIImpl::getNumberOfRegisters(bool Vector) {
122 if (Vector && !ST->hasSSE1())
123 return 0;
124
125 if (ST->is64Bit()) {
126 if (Vector && ST->hasAVX512())
127 return 32;
128 return 16;
129 }
130 return 8;
131 }
132
133 unsigned X86TTIImpl::getRegisterBitWidth(bool Vector) const {
134 unsigned PreferVectorWidth = ST->getPreferVectorWidth();
135 if (Vector) {
136 if (ST->hasAVX512() && PreferVectorWidth >= 512)
137 return 512;
138 if (ST->hasAVX() && PreferVectorWidth >= 256)
139 return 256;
140 if (ST->hasSSE1() && PreferVectorWidth >= 128)
141 return 128;
142 return 0;
143 }
144
145 if (ST->is64Bit())
146 return 64;
147
148 return 32;
149 }
150
151 unsigned X86TTIImpl::getLoadStoreVecRegBitWidth(unsigned) const {
152 return getRegisterBitWidth(true);
153 }
154
155 unsigned X86TTIImpl::getMaxInterleaveFactor(unsigned VF) {
156 // If the loop will not be vectorized, don't interleave the loop.
157 // Let regular unroll to unroll the loop, which saves the overflow
158 // check and memory check cost.
159 if (VF == 1)
160 return 1;
161
162 if (ST->isAtom())
163 return 1;
164
165 // Sandybridge and Haswell have multiple execution ports and pipelined
166 // vector units.
167 if (ST->hasAVX())
168 return 4;
169
170 return 2;
171 }
172
173 int X86TTIImpl::getArithmeticInstrCost(
174 unsigned Opcode, Type *Ty,
175 TTI::OperandValueKind Op1Info, TTI::OperandValueKind Op2Info,
176 TTI::OperandValueProperties Opd1PropInfo,
177 TTI::OperandValueProperties Opd2PropInfo,
178 ArrayRef<const Value *> Args) {
179 // Legalize the type.
180 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty);
181
182 int ISD = TLI->InstructionOpcodeToISD(Opcode);
183 assert(ISD && "Invalid opcode");
184
185 static const CostTblEntry GLMCostTable[] = {
186 { ISD::FDIV, MVT::f32, 18 }, // divss
187 { ISD::FDIV, MVT::v4f32, 35 }, // divps
188 { ISD::FDIV, MVT::f64, 33 }, // divsd
189 { ISD::FDIV, MVT::v2f64, 65 }, // divpd
190 };
191
192 if (ST->isGLM())
193 if (const auto *Entry = CostTableLookup(GLMCostTable, ISD,
194 LT.second))
195 return LT.first * Entry->Cost;
196
197 static const CostTblEntry SLMCostTable[] = {
198 { ISD::MUL, MVT::v4i32, 11 }, // pmulld
199 { ISD::MUL, MVT::v8i16, 2 }, // pmullw
200 { ISD::MUL, MVT::v16i8, 14 }, // extend/pmullw/trunc sequence.
201 { ISD::FMUL, MVT::f64, 2 }, // mulsd
202 { ISD::FMUL, MVT::v2f64, 4 }, // mulpd
203 { ISD::FMUL, MVT::v4f32, 2 }, // mulps
204 { ISD::FDIV, MVT::f32, 17 }, // divss
205 { ISD::FDIV, MVT::v4f32, 39 }, // divps
206 { ISD::FDIV, MVT::f64, 32 }, // divsd
207 { ISD::FDIV, MVT::v2f64, 69 }, // divpd
208 { ISD::FADD, MVT::v2f64, 2 }, // addpd
209 { ISD::FSUB, MVT::v2f64, 2 }, // subpd
210 // v2i64/v4i64 mul is custom lowered as a series of long:
211 // multiplies(3), shifts(3) and adds(2)
212 // slm muldq version throughput is 2 and addq throughput 4
213 // thus: 3X2 (muldq throughput) + 3X1 (shift throughput) +
214 // 3X4 (addq throughput) = 17
215 { ISD::MUL, MVT::v2i64, 17 },
216 // slm addq\subq throughput is 4
217 { ISD::ADD, MVT::v2i64, 4 },
218 { ISD::SUB, MVT::v2i64, 4 },
219 };
220
221 if (ST->isSLM()) {
222 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) {
223 // Check if the operands can be shrinked into a smaller datatype.
224 bool Op1Signed = false;
225 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed);
226 bool Op2Signed = false;
227 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed);
228
229 bool signedMode = Op1Signed | Op2Signed;
230 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize);
231
232 if (OpMinSize <= 7)
233 return LT.first * 3; // pmullw/sext
234 if (!signedMode && OpMinSize <= 8)
235 return LT.first * 3; // pmullw/zext
236 if (OpMinSize <= 15)
237 return LT.first * 5; // pmullw/pmulhw/pshuf
238 if (!signedMode && OpMinSize <= 16)
239 return LT.first * 5; // pmullw/pmulhw/pshuf
240 }
241
242 if (const auto *Entry = CostTableLookup(SLMCostTable, ISD,
243 LT.second)) {
244 return LT.first * Entry->Cost;
245 }
246 }
247
248 if ((ISD == ISD::SDIV || ISD == ISD::SREM || ISD == ISD::UDIV ||
249 ISD == ISD::UREM) &&
250 (Op2Info == TargetTransformInfo::OK_UniformConstantValue ||
251 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) &&
252 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) {
253 if (ISD == ISD::SDIV || ISD == ISD::SREM) {
254 // On X86, vector signed division by constants power-of-two are
255 // normally expanded to the sequence SRA + SRL + ADD + SRA.
256 // The OperandValue properties may not be the same as that of the previous
257 // operation; conservatively assume OP_None.
258 int Cost =
259 2 * getArithmeticInstrCost(Instruction::AShr, Ty, Op1Info, Op2Info,
260 TargetTransformInfo::OP_None,
261 TargetTransformInfo::OP_None);
262 Cost += getArithmeticInstrCost(Instruction::LShr, Ty, Op1Info, Op2Info,
263 TargetTransformInfo::OP_None,
264 TargetTransformInfo::OP_None);
265 Cost += getArithmeticInstrCost(Instruction::Add, Ty, Op1Info, Op2Info,
266 TargetTransformInfo::OP_None,
267 TargetTransformInfo::OP_None);
268
269 if (ISD == ISD::SREM) {
270 // For SREM: (X % C) is the equivalent of (X - (X/C)*C)
271 Cost += getArithmeticInstrCost(Instruction::Mul, Ty, Op1Info, Op2Info);
272 Cost += getArithmeticInstrCost(Instruction::Sub, Ty, Op1Info, Op2Info);
273 }
274
275 return Cost;
276 }
277
278 // Vector unsigned division/remainder will be simplified to shifts/masks.
279 if (ISD == ISD::UDIV)
280 return getArithmeticInstrCost(Instruction::LShr, Ty, Op1Info, Op2Info,
281 TargetTransformInfo::OP_None,
282 TargetTransformInfo::OP_None);
283
284 if (ISD == ISD::UREM)
285 return getArithmeticInstrCost(Instruction::And, Ty, Op1Info, Op2Info,
286 TargetTransformInfo::OP_None,
287 TargetTransformInfo::OP_None);
288 }
289
290 static const CostTblEntry AVX512BWUniformConstCostTable[] = {
291 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand.
292 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand.
293 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb.
294 };
295
296 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue &&
297 ST->hasBWI()) {
298 if (const auto *Entry = CostTableLookup(AVX512BWUniformConstCostTable, ISD,
299 LT.second))
300 return LT.first * Entry->Cost;
301 }
302
303 static const CostTblEntry AVX512UniformConstCostTable[] = {
304 { ISD::SRA, MVT::v2i64, 1 },
305 { ISD::SRA, MVT::v4i64, 1 },
306 { ISD::SRA, MVT::v8i64, 1 },
307 };
308
309 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue &&
310 ST->hasAVX512()) {
311 if (const auto *Entry = CostTableLookup(AVX512UniformConstCostTable, ISD,
312 LT.second))
313 return LT.first * Entry->Cost;
314 }
315
316 static const CostTblEntry AVX2UniformConstCostTable[] = {
317 { ISD::SHL, MVT::v32i8, 2 }, // psllw + pand.
318 { ISD::SRL, MVT::v32i8, 2 }, // psrlw + pand.
319 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb.
320
321 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle.
322 };
323
324 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue &&
325 ST->hasAVX2()) {
326 if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD,
327 LT.second))
328 return LT.first * Entry->Cost;
329 }
330
331 static const CostTblEntry SSE2UniformConstCostTable[] = {
332 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand.
333 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand.
334 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb.
335
336 { ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split.
337 { ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split.
338 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split.
339 };
340
341 // XOP has faster vXi8 shifts.
342 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue &&
343 ST->hasSSE2() && !ST->hasXOP()) {
344 if (const auto *Entry =
345 CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second))
346 return LT.first * Entry->Cost;
347 }
348
349 static const CostTblEntry AVX512BWConstCostTable[] = {
350 { ISD::SDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence
351 { ISD::SREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence
352 { ISD::UDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence
353 { ISD::UREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence
354 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence
355 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence
356 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence
357 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence
358 };
359
360 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue ||
361 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) &&
362 ST->hasBWI()) {
363 if (const auto *Entry =
364 CostTableLookup(AVX512BWConstCostTable, ISD, LT.second))
365 return LT.first * Entry->Cost;
366 }
367
368 static const CostTblEntry AVX512ConstCostTable[] = {
369 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence
370 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence
371 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence
372 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence
373 };
374
375 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue ||
376 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) &&
377 ST->hasAVX512()) {
378 if (const auto *Entry =
379 CostTableLookup(AVX512ConstCostTable, ISD, LT.second))
380 return LT.first * Entry->Cost;
381 }
382
383 static const CostTblEntry AVX2ConstCostTable[] = {
384 { ISD::SDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence
385 { ISD::SREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence
386 { ISD::UDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence
387 { ISD::UREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence
388 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence
389 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence
390 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence
391 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence
392 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence
393 { ISD::SREM, MVT::v8i32, 19 }, // vpmuldq+mul+sub sequence
394 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence
395 { ISD::UREM, MVT::v8i32, 19 }, // vpmuludq+mul+sub sequence
396 };
397
398 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue ||
399 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) &&
400 ST->hasAVX2()) {
401 if (const auto *Entry = CostTableLookup(AVX2ConstCostTable, ISD, LT.second))
402 return LT.first * Entry->Cost;
403 }
404
405 static const CostTblEntry SSE2ConstCostTable[] = {
406 { ISD::SDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split.
407 { ISD::SREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split.
408 { ISD::SDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence
409 { ISD::SREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence
410 { ISD::UDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split.
411 { ISD::UREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split.
412 { ISD::UDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence
413 { ISD::UREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence
414 { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split.
415 { ISD::SREM, MVT::v16i16, 16+2 }, // 2*pmulhw+mul+sub sequence + split.
416 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence
417 { ISD::SREM, MVT::v8i16, 8 }, // pmulhw+mul+sub sequence
418 { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split.
419 { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split.
420 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence
421 { ISD::UREM, MVT::v8i16, 8 }, // pmulhuw+mul+sub sequence
422 { ISD::SDIV, MVT::v8i32, 38+2 }, // 2*pmuludq sequence + split.
423 { ISD::SREM, MVT::v8i32, 48+2 }, // 2*pmuludq+mul+sub sequence + split.
424 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence
425 { ISD::SREM, MVT::v4i32, 24 }, // pmuludq+mul+sub sequence
426 { ISD::UDIV, MVT::v8i32, 30+2 }, // 2*pmuludq sequence + split.
427 { ISD::UREM, MVT::v8i32, 40+2 }, // 2*pmuludq+mul+sub sequence + split.
428 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence
429 { ISD::UREM, MVT::v4i32, 20 }, // pmuludq+mul+sub sequence
430 };
431
432 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue ||
433 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) &&
434 ST->hasSSE2()) {
435 // pmuldq sequence.
436 if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX())
437 return LT.first * 32;
438 if (ISD == ISD::SREM && LT.second == MVT::v8i32 && ST->hasAVX())
439 return LT.first * 38;
440 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41())
441 return LT.first * 15;
442 if (ISD == ISD::SREM && LT.second == MVT::v4i32 && ST->hasSSE41())
443 return LT.first * 20;
444
445 if (const auto *Entry = CostTableLookup(SSE2ConstCostTable, ISD, LT.second))
446 return LT.first * Entry->Cost;
447 }
448
449 static const CostTblEntry AVX2UniformCostTable[] = {
450 // Uniform splats are cheaper for the following instructions.
451 { ISD::SHL, MVT::v16i16, 1 }, // psllw.
452 { ISD::SRL, MVT::v16i16, 1 }, // psrlw.
453 { ISD::SRA, MVT::v16i16, 1 }, // psraw.
454 };
455
456 if (ST->hasAVX2() &&
457 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) ||
458 (Op2Info == TargetTransformInfo::OK_UniformValue))) {
459 if (const auto *Entry =
460 CostTableLookup(AVX2UniformCostTable, ISD, LT.second))
461 return LT.first * Entry->Cost;
462 }
463
464 static const CostTblEntry SSE2UniformCostTable[] = {
465 // Uniform splats are cheaper for the following instructions.
466 { ISD::SHL, MVT::v8i16, 1 }, // psllw.
467 { ISD::SHL, MVT::v4i32, 1 }, // pslld
468 { ISD::SHL, MVT::v2i64, 1 }, // psllq.
469
470 { ISD::SRL, MVT::v8i16, 1 }, // psrlw.
471 { ISD::SRL, MVT::v4i32, 1 }, // psrld.
472 { ISD::SRL, MVT::v2i64, 1 }, // psrlq.
473
474 { ISD::SRA, MVT::v8i16, 1 }, // psraw.
475 { ISD::SRA, MVT::v4i32, 1 }, // psrad.
476 };
477
478 if (ST->hasSSE2() &&
479 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) ||
480 (Op2Info == TargetTransformInfo::OK_UniformValue))) {
481 if (const auto *Entry =
482 CostTableLookup(SSE2UniformCostTable, ISD, LT.second))
483 return LT.first * Entry->Cost;
484 }
485
486 static const CostTblEntry AVX512DQCostTable[] = {
487 { ISD::MUL, MVT::v2i64, 1 },
488 { ISD::MUL, MVT::v4i64, 1 },
489 { ISD::MUL, MVT::v8i64, 1 }
490 };
491
492 // Look for AVX512DQ lowering tricks for custom cases.
493 if (ST->hasDQI())
494 if (const auto *Entry = CostTableLookup(AVX512DQCostTable, ISD, LT.second))
495 return LT.first * Entry->Cost;
496
497 static const CostTblEntry AVX512BWCostTable[] = {
498 { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw
499 { ISD::SRL, MVT::v8i16, 1 }, // vpsrlvw
500 { ISD::SRA, MVT::v8i16, 1 }, // vpsravw
501
502 { ISD::SHL, MVT::v16i16, 1 }, // vpsllvw
503 { ISD::SRL, MVT::v16i16, 1 }, // vpsrlvw
504 { ISD::SRA, MVT::v16i16, 1 }, // vpsravw
505
506 { ISD::SHL, MVT::v32i16, 1 }, // vpsllvw
507 { ISD::SRL, MVT::v32i16, 1 }, // vpsrlvw
508 { ISD::SRA, MVT::v32i16, 1 }, // vpsravw
509
510 { ISD::SHL, MVT::v64i8, 11 }, // vpblendvb sequence.
511 { ISD::SRL, MVT::v64i8, 11 }, // vpblendvb sequence.
512 { ISD::SRA, MVT::v64i8, 24 }, // vpblendvb sequence.
513
514 { ISD::MUL, MVT::v64i8, 11 }, // extend/pmullw/trunc sequence.
515 { ISD::MUL, MVT::v32i8, 4 }, // extend/pmullw/trunc sequence.
516 { ISD::MUL, MVT::v16i8, 4 }, // extend/pmullw/trunc sequence.
517 };
518
519 // Look for AVX512BW lowering tricks for custom cases.
520 if (ST->hasBWI())
521 if (const auto *Entry = CostTableLookup(AVX512BWCostTable, ISD, LT.second))
522 return LT.first * Entry->Cost;
523
524 static const CostTblEntry AVX512CostTable[] = {
525 { ISD::SHL, MVT::v16i32, 1 },
526 { ISD::SRL, MVT::v16i32, 1 },
527 { ISD::SRA, MVT::v16i32, 1 },
528
529 { ISD::SHL, MVT::v8i64, 1 },
530 { ISD::SRL, MVT::v8i64, 1 },
531
532 { ISD::SRA, MVT::v2i64, 1 },
533 { ISD::SRA, MVT::v4i64, 1 },
534 { ISD::SRA, MVT::v8i64, 1 },
535
536 { ISD::MUL, MVT::v32i8, 13 }, // extend/pmullw/trunc sequence.
537 { ISD::MUL, MVT::v16i8, 5 }, // extend/pmullw/trunc sequence.
538 { ISD::MUL, MVT::v16i32, 1 }, // pmulld (Skylake from agner.org)
539 { ISD::MUL, MVT::v8i32, 1 }, // pmulld (Skylake from agner.org)
540 { ISD::MUL, MVT::v4i32, 1 }, // pmulld (Skylake from agner.org)
541 { ISD::MUL, MVT::v8i64, 8 }, // 3*pmuludq/3*shift/2*add
542
543 { ISD::FADD, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/
544 { ISD::FSUB, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/
545 { ISD::FMUL, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/
546
547 { ISD::FADD, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/
548 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/
549 { ISD::FMUL, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/
550 };
551
552 if (ST->hasAVX512())
553 if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second))
554 return LT.first * Entry->Cost;
555
556 static const CostTblEntry AVX2ShiftCostTable[] = {
557 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to
558 // customize them to detect the cases where shift amount is a scalar one.
559 { ISD::SHL, MVT::v4i32, 1 },
560 { ISD::SRL, MVT::v4i32, 1 },
561 { ISD::SRA, MVT::v4i32, 1 },
562 { ISD::SHL, MVT::v8i32, 1 },
563 { ISD::SRL, MVT::v8i32, 1 },
564 { ISD::SRA, MVT::v8i32, 1 },
565 { ISD::SHL, MVT::v2i64, 1 },
566 { ISD::SRL, MVT::v2i64, 1 },
567 { ISD::SHL, MVT::v4i64, 1 },
568 { ISD::SRL, MVT::v4i64, 1 },
569 };
570
571 // Look for AVX2 lowering tricks.
572 if (ST->hasAVX2()) {
573 if (ISD == ISD::SHL && LT.second == MVT::v16i16 &&
574 (Op2Info == TargetTransformInfo::OK_UniformConstantValue ||
575 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue))
576 // On AVX2, a packed v16i16 shift left by a constant build_vector
577 // is lowered into a vector multiply (vpmullw).
578 return getArithmeticInstrCost(Instruction::Mul, Ty, Op1Info, Op2Info,
579 TargetTransformInfo::OP_None,
580 TargetTransformInfo::OP_None);
581
582 if (const auto *Entry = CostTableLookup(AVX2ShiftCostTable, ISD, LT.second))
583 return LT.first * Entry->Cost;
584 }
585
586 static const CostTblEntry XOPShiftCostTable[] = {
587 // 128bit shifts take 1cy, but right shifts require negation beforehand.
588 { ISD::SHL, MVT::v16i8, 1 },
589 { ISD::SRL, MVT::v16i8, 2 },
590 { ISD::SRA, MVT::v16i8, 2 },
591 { ISD::SHL, MVT::v8i16, 1 },
592 { ISD::SRL, MVT::v8i16, 2 },
593 { ISD::SRA, MVT::v8i16, 2 },
594 { ISD::SHL, MVT::v4i32, 1 },
595 { ISD::SRL, MVT::v4i32, 2 },
596 { ISD::SRA, MVT::v4i32, 2 },
597 { ISD::SHL, MVT::v2i64, 1 },
598 { ISD::SRL, MVT::v2i64, 2 },
599 { ISD::SRA, MVT::v2i64, 2 },
600 // 256bit shifts require splitting if AVX2 didn't catch them above.
601 { ISD::SHL, MVT::v32i8, 2+2 },
602 { ISD::SRL, MVT::v32i8, 4+2 },
603 { ISD::SRA, MVT::v32i8, 4+2 },
604 { ISD::SHL, MVT::v16i16, 2+2 },
605 { ISD::SRL, MVT::v16i16, 4+2 },
606 { ISD::SRA, MVT::v16i16, 4+2 },
607 { ISD::SHL, MVT::v8i32, 2+2 },
608 { ISD::SRL, MVT::v8i32, 4+2 },
609 { ISD::SRA, MVT::v8i32, 4+2 },
610 { ISD::SHL, MVT::v4i64, 2+2 },
611 { ISD::SRL, MVT::v4i64, 4+2 },
612 { ISD::SRA, MVT::v4i64, 4+2 },
613 };
614
615 // Look for XOP lowering tricks.
616 if (ST->hasXOP()) {
617 // If the right shift is constant then we'll fold the negation so
618 // it's as cheap as a left shift.
619 int ShiftISD = ISD;
620 if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) &&
621 (Op2Info == TargetTransformInfo::OK_UniformConstantValue ||
622 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue))
623 ShiftISD = ISD::SHL;
624 if (const auto *Entry =
625 CostTableLookup(XOPShiftCostTable, ShiftISD, LT.second))
626 return LT.first * Entry->Cost;
627 }
628
629 static const CostTblEntry SSE2UniformShiftCostTable[] = {
630 // Uniform splats are cheaper for the following instructions.
631 { ISD::SHL, MVT::v16i16, 2+2 }, // 2*psllw + split.
632 { ISD::SHL, MVT::v8i32, 2+2 }, // 2*pslld + split.
633 { ISD::SHL, MVT::v4i64, 2+2 }, // 2*psllq + split.
634
635 { ISD::SRL, MVT::v16i16, 2+2 }, // 2*psrlw + split.
636 { ISD::SRL, MVT::v8i32, 2+2 }, // 2*psrld + split.
637 { ISD::SRL, MVT::v4i64, 2+2 }, // 2*psrlq + split.
638
639 { ISD::SRA, MVT::v16i16, 2+2 }, // 2*psraw + split.
640 { ISD::SRA, MVT::v8i32, 2+2 }, // 2*psrad + split.
641 { ISD::SRA, MVT::v2i64, 4 }, // 2*psrad + shuffle.
642 { ISD::SRA, MVT::v4i64, 8+2 }, // 2*(2*psrad + shuffle) + split.
643 };
644
645 if (ST->hasSSE2() &&
646 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) ||
647 (Op2Info == TargetTransformInfo::OK_UniformValue))) {
648
649 // Handle AVX2 uniform v4i64 ISD::SRA, it's not worth a table.
650 if (ISD == ISD::SRA && LT.second == MVT::v4i64 && ST->hasAVX2())
651 return LT.first * 4; // 2*psrad + shuffle.
652
653 if (const auto *Entry =
654 CostTableLookup(SSE2UniformShiftCostTable, ISD, LT.second))
655 return LT.first * Entry->Cost;
656 }
657
658 if (ISD == ISD::SHL &&
659 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) {
660 MVT VT = LT.second;
661 // Vector shift left by non uniform constant can be lowered
662 // into vector multiply.
663 if (((VT == MVT::v8i16 || VT == MVT::v4i32) && ST->hasSSE2()) ||
664 ((VT == MVT::v16i16 || VT == MVT::v8i32) && ST->hasAVX()))
665 ISD = ISD::MUL;
666 }
667
668 static const CostTblEntry AVX2CostTable[] = {
669 { ISD::SHL, MVT::v32i8, 11 }, // vpblendvb sequence.
670 { ISD::SHL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence.
671
672 { ISD::SRL, MVT::v32i8, 11 }, // vpblendvb sequence.
673 { ISD::SRL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence.
674
675 { ISD::SRA, MVT::v32i8, 24 }, // vpblendvb sequence.
676 { ISD::SRA, MVT::v16i16, 10 }, // extend/vpsravd/pack sequence.
677 { ISD::SRA, MVT::v2i64, 4 }, // srl/xor/sub sequence.
678 { ISD::SRA, MVT::v4i64, 4 }, // srl/xor/sub sequence.
679
680 { ISD::SUB, MVT::v32i8, 1 }, // psubb
681 { ISD::ADD, MVT::v32i8, 1 }, // paddb
682 { ISD::SUB, MVT::v16i16, 1 }, // psubw
683 { ISD::ADD, MVT::v16i16, 1 }, // paddw
684 { ISD::SUB, MVT::v8i32, 1 }, // psubd
685 { ISD::ADD, MVT::v8i32, 1 }, // paddd
686 { ISD::SUB, MVT::v4i64, 1 }, // psubq
687 { ISD::ADD, MVT::v4i64, 1 }, // paddq
688
689 { ISD::MUL, MVT::v32i8, 17 }, // extend/pmullw/trunc sequence.
690 { ISD::MUL, MVT::v16i8, 7 }, // extend/pmullw/trunc sequence.
691 { ISD::MUL, MVT::v16i16, 1 }, // pmullw
692 { ISD::MUL, MVT::v8i32, 2 }, // pmulld (Haswell from agner.org)
693 { ISD::MUL, MVT::v4i64, 8 }, // 3*pmuludq/3*shift/2*add
694
695 { ISD::FADD, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/
696 { ISD::FADD, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/
697 { ISD::FSUB, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/
698 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/
699 { ISD::FMUL, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/
700 { ISD::FMUL, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/
701
702 { ISD::FDIV, MVT::f32, 7 }, // Haswell from http://www.agner.org/
703 { ISD::FDIV, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/
704 { ISD::FDIV, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/
705 { ISD::FDIV, MVT::f64, 14 }, // Haswell from http://www.agner.org/
706 { ISD::FDIV, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/
707 { ISD::FDIV, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/
708 };
709
710 // Look for AVX2 lowering tricks for custom cases.
711 if (ST->hasAVX2())
712 if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second))
713 return LT.first * Entry->Cost;
714
715 static const CostTblEntry AVX1CostTable[] = {
716 // We don't have to scalarize unsupported ops. We can issue two half-sized
717 // operations and we only need to extract the upper YMM half.
718 // Two ops + 1 extract + 1 insert = 4.
719 { ISD::MUL, MVT::v16i16, 4 },
720 { ISD::MUL, MVT::v8i32, 4 },
721 { ISD::SUB, MVT::v32i8, 4 },
722 { ISD::ADD, MVT::v32i8, 4 },
723 { ISD::SUB, MVT::v16i16, 4 },
724 { ISD::ADD, MVT::v16i16, 4 },
725 { ISD::SUB, MVT::v8i32, 4 },
726 { ISD::ADD, MVT::v8i32, 4 },
727 { ISD::SUB, MVT::v4i64, 4 },
728 { ISD::ADD, MVT::v4i64, 4 },
729
730 // A v4i64 multiply is custom lowered as two split v2i64 vectors that then
731 // are lowered as a series of long multiplies(3), shifts(3) and adds(2)
732 // Because we believe v4i64 to be a legal type, we must also include the
733 // extract+insert in the cost table. Therefore, the cost here is 18
734 // instead of 8.
735 { ISD::MUL, MVT::v4i64, 18 },
736
737 { ISD::MUL, MVT::v32i8, 26 }, // extend/pmullw/trunc sequence.
738
739 { ISD::FDIV, MVT::f32, 14 }, // SNB from http://www.agner.org/
740 { ISD::FDIV, MVT::v4f32, 14 }, // SNB from http://www.agner.org/
741 { ISD::FDIV, MVT::v8f32, 28 }, // SNB from http://www.agner.org/
742 { ISD::FDIV, MVT::f64, 22 }, // SNB from http://www.agner.org/
743 { ISD::FDIV, MVT::v2f64, 22 }, // SNB from http://www.agner.org/
744 { ISD::FDIV, MVT::v4f64, 44 }, // SNB from http://www.agner.org/
745 };
746
747 if (ST->hasAVX())
748 if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, LT.second))
749 return LT.first * Entry->Cost;
750
751 static const CostTblEntry SSE42CostTable[] = {
752 { ISD::FADD, MVT::f64, 1 }, // Nehalem from http://www.agner.org/
753 { ISD::FADD, MVT::f32, 1 }, // Nehalem from http://www.agner.org/
754 { ISD::FADD, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/
755 { ISD::FADD, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/
756
757 { ISD::FSUB, MVT::f64, 1 }, // Nehalem from http://www.agner.org/
758 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/
759 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/
760 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/
761
762 { ISD::FMUL, MVT::f64, 1 }, // Nehalem from http://www.agner.org/
763 { ISD::FMUL, MVT::f32, 1 }, // Nehalem from http://www.agner.org/
764 { ISD::FMUL, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/
765 { ISD::FMUL, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/
766
767 { ISD::FDIV, MVT::f32, 14 }, // Nehalem from http://www.agner.org/
768 { ISD::FDIV, MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/
769 { ISD::FDIV, MVT::f64, 22 }, // Nehalem from http://www.agner.org/
770 { ISD::FDIV, MVT::v2f64, 22 }, // Nehalem from http://www.agner.org/
771 };
772
773 if (ST->hasSSE42())
774 if (const auto *Entry = CostTableLookup(SSE42CostTable, ISD, LT.second))
775 return LT.first * Entry->Cost;
776
777 static const CostTblEntry SSE41CostTable[] = {
778 { ISD::SHL, MVT::v16i8, 11 }, // pblendvb sequence.
779 { ISD::SHL, MVT::v32i8, 2*11+2 }, // pblendvb sequence + split.
780 { ISD::SHL, MVT::v8i16, 14 }, // pblendvb sequence.
781 { ISD::SHL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split.
782 { ISD::SHL, MVT::v4i32, 4 }, // pslld/paddd/cvttps2dq/pmulld
783 { ISD::SHL, MVT::v8i32, 2*4+2 }, // pslld/paddd/cvttps2dq/pmulld + split
784
785 { ISD::SRL, MVT::v16i8, 12 }, // pblendvb sequence.
786 { ISD::SRL, MVT::v32i8, 2*12+2 }, // pblendvb sequence + split.
787 { ISD::SRL, MVT::v8i16, 14 }, // pblendvb sequence.
788 { ISD::SRL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split.
789 { ISD::SRL, MVT::v4i32, 11 }, // Shift each lane + blend.
790 { ISD::SRL, MVT::v8i32, 2*11+2 }, // Shift each lane + blend + split.
791
792 { ISD::SRA, MVT::v16i8, 24 }, // pblendvb sequence.
793 { ISD::SRA, MVT::v32i8, 2*24+2 }, // pblendvb sequence + split.
794 { ISD::SRA, MVT::v8i16, 14 }, // pblendvb sequence.
795 { ISD::SRA, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split.
796 { ISD::SRA, MVT::v4i32, 12 }, // Shift each lane + blend.
797 { ISD::SRA, MVT::v8i32, 2*12+2 }, // Shift each lane + blend + split.
798
799 { ISD::MUL, MVT::v4i32, 2 } // pmulld (Nehalem from agner.org)
800 };
801
802 if (ST->hasSSE41())
803 if (const auto *Entry = CostTableLookup(SSE41CostTable, ISD, LT.second))
804 return LT.first * Entry->Cost;
805
806 static const CostTblEntry SSE2CostTable[] = {
807 // We don't correctly identify costs of casts because they are marked as
808 // custom.
809 { ISD::SHL, MVT::v16i8, 26 }, // cmpgtb sequence.
810 { ISD::SHL, MVT::v8i16, 32 }, // cmpgtb sequence.
811 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul.
812 { ISD::SHL, MVT::v2i64, 4 }, // splat+shuffle sequence.
813 { ISD::SHL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split.
814
815 { ISD::SRL, MVT::v16i8, 26 }, // cmpgtb sequence.
816 { ISD::SRL, MVT::v8i16, 32 }, // cmpgtb sequence.
817 { ISD::SRL, MVT::v4i32, 16 }, // Shift each lane + blend.
818 { ISD::SRL, MVT::v2i64, 4 }, // splat+shuffle sequence.
819 { ISD::SRL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split.
820
821 { ISD::SRA, MVT::v16i8, 54 }, // unpacked cmpgtb sequence.
822 { ISD::SRA, MVT::v8i16, 32 }, // cmpgtb sequence.
823 { ISD::SRA, MVT::v4i32, 16 }, // Shift each lane + blend.
824 { ISD::SRA, MVT::v2i64, 12 }, // srl/xor/sub sequence.
825 { ISD::SRA, MVT::v4i64, 2*12+2 }, // srl/xor/sub sequence+split.
826
827 { ISD::MUL, MVT::v16i8, 12 }, // extend/pmullw/trunc sequence.
828 { ISD::MUL, MVT::v8i16, 1 }, // pmullw
829 { ISD::MUL, MVT::v4i32, 6 }, // 3*pmuludq/4*shuffle
830 { ISD::MUL, MVT::v2i64, 8 }, // 3*pmuludq/3*shift/2*add
831
832 { ISD::FDIV, MVT::f32, 23 }, // Pentium IV from http://www.agner.org/
833 { ISD::FDIV, MVT::v4f32, 39 }, // Pentium IV from http://www.agner.org/
834 { ISD::FDIV, MVT::f64, 38 }, // Pentium IV from http://www.agner.org/
835 { ISD::FDIV, MVT::v2f64, 69 }, // Pentium IV from http://www.agner.org/
836
837 { ISD::FADD, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/
838 { ISD::FADD, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/
839
840 { ISD::FSUB, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/
841 { ISD::FSUB, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/
842 };
843
844 if (ST->hasSSE2())
845 if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second))
846 return LT.first * Entry->Cost;
847
848 static const CostTblEntry SSE1CostTable[] = {
849 { ISD::FDIV, MVT::f32, 17 }, // Pentium III from http://www.agner.org/
850 { ISD::FDIV, MVT::v4f32, 34 }, // Pentium III from http://www.agner.org/
851
852 { ISD::FADD, MVT::f32, 1 }, // Pentium III from http://www.agner.org/
853 { ISD::FADD, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/
854
855 { ISD::FSUB, MVT::f32, 1 }, // Pentium III from http://www.agner.org/
856 { ISD::FSUB, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/
857
858 { ISD::ADD, MVT::i8, 1 }, // Pentium III from http://www.agner.org/
859 { ISD::ADD, MVT::i16, 1 }, // Pentium III from http://www.agner.org/
860 { ISD::ADD, MVT::i32, 1 }, // Pentium III from http://www.agner.org/
861
862 { ISD::SUB, MVT::i8, 1 }, // Pentium III from http://www.agner.org/
863 { ISD::SUB, MVT::i16, 1 }, // Pentium III from http://www.agner.org/
864 { ISD::SUB, MVT::i32, 1 }, // Pentium III from http://www.agner.org/
865 };
866
867 if (ST->hasSSE1())
868 if (const auto *Entry = CostTableLookup(SSE1CostTable, ISD, LT.second))
869 return LT.first * Entry->Cost;
870
871 // It is not a good idea to vectorize division. We have to scalarize it and
872 // in the process we will often end up having to spilling regular
873 // registers. The overhead of division is going to dominate most kernels
874 // anyways so try hard to prevent vectorization of division - it is
875 // generally a bad idea. Assume somewhat arbitrarily that we have to be able
876 // to hide "20 cycles" for each lane.
877 if (LT.second.isVector() && (ISD == ISD::SDIV || ISD == ISD::SREM ||
878 ISD == ISD::UDIV || ISD == ISD::UREM)) {
879 int ScalarCost = getArithmeticInstrCost(
880 Opcode, Ty->getScalarType(), Op1Info, Op2Info,
881 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None);
882 return 20 * LT.first * LT.second.getVectorNumElements() * ScalarCost;
883 }
884
885 // Fallback to the default implementation.
886 return BaseT::getArithmeticInstrCost(Opcode, Ty, Op1Info, Op2Info);
887 }
888
889 int X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index,
890 Type *SubTp) {
891 // 64-bit packed float vectors (v2f32) are widened to type v4f32.
892 // 64-bit packed integer vectors (v2i32) are widened to type v4i32.
893 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp);
894
895 // Treat Transpose as 2-op shuffles - there's no difference in lowering.
896 if (Kind == TTI::SK_Transpose)
897 Kind = TTI::SK_PermuteTwoSrc;
898
899 // For Broadcasts we are splatting the first element from the first input
900 // register, so only need to reference that input and all the output
901 // registers are the same.
902 if (Kind == TTI::SK_Broadcast)
903 LT.first = 1;
904
905 // Subvector extractions are free if they start at the beginning of a
906 // vector and cheap if the subvectors are aligned.
907 if (Kind == TTI::SK_ExtractSubvector && LT.second.isVector()) {
908 int NumElts = LT.second.getVectorNumElements();
909 if ((Index % NumElts) == 0)
910 return 0;
911 std::pair<int, MVT> SubLT = TLI->getTypeLegalizationCost(DL, SubTp);
912 if (SubLT.second.isVector()) {
913 int NumSubElts = SubLT.second.getVectorNumElements();
914 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0)
915 return SubLT.first;
916 // Handle some cases for widening legalization. For now we only handle
917 // cases where the original subvector was naturally aligned and evenly
918 // fit in its legalized subvector type.
919 // FIXME: Remove some of the alignment restrictions.
920 // FIXME: We can use permq for 64-bit or larger extracts from 256-bit
921 // vectors.
922 int OrigSubElts = SubTp->getVectorNumElements();
923 if (ExperimentalVectorWideningLegalization &&
924 NumSubElts > OrigSubElts &&
925 (Index % OrigSubElts) == 0 && (NumSubElts % OrigSubElts) == 0 &&
926 LT.second.getVectorElementType() ==
927 SubLT.second.getVectorElementType() &&
928 LT.second.getVectorElementType().getSizeInBits() ==
929 Tp->getVectorElementType()->getPrimitiveSizeInBits()) {
930 assert(NumElts >= NumSubElts && NumElts > OrigSubElts &&
931 "Unexpected number of elements!");
932 Type *VecTy = VectorType::get(Tp->getVectorElementType(),
933 LT.second.getVectorNumElements());
934 Type *SubTy = VectorType::get(Tp->getVectorElementType(),
935 SubLT.second.getVectorNumElements());
936 int ExtractIndex = alignDown((Index % NumElts), NumSubElts);
937 int ExtractCost = getShuffleCost(TTI::SK_ExtractSubvector, VecTy,
938 ExtractIndex, SubTy);
939
940 // If the original size is 32-bits or more, we can use pshufd. Otherwise
941 // if we have SSSE3 we can use pshufb.
942 if (SubTp->getPrimitiveSizeInBits() >= 32 || ST->hasSSSE3())
943 return ExtractCost + 1; // pshufd or pshufb
944
945 assert(SubTp->getPrimitiveSizeInBits() == 16 &&
946 "Unexpected vector size");
947
948 return ExtractCost + 2; // worst case pshufhw + pshufd
949 }
950 }
951 }
952
953 // We are going to permute multiple sources and the result will be in multiple
954 // destinations. Providing an accurate cost only for splits where the element
955 // type remains the same.
956 if (Kind == TTI::SK_PermuteSingleSrc && LT.first != 1) {
957 MVT LegalVT = LT.second;
958 if (LegalVT.isVector() &&
959 LegalVT.getVectorElementType().getSizeInBits() ==
960 Tp->getVectorElementType()->getPrimitiveSizeInBits() &&
961 LegalVT.getVectorNumElements() < Tp->getVectorNumElements()) {
962
963 unsigned VecTySize = DL.getTypeStoreSize(Tp);
964 unsigned LegalVTSize = LegalVT.getStoreSize();
965 // Number of source vectors after legalization:
966 unsigned NumOfSrcs = (VecTySize + LegalVTSize - 1) / LegalVTSize;
967 // Number of destination vectors after legalization:
968 unsigned NumOfDests = LT.first;
969
970 Type *SingleOpTy = VectorType::get(Tp->getVectorElementType(),
971 LegalVT.getVectorNumElements());
972
973 unsigned NumOfShuffles = (NumOfSrcs - 1) * NumOfDests;
974 return NumOfShuffles *
975 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy, 0, nullptr);
976 }
977
978 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp);
979 }
980
981 // For 2-input shuffles, we must account for splitting the 2 inputs into many.
982 if (Kind == TTI::SK_PermuteTwoSrc && LT.first != 1) {
983 // We assume that source and destination have the same vector type.
984 int NumOfDests = LT.first;
985 int NumOfShufflesPerDest = LT.first * 2 - 1;
986 LT.first = NumOfDests * NumOfShufflesPerDest;
987 }
988
989 static const CostTblEntry AVX512VBMIShuffleTbl[] = {
990 {TTI::SK_Reverse, MVT::v64i8, 1}, // vpermb
991 {TTI::SK_Reverse, MVT::v32i8, 1}, // vpermb
992
993 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 1}, // vpermb
994 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 1}, // vpermb
995
996 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 1}, // vpermt2b
997 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 1}, // vpermt2b
998 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1} // vpermt2b
999 };
1000
1001 if (ST->hasVBMI())
1002 if (const auto *Entry =
1003 CostTableLookup(AVX512VBMIShuffleTbl, Kind, LT.second))
1004 return LT.first * Entry->Cost;
1005
1006 static const CostTblEntry AVX512BWShuffleTbl[] = {
1007 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw
1008 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb
1009
1010 {TTI::SK_Reverse, MVT::v32i16, 1}, // vpermw
1011 {TTI::SK_Reverse, MVT::v16i16, 1}, // vpermw
1012 {TTI::SK_Reverse, MVT::v64i8, 2}, // pshufb + vshufi64x2
1013
1014 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 1}, // vpermw
1015 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 1}, // vpermw
1016 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // vpermw
1017 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 8}, // extend to v32i16
1018 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 3}, // vpermw + zext/trunc
1019
1020 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 1}, // vpermt2w
1021 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 1}, // vpermt2w
1022 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpermt2w
1023 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 3}, // zext + vpermt2w + trunc
1024 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 19}, // 6 * v32i8 + 1
1025 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3} // zext + vpermt2w + trunc
1026 };
1027
1028 if (ST->hasBWI())
1029 if (const auto *Entry =
1030 CostTableLookup(AVX512BWShuffleTbl, Kind, LT.second))
1031 return LT.first * Entry->Cost;
1032
1033 static const CostTblEntry AVX512ShuffleTbl[] = {
1034 {TTI::SK_Broadcast, MVT::v8f64, 1}, // vbroadcastpd
1035 {TTI::SK_Broadcast, MVT::v16f32, 1}, // vbroadcastps
1036 {TTI::SK_Broadcast, MVT::v8i64, 1}, // vpbroadcastq
1037 {TTI::SK_Broadcast, MVT::v16i32, 1}, // vpbroadcastd
1038
1039 {TTI::SK_Reverse, MVT::v8f64, 1}, // vpermpd
1040 {TTI::SK_Reverse, MVT::v16f32, 1}, // vpermps
1041 {TTI::SK_Reverse, MVT::v8i64, 1}, // vpermq
1042 {TTI::SK_Reverse, MVT::v16i32, 1}, // vpermd
1043
1044 {TTI::SK_PermuteSingleSrc, MVT::v8f64, 1}, // vpermpd
1045 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd
1046 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // vpermpd
1047 {TTI::SK_PermuteSingleSrc, MVT::v16f32, 1}, // vpermps
1048 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps
1049 {TTI::SK_PermuteSingleSrc, MVT::v4f32, 1}, // vpermps
1050 {TTI::SK_PermuteSingleSrc, MVT::v8i64, 1}, // vpermq
1051 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq
1052 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // vpermq
1053 {TTI::SK_PermuteSingleSrc, MVT::v16i32, 1}, // vpermd
1054 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd
1055 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // vpermd
1056 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb
1057
1058 {TTI::SK_PermuteTwoSrc, MVT::v8f64, 1}, // vpermt2pd
1059 {TTI::SK_PermuteTwoSrc, MVT::v16f32, 1}, // vpermt2ps
1060 {TTI::SK_PermuteTwoSrc, MVT::v8i64, 1}, // vpermt2q
1061 {TTI::SK_PermuteTwoSrc, MVT::v16i32, 1}, // vpermt2d
1062 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 1}, // vpermt2pd
1063 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 1}, // vpermt2ps
1064 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 1}, // vpermt2q
1065 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 1}, // vpermt2d
1066 {TTI::SK_PermuteTwoSrc, MVT::v2f64, 1}, // vpermt2pd
1067 {TTI::SK_PermuteTwoSrc, MVT::v4f32, 1}, // vpermt2ps
1068 {TTI::SK_PermuteTwoSrc, MVT::v2i64, 1}, // vpermt2q
1069 {TTI::SK_PermuteTwoSrc, MVT::v4i32, 1} // vpermt2d
1070 };
1071
1072 if (ST->hasAVX512())
1073 if (const auto *Entry = CostTableLookup(AVX512ShuffleTbl, Kind, LT.second))
1074 return LT.first * Entry->Cost;
1075
1076 static const CostTblEntry AVX2ShuffleTbl[] = {
1077 {TTI::SK_Broadcast, MVT::v4f64, 1}, // vbroadcastpd
1078 {TTI::SK_Broadcast, MVT::v8f32, 1}, // vbroadcastps
1079 {TTI::SK_Broadcast, MVT::v4i64, 1}, // vpbroadcastq
1080 {TTI::SK_Broadcast, MVT::v8i32, 1}, // vpbroadcastd
1081 {TTI::SK_Broadcast, MVT::v16i16, 1}, // vpbroadcastw
1082 {TTI::SK_Broadcast, MVT::v32i8, 1}, // vpbroadcastb
1083
1084 {TTI::SK_Reverse, MVT::v4f64, 1}, // vpermpd
1085 {TTI::SK_Reverse, MVT::v8f32, 1}, // vpermps
1086 {TTI::SK_Reverse, MVT::v4i64, 1}, // vpermq
1087 {TTI::SK_Reverse, MVT::v8i32, 1}, // vpermd
1088 {TTI::SK_Reverse, MVT::v16i16, 2}, // vperm2i128 + pshufb
1089 {TTI::SK_Reverse, MVT::v32i8, 2}, // vperm2i128 + pshufb
1090
1091 {TTI::SK_Select, MVT::v16i16, 1}, // vpblendvb
1092 {TTI::SK_Select, MVT::v32i8, 1}, // vpblendvb
1093
1094 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd
1095 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps
1096 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq
1097 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd
1098 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vperm2i128 + 2*vpshufb
1099 // + vpblendvb
1100 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vperm2i128 + 2*vpshufb
1101 // + vpblendvb
1102
1103 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vpermpd + vblendpd
1104 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 3}, // 2*vpermps + vblendps
1105 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vpermq + vpblendd
1106 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 3}, // 2*vpermd + vpblendd
1107 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 7}, // 2*vperm2i128 + 4*vpshufb
1108 // + vpblendvb
1109 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 7}, // 2*vperm2i128 + 4*vpshufb
1110 // + vpblendvb
1111 };
1112
1113 if (ST->hasAVX2())
1114 if (const auto *Entry = CostTableLookup(AVX2ShuffleTbl, Kind, LT.second))
1115 return LT.first * Entry->Cost;
1116
1117 static const CostTblEntry XOPShuffleTbl[] = {
1118 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vpermil2pd
1119 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 2}, // vperm2f128 + vpermil2ps
1120 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vpermil2pd
1121 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 2}, // vperm2f128 + vpermil2ps
1122 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vextractf128 + 2*vpperm
1123 // + vinsertf128
1124 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vextractf128 + 2*vpperm
1125 // + vinsertf128
1126
1127 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 9}, // 2*vextractf128 + 6*vpperm
1128 // + vinsertf128
1129 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpperm
1130 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 9}, // 2*vextractf128 + 6*vpperm
1131 // + vinsertf128
1132 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1}, // vpperm
1133 };
1134
1135 if (ST->hasXOP())
1136 if (const auto *Entry = CostTableLookup(XOPShuffleTbl, Kind, LT.second))
1137 return LT.first * Entry->Cost;
1138
1139 static const CostTblEntry AVX1ShuffleTbl[] = {
1140 {TTI::SK_Broadcast, MVT::v4f64, 2}, // vperm2f128 + vpermilpd
1141 {TTI::SK_Broadcast, MVT::v8f32, 2}, // vperm2f128 + vpermilps
1142 {TTI::SK_Broadcast, MVT::v4i64, 2}, // vperm2f128 + vpermilpd
1143 {TTI::SK_Broadcast, MVT::v8i32, 2}, // vperm2f128 + vpermilps
1144 {TTI::SK_Broadcast, MVT::v16i16, 3}, // vpshuflw + vpshufd + vinsertf128
1145 {TTI::SK_Broadcast, MVT::v32i8, 2}, // vpshufb + vinsertf128
1146
1147 {TTI::SK_Reverse, MVT::v4f64, 2}, // vperm2f128 + vpermilpd
1148 {TTI::SK_Reverse, MVT::v8f32, 2}, // vperm2f128 + vpermilps
1149 {TTI::SK_Reverse, MVT::v4i64, 2}, // vperm2f128 + vpermilpd
1150 {TTI::SK_Reverse, MVT::v8i32, 2}, // vperm2f128 + vpermilps
1151 {TTI::SK_Reverse, MVT::v16i16, 4}, // vextractf128 + 2*pshufb
1152 // + vinsertf128
1153 {TTI::SK_Reverse, MVT::v32i8, 4}, // vextractf128 + 2*pshufb
1154 // + vinsertf128
1155
1156 {TTI::SK_Select, MVT::v4i64, 1}, // vblendpd
1157 {TTI::SK_Select, MVT::v4f64, 1}, // vblendpd
1158 {TTI::SK_Select, MVT::v8i32, 1}, // vblendps
1159 {TTI::SK_Select, MVT::v8f32, 1}, // vblendps
1160 {TTI::SK_Select, MVT::v16i16, 3}, // vpand + vpandn + vpor
1161 {TTI::SK_Select, MVT::v32i8, 3}, // vpand + vpandn + vpor
1162
1163 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vshufpd
1164 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vshufpd
1165 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps
1166 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps
1167 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 8}, // vextractf128 + 4*pshufb
1168 // + 2*por + vinsertf128
1169 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 8}, // vextractf128 + 4*pshufb
1170 // + 2*por + vinsertf128
1171
1172 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vperm2f128 + vshufpd
1173 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vperm2f128 + vshufpd
1174 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps
1175 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps
1176 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 15}, // 2*vextractf128 + 8*pshufb
1177 // + 4*por + vinsertf128
1178 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 15}, // 2*vextractf128 + 8*pshufb
1179 // + 4*por + vinsertf128
1180 };
1181
1182 if (ST->hasAVX())
1183 if (const auto *Entry = CostTableLookup(AVX1ShuffleTbl, Kind, LT.second))
1184 return LT.first * Entry->Cost;
1185
1186 static const CostTblEntry SSE41ShuffleTbl[] = {
1187 {TTI::SK_Select, MVT::v2i64, 1}, // pblendw
1188 {TTI::SK_Select, MVT::v2f64, 1}, // movsd
1189 {TTI::SK_Select, MVT::v4i32, 1}, // pblendw
1190 {TTI::SK_Select, MVT::v4f32, 1}, // blendps
1191 {TTI::SK_Select, MVT::v8i16, 1}, // pblendw
1192 {TTI::SK_Select, MVT::v16i8, 1} // pblendvb
1193 };
1194
1195 if (ST->hasSSE41())
1196 if (const auto *Entry = CostTableLookup(SSE41ShuffleTbl, Kind, LT.second))
1197 return LT.first * Entry->Cost;
1198
1199 static const CostTblEntry SSSE3ShuffleTbl[] = {
1200 {TTI::SK_Broadcast, MVT::v8i16, 1}, // pshufb
1201 {TTI::SK_Broadcast, MVT::v16i8, 1}, // pshufb
1202
1203 {TTI::SK_Reverse, MVT::v8i16, 1}, // pshufb
1204 {TTI::SK_Reverse, MVT::v16i8, 1}, // pshufb
1205
1206 {TTI::SK_Select, MVT::v8i16, 3}, // 2*pshufb + por
1207 {TTI::SK_Select, MVT::v16i8, 3}, // 2*pshufb + por
1208
1209 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // pshufb
1210 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb
1211
1212 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 3}, // 2*pshufb + por
1213 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3}, // 2*pshufb + por
1214 };
1215
1216 if (ST->hasSSSE3())
1217 if (const auto *Entry = CostTableLookup(SSSE3ShuffleTbl, Kind, LT.second))
1218 return LT.first * Entry->Cost;
1219
1220 static const CostTblEntry SSE2ShuffleTbl[] = {
1221 {TTI::SK_Broadcast, MVT::v2f64, 1}, // shufpd
1222 {TTI::SK_Broadcast, MVT::v2i64, 1}, // pshufd
1223 {TTI::SK_Broadcast, MVT::v4i32, 1}, // pshufd
1224 {TTI::SK_Broadcast, MVT::v8i16, 2}, // pshuflw + pshufd
1225 {TTI::SK_Broadcast, MVT::v16i8, 3}, // unpck + pshuflw + pshufd
1226
1227 {TTI::SK_Reverse, MVT::v2f64, 1}, // shufpd
1228 {TTI::SK_Reverse, MVT::v2i64, 1}, // pshufd
1229 {TTI::SK_Reverse, MVT::v4i32, 1}, // pshufd
1230 {TTI::SK_Reverse, MVT::v8i16, 3}, // pshuflw + pshufhw + pshufd
1231 {TTI::SK_Reverse, MVT::v16i8, 9}, // 2*pshuflw + 2*pshufhw
1232 // + 2*pshufd + 2*unpck + packus
1233
1234 {TTI::SK_Select, MVT::v2i64, 1}, // movsd
1235 {TTI::SK_Select, MVT::v2f64, 1}, // movsd
1236 {TTI::SK_Select, MVT::v4i32, 2}, // 2*shufps
1237 {TTI::SK_Select, MVT::v8i16, 3}, // pand + pandn + por
1238 {TTI::SK_Select, MVT::v16i8, 3}, // pand + pandn + por
1239
1240 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // shufpd
1241 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // pshufd
1242 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // pshufd
1243 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 5}, // 2*pshuflw + 2*pshufhw
1244 // + pshufd/unpck
1245 { TTI::SK_PermuteSingleSrc, MVT::v16i8, 10 }, // 2*pshuflw + 2*pshufhw
1246 // + 2*pshufd + 2*unpck + 2*packus
1247
1248 { TTI::SK_PermuteTwoSrc, MVT::v2f64, 1 }, // shufpd
1249 { TTI::SK_PermuteTwoSrc, MVT::v2i64, 1 }, // shufpd
1250 { TTI::SK_PermuteTwoSrc, MVT::v4i32, 2 }, // 2*{unpck,movsd,pshufd}
1251 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 8 }, // blend+permute
1252 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 13 }, // blend+permute
1253 };
1254
1255 if (ST->hasSSE2())
1256 if (const auto *Entry = CostTableLookup(SSE2ShuffleTbl, Kind, LT.second))
1257 return LT.first * Entry->Cost;
1258
1259 static const CostTblEntry SSE1ShuffleTbl[] = {
1260 { TTI::SK_Broadcast, MVT::v4f32, 1 }, // shufps
1261 { TTI::SK_Reverse, MVT::v4f32, 1 }, // shufps
1262 { TTI::SK_Select, MVT::v4f32, 2 }, // 2*shufps
1263 { TTI::SK_PermuteSingleSrc, MVT::v4f32, 1 }, // shufps
1264 { TTI::SK_PermuteTwoSrc, MVT::v4f32, 2 }, // 2*shufps
1265 };
1266
1267 if (ST->hasSSE1())
1268 if (const auto *Entry = CostTableLookup(SSE1ShuffleTbl, Kind, LT.second))
1269 return LT.first * Entry->Cost;
1270
1271 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp);
1272 }
1273
1274 int X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
1275 const Instruction *I) {
1276 int ISD = TLI->InstructionOpcodeToISD(Opcode);
1277 assert(ISD && "Invalid opcode");
1278
1279 // FIXME: Need a better design of the cost table to handle non-simple types of
1280 // potential massive combinations (elem_num x src_type x dst_type).
1281
1282 static const TypeConversionCostTblEntry AVX512BWConversionTbl[] {
1283 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 1 },
1284 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 1 },
1285
1286 // Mask sign extend has an instruction.
1287 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 },
1288 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 },
1289 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 },
1290 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 },
1291 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 },
1292 { ISD::SIGN_EXTEND, MVT::v64i8, MVT::v64i1, 1 },
1293
1294 // Mask zero extend is a load + broadcast.
1295 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 },
1296 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 },
1297 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 },
1298 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 },
1299 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 },
1300 { ISD::ZERO_EXTEND, MVT::v64i8, MVT::v64i1, 2 },
1301 };
1302
1303 static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = {
1304 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 },
1305 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 },
1306 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 },
1307 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 },
1308 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 },
1309 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 },
1310
1311 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 },
1312 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 },
1313 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 },
1314 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 },
1315 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 },
1316 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 },
1317
1318 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 1 },
1319 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f32, 1 },
1320 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, 1 },
1321 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 },
1322 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f64, 1 },
1323 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, 1 },
1324
1325 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 1 },
1326 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 },
1327 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 },
1328 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 },
1329 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 },
1330 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 },
1331 };
1332
1333 // TODO: For AVX512DQ + AVX512VL, we also have cheap casts for 128-bit and
1334 // 256-bit wide vectors.
1335
1336 // Used with widening legalization
1337 static const TypeConversionCostTblEntry AVX512FConversionTblWide[] = {
1338 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 1 },
1339 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 1 },
1340 };
1341
1342 static const TypeConversionCostTblEntry AVX512FConversionTbl[] = {
1343 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 },
1344 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 },
1345 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 },
1346
1347 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 1 },
1348 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 1 },
1349 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 1 },
1350 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 },
1351
1352 // v16i1 -> v16i32 - load + broadcast
1353 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 2 },
1354 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 },
1355 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 },
1356 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 },
1357 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 },
1358 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 },
1359 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 },
1360 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 },
1361 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 },
1362 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1 },
1363
1364 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 },
1365 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 },
1366 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 },
1367 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 },
1368 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 },
1369 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 },
1370 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 },
1371 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 },
1372
1373 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 },
1374 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 },
1375 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 2 },
1376 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 },
1377 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 2 },
1378 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 },
1379 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 },
1380 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 5 },
1381 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 },
1382 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 },
1383 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 },
1384 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 },
1385 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 },
1386 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 },
1387 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
1388 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 },
1389 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 },
1390 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 },
1391 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 },
1392 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 5 },
1393 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 26 },
1394 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 },
1395 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 5 },
1396 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 5 },
1397
1398 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 1 },
1399 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 1 },
1400 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 1 },
1401
1402 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 },
1403 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 },
1404 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 1 },
1405 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 1 },
1406 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f64, 2 },
1407 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, 2 },
1408 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 },
1409 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 2 },
1410 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f32, 2 },
1411 };
1412
1413 static const TypeConversionCostTblEntry AVX2ConversionTblWide[] = {
1414 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 1 },
1415 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 1 },
1416 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 1 },
1417 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 1 },
1418 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 1 },
1419 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 1 },
1420 };
1421
1422 static const TypeConversionCostTblEntry AVX2ConversionTbl[] = {
1423 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 },
1424 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 },
1425 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 },
1426 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 },
1427 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 3 },
1428 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 3 },
1429 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
1430 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
1431 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 },
1432 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 },
1433 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
1434 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
1435 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
1436 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
1437 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
1438 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
1439
1440 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 },
1441 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 },
1442 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 },
1443 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 },
1444 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 },
1445 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 4 },
1446
1447 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 },
1448 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 },
1449
1450 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 },
1451 };
1452
1453 static const TypeConversionCostTblEntry AVXConversionTblWide[] = {
1454 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 4 },
1455 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 4 },
1456 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 4 },
1457 };
1458
1459 static const TypeConversionCostTblEntry AVXConversionTbl[] = {
1460 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 },
1461 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 },
1462 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 },
1463 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 },
1464 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 6 },
1465 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 },
1466 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 7 },
1467 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 4 },
1468 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 },
1469 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 4 },
1470 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 6 },
1471 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
1472 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 },
1473 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 4 },
1474 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 4 },
1475 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 4 },
1476
1477 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 4 },
1478 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 },
1479 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 },
1480 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 4 },
1481 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 4 },
1482 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 4 },
1483 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 11 },
1484 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 9 },
1485 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 9 },
1486 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 11 },
1487
1488 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
1489 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 },
1490 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 },
1491 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
1492 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 },
1493 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 },
1494 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 },
1495 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 },
1496 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 },
1497 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
1498 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 },
1499 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 },
1500
1501 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 },
1502 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 },
1503 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 },
1504 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 },
1505 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 },
1506 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 },
1507 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
1508 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 },
1509 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 },
1510 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 6 },
1511 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 6 },
1512 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 },
1513 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 9 },
1514 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 },
1515 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 6 },
1516 // The generic code to compute the scalar overhead is currently broken.
1517 // Workaround this limitation by estimating the scalarization overhead
1518 // here. We have roughly 10 instructions per scalar element.
1519 // Multiply that by the vector width.
1520 // FIXME: remove that when PR19268 is fixed.
1521 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 },
1522 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 },
1523
1524 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 },
1525 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 7 },
1526 // This node is expanded into scalarized operations but BasicTTI is overly
1527 // optimistic estimating its cost. It computes 3 per element (one
1528 // vector-extract, one scalar conversion and one vector-insert). The
1529 // problem is that the inserts form a read-modify-write chain so latency
1530 // should be factored in too. Inflating the cost per element by 1.
1531 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 8*4 },
1532 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4*4 },
1533
1534 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 },
1535 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 },
1536 };
1537
1538 static const TypeConversionCostTblEntry SSE41ConversionTbl[] = {
1539 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 2 },
1540 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 2 },
1541 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 2 },
1542 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 2 },
1543 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 },
1544 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 },
1545
1546 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 },
1547 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 2 },
1548 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 1 },
1549 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 1 },
1550 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 },
1551 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 1 },
1552 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 2 },
1553 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 2 },
1554 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 },
1555 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 },
1556 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 4 },
1557 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 4 },
1558 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 },
1559 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 1 },
1560 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 },
1561 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 },
1562 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 4 },
1563 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 4 },
1564
1565 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 },
1566 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 1 },
1567 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 1 },
1568 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 },
1569 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 },
1570 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 3 },
1571 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 6 },
1572 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 1 }, // PSHUFB
1573
1574 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 4 },
1575 };
1576
1577 static const TypeConversionCostTblEntry SSE2ConversionTblWide[] = {
1578 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 2*10 },
1579 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2*10 },
1580 };
1581
1582 static const TypeConversionCostTblEntry SSE2ConversionTbl[] = {
1583 // These are somewhat magic numbers justified by looking at the output of
1584 // Intel's IACA, running some kernels and making sure when we take
1585 // legalization into account the throughput will be overestimated.
1586 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 },
1587 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 },
1588 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 },
1589 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 },
1590 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 },
1591 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 },
1592 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 },
1593 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 },
1594
1595 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 },
1596 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 },
1597 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 },
1598 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 },
1599 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 },
1600 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 8 },
1601 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 6 },
1602 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 },
1603
1604 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 3 },
1605
1606 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 6 },
1607 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 4 },
1608 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 4 },
1609
1610 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 },
1611 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 6 },
1612 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 2 },
1613 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 3 },
1614 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 },
1615 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 8 },
1616 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 },
1617 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 2 },
1618 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 6 },
1619 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 6 },
1620 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 },
1621 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 },
1622 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 9 },
1623 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 12 },
1624 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 },
1625 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 2 },
1626 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
1627 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 10 },
1628 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 },
1629 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 },
1630 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 6 },
1631 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 8 },
1632 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 },
1633 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 5 },
1634
1635 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 2 }, // PAND+PACKUSWB
1636 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 4 },
1637 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 },
1638 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 },
1639 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i32, 3 }, // PAND+3*PACKUSWB
1640 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i32, 1 },
1641 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 3 },
1642 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 3 },
1643 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 },
1644 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 7 },
1645 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 },
1646 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 10 },
1647 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 4 }, // PAND+3*PACKUSWB
1648 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i64, 2 }, // PSHUFD+PSHUFLW
1649 { ISD::TRUNCATE, MVT::v2i32, MVT::v2i64, 1 }, // PSHUFD
1650 };
1651
1652 std::pair<int, MVT> LTSrc = TLI->getTypeLegalizationCost(DL, Src);
1653 std::pair<int, MVT> LTDest = TLI->getTypeLegalizationCost(DL, Dst);
1654
1655 if (ST->hasSSE2() && !ST->hasAVX() &&
1656 ExperimentalVectorWideningLegalization) {
1657 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTblWide, ISD,
1658 LTDest.second, LTSrc.second))
1659 return LTSrc.first * Entry->Cost;
1660 }
1661
1662 if (ST->hasSSE2() && !ST->hasAVX()) {
1663 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD,
1664 LTDest.second, LTSrc.second))
1665 return LTSrc.first * Entry->Cost;
1666 }
1667
1668 EVT SrcTy = TLI->getValueType(DL, Src);
1669 EVT DstTy = TLI->getValueType(DL, Dst);
1670
1671 // The function getSimpleVT only handles simple value types.
1672 if (!SrcTy.isSimple() || !DstTy.isSimple())
1673 return BaseT::getCastInstrCost(Opcode, Dst, Src);
1674
1675 MVT SimpleSrcTy = SrcTy.getSimpleVT();
1676 MVT SimpleDstTy = DstTy.getSimpleVT();
1677
1678 // Make sure that neither type is going to be split before using the
1679 // AVX512 tables. This handles -mprefer-vector-width=256
1680 // with -min-legal-vector-width<=256
1681 if (TLI->getTypeAction(SimpleSrcTy) != TargetLowering::TypeSplitVector &&
1682 TLI->getTypeAction(SimpleDstTy) != TargetLowering::TypeSplitVector) {
1683 if (ST->hasBWI())
1684 if (const auto *Entry = ConvertCostTableLookup(AVX512BWConversionTbl, ISD,
1685 SimpleDstTy, SimpleSrcTy))
1686 return Entry->Cost;
1687
1688 if (ST->hasDQI())
1689 if (const auto *Entry = ConvertCostTableLookup(AVX512DQConversionTbl, ISD,
1690 SimpleDstTy, SimpleSrcTy))
1691 return Entry->Cost;
1692
1693 if (ST->hasAVX512() && ExperimentalVectorWideningLegalization)
1694 if (const auto *Entry = ConvertCostTableLookup(AVX512FConversionTblWide, ISD,
1695 SimpleDstTy, SimpleSrcTy))
1696 return Entry->Cost;
1697
1698 if (ST->hasAVX512())
1699 if (const auto *Entry = ConvertCostTableLookup(AVX512FConversionTbl, ISD,
1700 SimpleDstTy, SimpleSrcTy))
1701 return Entry->Cost;
1702 }
1703
1704 if (ST->hasAVX2() && ExperimentalVectorWideningLegalization) {
1705 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTblWide, ISD,
1706 SimpleDstTy, SimpleSrcTy))
1707 return Entry->Cost;
1708 }
1709
1710 if (ST->hasAVX2()) {
1711 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD,
1712 SimpleDstTy, SimpleSrcTy))
1713 return Entry->Cost;
1714 }
1715
1716 if (ST->hasAVX() && ExperimentalVectorWideningLegalization) {
1717 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTblWide, ISD,
1718 SimpleDstTy, SimpleSrcTy))
1719 return Entry->Cost;
1720 }
1721
1722 if (ST->hasAVX()) {
1723 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD,
1724 SimpleDstTy, SimpleSrcTy))
1725 return Entry->Cost;
1726 }
1727
1728 if (ST->hasSSE41()) {
1729 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD,
1730 SimpleDstTy, SimpleSrcTy))
1731 return Entry->Cost;
1732 }
1733
1734 if (ST->hasSSE2() && ExperimentalVectorWideningLegalization) {
1735 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTblWide, ISD,
1736 SimpleDstTy, SimpleSrcTy))
1737 return Entry->Cost;
1738 }
1739
1740 if (ST->hasSSE2()) {
1741 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD,
1742 SimpleDstTy, SimpleSrcTy))
1743 return Entry->Cost;
1744 }
1745
1746 return BaseT::getCastInstrCost(Opcode, Dst, Src, I);
1747 }
1748
1749 int X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
1750 const Instruction *I) {
1751 // Legalize the type.
1752 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy);
1753
1754 MVT MTy = LT.second;
1755
1756 int ISD = TLI->InstructionOpcodeToISD(Opcode);
1757 assert(ISD && "Invalid opcode");
1758
1759 unsigned ExtraCost = 0;
1760 if (I && (Opcode == Instruction::ICmp || Opcode == Instruction::FCmp)) {
1761 // Some vector comparison predicates cost extra instructions.
1762 if (MTy.isVector() &&
1763 !((ST->hasXOP() && (!ST->hasAVX2() || MTy.is128BitVector())) ||
1764 (ST->hasAVX512() && 32 <= MTy.getScalarSizeInBits()) ||
1765 ST->hasBWI())) {
1766 switch (cast<CmpInst>(I)->getPredicate()) {
1767 case CmpInst::Predicate::ICMP_NE:
1768 // xor(cmpeq(x,y),-1)
1769 ExtraCost = 1;
1770 break;
1771 case CmpInst::Predicate::ICMP_SGE:
1772 case CmpInst::Predicate::ICMP_SLE:
1773 // xor(cmpgt(x,y),-1)
1774 ExtraCost = 1;
1775 break;
1776 case CmpInst::Predicate::ICMP_ULT:
1777 case CmpInst::Predicate::ICMP_UGT:
1778 // cmpgt(xor(x,signbit),xor(y,signbit))
1779 // xor(cmpeq(pmaxu(x,y),x),-1)
1780 ExtraCost = 2;
1781 break;
1782 case CmpInst::Predicate::ICMP_ULE:
1783 case CmpInst::Predicate::ICMP_UGE:
1784 if ((ST->hasSSE41() && MTy.getScalarSizeInBits() == 32) ||
1785 (ST->hasSSE2() && MTy.getScalarSizeInBits() < 32)) {
1786 // cmpeq(psubus(x,y),0)
1787 // cmpeq(pminu(x,y),x)
1788 ExtraCost = 1;
1789 } else {
1790 // xor(cmpgt(xor(x,signbit),xor(y,signbit)),-1)
1791 ExtraCost = 3;
1792 }
1793 break;
1794 default:
1795 break;
1796 }
1797 }
1798 }
1799
1800 static const CostTblEntry SLMCostTbl[] = {
1801 // slm pcmpeq/pcmpgt throughput is 2
1802 { ISD::SETCC, MVT::v2i64, 2 },
1803 };
1804
1805 static const CostTblEntry AVX512BWCostTbl[] = {
1806 { ISD::SETCC, MVT::v32i16, 1 },
1807 { ISD::SETCC, MVT::v64i8, 1 },
1808
1809 { ISD::SELECT, MVT::v32i16, 1 },
1810 { ISD::SELECT, MVT::v64i8, 1 },
1811 };
1812
1813 static const CostTblEntry AVX512CostTbl[] = {
1814 { ISD::SETCC, MVT::v8i64, 1 },
1815 { ISD::SETCC, MVT::v16i32, 1 },
1816 { ISD::SETCC, MVT::v8f64, 1 },
1817 { ISD::SETCC, MVT::v16f32, 1 },
1818
1819 { ISD::SELECT, MVT::v8i64, 1 },
1820 { ISD::SELECT, MVT::v16i32, 1 },
1821 { ISD::SELECT, MVT::v8f64, 1 },
1822 { ISD::SELECT, MVT::v16f32, 1 },
1823 };
1824
1825 static const CostTblEntry AVX2CostTbl[] = {
1826 { ISD::SETCC, MVT::v4i64, 1 },
1827 { ISD::SETCC, MVT::v8i32, 1 },
1828 { ISD::SETCC, MVT::v16i16, 1 },
1829 { ISD::SETCC, MVT::v32i8, 1 },
1830
1831 { ISD::SELECT, MVT::v4i64, 1 }, // pblendvb
1832 { ISD::SELECT, MVT::v8i32, 1 }, // pblendvb
1833 { ISD::SELECT, MVT::v16i16, 1 }, // pblendvb
1834 { ISD::SELECT, MVT::v32i8, 1 }, // pblendvb
1835 };
1836
1837 static const CostTblEntry AVX1CostTbl[] = {
1838 { ISD::SETCC, MVT::v4f64, 1 },
1839 { ISD::SETCC, MVT::v8f32, 1 },
1840 // AVX1 does not support 8-wide integer compare.
1841 { ISD::SETCC, MVT::v4i64, 4 },
1842 { ISD::SETCC, MVT::v8i32, 4 },
1843 { ISD::SETCC, MVT::v16i16, 4 },
1844 { ISD::SETCC, MVT::v32i8, 4 },
1845
1846 { ISD::SELECT, MVT::v4f64, 1 }, // vblendvpd
1847 { ISD::SELECT, MVT::v8f32, 1 }, // vblendvps
1848 { ISD::SELECT, MVT::v4i64, 1 }, // vblendvpd
1849 { ISD::SELECT, MVT::v8i32, 1 }, // vblendvps
1850 { ISD::SELECT, MVT::v16i16, 3 }, // vandps + vandnps + vorps
1851 { ISD::SELECT, MVT::v32i8, 3 }, // vandps + vandnps + vorps
1852 };
1853
1854 static const CostTblEntry SSE42CostTbl[] = {
1855 { ISD::SETCC, MVT::v2f64, 1 },
1856 { ISD::SETCC, MVT::v4f32, 1 },
1857 { ISD::SETCC, MVT::v2i64, 1 },
1858 };
1859
1860 static const CostTblEntry SSE41CostTbl[] = {
1861 { ISD::SELECT, MVT::v2f64, 1 }, // blendvpd
1862 { ISD::SELECT, MVT::v4f32, 1 }, // blendvps
1863 { ISD::SELECT, MVT::v2i64, 1 }, // pblendvb
1864 { ISD::SELECT, MVT::v4i32, 1 }, // pblendvb
1865 { ISD::SELECT, MVT::v8i16, 1 }, // pblendvb
1866 { ISD::SELECT, MVT::v16i8, 1 }, // pblendvb
1867 };
1868
1869 static const CostTblEntry SSE2CostTbl[] = {
1870 { ISD::SETCC, MVT::v2f64, 2 },
1871 { ISD::SETCC, MVT::f64, 1 },
1872 { ISD::SETCC, MVT::v2i64, 8 },
1873 { ISD::SETCC, MVT::v4i32, 1 },
1874 { ISD::SETCC, MVT::v8i16, 1 },
1875 { ISD::SETCC, MVT::v16i8, 1 },
1876
1877 { ISD::SELECT, MVT::v2f64, 3 }, // andpd + andnpd + orpd
1878 { ISD::SELECT, MVT::v2i64, 3 }, // pand + pandn + por
1879 { ISD::SELECT, MVT::v4i32, 3 }, // pand + pandn + por
1880 { ISD::SELECT, MVT::v8i16, 3 }, // pand + pandn + por
1881 { ISD::SELECT, MVT::v16i8, 3 }, // pand + pandn + por
1882 };
1883
1884 static const CostTblEntry SSE1CostTbl[] = {
1885 { ISD::SETCC, MVT::v4f32, 2 },
1886 { ISD::SETCC, MVT::f32, 1 },
1887
1888 { ISD::SELECT, MVT::v4f32, 3 }, // andps + andnps + orps
1889 };
1890
1891 if (ST->isSLM())
1892 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy))
1893 return LT.first * (ExtraCost + Entry->Cost);
1894
1895 if (ST->hasBWI())
1896 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy))
1897 return LT.first * (ExtraCost + Entry->Cost);
1898
1899 if (ST->hasAVX512())
1900 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy))
1901 return LT.first * (ExtraCost + Entry->Cost);
1902
1903 if (ST->hasAVX2())
1904 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy))
1905 return LT.first * (ExtraCost + Entry->Cost);
1906
1907 if (ST->hasAVX())
1908 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy))
1909 return LT.first * (ExtraCost + Entry->Cost);
1910
1911 if (ST->hasSSE42())
1912 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy))
1913 return LT.first * (ExtraCost + Entry->Cost);
1914
1915 if (ST->hasSSE41())
1916 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy))
1917 return LT.first * (ExtraCost + Entry->Cost);
1918
1919 if (ST->hasSSE2())
1920 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy))
1921 return LT.first * (ExtraCost + Entry->Cost);
1922
1923 if (ST->hasSSE1())
1924 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy))
1925 return LT.first * (ExtraCost + Entry->Cost);
1926
1927 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, I);
1928 }
1929
1930 unsigned X86TTIImpl::getAtomicMemIntrinsicMaxElementSize() const { return 16; }
1931
1932 int X86TTIImpl::getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy,
1933 ArrayRef<Type *> Tys, FastMathFlags FMF,
1934 unsigned ScalarizationCostPassed) {
1935 // Costs should match the codegen from:
1936 // BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll
1937 // BSWAP: llvm\test\CodeGen\X86\bswap-vector.ll
1938 // CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll
1939 // CTPOP: llvm\test\CodeGen\X86\vector-popcnt-*.ll
1940 // CTTZ: llvm\test\CodeGen\X86\vector-tzcnt-*.ll
1941 static const CostTblEntry AVX512CDCostTbl[] = {
1942 { ISD::CTLZ, MVT::v8i64, 1 },
1943 { ISD::CTLZ, MVT::v16i32, 1 },
1944 { ISD::CTLZ, MVT::v32i16, 8 },
1945 { ISD::CTLZ, MVT::v64i8, 20 },
1946 { ISD::CTLZ, MVT::v4i64, 1 },
1947 { ISD::CTLZ, MVT::v8i32, 1 },
1948 { ISD::CTLZ, MVT::v16i16, 4 },
1949 { ISD::CTLZ, MVT::v32i8, 10 },
1950 { ISD::CTLZ, MVT::v2i64, 1 },
1951 { ISD::CTLZ, MVT::v4i32, 1 },
1952 { ISD::CTLZ, MVT::v8i16, 4 },
1953 { ISD::CTLZ, MVT::v16i8, 4 },
1954 };
1955 static const CostTblEntry AVX512BWCostTbl[] = {
1956 { ISD::BITREVERSE, MVT::v8i64, 5 },
1957 { ISD::BITREVERSE, MVT::v16i32, 5 },
1958 { ISD::BITREVERSE, MVT::v32i16, 5 },
1959 { ISD::BITREVERSE, MVT::v64i8, 5 },
1960 { ISD::CTLZ, MVT::v8i64, 23 },
1961 { ISD::CTLZ, MVT::v16i32, 22 },
1962 { ISD::CTLZ, MVT::v32i16, 18 },
1963 { ISD::CTLZ, MVT::v64i8, 17 },
1964 { ISD::CTPOP, MVT::v8i64, 7 },
1965 { ISD::CTPOP, MVT::v16i32, 11 },
1966 { ISD::CTPOP, MVT::v32i16, 9 },
1967 { ISD::CTPOP, MVT::v64i8, 6 },
1968 { ISD::CTTZ, MVT::v8i64, 10 },
1969 { ISD::CTTZ, MVT::v16i32, 14 },
1970 { ISD::CTTZ, MVT::v32i16, 12 },
1971 { ISD::CTTZ, MVT::v64i8, 9 },
1972 { ISD::SADDSAT, MVT::v32i16, 1 },
1973 { ISD::SADDSAT, MVT::v64i8, 1 },
1974 { ISD::SSUBSAT, MVT::v32i16, 1 },
1975 { ISD::SSUBSAT, MVT::v64i8, 1 },
1976 { ISD::UADDSAT, MVT::v32i16, 1 },
1977 { ISD::UADDSAT, MVT::v64i8, 1 },
1978 { ISD::USUBSAT, MVT::v32i16, 1 },
1979 { ISD::USUBSAT, MVT::v64i8, 1 },
1980 };
1981 static const CostTblEntry AVX512CostTbl[] = {
1982 { ISD::BITREVERSE, MVT::v8i64, 36 },
1983 { ISD::BITREVERSE, MVT::v16i32, 24 },
1984 { ISD::CTLZ, MVT::v8i64, 29 },
1985 { ISD::CTLZ, MVT::v16i32, 35 },
1986 { ISD::CTPOP, MVT::v8i64, 16 },
1987 { ISD::CTPOP, MVT::v16i32, 24 },
1988 { ISD::CTTZ, MVT::v8i64, 20 },
1989 { ISD::CTTZ, MVT::v16i32, 28 },
1990 { ISD::USUBSAT, MVT::v16i32, 2 }, // pmaxud + psubd
1991 { ISD::USUBSAT, MVT::v2i64, 2 }, // pmaxuq + psubq
1992 { ISD::USUBSAT, MVT::v4i64, 2 }, // pmaxuq + psubq
1993 { ISD::USUBSAT, MVT::v8i64, 2 }, // pmaxuq + psubq
1994 { ISD::UADDSAT, MVT::v16i32, 3 }, // not + pminud + paddd
1995 { ISD::UADDSAT, MVT::v2i64, 3 }, // not + pminuq + paddq
1996 { ISD::UADDSAT, MVT::v4i64, 3 }, // not + pminuq + paddq
1997 { ISD::UADDSAT, MVT::v8i64, 3 }, // not + pminuq + paddq
1998 };
1999 static const CostTblEntry XOPCostTbl[] = {
2000 { ISD::BITREVERSE, MVT::v4i64, 4 },
2001 { ISD::BITREVERSE, MVT::v8i32, 4 },
2002 { ISD::BITREVERSE, MVT::v16i16, 4 },
2003 { ISD::BITREVERSE, MVT::v32i8, 4 },
2004 { ISD::BITREVERSE, MVT::v2i64, 1 },
2005 { ISD::BITREVERSE, MVT::v4i32, 1 },
2006 { ISD::BITREVERSE, MVT::v8i16, 1 },
2007 { ISD::BITREVERSE, MVT::v16i8, 1 },
2008 { ISD::BITREVERSE, MVT::i64, 3 },
2009 { ISD::BITREVERSE, MVT::i32, 3 },
2010 { ISD::BITREVERSE, MVT::i16, 3 },
2011 { ISD::BITREVERSE, MVT::i8, 3 }
2012 };
2013 static const CostTblEntry AVX2CostTbl[] = {
2014 { ISD::BITREVERSE, MVT::v4i64, 5 },
2015 { ISD::BITREVERSE, MVT::v8i32, 5 },
2016 { ISD::BITREVERSE, MVT::v16i16, 5 },
2017 { ISD::BITREVERSE, MVT::v32i8, 5 },
2018 { ISD::BSWAP, MVT::v4i64, 1 },
2019 { ISD::BSWAP, MVT::v8i32, 1 },
2020 { ISD::BSWAP, MVT::v16i16, 1 },
2021 { ISD::CTLZ, MVT::v4i64, 23 },
2022 { ISD::CTLZ, MVT::v8i32, 18 },
2023 { ISD::CTLZ, MVT::v16i16, 14 },
2024 { ISD::CTLZ, MVT::v32i8, 9 },
2025 { ISD::CTPOP, MVT::v4i64, 7 },
2026 { ISD::CTPOP, MVT::v8i32, 11 },
2027 { ISD::CTPOP, MVT::v16i16, 9 },
2028 { ISD::CTPOP, MVT::v32i8, 6 },
2029 { ISD::CTTZ, MVT::v4i64, 10 },
2030 { ISD::CTTZ, MVT::v8i32, 14 },
2031 { ISD::CTTZ, MVT::v16i16, 12 },
2032 { ISD::CTTZ, MVT::v32i8, 9 },
2033 { ISD::SADDSAT, MVT::v16i16, 1 },
2034 { ISD::SADDSAT, MVT::v32i8, 1 },
2035 { ISD::SSUBSAT, MVT::v16i16, 1 },
2036 { ISD::SSUBSAT, MVT::v32i8, 1 },
2037 { ISD::UADDSAT, MVT::v16i16, 1 },
2038 { ISD::UADDSAT, MVT::v32i8, 1 },
2039 { ISD::UADDSAT, MVT::v8i32, 3 }, // not + pminud + paddd
2040 { ISD::USUBSAT, MVT::v16i16, 1 },
2041 { ISD::USUBSAT, MVT::v32i8, 1 },
2042 { ISD::USUBSAT, MVT::v8i32, 2 }, // pmaxud + psubd
2043 { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/
2044 { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/
2045 { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/
2046 { ISD::FSQRT, MVT::f64, 14 }, // Haswell from http://www.agner.org/
2047 { ISD::FSQRT, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/
2048 { ISD::FSQRT, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/
2049 };
2050 static const CostTblEntry AVX1CostTbl[] = {
2051 { ISD::BITREVERSE, MVT::v4i64, 12 }, // 2 x 128-bit Op + extract/insert
2052 { ISD::BITREVERSE, MVT::v8i32, 12 }, // 2 x 128-bit Op + extract/insert
2053 { ISD::BITREVERSE, MVT::v16i16, 12 }, // 2 x 128-bit Op + extract/insert
2054 { ISD::BITREVERSE, MVT::v32i8, 12 }, // 2 x 128-bit Op + extract/insert
2055 { ISD::BSWAP, MVT::v4i64, 4 },
2056 { ISD::BSWAP, MVT::v8i32, 4 },
2057 { ISD::BSWAP, MVT::v16i16, 4 },
2058 { ISD::CTLZ, MVT::v4i64, 48 }, // 2 x 128-bit Op + extract/insert
2059 { ISD::CTLZ, MVT::v8i32, 38 }, // 2 x 128-bit Op + extract/insert
2060 { ISD::CTLZ, MVT::v16i16, 30 }, // 2 x 128-bit Op + extract/insert
2061 { ISD::CTLZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert
2062 { ISD::CTPOP, MVT::v4i64, 16 }, // 2 x 128-bit Op + extract/insert
2063 { ISD::CTPOP, MVT::v8i32, 24 }, // 2 x 128-bit Op + extract/insert
2064 { ISD::CTPOP, MVT::v16i16, 20 }, // 2 x 128-bit Op + extract/insert
2065 { ISD::CTPOP, MVT::v32i8, 14 }, // 2 x 128-bit Op + extract/insert
2066 { ISD::CTTZ, MVT::v4i64, 22 }, // 2 x 128-bit Op + extract/insert
2067 { ISD::CTTZ, MVT::v8i32, 30 }, // 2 x 128-bit Op + extract/insert
2068 { ISD::CTTZ, MVT::v16i16, 26 }, // 2 x 128-bit Op + extract/insert
2069 { ISD::CTTZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert
2070 { ISD::SADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert
2071 { ISD::SADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert
2072 { ISD::SSUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert
2073 { ISD::SSUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert
2074 { ISD::UADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert
2075 { ISD::UADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert
2076 { ISD::UADDSAT, MVT::v8i32, 8 }, // 2 x 128-bit Op + extract/insert
2077 { ISD::USUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert
2078 { ISD::USUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert
2079 { ISD::USUBSAT, MVT::v8i32, 6 }, // 2 x 128-bit Op + extract/insert
2080 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/
2081 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/
2082 { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/
2083 { ISD::FSQRT, MVT::f64, 21 }, // SNB from http://www.agner.org/
2084 { ISD::FSQRT, MVT::v2f64, 21 }, // SNB from http://www.agner.org/
2085 { ISD::FSQRT, MVT::v4f64, 43 }, // SNB from http://www.agner.org/
2086 };
2087 static const CostTblEntry GLMCostTbl[] = {
2088 { ISD::FSQRT, MVT::f32, 19 }, // sqrtss
2089 { ISD::FSQRT, MVT::v4f32, 37 }, // sqrtps
2090 { ISD::FSQRT, MVT::f64, 34 }, // sqrtsd
2091 { ISD::FSQRT, MVT::v2f64, 67 }, // sqrtpd
2092 };
2093 static const CostTblEntry SLMCostTbl[] = {
2094 { ISD::FSQRT, MVT::f32, 20 }, // sqrtss
2095 { ISD::FSQRT, MVT::v4f32, 40 }, // sqrtps
2096 { ISD::FSQRT, MVT::f64, 35 }, // sqrtsd
2097 { ISD::FSQRT, MVT::v2f64, 70 }, // sqrtpd
2098 };
2099 static const CostTblEntry SSE42CostTbl[] = {
2100 { ISD::USUBSAT, MVT::v4i32, 2 }, // pmaxud + psubd
2101 { ISD::UADDSAT, MVT::v4i32, 3 }, // not + pminud + paddd
2102 { ISD::FSQRT, MVT::f32, 18 }, // Nehalem from http://www.agner.org/
2103 { ISD::FSQRT, MVT::v4f32, 18 }, // Nehalem from http://www.agner.org/
2104 };
2105 static const CostTblEntry SSSE3CostTbl[] = {
2106 { ISD::BITREVERSE, MVT::v2i64, 5 },
2107 { ISD::BITREVERSE, MVT::v4i32, 5 },
2108 { ISD::BITREVERSE, MVT::v8i16, 5 },
2109 { ISD::BITREVERSE, MVT::v16i8, 5 },
2110 { ISD::BSWAP, MVT::v2i64, 1 },
2111 { ISD::BSWAP, MVT::v4i32, 1 },
2112 { ISD::BSWAP, MVT::v8i16, 1 },
2113 { ISD::CTLZ, MVT::v2i64, 23 },
2114 { ISD::CTLZ, MVT::v4i32, 18 },
2115 { ISD::CTLZ, MVT::v8i16, 14 },
2116 { ISD::CTLZ, MVT::v16i8, 9 },
2117 { ISD::CTPOP, MVT::v2i64, 7 },
2118 { ISD::CTPOP, MVT::v4i32, 11 },
2119 { ISD::CTPOP, MVT::v8i16, 9 },
2120 { ISD::CTPOP, MVT::v16i8, 6 },
2121 { ISD::CTTZ, MVT::v2i64, 10 },
2122 { ISD::CTTZ, MVT::v4i32, 14 },
2123 { ISD::CTTZ, MVT::v8i16, 12 },
2124 { ISD::CTTZ, MVT::v16i8, 9 }
2125 };
2126 static const CostTblEntry SSE2CostTbl[] = {
2127 { ISD::BITREVERSE, MVT::v2i64, 29 },
2128 { ISD::BITREVERSE, MVT::v4i32, 27 },
2129 { ISD::BITREVERSE, MVT::v8i16, 27 },
2130 { ISD::BITREVERSE, MVT::v16i8, 20 },
2131 { ISD::BSWAP, MVT::v2i64, 7 },
2132 { ISD::BSWAP, MVT::v4i32, 7 },
2133 { ISD::BSWAP, MVT::v8i16, 7 },
2134 { ISD::CTLZ, MVT::v2i64, 25 },
2135 { ISD::CTLZ, MVT::v4i32, 26 },
2136 { ISD::CTLZ, MVT::v8i16, 20 },
2137 { ISD::CTLZ, MVT::v16i8, 17 },
2138 { ISD::CTPOP, MVT::v2i64, 12 },
2139 { ISD::CTPOP, MVT::v4i32, 15 },
2140 { ISD::CTPOP, MVT::v8i16, 13 },
2141 { ISD::CTPOP, MVT::v16i8, 10 },
2142 { ISD::CTTZ, MVT::v2i64, 14 },
2143 { ISD::CTTZ, MVT::v4i32, 18 },
2144 { ISD::CTTZ, MVT::v8i16, 16 },
2145 { ISD::CTTZ, MVT::v16i8, 13 },
2146 { ISD::SADDSAT, MVT::v8i16, 1 },
2147 { ISD::SADDSAT, MVT::v16i8, 1 },
2148 { ISD::SSUBSAT, MVT::v8i16, 1 },
2149 { ISD::SSUBSAT, MVT::v16i8, 1 },
2150 { ISD::UADDSAT, MVT::v8i16, 1 },
2151 { ISD::UADDSAT, MVT::v16i8, 1 },
2152 { ISD::USUBSAT, MVT::v8i16, 1 },
2153 { ISD::USUBSAT, MVT::v16i8, 1 },
2154 { ISD::FSQRT, MVT::f64, 32 }, // Nehalem from http://www.agner.org/
2155 { ISD::FSQRT, MVT::v2f64, 32 }, // Nehalem from http://www.agner.org/
2156 };
2157 static const CostTblEntry SSE1CostTbl[] = {
2158 { ISD::FSQRT, MVT::f32, 28 }, // Pentium III from http://www.agner.org/
2159 { ISD::FSQRT, MVT::v4f32, 56 }, // Pentium III from http://www.agner.org/
2160 };
2161 static const CostTblEntry X64CostTbl[] = { // 64-bit targets
2162 { ISD::BITREVERSE, MVT::i64, 14 },
2163 { ISD::SADDO, MVT::i64, 1 },
2164 { ISD::UADDO, MVT::i64, 1 },
2165 };
2166 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets
2167 { ISD::BITREVERSE, MVT::i32, 14 },
2168 { ISD::BITREVERSE, MVT::i16, 14 },
2169 { ISD::BITREVERSE, MVT::i8, 11 },
2170 { ISD::SADDO, MVT::i32, 1 },
2171 { ISD::SADDO, MVT::i16, 1 },
2172 { ISD::SADDO, MVT::i8, 1 },
2173 { ISD::UADDO, MVT::i32, 1 },
2174 { ISD::UADDO, MVT::i16, 1 },
2175 { ISD::UADDO, MVT::i8, 1 },
2176 };
2177
2178 Type *OpTy = RetTy;
2179 unsigned ISD = ISD::DELETED_NODE;
2180 switch (IID) {
2181 default:
2182 break;
2183 case Intrinsic::bitreverse:
2184 ISD = ISD::BITREVERSE;
2185 break;
2186 case Intrinsic::bswap:
2187 ISD = ISD::BSWAP;
2188 break;
2189 case Intrinsic::ctlz:
2190 ISD = ISD::CTLZ;
2191 break;
2192 case Intrinsic::ctpop:
2193 ISD = ISD::CTPOP;
2194 break;
2195 case Intrinsic::cttz:
2196 ISD = ISD::CTTZ;
2197 break;
2198 case Intrinsic::sadd_sat:
2199 ISD = ISD::SADDSAT;
2200 break;
2201 case Intrinsic::ssub_sat:
2202 ISD = ISD::SSUBSAT;
2203 break;
2204 case Intrinsic::uadd_sat:
2205 ISD = ISD::UADDSAT;
2206 break;
2207 case Intrinsic::usub_sat:
2208 ISD = ISD::USUBSAT;
2209 break;
2210 case Intrinsic::sqrt:
2211 ISD = ISD::FSQRT;
2212 break;
2213 case Intrinsic::sadd_with_overflow:
2214 case Intrinsic::ssub_with_overflow:
2215 // SSUBO has same costs so don't duplicate.
2216 ISD = ISD::SADDO;
2217 OpTy = RetTy->getContainedType(0);
2218 break;
2219 case Intrinsic::uadd_with_overflow:
2220 case Intrinsic::usub_with_overflow:
2221 // USUBO has same costs so don't duplicate.
2222 ISD = ISD::UADDO;
2223 OpTy = RetTy->getContainedType(0);
2224 break;
2225 }
2226
2227 if (ISD != ISD::DELETED_NODE) {
2228 // Legalize the type.
2229 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, OpTy);
2230 MVT MTy = LT.second;
2231
2232 // Attempt to lookup cost.
2233 if (ST->isGLM())
2234 if (const auto *Entry = CostTableLookup(GLMCostTbl, ISD, MTy))
2235 return LT.first * Entry->Cost;
2236
2237 if (ST->isSLM())
2238 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy))
2239 return LT.first * Entry->Cost;
2240
2241 if (ST->hasCDI())
2242 if (const auto *Entry = CostTableLookup(AVX512CDCostTbl, ISD, MTy))
2243 return LT.first * Entry->Cost;
2244
2245 if (ST->hasBWI())
2246 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy))
2247 return LT.first * Entry->Cost;
2248
2249 if (ST->hasAVX512())
2250 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy))
2251 return LT.first * Entry->Cost;
2252
2253 if (ST->hasXOP())
2254 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy))
2255 return LT.first * Entry->Cost;
2256
2257 if (ST->hasAVX2())
2258 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy))
2259 return LT.first * Entry->Cost;
2260
2261 if (ST->hasAVX())
2262 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy))
2263 return LT.first * Entry->Cost;
2264
2265 if (ST->hasSSE42())
2266 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy))
2267 return LT.first * Entry->Cost;
2268
2269 if (ST->hasSSSE3())
2270 if (const auto *Entry = CostTableLookup(SSSE3CostTbl, ISD, MTy))
2271 return LT.first * Entry->Cost;
2272
2273 if (ST->hasSSE2())
2274 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy))
2275 return LT.first * Entry->Cost;
2276
2277 if (ST->hasSSE1())
2278 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy))
2279 return LT.first * Entry->Cost;
2280
2281 if (ST->is64Bit())
2282 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy))
2283 return LT.first * Entry->Cost;
2284
2285 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy))
2286 return LT.first * Entry->Cost;
2287 }
2288
2289 return BaseT::getIntrinsicInstrCost(IID, RetTy, Tys, FMF, ScalarizationCostPassed);
2290 }
2291
2292 int X86TTIImpl::getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy,
2293 ArrayRef<Value *> Args, FastMathFlags FMF,
2294 unsigned VF) {
2295 static const CostTblEntry AVX512CostTbl[] = {
2296 { ISD::ROTL, MVT::v8i64, 1 },
2297 { ISD::ROTL, MVT::v4i64, 1 },
2298 { ISD::ROTL, MVT::v2i64, 1 },
2299 { ISD::ROTL, MVT::v16i32, 1 },
2300 { ISD::ROTL, MVT::v8i32, 1 },
2301 { ISD::ROTL, MVT::v4i32, 1 },
2302 { ISD::ROTR, MVT::v8i64, 1 },
2303 { ISD::ROTR, MVT::v4i64, 1 },
2304 { ISD::ROTR, MVT::v2i64, 1 },
2305 { ISD::ROTR, MVT::v16i32, 1 },
2306 { ISD::ROTR, MVT::v8i32, 1 },
2307 { ISD::ROTR, MVT::v4i32, 1 }
2308 };
2309 // XOP: ROTL = VPROT(X,Y), ROTR = VPROT(X,SUB(0,Y))
2310 static const CostTblEntry XOPCostTbl[] = {
2311 { ISD::ROTL, MVT::v4i64, 4 },
2312 { ISD::ROTL, MVT::v8i32, 4 },
2313 { ISD::ROTL, MVT::v16i16, 4 },
2314 { ISD::ROTL, MVT::v32i8, 4 },
2315 { ISD::ROTL, MVT::v2i64, 1 },
2316 { ISD::ROTL, MVT::v4i32, 1 },
2317 { ISD::ROTL, MVT::v8i16, 1 },
2318 { ISD::ROTL, MVT::v16i8, 1 },
2319 { ISD::ROTR, MVT::v4i64, 6 },
2320 { ISD::ROTR, MVT::v8i32, 6 },
2321 { ISD::ROTR, MVT::v16i16, 6 },
2322 { ISD::ROTR, MVT::v32i8, 6 },
2323 { ISD::ROTR, MVT::v2i64, 2 },
2324 { ISD::ROTR, MVT::v4i32, 2 },
2325 { ISD::ROTR, MVT::v8i16, 2 },
2326 { ISD::ROTR, MVT::v16i8, 2 }
2327 };
2328 static const CostTblEntry X64CostTbl[] = { // 64-bit targets
2329 { ISD::ROTL, MVT::i64, 1 },
2330 { ISD::ROTR, MVT::i64, 1 },
2331 { ISD::FSHL, MVT::i64, 4 }
2332 };
2333 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets
2334 { ISD::ROTL, MVT::i32, 1 },
2335 { ISD::ROTL, MVT::i16, 1 },
2336 { ISD::ROTL, MVT::i8, 1 },
2337 { ISD::ROTR, MVT::i32, 1 },
2338 { ISD::ROTR, MVT::i16, 1 },
2339 { ISD::ROTR, MVT::i8, 1 },
2340 { ISD::FSHL, MVT::i32, 4 },
2341 { ISD::FSHL, MVT::i16, 4 },
2342 { ISD::FSHL, MVT::i8, 4 }
2343 };
2344
2345 unsigned ISD = ISD::DELETED_NODE;
2346 switch (IID) {
2347 default:
2348 break;
2349 case Intrinsic::fshl:
2350 ISD = ISD::FSHL;
2351 if (Args[0] == Args[1])
2352 ISD = ISD::ROTL;
2353 break;
2354 case Intrinsic::fshr:
2355 // FSHR has same costs so don't duplicate.
2356 ISD = ISD::FSHL;
2357 if (Args[0] == Args[1])
2358 ISD = ISD::ROTR;
2359 break;
2360 }
2361
2362 if (ISD != ISD::DELETED_NODE) {
2363 // Legalize the type.
2364 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, RetTy);
2365 MVT MTy = LT.second;
2366
2367 // Attempt to lookup cost.
2368 if (ST->hasAVX512())
2369 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy))
2370 return LT.first * Entry->Cost;
2371
2372 if (ST->hasXOP())
2373 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy))
2374 return LT.first * Entry->Cost;
2375
2376 if (ST->is64Bit())
2377 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy))
2378 return LT.first * Entry->Cost;
2379
2380 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy))
2381 return LT.first * Entry->Cost;
2382 }
2383
2384 return BaseT::getIntrinsicInstrCost(IID, RetTy, Args, FMF, VF);
2385 }
2386
2387 int X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) {
2388 assert(Val->isVectorTy() && "This must be a vector type");
2389
2390 Type *ScalarType = Val->getScalarType();
2391
2392 if (Index != -1U) {
2393 // Legalize the type.
2394 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Val);
2395
2396 // This type is legalized to a scalar type.
2397 if (!LT.second.isVector())
2398 return 0;
2399
2400 // The type may be split. Normalize the index to the new type.
2401 unsigned Width = LT.second.getVectorNumElements();
2402 Index = Index % Width;
2403
2404 // Floating point scalars are already located in index #0.
2405 if (ScalarType->isFloatingPointTy() && Index == 0)
2406 return 0;
2407 }
2408
2409 // Add to the base cost if we know that the extracted element of a vector is
2410 // destined to be moved to and used in the integer register file.
2411 int RegisterFileMoveCost = 0;
2412 if (Opcode == Instruction::ExtractElement && ScalarType->isPointerTy())
2413 RegisterFileMoveCost = 1;
2414
2415 return BaseT::getVectorInstrCost(Opcode, Val, Index) + RegisterFileMoveCost;
2416 }
2417
2418 int X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
2419 unsigned AddressSpace, const Instruction *I) {
2420 // Handle non-power-of-two vectors such as <3 x float>
2421 if (VectorType *VTy = dyn_cast<VectorType>(Src)) {
2422 unsigned NumElem = VTy->getVectorNumElements();
2423
2424 // Handle a few common cases:
2425 // <3 x float>
2426 if (NumElem == 3 && VTy->getScalarSizeInBits() == 32)
2427 // Cost = 64 bit store + extract + 32 bit store.
2428 return 3;
2429
2430 // <3 x double>
2431 if (NumElem == 3 && VTy->getScalarSizeInBits() == 64)
2432 // Cost = 128 bit store + unpack + 64 bit store.
2433 return 3;
2434
2435 // Assume that all other non-power-of-two numbers are scalarized.
2436 if (!isPowerOf2_32(NumElem)) {
2437 int Cost = BaseT::getMemoryOpCost(Opcode, VTy->getScalarType(), Alignment,
2438 AddressSpace);
2439 int SplitCost = getScalarizationOverhead(Src, Opcode == Instruction::Load,
2440 Opcode == Instruction::Store);
2441 return NumElem * Cost + SplitCost;
2442 }
2443 }
2444
2445 // Legalize the type.
2446 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src);
2447 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) &&
2448 "Invalid Opcode");
2449
2450 // Each load/store unit costs 1.
2451 int Cost = LT.first * 1;
2452
2453 // This isn't exactly right. We're using slow unaligned 32-byte accesses as a
2454 // proxy for a double-pumped AVX memory interface such as on Sandybridge.
2455 if (LT.second.getStoreSize() == 32 && ST->isUnalignedMem32Slow())
2456 Cost *= 2;
2457
2458 return Cost;
2459 }
2460
2461 int X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy,
2462 unsigned Alignment,
2463 unsigned AddressSpace) {
2464 bool IsLoad = (Instruction::Load == Opcode);
2465 bool IsStore = (Instruction::Store == Opcode);
2466
2467 VectorType *SrcVTy = dyn_cast<VectorType>(SrcTy);
2468 if (!SrcVTy)
2469 // To calculate scalar take the regular cost, without mask
2470 return getMemoryOpCost(Opcode, SrcTy, Alignment, AddressSpace);
2471
2472 unsigned NumElem = SrcVTy->getVectorNumElements();
2473 VectorType *MaskTy =
2474 VectorType::get(Type::getInt8Ty(SrcVTy->getContext()), NumElem);
2475 if ((IsLoad && !isLegalMaskedLoad(SrcVTy)) ||
2476 (IsStore && !isLegalMaskedStore(SrcVTy)) || !isPowerOf2_32(NumElem)) {
2477 // Scalarization
2478 int MaskSplitCost = getScalarizationOverhead(MaskTy, false, true);
2479 int ScalarCompareCost = getCmpSelInstrCost(
2480 Instruction::ICmp, Type::getInt8Ty(SrcVTy->getContext()), nullptr);
2481 int BranchCost = getCFInstrCost(Instruction::Br);
2482 int MaskCmpCost = NumElem * (BranchCost + ScalarCompareCost);
2483
2484 int ValueSplitCost = getScalarizationOverhead(SrcVTy, IsLoad, IsStore);
2485 int MemopCost =
2486 NumElem * BaseT::getMemoryOpCost(Opcode, SrcVTy->getScalarType(),
2487 Alignment, AddressSpace);
2488 return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost;
2489 }
2490
2491 // Legalize the type.
2492 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, SrcVTy);
2493 auto VT = TLI->getValueType(DL, SrcVTy);
2494 int Cost = 0;
2495 if (VT.isSimple() && LT.second != VT.getSimpleVT() &&
2496 LT.second.getVectorNumElements() == NumElem)
2497 // Promotion requires expand/truncate for data and a shuffle for mask.
2498 Cost += getShuffleCost(TTI::SK_PermuteTwoSrc, SrcVTy, 0, nullptr) +
2499 getShuffleCost(TTI::SK_PermuteTwoSrc, MaskTy, 0, nullptr);
2500
2501 else if (LT.second.getVectorNumElements() > NumElem) {
2502 VectorType *NewMaskTy = VectorType::get(MaskTy->getVectorElementType(),
2503 LT.second.getVectorNumElements());
2504 // Expanding requires fill mask with zeroes
2505 Cost += getShuffleCost(TTI::SK_InsertSubvector, NewMaskTy, 0, MaskTy);
2506 }
2507
2508 // Pre-AVX512 - each maskmov load costs 2 + store costs ~8.
2509 if (!ST->hasAVX512())
2510 return Cost + LT.first * (IsLoad ? 2 : 8);
2511
2512 // AVX-512 masked load/store is cheapper
2513 return Cost + LT.first;
2514 }
2515
2516 int X86TTIImpl::getAddressComputationCost(Type *Ty, ScalarEvolution *SE,
2517 const SCEV *Ptr) {
2518 // Address computations in vectorized code with non-consecutive addresses will
2519 // likely result in more instructions compared to scalar code where the
2520 // computation can more often be merged into the index mode. The resulting
2521 // extra micro-ops can significantly decrease throughput.
2522 const unsigned NumVectorInstToHideOverhead = 10;
2523
2524 // Cost modeling of Strided Access Computation is hidden by the indexing
2525 // modes of X86 regardless of the stride value. We dont believe that there
2526 // is a difference between constant strided access in gerenal and constant
2527 // strided value which is less than or equal to 64.
2528 // Even in the case of (loop invariant) stride whose value is not known at
2529 // compile time, the address computation will not incur more than one extra
2530 // ADD instruction.
2531 if (Ty->isVectorTy() && SE) {
2532 if (!BaseT::isStridedAccess(Ptr))
2533 return NumVectorInstToHideOverhead;
2534 if (!BaseT::getConstantStrideStep(SE, Ptr))
2535 return 1;
2536 }
2537
2538 return BaseT::getAddressComputationCost(Ty, SE, Ptr);
2539 }
2540
2541 int X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, Type *ValTy,
2542 bool IsPairwise) {
2543 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput
2544 // and make it as the cost.
2545
2546 static const CostTblEntry SSE42CostTblPairWise[] = {
2547 { ISD::FADD, MVT::v2f64, 2 },
2548 { ISD::FADD, MVT::v4f32, 4 },
2549 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6".
2550 { ISD::ADD, MVT::v2i32, 2 }, // FIXME: chosen to be less than v4i32.
2551 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.5".
2552 { ISD::ADD, MVT::v2i16, 3 }, // FIXME: chosen to be less than v4i16
2553 { ISD::ADD, MVT::v4i16, 4 }, // FIXME: chosen to be less than v8i16
2554 { ISD::ADD, MVT::v8i16, 5 },
2555 };
2556
2557 static const CostTblEntry AVX1CostTblPairWise[] = {
2558 { ISD::FADD, MVT::v4f32, 4 },
2559 { ISD::FADD, MVT::v4f64, 5 },
2560 { ISD::FADD, MVT::v8f32, 7 },
2561 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5".
2562 { ISD::ADD, MVT::v2i32, 2 }, // FIXME: chosen to be less than v4i32
2563 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.5".
2564 { ISD::ADD, MVT::v4i64, 5 }, // The data reported by the IACA tool is "4.8".
2565 { ISD::ADD, MVT::v2i16, 3 }, // FIXME: chosen to be less than v4i16
2566 { ISD::ADD, MVT::v4i16, 4 }, // FIXME: chosen to be less than v8i16
2567 { ISD::ADD, MVT::v8i16, 5 },
2568 { ISD::ADD, MVT::v8i32, 5 },
2569 };
2570
2571 static const CostTblEntry SSE42CostTblNoPairWise[] = {
2572 { ISD::FADD, MVT::v2f64, 2 },
2573 { ISD::FADD, MVT::v4f32, 4 },
2574 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6".
2575 { ISD::ADD, MVT::v2i32, 2 }, // FIXME: chosen to be less than v4i32
2576 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3".
2577 { ISD::ADD, MVT::v2i16, 2 }, // The data reported by the IACA tool is "4.3".
2578 { ISD::ADD, MVT::v4i16, 3 }, // The data reported by the IACA tool is "4.3".
2579 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3".
2580 };
2581
2582 static const CostTblEntry AVX1CostTblNoPairWise[] = {
2583 { ISD::FADD, MVT::v4f32, 3 },
2584 { ISD::FADD, MVT::v4f64, 3 },
2585 { ISD::FADD, MVT::v8f32, 4 },
2586 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5".
2587 { ISD::ADD, MVT::v2i32, 2 }, // FIXME: chosen to be less than v4i32
2588 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "2.8".
2589 { ISD::ADD, MVT::v4i64, 3 },
2590 { ISD::ADD, MVT::v2i16, 2 }, // The data reported by the IACA tool is "4.3".
2591 { ISD::ADD, MVT::v4i16, 3 }, // The data reported by the IACA tool is "4.3".
2592 { ISD::ADD, MVT::v8i16, 4 },
2593 { ISD::ADD, MVT::v8i32, 5 },
2594 };
2595
2596 int ISD = TLI->InstructionOpcodeToISD(Opcode);
2597 assert(ISD && "Invalid opcode");
2598
2599 // Before legalizing the type, give a chance to look up illegal narrow types
2600 // in the table.
2601 // FIXME: Is there a better way to do this?
2602 EVT VT = TLI->getValueType(DL, ValTy);
2603 if (VT.isSimple() && ExperimentalVectorWideningLegalization) {
2604 MVT MTy = VT.getSimpleVT();
2605 if (IsPairwise) {
2606 if (ST->hasAVX())
2607 if (const auto *Entry = CostTableLookup(AVX1CostTblPairWise, ISD, MTy))
2608 return Entry->Cost;
2609
2610 if (ST->hasSSE42())
2611 if (const auto *Entry = CostTableLookup(SSE42CostTblPairWise, ISD, MTy))
2612 return Entry->Cost;
2613 } else {
2614 if (ST->hasAVX())
2615 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy))
2616 return Entry->Cost;
2617
2618 if (ST->hasSSE42())
2619 if (const auto *Entry = CostTableLookup(SSE42CostTblNoPairWise, ISD, MTy))
2620 return Entry->Cost;
2621 }
2622 }
2623
2624 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy);
2625
2626 MVT MTy = LT.second;
2627
2628 if (IsPairwise) {
2629 if (ST->hasAVX())
2630 if (const auto *Entry = CostTableLookup(AVX1CostTblPairWise, ISD, MTy))
2631 return LT.first * Entry->Cost;
2632
2633 if (ST->hasSSE42())
2634 if (const auto *Entry = CostTableLookup(SSE42CostTblPairWise, ISD, MTy))
2635 return LT.first * Entry->Cost;
2636 } else {
2637 if (ST->hasAVX())
2638 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy))
2639 return LT.first * Entry->Cost;
2640
2641 if (ST->hasSSE42())
2642 if (const auto *Entry = CostTableLookup(SSE42CostTblNoPairWise, ISD, MTy))
2643 return LT.first * Entry->Cost;
2644 }
2645
2646 static const CostTblEntry AVX2BoolReduction[] = {
2647 { ISD::AND, MVT::v16i16, 2 }, // vpmovmskb + cmp
2648 { ISD::AND, MVT::v32i8, 2 }, // vpmovmskb + cmp
2649 { ISD::OR, MVT::v16i16, 2 }, // vpmovmskb + cmp
2650 { ISD::OR, MVT::v32i8, 2 }, // vpmovmskb + cmp
2651 };
2652
2653 static const CostTblEntry AVX1BoolReduction[] = {
2654 { ISD::AND, MVT::v4i64, 2 }, // vmovmskpd + cmp
2655 { ISD::AND, MVT::v8i32, 2 }, // vmovmskps + cmp
2656 { ISD::AND, MVT::v16i16, 4 }, // vextractf128 + vpand + vpmovmskb + cmp
2657 { ISD::AND, MVT::v32i8, 4 }, // vextractf128 + vpand + vpmovmskb + cmp
2658 { ISD::OR, MVT::v4i64, 2 }, // vmovmskpd + cmp
2659 { ISD::OR, MVT::v8i32, 2 }, // vmovmskps + cmp
2660 { ISD::OR, MVT::v16i16, 4 }, // vextractf128 + vpor + vpmovmskb + cmp
2661 { ISD::OR, MVT::v32i8, 4 }, // vextractf128 + vpor + vpmovmskb + cmp
2662 };
2663
2664 static const CostTblEntry SSE2BoolReduction[] = {
2665 { ISD::AND, MVT::v2i64, 2 }, // movmskpd + cmp
2666 { ISD::AND, MVT::v4i32, 2 }, // movmskps + cmp
2667 { ISD::AND, MVT::v8i16, 2 }, // pmovmskb + cmp
2668 { ISD::AND, MVT::v16i8, 2 }, // pmovmskb + cmp
2669 { ISD::OR, MVT::v2i64, 2 }, // movmskpd + cmp
2670 { ISD::OR, MVT::v4i32, 2 }, // movmskps + cmp
2671 { ISD::OR, MVT::v8i16, 2 }, // pmovmskb + cmp
2672 { ISD::OR, MVT::v16i8, 2 }, // pmovmskb + cmp
2673 };
2674
2675 // Handle bool allof/anyof patterns.
2676 if (ValTy->getVectorElementType()->isIntegerTy(1)) {
2677 if (ST->hasAVX2())
2678 if (const auto *Entry = CostTableLookup(AVX2BoolReduction, ISD, MTy))
2679 return LT.first * Entry->Cost;
2680 if (ST->hasAVX())
2681 if (const auto *Entry = CostTableLookup(AVX1BoolReduction, ISD, MTy))
2682 return LT.first * Entry->Cost;
2683 if (ST->hasSSE2())
2684 if (const auto *Entry = CostTableLookup(SSE2BoolReduction, ISD, MTy))
2685 return LT.first * Entry->Cost;
2686 }
2687
2688 return BaseT::getArithmeticReductionCost(Opcode, ValTy, IsPairwise);
2689 }
2690
2691 int X86TTIImpl::getMinMaxReductionCost(Type *ValTy, Type *CondTy,
2692 bool IsPairwise, bool IsUnsigned) {
2693 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy);
2694
2695 MVT MTy = LT.second;
2696
2697 int ISD;
2698 if (ValTy->isIntOrIntVectorTy()) {
2699 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN;
2700 } else {
2701 assert(ValTy->isFPOrFPVectorTy() &&
2702 "Expected float point or integer vector type.");
2703 ISD = ISD::FMINNUM;
2704 }
2705
2706 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput
2707 // and make it as the cost.
2708
2709 static const CostTblEntry SSE1CostTblPairWise[] = {
2710 {ISD::FMINNUM, MVT::v4f32, 4},
2711 };
2712
2713 static const CostTblEntry SSE2CostTblPairWise[] = {
2714 {ISD::FMINNUM, MVT::v2f64, 3},
2715 {ISD::SMIN, MVT::v2i64, 6},
2716 {ISD::UMIN, MVT::v2i64, 8},
2717 {ISD::SMIN, MVT::v4i32, 6},
2718 {ISD::UMIN, MVT::v4i32, 8},
2719 {ISD::SMIN, MVT::v8i16, 4},
2720 {ISD::UMIN, MVT::v8i16, 6},
2721 {ISD::SMIN, MVT::v16i8, 8},
2722 {ISD::UMIN, MVT::v16i8, 6},
2723 };
2724
2725 static const CostTblEntry SSE41CostTblPairWise[] = {
2726 {ISD::FMINNUM, MVT::v4f32, 2},
2727 {ISD::SMIN, MVT::v2i64, 9},
2728 {ISD::UMIN, MVT::v2i64,10},
2729 {ISD::SMIN, MVT::v4i32, 1}, // The data reported by the IACA is "1.5"
2730 {ISD::UMIN, MVT::v4i32, 2}, // The data reported by the IACA is "1.8"
2731 {ISD::SMIN, MVT::v8i16, 2},
2732 {ISD::UMIN, MVT::v8i16, 2},
2733 {ISD::SMIN, MVT::v16i8, 3},
2734 {ISD::UMIN, MVT::v16i8, 3},
2735 };
2736
2737 static const CostTblEntry SSE42CostTblPairWise[] = {
2738 {ISD::SMIN, MVT::v2i64, 7}, // The data reported by the IACA is "6.8"
2739 {ISD::UMIN, MVT::v2i64, 8}, // The data reported by the IACA is "8.6"
2740 };
2741
2742 static const CostTblEntry AVX1CostTblPairWise[] = {
2743 {ISD::FMINNUM, MVT::v4f32, 1},
2744 {ISD::FMINNUM, MVT::v4f64, 1},
2745 {ISD::FMINNUM, MVT::v8f32, 2},
2746 {ISD::SMIN, MVT::v2i64, 3},
2747 {ISD::UMIN, MVT::v2i64, 3},
2748 {ISD::SMIN, MVT::v4i32, 1},
2749 {ISD::UMIN, MVT::v4i32, 1},
2750 {ISD::SMIN, MVT::v8i16, 1},
2751 {ISD::UMIN, MVT::v8i16, 1},
2752 {ISD::SMIN, MVT::v16i8, 2},
2753 {ISD::UMIN, MVT::v16i8, 2},
2754 {ISD::SMIN, MVT::v4i64, 7},
2755 {ISD::UMIN, MVT::v4i64, 7},
2756 {ISD::SMIN, MVT::v8i32, 3},
2757 {ISD::UMIN, MVT::v8i32, 3},
2758 {ISD::SMIN, MVT::v16i16, 3},
2759 {ISD::UMIN, MVT::v16i16, 3},
2760 {ISD::SMIN, MVT::v32i8, 3},
2761 {ISD::UMIN, MVT::v32i8, 3},
2762 };
2763
2764 static const CostTblEntry AVX2CostTblPairWise[] = {
2765 {ISD::SMIN, MVT::v4i64, 2},
2766 {ISD::UMIN, MVT::v4i64, 2},
2767 {ISD::SMIN, MVT::v8i32, 1},
2768 {ISD::UMIN, MVT::v8i32, 1},
2769 {ISD::SMIN, MVT::v16i16, 1},
2770 {ISD::UMIN, MVT::v16i16, 1},
2771 {ISD::SMIN, MVT::v32i8, 2},
2772 {ISD::UMIN, MVT::v32i8, 2},
2773 };
2774
2775 static const CostTblEntry AVX512CostTblPairWise[] = {
2776 {ISD::FMINNUM, MVT::v8f64, 1},
2777 {ISD::FMINNUM, MVT::v16f32, 2},
2778 {ISD::SMIN, MVT::v8i64, 2},
2779 {ISD::UMIN, MVT::v8i64, 2},
2780 {ISD::SMIN, MVT::v16i32, 1},
2781 {ISD::UMIN, MVT::v16i32, 1},
2782 };
2783
2784 static const CostTblEntry SSE1CostTblNoPairWise[] = {
2785 {ISD::FMINNUM, MVT::v4f32, 4},
2786 };
2787
2788 static const CostTblEntry SSE2CostTblNoPairWise[] = {
2789 {ISD::FMINNUM, MVT::v2f64, 3},
2790 {ISD::SMIN, MVT::v2i64, 6},
2791 {ISD::UMIN, MVT::v2i64, 8},
2792 {ISD::SMIN, MVT::v4i32, 6},
2793 {ISD::UMIN, MVT::v4i32, 8},
2794 {ISD::SMIN, MVT::v8i16, 4},
2795 {ISD::UMIN, MVT::v8i16, 6},
2796 {ISD::SMIN, MVT::v16i8, 8},
2797 {ISD::UMIN, MVT::v16i8, 6},
2798 };
2799
2800 static const CostTblEntry SSE41CostTblNoPairWise[] = {
2801 {ISD::FMINNUM, MVT::v4f32, 3},
2802 {ISD::SMIN, MVT::v2i64, 9},
2803 {ISD::UMIN, MVT::v2i64,11},
2804 {ISD::SMIN, MVT::v4i32, 1}, // The data reported by the IACA is "1.5"
2805 {ISD::UMIN, MVT::v4i32, 2}, // The data reported by the IACA is "1.8"
2806 {ISD::SMIN, MVT::v8i16, 1}, // The data reported by the IACA is "1.5"
2807 {ISD::UMIN, MVT::v8i16, 2}, // The data reported by the IACA is "1.8"
2808 {ISD::SMIN, MVT::v16i8, 3},
2809 {ISD::UMIN, MVT::v16i8, 3},
2810 };
2811
2812 static const CostTblEntry SSE42CostTblNoPairWise[] = {
2813 {ISD::SMIN, MVT::v2i64, 7}, // The data reported by the IACA is "6.8"
2814 {ISD::UMIN, MVT::v2i64, 9}, // The data reported by the IACA is "8.6"
2815 };
2816
2817 static const CostTblEntry AVX1CostTblNoPairWise[] = {
2818 {ISD::FMINNUM, MVT::v4f32, 1},
2819 {ISD::FMINNUM, MVT::v4f64, 1},
2820 {ISD::FMINNUM, MVT::v8f32, 1},
2821 {ISD::SMIN, MVT::v2i64, 3},
2822 {ISD::UMIN, MVT::v2i64, 3},
2823 {ISD::SMIN, MVT::v4i32, 1},
2824 {ISD::UMIN, MVT::v4i32, 1},
2825 {ISD::SMIN, MVT::v8i16, 1},
2826 {ISD::UMIN, MVT::v8i16, 1},
2827 {ISD::SMIN, MVT::v16i8, 2},
2828 {ISD::UMIN, MVT::v16i8, 2},
2829 {ISD::SMIN, MVT::v4i64, 7},
2830 {ISD::UMIN, MVT::v4i64, 7},
2831 {ISD::SMIN, MVT::v8i32, 2},
2832 {ISD::UMIN, MVT::v8i32, 2},
2833 {ISD::SMIN, MVT::v16i16, 2},
2834 {ISD::UMIN, MVT::v16i16, 2},
2835 {ISD::SMIN, MVT::v32i8, 2},
2836 {ISD::UMIN, MVT::v32i8, 2},
2837 };
2838
2839 static const CostTblEntry AVX2CostTblNoPairWise[] = {
2840 {ISD::SMIN, MVT::v4i64, 1},
2841 {ISD::UMIN, MVT::v4i64, 1},
2842 {ISD::SMIN, MVT::v8i32, 1},
2843 {ISD::UMIN, MVT::v8i32, 1},
2844 {ISD::SMIN, MVT::v16i16, 1},
2845 {ISD::UMIN, MVT::v16i16, 1},
2846 {ISD::SMIN, MVT::v32i8, 1},
2847 {ISD::UMIN, MVT::v32i8, 1},
2848 };
2849
2850 static const CostTblEntry AVX512CostTblNoPairWise[] = {
2851 {ISD::FMINNUM, MVT::v8f64, 1},
2852 {ISD::FMINNUM, MVT::v16f32, 2},
2853 {ISD::SMIN, MVT::v8i64, 1},
2854 {ISD::UMIN, MVT::v8i64, 1},
2855 {ISD::SMIN, MVT::v16i32, 1},
2856 {ISD::UMIN, MVT::v16i32, 1},
2857 };
2858
2859 if (IsPairwise) {
2860 if (ST->hasAVX512())
2861 if (const auto *Entry = CostTableLookup(AVX512CostTblPairWise, ISD, MTy))
2862 return LT.first * Entry->Cost;
2863
2864 if (ST->hasAVX2())
2865 if (const auto *Entry = CostTableLookup(AVX2CostTblPairWise, ISD, MTy))
2866 return LT.first * Entry->Cost;
2867
2868 if (ST->hasAVX())
2869 if (const auto *Entry = CostTableLookup(AVX1CostTblPairWise, ISD, MTy))
2870 return LT.first * Entry->Cost;
2871
2872 if (ST->hasSSE42())
2873 if (const auto *Entry = CostTableLookup(SSE42CostTblPairWise, ISD, MTy))
2874 return LT.first * Entry->Cost;
2875
2876 if (ST->hasSSE41())
2877 if (const auto *Entry = CostTableLookup(SSE41CostTblPairWise, ISD, MTy))
2878 return LT.first * Entry->Cost;
2879
2880 if (ST->hasSSE2())
2881 if (const auto *Entry = CostTableLookup(SSE2CostTblPairWise, ISD, MTy))
2882 return LT.first * Entry->Cost;
2883
2884 if (ST->hasSSE1())
2885 if (const auto *Entry = CostTableLookup(SSE1CostTblPairWise, ISD, MTy))
2886 return LT.first * Entry->Cost;
2887 } else {
2888 if (ST->hasAVX512())
2889 if (const auto *Entry =
2890 CostTableLookup(AVX512CostTblNoPairWise, ISD, MTy))
2891 return LT.first * Entry->Cost;
2892
2893 if (ST->hasAVX2())
2894 if (const auto *Entry = CostTableLookup(AVX2CostTblNoPairWise, ISD, MTy))
2895 return LT.first * Entry->Cost;
2896
2897 if (ST->hasAVX())
2898 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy))
2899 return LT.first * Entry->Cost;
2900
2901 if (ST->hasSSE42())
2902 if (const auto *Entry = CostTableLookup(SSE42CostTblNoPairWise, ISD, MTy))
2903 return LT.first * Entry->Cost;
2904
2905 if (ST->hasSSE41())
2906 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy))
2907 return LT.first * Entry->Cost;
2908
2909 if (ST->hasSSE2())
2910 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy))
2911 return LT.first * Entry->Cost;
2912
2913 if (ST->hasSSE1())
2914 if (const auto *Entry = CostTableLookup(SSE1CostTblNoPairWise, ISD, MTy))
2915 return LT.first * Entry->Cost;
2916 }
2917
2918 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned);
2919 }
2920
2921 /// Calculate the cost of materializing a 64-bit value. This helper
2922 /// method might only calculate a fraction of a larger immediate. Therefore it
2923 /// is valid to return a cost of ZERO.
2924 int X86TTIImpl::getIntImmCost(int64_t Val) {
2925 if (Val == 0)
2926 return TTI::TCC_Free;
2927
2928 if (isInt<32>(Val))
2929 return TTI::TCC_Basic;
2930
2931 return 2 * TTI::TCC_Basic;
2932 }
2933
2934 int X86TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) {
2935 assert(Ty->isIntegerTy());
2936
2937 unsigned BitSize = Ty->getPrimitiveSizeInBits();
2938 if (BitSize == 0)
2939 return ~0U;
2940
2941 // Never hoist constants larger than 128bit, because this might lead to
2942 // incorrect code generation or assertions in codegen.
2943 // Fixme: Create a cost model for types larger than i128 once the codegen
2944 // issues have been fixed.
2945 if (BitSize > 128)
2946 return TTI::TCC_Free;
2947
2948 if (Imm == 0)
2949 return TTI::TCC_Free;
2950
2951 // Sign-extend all constants to a multiple of 64-bit.
2952 APInt ImmVal = Imm;
2953 if (BitSize % 64 != 0)
2954 ImmVal = Imm.sext(alignTo(BitSize, 64));
2955
2956 // Split the constant into 64-bit chunks and calculate the cost for each
2957 // chunk.
2958 int Cost = 0;
2959 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) {
2960 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64);
2961 int64_t Val = Tmp.getSExtValue();
2962 Cost += getIntImmCost(Val);
2963 }
2964 // We need at least one instruction to materialize the constant.
2965 return std::max(1, Cost);
2966 }
2967
2968 int X86TTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
2969 Type *Ty) {
2970 assert(Ty->isIntegerTy());
2971
2972 unsigned BitSize = Ty->getPrimitiveSizeInBits();
2973 // There is no cost model for constants with a bit size of 0. Return TCC_Free
2974 // here, so that constant hoisting will ignore this constant.
2975 if (BitSize == 0)
2976 return TTI::TCC_Free;
2977
2978 unsigned ImmIdx = ~0U;
2979 switch (Opcode) {
2980 default:
2981 return TTI::TCC_Free;
2982 case Instruction::GetElementPtr:
2983 // Always hoist the base address of a GetElementPtr. This prevents the
2984 // creation of new constants for every base constant that gets constant
2985 // folded with the offset.
2986 if (Idx == 0)
2987 return 2 * TTI::TCC_Basic;
2988 return TTI::TCC_Free;
2989 case Instruction::Store:
2990 ImmIdx = 0;
2991 break;
2992 case Instruction::ICmp:
2993 // This is an imperfect hack to prevent constant hoisting of
2994 // compares that might be trying to check if a 64-bit value fits in
2995 // 32-bits. The backend can optimize these cases using a right shift by 32.
2996 // Ideally we would check the compare predicate here. There also other
2997 // similar immediates the backend can use shifts for.
2998 if (Idx == 1 && Imm.getBitWidth() == 64) {
2999 uint64_t ImmVal = Imm.getZExtValue();
3000 if (ImmVal == 0x100000000ULL || ImmVal == 0xffffffff)
3001 return TTI::TCC_Free;
3002 }
3003 ImmIdx = 1;
3004 break;
3005 case Instruction::And:
3006 // We support 64-bit ANDs with immediates with 32-bits of leading zeroes
3007 // by using a 32-bit operation with implicit zero extension. Detect such
3008 // immediates here as the normal path expects bit 31 to be sign extended.
3009 if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32>(Imm.getZExtValue()))
3010 return TTI::TCC_Free;
3011 ImmIdx = 1;
3012 break;
3013 case Instruction::Add:
3014 case Instruction::Sub:
3015 // For add/sub, we can use the opposite instruction for INT32_MIN.
3016 if (Idx == 1 && Imm.getBitWidth() == 64 && Imm.getZExtValue() == 0x80000000)
3017 return TTI::TCC_Free;
3018 ImmIdx = 1;
3019 break;
3020 case Instruction::UDiv:
3021 case Instruction::SDiv:
3022 case Instruction::URem:
3023 case Instruction::SRem:
3024 // Division by constant is typically expanded later into a different
3025 // instruction sequence. This completely changes the constants.
3026 // Report them as "free" to stop ConstantHoist from marking them as opaque.
3027 return TTI::TCC_Free;
3028 case Instruction::Mul:
3029 case Instruction::Or:
3030 case Instruction::Xor:
3031 ImmIdx = 1;
3032 break;
3033 // Always return TCC_Free for the shift value of a shift instruction.
3034 case Instruction::Shl:
3035 case Instruction::LShr:
3036 case Instruction::AShr:
3037 if (Idx == 1)
3038 return TTI::TCC_Free;
3039 break;
3040 case Instruction::Trunc:
3041 case Instruction::ZExt:
3042 case Instruction::SExt:
3043 case Instruction::IntToPtr:
3044 case Instruction::PtrToInt:
3045 case Instruction::BitCast:
3046 case Instruction::PHI:
3047 case Instruction::Call:
3048 case Instruction::Select:
3049 case Instruction::Ret:
3050 case Instruction::Load:
3051 break;
3052 }
3053
3054 if (Idx == ImmIdx) {
3055 int NumConstants = divideCeil(BitSize, 64);
3056 int Cost = X86TTIImpl::getIntImmCost(Imm, Ty);
3057 return (Cost <= NumConstants * TTI::TCC_Basic)
3058 ? static_cast<int>(TTI::TCC_Free)
3059 : Cost;
3060 }
3061
3062 return X86TTIImpl::getIntImmCost(Imm, Ty);
3063 }
3064
3065 int X86TTIImpl::getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
3066 Type *Ty) {
3067 assert(Ty->isIntegerTy());
3068
3069 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3070 // There is no cost model for constants with a bit size of 0. Return TCC_Free
3071 // here, so that constant hoisting will ignore this constant.
3072 if (BitSize == 0)
3073 return TTI::TCC_Free;
3074
3075 switch (IID) {
3076 default:
3077 return TTI::TCC_Free;
3078 case Intrinsic::sadd_with_overflow:
3079 case Intrinsic::uadd_with_overflow:
3080 case Intrinsic::ssub_with_overflow:
3081 case Intrinsic::usub_with_overflow:
3082 case Intrinsic::smul_with_overflow:
3083 case Intrinsic::umul_with_overflow:
3084 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue()))
3085 return TTI::TCC_Free;
3086 break;
3087 case Intrinsic::experimental_stackmap:
3088 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
3089 return TTI::TCC_Free;
3090 break;
3091 case Intrinsic::experimental_patchpoint_void:
3092 case Intrinsic::experimental_patchpoint_i64:
3093 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
3094 return TTI::TCC_Free;
3095 break;
3096 }
3097 return X86TTIImpl::getIntImmCost(Imm, Ty);
3098 }
3099
3100 unsigned X86TTIImpl::getUserCost(const User *U,
3101 ArrayRef<const Value *> Operands) {
3102 if (isa<StoreInst>(U)) {
3103 Value *Ptr = U->getOperand(1);
3104 // Store instruction with index and scale costs 2 Uops.
3105 // Check the preceding GEP to identify non-const indices.
3106 if (auto GEP = dyn_cast<GetElementPtrInst>(Ptr)) {
3107 if (!all_of(GEP->indices(), [](Value *V) { return isa<Constant>(V); }))
3108 return TTI::TCC_Basic * 2;
3109 }
3110 return TTI::TCC_Basic;
3111 }
3112 return BaseT::getUserCost(U, Operands);
3113 }
3114
3115 // Return an average cost of Gather / Scatter instruction, maybe improved later
3116 int X86TTIImpl::getGSVectorCost(unsigned Opcode, Type *SrcVTy, Value *Ptr,
3117 unsigned Alignment, unsigned AddressSpace) {
3118
3119 assert(isa<VectorType>(SrcVTy) && "Unexpected type in getGSVectorCost");
3120 unsigned VF = SrcVTy->getVectorNumElements();
3121
3122 // Try to reduce index size from 64 bit (default for GEP)
3123 // to 32. It is essential for VF 16. If the index can't be reduced to 32, the
3124 // operation will use 16 x 64 indices which do not fit in a zmm and needs
3125 // to split. Also check that the base pointer is the same for all lanes,
3126 // and that there's at most one variable index.
3127 auto getIndexSizeInBits = [](Value *Ptr, const DataLayout& DL) {
3128 unsigned IndexSize = DL.getPointerSizeInBits();
3129 GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr);
3130 if (IndexSize < 64 || !GEP)
3131 return IndexSize;
3132
3133 unsigned NumOfVarIndices = 0;
3134 Value *Ptrs = GEP->getPointerOperand();
3135 if (Ptrs->getType()->isVectorTy() && !getSplatValue(Ptrs))
3136 return IndexSize;
3137 for (unsigned i = 1; i < GEP->getNumOperands(); ++i) {
3138 if (isa<Constant>(GEP->getOperand(i)))
3139 continue;
3140 Type *IndxTy = GEP->getOperand(i)->getType();
3141 if (IndxTy->isVectorTy())
3142 IndxTy = IndxTy->getVectorElementType();
3143 if ((IndxTy->getPrimitiveSizeInBits() == 64 &&
3144 !isa<SExtInst>(GEP->getOperand(i))) ||
3145 ++NumOfVarIndices > 1)
3146 return IndexSize; // 64
3147 }
3148 return (unsigned)32;
3149 };
3150
3151
3152 // Trying to reduce IndexSize to 32 bits for vector 16.
3153 // By default the IndexSize is equal to pointer size.
3154 unsigned IndexSize = (ST->hasAVX512() && VF >= 16)
3155 ? getIndexSizeInBits(Ptr, DL)
3156 : DL.getPointerSizeInBits();
3157
3158 Type *IndexVTy = VectorType::get(IntegerType::get(SrcVTy->getContext(),
3159 IndexSize), VF);
3160 std::pair<int, MVT> IdxsLT = TLI->getTypeLegalizationCost(DL, IndexVTy);
3161 std::pair<int, MVT> SrcLT = TLI->getTypeLegalizationCost(DL, SrcVTy);
3162 int SplitFactor = std::max(IdxsLT.first, SrcLT.first);
3163 if (SplitFactor > 1) {
3164 // Handle splitting of vector of pointers
3165 Type *SplitSrcTy = VectorType::get(SrcVTy->getScalarType(), VF / SplitFactor);
3166 return SplitFactor * getGSVectorCost(Opcode, SplitSrcTy, Ptr, Alignment,
3167 AddressSpace);
3168 }
3169
3170 // The gather / scatter cost is given by Intel architects. It is a rough
3171 // number since we are looking at one instruction in a time.
3172 const int GSOverhead = (Opcode == Instruction::Load)
3173 ? ST->getGatherOverhead()
3174 : ST->getScatterOverhead();
3175 return GSOverhead + VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(),
3176 Alignment, AddressSpace);
3177 }
3178
3179 /// Return the cost of full scalarization of gather / scatter operation.
3180 ///
3181 /// Opcode - Load or Store instruction.
3182 /// SrcVTy - The type of the data vector that should be gathered or scattered.
3183 /// VariableMask - The mask is non-constant at compile time.
3184 /// Alignment - Alignment for one element.
3185 /// AddressSpace - pointer[s] address space.
3186 ///
3187 int X86TTIImpl::getGSScalarCost(unsigned Opcode, Type *SrcVTy,
3188 bool VariableMask, unsigned Alignment,
3189 unsigned AddressSpace) {
3190 unsigned VF = SrcVTy->getVectorNumElements();
3191
3192 int MaskUnpackCost = 0;
3193 if (VariableMask) {
3194 VectorType *MaskTy =
3195 VectorType::get(Type::getInt1Ty(SrcVTy->getContext()), VF);
3196 MaskUnpackCost = getScalarizationOverhead(MaskTy, false, true);
3197 int ScalarCompareCost =
3198 getCmpSelInstrCost(Instruction::ICmp, Type::getInt1Ty(SrcVTy->getContext()),
3199 nullptr);
3200 int BranchCost = getCFInstrCost(Instruction::Br);
3201 MaskUnpackCost += VF * (BranchCost + ScalarCompareCost);
3202 }
3203
3204 // The cost of the scalar loads/stores.
3205 int MemoryOpCost = VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(),
3206 Alignment, AddressSpace);
3207
3208 int InsertExtractCost = 0;
3209 if (Opcode == Instruction::Load)
3210 for (unsigned i = 0; i < VF; ++i)
3211 // Add the cost of inserting each scalar load into the vector
3212 InsertExtractCost +=
3213 getVectorInstrCost(Instruction::InsertElement, SrcVTy, i);
3214 else
3215 for (unsigned i = 0; i < VF; ++i)
3216 // Add the cost of extracting each element out of the data vector
3217 InsertExtractCost +=
3218 getVectorInstrCost(Instruction::ExtractElement, SrcVTy, i);
3219
3220 return MemoryOpCost + MaskUnpackCost + InsertExtractCost;
3221 }
3222
3223 /// Calculate the cost of Gather / Scatter operation
3224 int X86TTIImpl::getGatherScatterOpCost(unsigned Opcode, Type *SrcVTy,
3225 Value *Ptr, bool VariableMask,
3226 unsigned Alignment) {
3227 assert(SrcVTy->isVectorTy() && "Unexpected data type for Gather/Scatter");
3228 unsigned VF = SrcVTy->getVectorNumElements();
3229 PointerType *PtrTy = dyn_cast<PointerType>(Ptr->getType());
3230 if (!PtrTy && Ptr->getType()->isVectorTy())
3231 PtrTy = dyn_cast<PointerType>(Ptr->getType()->getVectorElementType());
3232 assert(PtrTy && "Unexpected type for Ptr argument");
3233 unsigned AddressSpace = PtrTy->getAddressSpace();
3234
3235 bool Scalarize = false;
3236 if ((Opcode == Instruction::Load && !isLegalMaskedGather(SrcVTy)) ||
3237 (Opcode == Instruction::Store && !isLegalMaskedScatter(SrcVTy)))
3238 Scalarize = true;
3239 // Gather / Scatter for vector 2 is not profitable on KNL / SKX
3240 // Vector-4 of gather/scatter instruction does not exist on KNL.
3241 // We can extend it to 8 elements, but zeroing upper bits of
3242 // the mask vector will add more instructions. Right now we give the scalar
3243 // cost of vector-4 for KNL. TODO: Check, maybe the gather/scatter instruction
3244 // is better in the VariableMask case.
3245 if (ST->hasAVX512() && (VF == 2 || (VF == 4 && !ST->hasVLX())))
3246 Scalarize = true;
3247
3248 if (Scalarize)
3249 return getGSScalarCost(Opcode, SrcVTy, VariableMask, Alignment,
3250 AddressSpace);
3251
3252 return getGSVectorCost(Opcode, SrcVTy, Ptr, Alignment, AddressSpace);
3253 }
3254
3255 bool X86TTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1,
3256 TargetTransformInfo::LSRCost &C2) {
3257 // X86 specific here are "instruction number 1st priority".
3258 return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost,
3259 C1.NumIVMuls, C1.NumBaseAdds,
3260 C1.ScaleCost, C1.ImmCost, C1.SetupCost) <
3261 std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost,
3262 C2.NumIVMuls, C2.NumBaseAdds,
3263 C2.ScaleCost, C2.ImmCost, C2.SetupCost);
3264 }
3265
3266 bool X86TTIImpl::canMacroFuseCmp() {
3267 return ST->hasMacroFusion() || ST->hasBranchFusion();
3268 }
3269
3270 bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy) {
3271 if (!ST->hasAVX())
3272 return false;
3273
3274 // The backend can't handle a single element vector.
3275 if (isa<VectorType>(DataTy) && DataTy->getVectorNumElements() == 1)
3276 return false;
3277 Type *ScalarTy = DataTy->getScalarType();
3278
3279 if (ScalarTy->isPointerTy())
3280 return true;
3281
3282 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy())
3283 return true;
3284
3285 if (!ScalarTy->isIntegerTy())
3286 return false;
3287
3288 unsigned IntWidth = ScalarTy->getIntegerBitWidth();
3289 return IntWidth == 32 || IntWidth == 64 ||
3290 ((IntWidth == 8 || IntWidth == 16) && ST->hasBWI());
3291 }
3292
3293 bool X86TTIImpl::isLegalMaskedStore(Type *DataType) {
3294 return isLegalMaskedLoad(DataType);
3295 }
3296
3297 bool X86TTIImpl::isLegalNTLoad(Type *DataType, Align Alignment) {
3298 unsigned DataSize = DL.getTypeStoreSize(DataType);
3299 // The only supported nontemporal loads are for aligned vectors of 16 or 32
3300 // bytes. Note that 32-byte nontemporal vector loads are supported by AVX2
3301 // (the equivalent stores only require AVX).
3302 if (Alignment >= DataSize && (DataSize == 16 || DataSize == 32))
3303 return DataSize == 16 ? ST->hasSSE1() : ST->hasAVX2();
3304
3305 return false;
3306 }
3307
3308 bool X86TTIImpl::isLegalNTStore(Type *DataType, Align Alignment) {
3309 unsigned DataSize = DL.getTypeStoreSize(DataType);
3310
3311 // SSE4A supports nontemporal stores of float and double at arbitrary
3312 // alignment.
3313 if (ST->hasSSE4A() && (DataType->isFloatTy() || DataType->isDoubleTy()))
3314 return true;
3315
3316 // Besides the SSE4A subtarget exception above, only aligned stores are
3317 // available nontemporaly on any other subtarget. And only stores with a size
3318 // of 4..32 bytes (powers of 2, only) are permitted.
3319 if (Alignment < DataSize || DataSize < 4 || DataSize > 32 ||
3320 !isPowerOf2_32(DataSize))
3321 return false;
3322
3323 // 32-byte vector nontemporal stores are supported by AVX (the equivalent
3324 // loads require AVX2).
3325 if (DataSize == 32)
3326 return ST->hasAVX();
3327 else if (DataSize == 16)
3328 return ST->hasSSE1();
3329 return true;
3330 }
3331
3332 bool X86TTIImpl::isLegalMaskedExpandLoad(Type *DataTy) {
3333 if (!isa<VectorType>(DataTy))
3334 return false;
3335
3336 if (!ST->hasAVX512())
3337 return false;
3338
3339 // The backend can't handle a single element vector.
3340 if (DataTy->getVectorNumElements() == 1)
3341 return false;
3342
3343 Type *ScalarTy = DataTy->getVectorElementType();
3344
3345 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy())
3346 return true;
3347
3348 if (!ScalarTy->isIntegerTy())
3349 return false;
3350
3351 unsigned IntWidth = ScalarTy->getIntegerBitWidth();
3352 return IntWidth == 32 || IntWidth == 64 ||
3353 ((IntWidth == 8 || IntWidth == 16) && ST->hasVBMI2());
3354 }
3355
3356 bool X86TTIImpl::isLegalMaskedCompressStore(Type *DataTy) {
3357 return isLegalMaskedExpandLoad(DataTy);
3358 }
3359
3360 bool X86TTIImpl::isLegalMaskedGather(Type *DataTy) {
3361 // Some CPUs have better gather performance than others.
3362 // TODO: Remove the explicit ST->hasAVX512()?, That would mean we would only
3363 // enable gather with a -march.
3364 if (!(ST->hasAVX512() || (ST->hasFastGather() && ST->hasAVX2())))
3365 return false;
3366
3367 // This function is called now in two cases: from the Loop Vectorizer
3368 // and from the Scalarizer.
3369 // When the Loop Vectorizer asks about legality of the feature,
3370 // the vectorization factor is not calculated yet. The Loop Vectorizer
3371 // sends a scalar type and the decision is based on the width of the
3372 // scalar element.
3373 // Later on, the cost model will estimate usage this intrinsic based on
3374 // the vector type.
3375 // The Scalarizer asks again about legality. It sends a vector type.
3376 // In this case we can reject non-power-of-2 vectors.
3377 // We also reject single element vectors as the type legalizer can't
3378 // scalarize it.
3379 if (isa<VectorType>(DataTy)) {
3380 unsigned NumElts = DataTy->getVectorNumElements();
3381 if (NumElts == 1 || !isPowerOf2_32(NumElts))
3382 return false;
3383 }
3384 Type *ScalarTy = DataTy->getScalarType();
3385 if (ScalarTy->isPointerTy())
3386 return true;
3387
3388 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy())
3389 return true;
3390
3391 if (!ScalarTy->isIntegerTy())
3392 return false;
3393
3394 unsigned IntWidth = ScalarTy->getIntegerBitWidth();
3395 return IntWidth == 32 || IntWidth == 64;
3396 }
3397
3398 bool X86TTIImpl::isLegalMaskedScatter(Type *DataType) {
3399 // AVX2 doesn't support scatter
3400 if (!ST->hasAVX512())
3401 return false;
3402 return isLegalMaskedGather(DataType);
3403 }
3404
3405 bool X86TTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) {
3406 EVT VT = TLI->getValueType(DL, DataType);
3407 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT);
3408 }
3409
3410 bool X86TTIImpl::isFCmpOrdCheaperThanFCmpZero(Type *Ty) {
3411 return false;
3412 }
3413
3414 bool X86TTIImpl::areInlineCompatible(const Function *Caller,
3415 const Function *Callee) const {
3416 const TargetMachine &TM = getTLI()->getTargetMachine();
3417
3418 // Work this as a subsetting of subtarget features.
3419 const FeatureBitset &CallerBits =
3420 TM.getSubtargetImpl(*Caller)->getFeatureBits();
3421 const FeatureBitset &CalleeBits =
3422 TM.getSubtargetImpl(*Callee)->getFeatureBits();
3423
3424 FeatureBitset RealCallerBits = CallerBits & ~InlineFeatureIgnoreList;
3425 FeatureBitset RealCalleeBits = CalleeBits & ~InlineFeatureIgnoreList;
3426 return (RealCallerBits & RealCalleeBits) == RealCalleeBits;
3427 }
3428
3429 bool X86TTIImpl::areFunctionArgsABICompatible(
3430 const Function *Caller, const Function *Callee,
3431 SmallPtrSetImpl<Argument *> &Args) const {
3432 if (!BaseT::areFunctionArgsABICompatible(Caller, Callee, Args))
3433 return false;
3434
3435 // If we get here, we know the target features match. If one function
3436 // considers 512-bit vectors legal and the other does not, consider them
3437 // incompatible.
3438 // FIXME Look at the arguments and only consider 512 bit or larger vectors?
3439 const TargetMachine &TM = getTLI()->getTargetMachine();
3440
3441 return TM.getSubtarget<X86Subtarget>(*Caller).useAVX512Regs() ==
3442 TM.getSubtarget<X86Subtarget>(*Callee).useAVX512Regs();
3443 }
3444
3445 X86TTIImpl::TTI::MemCmpExpansionOptions
3446 X86TTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
3447 TTI::MemCmpExpansionOptions Options;
3448 Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize);
3449 Options.NumLoadsPerBlock = 2;
3450 if (IsZeroCmp) {
3451 // Only enable vector loads for equality comparison. Right now the vector
3452 // version is not as fast for three way compare (see #33329).
3453 // TODO: enable AVX512 when the DAG is ready.
3454 // if (ST->hasAVX512()) Options.LoadSizes.push_back(64);
3455 const unsigned PreferredWidth = ST->getPreferVectorWidth();
3456 if (PreferredWidth >= 256 && ST->hasAVX2()) Options.LoadSizes.push_back(32);
3457 if (PreferredWidth >= 128 && ST->hasSSE2()) Options.LoadSizes.push_back(16);
3458 // All GPR and vector loads can be unaligned. SIMD compare requires integer
3459 // vectors (SSE2/AVX2).
3460 Options.AllowOverlappingLoads = true;
3461 }
3462 if (ST->is64Bit()) {
3463 Options.LoadSizes.push_back(8);
3464 }
3465 Options.LoadSizes.push_back(4);
3466 Options.LoadSizes.push_back(2);
3467 Options.LoadSizes.push_back(1);
3468 return Options;
3469 }
3470
3471 bool X86TTIImpl::enableInterleavedAccessVectorization() {
3472 // TODO: We expect this to be beneficial regardless of arch,
3473 // but there are currently some unexplained performance artifacts on Atom.
3474 // As a temporary solution, disable on Atom.
3475 return !(ST->isAtom());
3476 }
3477
3478 // Get estimation for interleaved load/store operations for AVX2.
3479 // \p Factor is the interleaved-access factor (stride) - number of
3480 // (interleaved) elements in the group.
3481 // \p Indices contains the indices for a strided load: when the
3482 // interleaved load has gaps they indicate which elements are used.
3483 // If Indices is empty (or if the number of indices is equal to the size
3484 // of the interleaved-access as given in \p Factor) the access has no gaps.
3485 //
3486 // As opposed to AVX-512, AVX2 does not have generic shuffles that allow
3487 // computing the cost using a generic formula as a function of generic
3488 // shuffles. We therefore use a lookup table instead, filled according to
3489 // the instruction sequences that codegen currently generates.
3490 int X86TTIImpl::getInterleavedMemoryOpCostAVX2(unsigned Opcode, Type *VecTy,
3491 unsigned Factor,
3492 ArrayRef<unsigned> Indices,
3493 unsigned Alignment,
3494 unsigned AddressSpace,
3495 bool UseMaskForCond,
3496 bool UseMaskForGaps) {
3497
3498 if (UseMaskForCond || UseMaskForGaps)
3499 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
3500 Alignment, AddressSpace,
3501 UseMaskForCond, UseMaskForGaps);
3502
3503 // We currently Support only fully-interleaved groups, with no gaps.
3504 // TODO: Support also strided loads (interleaved-groups with gaps).
3505 if (Indices.size() && Indices.size() != Factor)
3506 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
3507 Alignment, AddressSpace);
3508
3509 // VecTy for interleave memop is <VF*Factor x Elt>.
3510 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have
3511 // VecTy = <12 x i32>.
3512 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second;
3513
3514 // This function can be called with VecTy=<6xi128>, Factor=3, in which case
3515 // the VF=2, while v2i128 is an unsupported MVT vector type
3516 // (see MachineValueType.h::getVectorVT()).
3517 if (!LegalVT.isVector())
3518 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
3519 Alignment, AddressSpace);
3520
3521 unsigned VF = VecTy->getVectorNumElements() / Factor;
3522 Type *ScalarTy = VecTy->getVectorElementType();
3523
3524 // Calculate the number of memory operations (NumOfMemOps), required
3525 // for load/store the VecTy.
3526 unsigned VecTySize = DL.getTypeStoreSize(VecTy);
3527 unsigned LegalVTSize = LegalVT.getStoreSize();
3528 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize;
3529
3530 // Get the cost of one memory operation.
3531 Type *SingleMemOpTy = VectorType::get(VecTy->getVectorElementType(),
3532 LegalVT.getVectorNumElements());
3533 unsigned MemOpCost =
3534 getMemoryOpCost(Opcode, SingleMemOpTy, Alignment, AddressSpace);
3535
3536 VectorType *VT = VectorType::get(ScalarTy, VF);
3537 EVT ETy = TLI->getValueType(DL, VT);
3538 if (!ETy.isSimple())
3539 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
3540 Alignment, AddressSpace);
3541
3542 // TODO: Complete for other data-types and strides.
3543 // Each combination of Stride, ElementTy and VF results in a different
3544 // sequence; The cost tables are therefore accessed with:
3545 // Factor (stride) and VectorType=VFxElemType.
3546 // The Cost accounts only for the shuffle sequence;
3547 // The cost of the loads/stores is accounted for separately.
3548 //
3549 static const CostTblEntry AVX2InterleavedLoadTbl[] = {
3550 { 2, MVT::v4i64, 6 }, //(load 8i64 and) deinterleave into 2 x 4i64
3551 { 2, MVT::v4f64, 6 }, //(load 8f64 and) deinterleave into 2 x 4f64
3552
3553 { 3, MVT::v2i8, 10 }, //(load 6i8 and) deinterleave into 3 x 2i8
3554 { 3, MVT::v4i8, 4 }, //(load 12i8 and) deinterleave into 3 x 4i8
3555 { 3, MVT::v8i8, 9 }, //(load 24i8 and) deinterleave into 3 x 8i8
3556 { 3, MVT::v16i8, 11}, //(load 48i8 and) deinterleave into 3 x 16i8
3557 { 3, MVT::v32i8, 13}, //(load 96i8 and) deinterleave into 3 x 32i8
3558 { 3, MVT::v8f32, 17 }, //(load 24f32 and)deinterleave into 3 x 8f32
3559
3560 { 4, MVT::v2i8, 12 }, //(load 8i8 and) deinterleave into 4 x 2i8
3561 { 4, MVT::v4i8, 4 }, //(load 16i8 and) deinterleave into 4 x 4i8
3562 { 4, MVT::v8i8, 20 }, //(load 32i8 and) deinterleave into 4 x 8i8
3563 { 4, MVT::v16i8, 39 }, //(load 64i8 and) deinterleave into 4 x 16i8
3564 { 4, MVT::v32i8, 80 }, //(load 128i8 and) deinterleave into 4 x 32i8
3565
3566 { 8, MVT::v8f32, 40 } //(load 64f32 and)deinterleave into 8 x 8f32
3567 };
3568
3569 static const CostTblEntry AVX2InterleavedStoreTbl[] = {
3570 { 2, MVT::v4i64, 6 }, //interleave into 2 x 4i64 into 8i64 (and store)
3571 { 2, MVT::v4f64, 6 }, //interleave into 2 x 4f64 into 8f64 (and store)
3572
3573 { 3, MVT::v2i8, 7 }, //interleave 3 x 2i8 into 6i8 (and store)
3574 { 3, MVT::v4i8, 8 }, //interleave 3 x 4i8 into 12i8 (and store)
3575 { 3, MVT::v8i8, 11 }, //interleave 3 x 8i8 into 24i8 (and store)
3576 { 3, MVT::v16i8, 11 }, //interleave 3 x 16i8 into 48i8 (and store)
3577 { 3, MVT::v32i8, 13 }, //interleave 3 x 32i8 into 96i8 (and store)
3578
3579 { 4, MVT::v2i8, 12 }, //interleave 4 x 2i8 into 8i8 (and store)
3580 { 4, MVT::v4i8, 9 }, //interleave 4 x 4i8 into 16i8 (and store)
3581 { 4, MVT::v8i8, 10 }, //interleave 4 x 8i8 into 32i8 (and store)
3582 { 4, MVT::v16i8, 10 }, //interleave 4 x 16i8 into 64i8 (and store)
3583 { 4, MVT::v32i8, 12 } //interleave 4 x 32i8 into 128i8 (and store)
3584 };
3585
3586 if (Opcode == Instruction::Load) {
3587 if (const auto *Entry =
3588 CostTableLookup(AVX2InterleavedLoadTbl, Factor, ETy.getSimpleVT()))
3589 return NumOfMemOps * MemOpCost + Entry->Cost;
3590 } else {
3591 assert(Opcode == Instruction::Store &&
3592 "Expected Store Instruction at this point");
3593 if (const auto *Entry =
3594 CostTableLookup(AVX2InterleavedStoreTbl, Factor, ETy.getSimpleVT()))
3595 return NumOfMemOps * MemOpCost + Entry->Cost;
3596 }
3597
3598 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
3599 Alignment, AddressSpace);
3600 }
3601
3602 // Get estimation for interleaved load/store operations and strided load.
3603 // \p Indices contains indices for strided load.
3604 // \p Factor - the factor of interleaving.
3605 // AVX-512 provides 3-src shuffles that significantly reduces the cost.
3606 int X86TTIImpl::getInterleavedMemoryOpCostAVX512(unsigned Opcode, Type *VecTy,
3607 unsigned Factor,
3608 ArrayRef<unsigned> Indices,
3609 unsigned Alignment,
3610 unsigned AddressSpace,
3611 bool UseMaskForCond,
3612 bool UseMaskForGaps) {
3613
3614 if (UseMaskForCond || UseMaskForGaps)
3615 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
3616 Alignment, AddressSpace,
3617 UseMaskForCond, UseMaskForGaps);
3618
3619 // VecTy for interleave memop is <VF*Factor x Elt>.
3620 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have
3621 // VecTy = <12 x i32>.
3622
3623 // Calculate the number of memory operations (NumOfMemOps), required
3624 // for load/store the VecTy.
3625 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second;
3626 unsigned VecTySize = DL.getTypeStoreSize(VecTy);
3627 unsigned LegalVTSize = LegalVT.getStoreSize();
3628 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize;
3629
3630 // Get the cost of one memory operation.
3631 Type *SingleMemOpTy = VectorType::get(VecTy->getVectorElementType(),
3632 LegalVT.getVectorNumElements());
3633 unsigned MemOpCost =
3634 getMemoryOpCost(Opcode, SingleMemOpTy, Alignment, AddressSpace);
3635
3636 unsigned VF = VecTy->getVectorNumElements() / Factor;
3637 MVT VT = MVT::getVectorVT(MVT::getVT(VecTy->getScalarType()), VF);
3638
3639 if (Opcode == Instruction::Load) {
3640 // The tables (AVX512InterleavedLoadTbl and AVX512InterleavedStoreTbl)
3641 // contain the cost of the optimized shuffle sequence that the
3642 // X86InterleavedAccess pass will generate.
3643 // The cost of loads and stores are computed separately from the table.
3644
3645 // X86InterleavedAccess support only the following interleaved-access group.
3646 static const CostTblEntry AVX512InterleavedLoadTbl[] = {
3647 {3, MVT::v16i8, 12}, //(load 48i8 and) deinterleave into 3 x 16i8
3648 {3, MVT::v32i8, 14}, //(load 96i8 and) deinterleave into 3 x 32i8
3649 {3, MVT::v64i8, 22}, //(load 96i8 and) deinterleave into 3 x 32i8
3650 };
3651
3652 if (const auto *Entry =
3653 CostTableLookup(AVX512InterleavedLoadTbl, Factor, VT))
3654 return NumOfMemOps * MemOpCost + Entry->Cost;
3655 //If an entry does not exist, fallback to the default implementation.
3656
3657 // Kind of shuffle depends on number of loaded values.
3658 // If we load the entire data in one register, we can use a 1-src shuffle.
3659 // Otherwise, we'll merge 2 sources in each operation.
3660 TTI::ShuffleKind ShuffleKind =
3661 (NumOfMemOps > 1) ? TTI::SK_PermuteTwoSrc : TTI::SK_PermuteSingleSrc;
3662
3663 unsigned ShuffleCost =
3664 getShuffleCost(ShuffleKind, SingleMemOpTy, 0, nullptr);
3665
3666 unsigned NumOfLoadsInInterleaveGrp =
3667 Indices.size() ? Indices.size() : Factor;
3668 Type *ResultTy = VectorType::get(VecTy->getVectorElementType(),
3669 VecTy->getVectorNumElements() / Factor);
3670 unsigned NumOfResults =
3671 getTLI()->getTypeLegalizationCost(DL, ResultTy).first *
3672 NumOfLoadsInInterleaveGrp;
3673
3674 // About a half of the loads may be folded in shuffles when we have only
3675 // one result. If we have more than one result, we do not fold loads at all.
3676 unsigned NumOfUnfoldedLoads =
3677 NumOfResults > 1 ? NumOfMemOps : NumOfMemOps / 2;
3678
3679 // Get a number of shuffle operations per result.
3680 unsigned NumOfShufflesPerResult =
3681 std::max((unsigned)1, (unsigned)(NumOfMemOps - 1));
3682
3683 // The SK_MergeTwoSrc shuffle clobbers one of src operands.
3684 // When we have more than one destination, we need additional instructions
3685 // to keep sources.
3686 unsigned NumOfMoves = 0;
3687 if (NumOfResults > 1 && ShuffleKind == TTI::SK_PermuteTwoSrc)
3688 NumOfMoves = NumOfResults * NumOfShufflesPerResult / 2;
3689
3690 int Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost +
3691 NumOfUnfoldedLoads * MemOpCost + NumOfMoves;
3692
3693 return Cost;
3694 }
3695
3696 // Store.
3697 assert(Opcode == Instruction::Store &&
3698 "Expected Store Instruction at this point");
3699 // X86InterleavedAccess support only the following interleaved-access group.
3700 static const CostTblEntry AVX512InterleavedStoreTbl[] = {
3701 {3, MVT::v16i8, 12}, // interleave 3 x 16i8 into 48i8 (and store)
3702 {3, MVT::v32i8, 14}, // interleave 3 x 32i8 into 96i8 (and store)
3703 {3, MVT::v64i8, 26}, // interleave 3 x 64i8 into 96i8 (and store)
3704
3705 {4, MVT::v8i8, 10}, // interleave 4 x 8i8 into 32i8 (and store)
3706 {4, MVT::v16i8, 11}, // interleave 4 x 16i8 into 64i8 (and store)
3707 {4, MVT::v32i8, 14}, // interleave 4 x 32i8 into 128i8 (and store)
3708 {4, MVT::v64i8, 24} // interleave 4 x 32i8 into 256i8 (and store)
3709 };
3710
3711 if (const auto *Entry =
3712 CostTableLookup(AVX512InterleavedStoreTbl, Factor, VT))
3713 return NumOfMemOps * MemOpCost + Entry->Cost;
3714 //If an entry does not exist, fallback to the default implementation.
3715
3716 // There is no strided stores meanwhile. And store can't be folded in
3717 // shuffle.
3718 unsigned NumOfSources = Factor; // The number of values to be merged.
3719 unsigned ShuffleCost =
3720 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleMemOpTy, 0, nullptr);
3721 unsigned NumOfShufflesPerStore = NumOfSources - 1;
3722
3723 // The SK_MergeTwoSrc shuffle clobbers one of src operands.
3724 // We need additional instructions to keep sources.
3725 unsigned NumOfMoves = NumOfMemOps * NumOfShufflesPerStore / 2;
3726 int Cost = NumOfMemOps * (MemOpCost + NumOfShufflesPerStore * ShuffleCost) +
3727 NumOfMoves;
3728 return Cost;
3729 }
3730
3731 int X86TTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy,
3732 unsigned Factor,
3733 ArrayRef<unsigned> Indices,
3734 unsigned Alignment,
3735 unsigned AddressSpace,
3736 bool UseMaskForCond,
3737 bool UseMaskForGaps) {
3738 auto isSupportedOnAVX512 = [](Type *VecTy, bool HasBW) {
3739 Type *EltTy = VecTy->getVectorElementType();
3740 if (EltTy->isFloatTy() || EltTy->isDoubleTy() || EltTy->isIntegerTy(64) ||
3741 EltTy->isIntegerTy(32) || EltTy->isPointerTy())
3742 return true;
3743 if (EltTy->isIntegerTy(16) || EltTy->isIntegerTy(8))
3744 return HasBW;
3745 return false;
3746 };
3747 if (ST->hasAVX512() && isSupportedOnAVX512(VecTy, ST->hasBWI()))
3748 return getInterleavedMemoryOpCostAVX512(Opcode, VecTy, Factor, Indices,
3749 Alignment, AddressSpace,
3750 UseMaskForCond, UseMaskForGaps);
3751 if (ST->hasAVX2())
3752 return getInterleavedMemoryOpCostAVX2(Opcode, VecTy, Factor, Indices,
3753 Alignment, AddressSpace,
3754 UseMaskForCond, UseMaskForGaps);
3755
3756 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
3757 Alignment, AddressSpace,
3758 UseMaskForCond, UseMaskForGaps);
3759 }
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