lib/Target/RISCV/RISCVAsmPrinter.cpp

   1 //===-- RISCVAsmPrinter.cpp - RISCV LLVM assembly writer ------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains a printer that converts from our internal representation
  11 // of machine-dependent LLVM code to the RISCV assembly language.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "RISCV.h"
  16 #include "InstPrinter/RISCVInstPrinter.h"
  17 #include "MCTargetDesc/RISCVMCExpr.h"
  18 #include "RISCVTargetMachine.h"
  19 #include "llvm/CodeGen/AsmPrinter.h"
  20 #include "llvm/CodeGen/MachineConstantPool.h"
  21 #include "llvm/CodeGen/MachineFunctionPass.h"
  22 #include "llvm/CodeGen/MachineInstr.h"
  23 #include "llvm/CodeGen/MachineModuleInfo.h"
  24 #include "llvm/MC/MCAsmInfo.h"
  25 #include "llvm/MC/MCInst.h"
  26 #include "llvm/MC/MCStreamer.h"
  27 #include "llvm/MC/MCSymbol.h"
  28 #include "llvm/Support/TargetRegistry.h"
  29 #include "llvm/Support/raw_ostream.h"
  30 using namespace llvm;
  31
  32 #define DEBUG_TYPE "asm-printer"
  33
  34 namespace {
  35 class RISCVAsmPrinter : public AsmPrinter {
  36 public:
  37   explicit RISCVAsmPrinter(TargetMachine &TM,
  38                            std::unique_ptr<MCStreamer> Streamer)
  39       : AsmPrinter(TM, std::move(Streamer)) {}
  40
  41   StringRef getPassName() const override { return "RISCV Assembly Printer"; }
  42
  43   void EmitInstruction(const MachineInstr *MI) override;
  44
  45   bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
  46                        unsigned AsmVariant, const char *ExtraCode,
  47                        raw_ostream &OS) override;
  48   bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
  49                              unsigned AsmVariant, const char *ExtraCode,
  50                              raw_ostream &OS) override;
  51
  52   void EmitToStreamer(MCStreamer &S, const MCInst &Inst);
  53   bool emitPseudoExpansionLowering(MCStreamer &OutStreamer,
  54                                    const MachineInstr *MI);
  55
  56   // Wrapper needed for tblgenned pseudo lowering.
  57   bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const {
  58     return LowerRISCVMachineOperandToMCOperand(MO, MCOp, *this);
  59   }
  60 };
  61 }
  62
  63 #define GEN_COMPRESS_INSTR
  64 #include "RISCVGenCompressInstEmitter.inc"
  65 void RISCVAsmPrinter::EmitToStreamer(MCStreamer &S, const MCInst &Inst) {
  66   MCInst CInst;
  67   bool Res = compressInst(CInst, Inst, *TM.getMCSubtargetInfo(),
  68                           OutStreamer->getContext());
  69   AsmPrinter::EmitToStreamer(*OutStreamer, Res ? CInst : Inst);
  70 }
  71
  72 // Simple pseudo-instructions have their lowering (with expansion to real
  73 // instructions) auto-generated.
  74 #include "RISCVGenMCPseudoLowering.inc"
  75
  76 void RISCVAsmPrinter::EmitInstruction(const MachineInstr *MI) {
  77   // Do any auto-generated pseudo lowerings.
  78   if (emitPseudoExpansionLowering(*OutStreamer, MI))
  79     return;
  80
  81   MCInst TmpInst;
  82   LowerRISCVMachineInstrToMCInst(MI, TmpInst, *this);
  83   EmitToStreamer(*OutStreamer, TmpInst);
  84 }
  85
  86 bool RISCVAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
  87                                       unsigned AsmVariant,
  88                                       const char *ExtraCode, raw_ostream &OS) {
  89   if (AsmVariant != 0)
  90     report_fatal_error("There are no defined alternate asm variants");
  91
  92   // First try the generic code, which knows about modifiers like 'c' and 'n'.
  93   if (!AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, OS))
  94     return false;
  95
  96   if (!ExtraCode) {
  97     const MachineOperand &MO = MI->getOperand(OpNo);
  98     switch (MO.getType()) {
  99     case MachineOperand::MO_Immediate:
 100       OS << MO.getImm();
 101       return false;
 102     case MachineOperand::MO_Register:
 103       OS << RISCVInstPrinter::getRegisterName(MO.getReg());
 104       return false;
 105     default:
 106       break;
 107     }
 108   }
 109
 110   return true;
 111 }
 112
 113 bool RISCVAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
 114                                             unsigned OpNo, unsigned AsmVariant,
 115                                             const char *ExtraCode,
 116                                             raw_ostream &OS) {
 117   if (AsmVariant != 0)
 118     report_fatal_error("There are no defined alternate asm variants");
 119
 120   if (!ExtraCode) {
 121     const MachineOperand &MO = MI->getOperand(OpNo);
 122     // For now, we only support register memory operands in registers and
 123     // assume there is no addend
 124     if (!MO.isReg())
 125       return true;
 126
 127     OS << "0(" << RISCVInstPrinter::getRegisterName(MO.getReg()) << ")";
 128     return false;
 129   }
 130
 131   return AsmPrinter::PrintAsmMemoryOperand(MI, OpNo, AsmVariant, ExtraCode, OS);
 132 }
 133
 134 // Force static initialization.
 135 extern "C" void LLVMInitializeRISCVAsmPrinter() {
 136   RegisterAsmPrinter<RISCVAsmPrinter> X(getTheRISCV32Target());
 137   RegisterAsmPrinter<RISCVAsmPrinter> Y(getTheRISCV64Target());
 138 }