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[Alignment][NFC] Use Align with TargetLowering::setMinFunctionAlignment
[llvm-core.git] / lib / Target / X86 / X86MCInstLower.cpp
blob0726b91c1966cd81ef2068a2ed36c7ded99917e3
1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains code to lower X86 MachineInstrs to their corresponding
10 // MCInst records.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "MCTargetDesc/X86ATTInstPrinter.h"
15 #include "MCTargetDesc/X86BaseInfo.h"
16 #include "MCTargetDesc/X86InstComments.h"
17 #include "MCTargetDesc/X86TargetStreamer.h"
18 #include "Utils/X86ShuffleDecode.h"
19 #include "X86AsmPrinter.h"
20 #include "X86RegisterInfo.h"
21 #include "X86ShuffleDecodeConstantPool.h"
22 #include "llvm/ADT/Optional.h"
23 #include "llvm/ADT/SmallString.h"
24 #include "llvm/ADT/iterator_range.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
28 #include "llvm/CodeGen/MachineOperand.h"
29 #include "llvm/CodeGen/StackMaps.h"
30 #include "llvm/IR/DataLayout.h"
31 #include "llvm/IR/GlobalValue.h"
32 #include "llvm/IR/Mangler.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/MC/MCCodeEmitter.h"
35 #include "llvm/MC/MCContext.h"
36 #include "llvm/MC/MCExpr.h"
37 #include "llvm/MC/MCFixup.h"
38 #include "llvm/MC/MCInst.h"
39 #include "llvm/MC/MCInstBuilder.h"
40 #include "llvm/MC/MCSection.h"
41 #include "llvm/MC/MCSectionELF.h"
42 #include "llvm/MC/MCStreamer.h"
43 #include "llvm/MC/MCSymbol.h"
44 #include "llvm/MC/MCSymbolELF.h"
45 #include "llvm/Target/TargetLoweringObjectFile.h"
46
47 using namespace llvm;
48
49 namespace {
50
51 /// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst.
52 class X86MCInstLower {
53 MCContext &Ctx;
54 const MachineFunction &MF;
55 const TargetMachine &TM;
56 const MCAsmInfo &MAI;
57 X86AsmPrinter &AsmPrinter;
58
59 public:
60 X86MCInstLower(const MachineFunction &MF, X86AsmPrinter &asmprinter);
61
62 Optional<MCOperand> LowerMachineOperand(const MachineInstr *MI,
63 const MachineOperand &MO) const;
64 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
65
66 MCSymbol *GetSymbolFromOperand(const MachineOperand &MO) const;
67 MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
68
69 private:
70 MachineModuleInfoMachO &getMachOMMI() const;
71 };
72
73 } // end anonymous namespace
74
75 // Emit a minimal sequence of nops spanning NumBytes bytes.
76 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
77 const MCSubtargetInfo &STI);
78
79 void X86AsmPrinter::StackMapShadowTracker::count(MCInst &Inst,
80 const MCSubtargetInfo &STI,
81 MCCodeEmitter *CodeEmitter) {
82 if (InShadow) {
83 SmallString<256> Code;
84 SmallVector<MCFixup, 4> Fixups;
85 raw_svector_ostream VecOS(Code);
86 CodeEmitter->encodeInstruction(Inst, VecOS, Fixups, STI);
87 CurrentShadowSize += Code.size();
88 if (CurrentShadowSize >= RequiredShadowSize)
89 InShadow = false; // The shadow is big enough. Stop counting.
90 }
91 }
92
93 void X86AsmPrinter::StackMapShadowTracker::emitShadowPadding(
94 MCStreamer &OutStreamer, const MCSubtargetInfo &STI) {
95 if (InShadow && CurrentShadowSize < RequiredShadowSize) {
96 InShadow = false;
97 EmitNops(OutStreamer, RequiredShadowSize - CurrentShadowSize,
98 MF->getSubtarget<X86Subtarget>().is64Bit(), STI);
99 }
100 }
101
102 void X86AsmPrinter::EmitAndCountInstruction(MCInst &Inst) {
103 OutStreamer->EmitInstruction(Inst, getSubtargetInfo());
104 SMShadowTracker.count(Inst, getSubtargetInfo(), CodeEmitter.get());
105 }
106
107 X86MCInstLower::X86MCInstLower(const MachineFunction &mf,
108 X86AsmPrinter &asmprinter)
109 : Ctx(mf.getContext()), MF(mf), TM(mf.getTarget()), MAI(*TM.getMCAsmInfo()),
110 AsmPrinter(asmprinter) {}
111
112 MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const {
113 return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>();
114 }
115
116 /// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol
117 /// operand to an MCSymbol.
118 MCSymbol *X86MCInstLower::GetSymbolFromOperand(const MachineOperand &MO) const {
119 const DataLayout &DL = MF.getDataLayout();
120 assert((MO.isGlobal() || MO.isSymbol() || MO.isMBB()) &&
121 "Isn't a symbol reference");
122
123 MCSymbol *Sym = nullptr;
124 SmallString<128> Name;
125 StringRef Suffix;
126
127 switch (MO.getTargetFlags()) {
128 case X86II::MO_DLLIMPORT:
129 // Handle dllimport linkage.
130 Name += "__imp_";
131 break;
132 case X86II::MO_COFFSTUB:
133 Name += ".refptr.";
134 break;
135 case X86II::MO_DARWIN_NONLAZY:
136 case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
137 Suffix = "$non_lazy_ptr";
138 break;
139 }
140
141 if (!Suffix.empty())
142 Name += DL.getPrivateGlobalPrefix();
143
144 if (MO.isGlobal()) {
145 const GlobalValue *GV = MO.getGlobal();
146 AsmPrinter.getNameWithPrefix(Name, GV);
147 } else if (MO.isSymbol()) {
148 Mangler::getNameWithPrefix(Name, MO.getSymbolName(), DL);
149 } else if (MO.isMBB()) {
150 assert(Suffix.empty());
151 Sym = MO.getMBB()->getSymbol();
152 }
153
154 Name += Suffix;
155 if (!Sym)
156 Sym = Ctx.getOrCreateSymbol(Name);
157
158 // If the target flags on the operand changes the name of the symbol, do that
159 // before we return the symbol.
160 switch (MO.getTargetFlags()) {
161 default:
162 break;
163 case X86II::MO_COFFSTUB: {
164 MachineModuleInfoCOFF &MMICOFF =
165 MF.getMMI().getObjFileInfo<MachineModuleInfoCOFF>();
166 MachineModuleInfoImpl::StubValueTy &StubSym = MMICOFF.getGVStubEntry(Sym);
167 if (!StubSym.getPointer()) {
168 assert(MO.isGlobal() && "Extern symbol not handled yet");
169 StubSym = MachineModuleInfoImpl::StubValueTy(
170 AsmPrinter.getSymbol(MO.getGlobal()), true);
171 }
172 break;
173 }
174 case X86II::MO_DARWIN_NONLAZY:
175 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: {
176 MachineModuleInfoImpl::StubValueTy &StubSym =
177 getMachOMMI().getGVStubEntry(Sym);
178 if (!StubSym.getPointer()) {
179 assert(MO.isGlobal() && "Extern symbol not handled yet");
180 StubSym = MachineModuleInfoImpl::StubValueTy(
181 AsmPrinter.getSymbol(MO.getGlobal()),
182 !MO.getGlobal()->hasInternalLinkage());
183 }
184 break;
185 }
186 }
187
188 return Sym;
189 }
190
191 MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
192 MCSymbol *Sym) const {
193 // FIXME: We would like an efficient form for this, so we don't have to do a
194 // lot of extra uniquing.
195 const MCExpr *Expr = nullptr;
196 MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None;
197
198 switch (MO.getTargetFlags()) {
199 default:
200 llvm_unreachable("Unknown target flag on GV operand");
201 case X86II::MO_NO_FLAG: // No flag.
202 // These affect the name of the symbol, not any suffix.
203 case X86II::MO_DARWIN_NONLAZY:
204 case X86II::MO_DLLIMPORT:
205 case X86II::MO_COFFSTUB:
206 break;
207
208 case X86II::MO_TLVP:
209 RefKind = MCSymbolRefExpr::VK_TLVP;
210 break;
211 case X86II::MO_TLVP_PIC_BASE:
212 Expr = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx);
213 // Subtract the pic base.
214 Expr = MCBinaryExpr::createSub(
215 Expr, MCSymbolRefExpr::create(MF.getPICBaseSymbol(), Ctx), Ctx);
216 break;
217 case X86II::MO_SECREL:
218 RefKind = MCSymbolRefExpr::VK_SECREL;
219 break;
220 case X86II::MO_TLSGD:
221 RefKind = MCSymbolRefExpr::VK_TLSGD;
222 break;
223 case X86II::MO_TLSLD:
224 RefKind = MCSymbolRefExpr::VK_TLSLD;
225 break;
226 case X86II::MO_TLSLDM:
227 RefKind = MCSymbolRefExpr::VK_TLSLDM;
228 break;
229 case X86II::MO_GOTTPOFF:
230 RefKind = MCSymbolRefExpr::VK_GOTTPOFF;
231 break;
232 case X86II::MO_INDNTPOFF:
233 RefKind = MCSymbolRefExpr::VK_INDNTPOFF;
234 break;
235 case X86II::MO_TPOFF:
236 RefKind = MCSymbolRefExpr::VK_TPOFF;
237 break;
238 case X86II::MO_DTPOFF:
239 RefKind = MCSymbolRefExpr::VK_DTPOFF;
240 break;
241 case X86II::MO_NTPOFF:
242 RefKind = MCSymbolRefExpr::VK_NTPOFF;
243 break;
244 case X86II::MO_GOTNTPOFF:
245 RefKind = MCSymbolRefExpr::VK_GOTNTPOFF;
246 break;
247 case X86II::MO_GOTPCREL:
248 RefKind = MCSymbolRefExpr::VK_GOTPCREL;
249 break;
250 case X86II::MO_GOT:
251 RefKind = MCSymbolRefExpr::VK_GOT;
252 break;
253 case X86II::MO_GOTOFF:
254 RefKind = MCSymbolRefExpr::VK_GOTOFF;
255 break;
256 case X86II::MO_PLT:
257 RefKind = MCSymbolRefExpr::VK_PLT;
258 break;
259 case X86II::MO_ABS8:
260 RefKind = MCSymbolRefExpr::VK_X86_ABS8;
261 break;
262 case X86II::MO_PIC_BASE_OFFSET:
263 case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
264 Expr = MCSymbolRefExpr::create(Sym, Ctx);
265 // Subtract the pic base.
266 Expr = MCBinaryExpr::createSub(
267 Expr, MCSymbolRefExpr::create(MF.getPICBaseSymbol(), Ctx), Ctx);
268 if (MO.isJTI()) {
269 assert(MAI.doesSetDirectiveSuppressReloc());
270 // If .set directive is supported, use it to reduce the number of
271 // relocations the assembler will generate for differences between
272 // local labels. This is only safe when the symbols are in the same
273 // section so we are restricting it to jumptable references.
274 MCSymbol *Label = Ctx.createTempSymbol();
275 AsmPrinter.OutStreamer->EmitAssignment(Label, Expr);
276 Expr = MCSymbolRefExpr::create(Label, Ctx);
277 }
278 break;
279 }
280
281 if (!Expr)
282 Expr = MCSymbolRefExpr::create(Sym, RefKind, Ctx);
283
284 if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
285 Expr = MCBinaryExpr::createAdd(
286 Expr, MCConstantExpr::create(MO.getOffset(), Ctx), Ctx);
287 return MCOperand::createExpr(Expr);
288 }
289
290 /// Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with
291 /// a short fixed-register form.
292 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
293 unsigned ImmOp = Inst.getNumOperands() - 1;
294 assert(Inst.getOperand(0).isReg() &&
295 (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) &&
296 ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
297 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
298 Inst.getNumOperands() == 2) &&
299 "Unexpected instruction!");
300
301 // Check whether the destination register can be fixed.
302 unsigned Reg = Inst.getOperand(0).getReg();
303 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
304 return;
305
306 // If so, rewrite the instruction.
307 MCOperand Saved = Inst.getOperand(ImmOp);
308 Inst = MCInst();
309 Inst.setOpcode(Opcode);
310 Inst.addOperand(Saved);
311 }
312
313 /// If a movsx instruction has a shorter encoding for the used register
314 /// simplify the instruction to use it instead.
315 static void SimplifyMOVSX(MCInst &Inst) {
316 unsigned NewOpcode = 0;
317 unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg();
318 switch (Inst.getOpcode()) {
319 default:
320 llvm_unreachable("Unexpected instruction!");
321 case X86::MOVSX16rr8: // movsbw %al, %ax --> cbtw
322 if (Op0 == X86::AX && Op1 == X86::AL)
323 NewOpcode = X86::CBW;
324 break;
325 case X86::MOVSX32rr16: // movswl %ax, %eax --> cwtl
326 if (Op0 == X86::EAX && Op1 == X86::AX)
327 NewOpcode = X86::CWDE;
328 break;
329 case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq
330 if (Op0 == X86::RAX && Op1 == X86::EAX)
331 NewOpcode = X86::CDQE;
332 break;
333 }
334
335 if (NewOpcode != 0) {
336 Inst = MCInst();
337 Inst.setOpcode(NewOpcode);
338 }
339 }
340
341 /// Simplify things like MOV32rm to MOV32o32a.
342 static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst,
343 unsigned Opcode) {
344 // Don't make these simplifications in 64-bit mode; other assemblers don't
345 // perform them because they make the code larger.
346 if (Printer.getSubtarget().is64Bit())
347 return;
348
349 bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg();
350 unsigned AddrBase = IsStore;
351 unsigned RegOp = IsStore ? 0 : 5;
352 unsigned AddrOp = AddrBase + 3;
353 assert(
354 Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
355 Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() &&
356 Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() &&
357 Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() &&
358 Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() &&
359 (Inst.getOperand(AddrOp).isExpr() || Inst.getOperand(AddrOp).isImm()) &&
360 "Unexpected instruction!");
361
362 // Check whether the destination register can be fixed.
363 unsigned Reg = Inst.getOperand(RegOp).getReg();
364 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
365 return;
366
367 // Check whether this is an absolute address.
368 // FIXME: We know TLVP symbol refs aren't, but there should be a better way
369 // to do this here.
370 bool Absolute = true;
371 if (Inst.getOperand(AddrOp).isExpr()) {
372 const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr();
373 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE))
374 if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP)
375 Absolute = false;
376 }
377
378 if (Absolute &&
379 (Inst.getOperand(AddrBase + X86::AddrBaseReg).getReg() != 0 ||
380 Inst.getOperand(AddrBase + X86::AddrScaleAmt).getImm() != 1 ||
381 Inst.getOperand(AddrBase + X86::AddrIndexReg).getReg() != 0))
382 return;
383
384 // If so, rewrite the instruction.
385 MCOperand Saved = Inst.getOperand(AddrOp);
386 MCOperand Seg = Inst.getOperand(AddrBase + X86::AddrSegmentReg);
387 Inst = MCInst();
388 Inst.setOpcode(Opcode);
389 Inst.addOperand(Saved);
390 Inst.addOperand(Seg);
391 }
392
393 static unsigned getRetOpcode(const X86Subtarget &Subtarget) {
394 return Subtarget.is64Bit() ? X86::RETQ : X86::RETL;
395 }
396
397 Optional<MCOperand>
398 X86MCInstLower::LowerMachineOperand(const MachineInstr *MI,
399 const MachineOperand &MO) const {
400 switch (MO.getType()) {
401 default:
402 MI->print(errs());
403 llvm_unreachable("unknown operand type");
404 case MachineOperand::MO_Register:
405 // Ignore all implicit register operands.
406 if (MO.isImplicit())
407 return None;
408 return MCOperand::createReg(MO.getReg());
409 case MachineOperand::MO_Immediate:
410 return MCOperand::createImm(MO.getImm());
411 case MachineOperand::MO_MachineBasicBlock:
412 case MachineOperand::MO_GlobalAddress:
413 case MachineOperand::MO_ExternalSymbol:
414 return LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
415 case MachineOperand::MO_MCSymbol:
416 return LowerSymbolOperand(MO, MO.getMCSymbol());
417 case MachineOperand::MO_JumpTableIndex:
418 return LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex()));
419 case MachineOperand::MO_ConstantPoolIndex:
420 return LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex()));
421 case MachineOperand::MO_BlockAddress:
422 return LowerSymbolOperand(
423 MO, AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress()));
424 case MachineOperand::MO_RegisterMask:
425 // Ignore call clobbers.
426 return None;
427 }
428 }
429
430 // Replace TAILJMP opcodes with their equivalent opcodes that have encoding
431 // information.
432 static unsigned convertTailJumpOpcode(unsigned Opcode) {
433 switch (Opcode) {
434 case X86::TAILJMPr:
435 Opcode = X86::JMP32r;
436 break;
437 case X86::TAILJMPm:
438 Opcode = X86::JMP32m;
439 break;
440 case X86::TAILJMPr64:
441 Opcode = X86::JMP64r;
442 break;
443 case X86::TAILJMPm64:
444 Opcode = X86::JMP64m;
445 break;
446 case X86::TAILJMPr64_REX:
447 Opcode = X86::JMP64r_REX;
448 break;
449 case X86::TAILJMPm64_REX:
450 Opcode = X86::JMP64m_REX;
451 break;
452 case X86::TAILJMPd:
453 case X86::TAILJMPd64:
454 Opcode = X86::JMP_1;
455 break;
456 case X86::TAILJMPd_CC:
457 case X86::TAILJMPd64_CC:
458 Opcode = X86::JCC_1;
459 break;
460 }
461
462 return Opcode;
463 }
464
465 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
466 OutMI.setOpcode(MI->getOpcode());
467
468 for (const MachineOperand &MO : MI->operands())
469 if (auto MaybeMCOp = LowerMachineOperand(MI, MO))
470 OutMI.addOperand(MaybeMCOp.getValue());
471
472 // Handle a few special cases to eliminate operand modifiers.
473 switch (OutMI.getOpcode()) {
474 case X86::LEA64_32r:
475 case X86::LEA64r:
476 case X86::LEA16r:
477 case X86::LEA32r:
478 // LEA should have a segment register, but it must be empty.
479 assert(OutMI.getNumOperands() == 1 + X86::AddrNumOperands &&
480 "Unexpected # of LEA operands");
481 assert(OutMI.getOperand(1 + X86::AddrSegmentReg).getReg() == 0 &&
482 "LEA has segment specified!");
483 break;
484
485 // Commute operands to get a smaller encoding by using VEX.R instead of VEX.B
486 // if one of the registers is extended, but other isn't.
487 case X86::VMOVZPQILo2PQIrr:
488 case X86::VMOVAPDrr:
489 case X86::VMOVAPDYrr:
490 case X86::VMOVAPSrr:
491 case X86::VMOVAPSYrr:
492 case X86::VMOVDQArr:
493 case X86::VMOVDQAYrr:
494 case X86::VMOVDQUrr:
495 case X86::VMOVDQUYrr:
496 case X86::VMOVUPDrr:
497 case X86::VMOVUPDYrr:
498 case X86::VMOVUPSrr:
499 case X86::VMOVUPSYrr: {
500 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
501 X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg())) {
502 unsigned NewOpc;
503 switch (OutMI.getOpcode()) {
504 default: llvm_unreachable("Invalid opcode");
505 case X86::VMOVZPQILo2PQIrr: NewOpc = X86::VMOVPQI2QIrr; break;
506 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
507 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
508 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break;
509 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
510 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break;
511 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
512 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break;
513 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
514 case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break;
515 case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
516 case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break;
517 case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
518 }
519 OutMI.setOpcode(NewOpc);
520 }
521 break;
522 }
523 case X86::VMOVSDrr:
524 case X86::VMOVSSrr: {
525 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
526 X86II::isX86_64ExtendedReg(OutMI.getOperand(2).getReg())) {
527 unsigned NewOpc;
528 switch (OutMI.getOpcode()) {
529 default: llvm_unreachable("Invalid opcode");
530 case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV; break;
531 case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV; break;
532 }
533 OutMI.setOpcode(NewOpc);
534 }
535 break;
536 }
537
538 // CALL64r, CALL64pcrel32 - These instructions used to have
539 // register inputs modeled as normal uses instead of implicit uses. As such,
540 // they we used to truncate off all but the first operand (the callee). This
541 // issue seems to have been fixed at some point. This assert verifies that.
542 case X86::CALL64r:
543 case X86::CALL64pcrel32:
544 assert(OutMI.getNumOperands() == 1 && "Unexpected number of operands!");
545 break;
546
547 case X86::EH_RETURN:
548 case X86::EH_RETURN64: {
549 OutMI = MCInst();
550 OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget()));
551 break;
552 }
553
554 case X86::CLEANUPRET: {
555 // Replace CLEANUPRET with the appropriate RET.
556 OutMI = MCInst();
557 OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget()));
558 break;
559 }
560
561 case X86::CATCHRET: {
562 // Replace CATCHRET with the appropriate RET.
563 const X86Subtarget &Subtarget = AsmPrinter.getSubtarget();
564 unsigned ReturnReg = Subtarget.is64Bit() ? X86::RAX : X86::EAX;
565 OutMI = MCInst();
566 OutMI.setOpcode(getRetOpcode(Subtarget));
567 OutMI.addOperand(MCOperand::createReg(ReturnReg));
568 break;
569 }
570
571 // TAILJMPd, TAILJMPd64, TailJMPd_cc - Lower to the correct jump
572 // instruction.
573 case X86::TAILJMPr:
574 case X86::TAILJMPr64:
575 case X86::TAILJMPr64_REX:
576 case X86::TAILJMPd:
577 case X86::TAILJMPd64:
578 assert(OutMI.getNumOperands() == 1 && "Unexpected number of operands!");
579 OutMI.setOpcode(convertTailJumpOpcode(OutMI.getOpcode()));
580 break;
581
582 case X86::TAILJMPd_CC:
583 case X86::TAILJMPd64_CC:
584 assert(OutMI.getNumOperands() == 2 && "Unexpected number of operands!");
585 OutMI.setOpcode(convertTailJumpOpcode(OutMI.getOpcode()));
586 break;
587
588 case X86::TAILJMPm:
589 case X86::TAILJMPm64:
590 case X86::TAILJMPm64_REX:
591 assert(OutMI.getNumOperands() == X86::AddrNumOperands &&
592 "Unexpected number of operands!");
593 OutMI.setOpcode(convertTailJumpOpcode(OutMI.getOpcode()));
594 break;
595
596 case X86::DEC16r:
597 case X86::DEC32r:
598 case X86::INC16r:
599 case X86::INC32r:
600 // If we aren't in 64-bit mode we can use the 1-byte inc/dec instructions.
601 if (!AsmPrinter.getSubtarget().is64Bit()) {
602 unsigned Opcode;
603 switch (OutMI.getOpcode()) {
604 default: llvm_unreachable("Invalid opcode");
605 case X86::DEC16r: Opcode = X86::DEC16r_alt; break;
606 case X86::DEC32r: Opcode = X86::DEC32r_alt; break;
607 case X86::INC16r: Opcode = X86::INC16r_alt; break;
608 case X86::INC32r: Opcode = X86::INC32r_alt; break;
609 }
610 OutMI.setOpcode(Opcode);
611 }
612 break;
613
614 // We don't currently select the correct instruction form for instructions
615 // which have a short %eax, etc. form. Handle this by custom lowering, for
616 // now.
617 //
618 // Note, we are currently not handling the following instructions:
619 // MOV64ao8, MOV64o8a
620 // XCHG16ar, XCHG32ar, XCHG64ar
621 case X86::MOV8mr_NOREX:
622 case X86::MOV8mr:
623 case X86::MOV8rm_NOREX:
624 case X86::MOV8rm:
625 case X86::MOV16mr:
626 case X86::MOV16rm:
627 case X86::MOV32mr:
628 case X86::MOV32rm: {
629 unsigned NewOpc;
630 switch (OutMI.getOpcode()) {
631 default: llvm_unreachable("Invalid opcode");
632 case X86::MOV8mr_NOREX:
633 case X86::MOV8mr: NewOpc = X86::MOV8o32a; break;
634 case X86::MOV8rm_NOREX:
635 case X86::MOV8rm: NewOpc = X86::MOV8ao32; break;
636 case X86::MOV16mr: NewOpc = X86::MOV16o32a; break;
637 case X86::MOV16rm: NewOpc = X86::MOV16ao32; break;
638 case X86::MOV32mr: NewOpc = X86::MOV32o32a; break;
639 case X86::MOV32rm: NewOpc = X86::MOV32ao32; break;
640 }
641 SimplifyShortMoveForm(AsmPrinter, OutMI, NewOpc);
642 break;
643 }
644
645 case X86::ADC8ri: case X86::ADC16ri: case X86::ADC32ri: case X86::ADC64ri32:
646 case X86::ADD8ri: case X86::ADD16ri: case X86::ADD32ri: case X86::ADD64ri32:
647 case X86::AND8ri: case X86::AND16ri: case X86::AND32ri: case X86::AND64ri32:
648 case X86::CMP8ri: case X86::CMP16ri: case X86::CMP32ri: case X86::CMP64ri32:
649 case X86::OR8ri: case X86::OR16ri: case X86::OR32ri: case X86::OR64ri32:
650 case X86::SBB8ri: case X86::SBB16ri: case X86::SBB32ri: case X86::SBB64ri32:
651 case X86::SUB8ri: case X86::SUB16ri: case X86::SUB32ri: case X86::SUB64ri32:
652 case X86::TEST8ri:case X86::TEST16ri:case X86::TEST32ri:case X86::TEST64ri32:
653 case X86::XOR8ri: case X86::XOR16ri: case X86::XOR32ri: case X86::XOR64ri32: {
654 unsigned NewOpc;
655 switch (OutMI.getOpcode()) {
656 default: llvm_unreachable("Invalid opcode");
657 case X86::ADC8ri: NewOpc = X86::ADC8i8; break;
658 case X86::ADC16ri: NewOpc = X86::ADC16i16; break;
659 case X86::ADC32ri: NewOpc = X86::ADC32i32; break;
660 case X86::ADC64ri32: NewOpc = X86::ADC64i32; break;
661 case X86::ADD8ri: NewOpc = X86::ADD8i8; break;
662 case X86::ADD16ri: NewOpc = X86::ADD16i16; break;
663 case X86::ADD32ri: NewOpc = X86::ADD32i32; break;
664 case X86::ADD64ri32: NewOpc = X86::ADD64i32; break;
665 case X86::AND8ri: NewOpc = X86::AND8i8; break;
666 case X86::AND16ri: NewOpc = X86::AND16i16; break;
667 case X86::AND32ri: NewOpc = X86::AND32i32; break;
668 case X86::AND64ri32: NewOpc = X86::AND64i32; break;
669 case X86::CMP8ri: NewOpc = X86::CMP8i8; break;
670 case X86::CMP16ri: NewOpc = X86::CMP16i16; break;
671 case X86::CMP32ri: NewOpc = X86::CMP32i32; break;
672 case X86::CMP64ri32: NewOpc = X86::CMP64i32; break;
673 case X86::OR8ri: NewOpc = X86::OR8i8; break;
674 case X86::OR16ri: NewOpc = X86::OR16i16; break;
675 case X86::OR32ri: NewOpc = X86::OR32i32; break;
676 case X86::OR64ri32: NewOpc = X86::OR64i32; break;
677 case X86::SBB8ri: NewOpc = X86::SBB8i8; break;
678 case X86::SBB16ri: NewOpc = X86::SBB16i16; break;
679 case X86::SBB32ri: NewOpc = X86::SBB32i32; break;
680 case X86::SBB64ri32: NewOpc = X86::SBB64i32; break;
681 case X86::SUB8ri: NewOpc = X86::SUB8i8; break;
682 case X86::SUB16ri: NewOpc = X86::SUB16i16; break;
683 case X86::SUB32ri: NewOpc = X86::SUB32i32; break;
684 case X86::SUB64ri32: NewOpc = X86::SUB64i32; break;
685 case X86::TEST8ri: NewOpc = X86::TEST8i8; break;
686 case X86::TEST16ri: NewOpc = X86::TEST16i16; break;
687 case X86::TEST32ri: NewOpc = X86::TEST32i32; break;
688 case X86::TEST64ri32: NewOpc = X86::TEST64i32; break;
689 case X86::XOR8ri: NewOpc = X86::XOR8i8; break;
690 case X86::XOR16ri: NewOpc = X86::XOR16i16; break;
691 case X86::XOR32ri: NewOpc = X86::XOR32i32; break;
692 case X86::XOR64ri32: NewOpc = X86::XOR64i32; break;
693 }
694 SimplifyShortImmForm(OutMI, NewOpc);
695 break;
696 }
697
698 // Try to shrink some forms of movsx.
699 case X86::MOVSX16rr8:
700 case X86::MOVSX32rr16:
701 case X86::MOVSX64rr32:
702 SimplifyMOVSX(OutMI);
703 break;
704 }
705 }
706
707 void X86AsmPrinter::LowerTlsAddr(X86MCInstLower &MCInstLowering,
708 const MachineInstr &MI) {
709 bool Is64Bits = MI.getOpcode() == X86::TLS_addr64 ||
710 MI.getOpcode() == X86::TLS_base_addr64;
711 MCContext &Ctx = OutStreamer->getContext();
712
713 MCSymbolRefExpr::VariantKind SRVK;
714 switch (MI.getOpcode()) {
715 case X86::TLS_addr32:
716 case X86::TLS_addr64:
717 SRVK = MCSymbolRefExpr::VK_TLSGD;
718 break;
719 case X86::TLS_base_addr32:
720 SRVK = MCSymbolRefExpr::VK_TLSLDM;
721 break;
722 case X86::TLS_base_addr64:
723 SRVK = MCSymbolRefExpr::VK_TLSLD;
724 break;
725 default:
726 llvm_unreachable("unexpected opcode");
727 }
728
729 const MCSymbolRefExpr *Sym = MCSymbolRefExpr::create(
730 MCInstLowering.GetSymbolFromOperand(MI.getOperand(3)), SRVK, Ctx);
731
732 // As of binutils 2.32, ld has a bogus TLS relaxation error when the GD/LD
733 // code sequence using R_X86_64_GOTPCREL (instead of R_X86_64_GOTPCRELX) is
734 // attempted to be relaxed to IE/LE (binutils PR24784). Work around the bug by
735 // only using GOT when GOTPCRELX is enabled.
736 // TODO Delete the workaround when GOTPCRELX becomes commonplace.
737 bool UseGot = MMI->getModule()->getRtLibUseGOT() &&
738 Ctx.getAsmInfo()->canRelaxRelocations();
739
740 if (Is64Bits) {
741 bool NeedsPadding = SRVK == MCSymbolRefExpr::VK_TLSGD;
742 if (NeedsPadding)
743 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
744 EmitAndCountInstruction(MCInstBuilder(X86::LEA64r)
745 .addReg(X86::RDI)
746 .addReg(X86::RIP)
747 .addImm(1)
748 .addReg(0)
749 .addExpr(Sym)
750 .addReg(0));
751 const MCSymbol *TlsGetAddr = Ctx.getOrCreateSymbol("__tls_get_addr");
752 if (NeedsPadding) {
753 if (!UseGot)
754 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
755 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
756 EmitAndCountInstruction(MCInstBuilder(X86::REX64_PREFIX));
757 }
758 if (UseGot) {
759 const MCExpr *Expr = MCSymbolRefExpr::create(
760 TlsGetAddr, MCSymbolRefExpr::VK_GOTPCREL, Ctx);
761 EmitAndCountInstruction(MCInstBuilder(X86::CALL64m)
762 .addReg(X86::RIP)
763 .addImm(1)
764 .addReg(0)
765 .addExpr(Expr)
766 .addReg(0));
767 } else {
768 EmitAndCountInstruction(
769 MCInstBuilder(X86::CALL64pcrel32)
770 .addExpr(MCSymbolRefExpr::create(TlsGetAddr,
771 MCSymbolRefExpr::VK_PLT, Ctx)));
772 }
773 } else {
774 if (SRVK == MCSymbolRefExpr::VK_TLSGD && !UseGot) {
775 EmitAndCountInstruction(MCInstBuilder(X86::LEA32r)
776 .addReg(X86::EAX)
777 .addReg(0)
778 .addImm(1)
779 .addReg(X86::EBX)
780 .addExpr(Sym)
781 .addReg(0));
782 } else {
783 EmitAndCountInstruction(MCInstBuilder(X86::LEA32r)
784 .addReg(X86::EAX)
785 .addReg(X86::EBX)
786 .addImm(1)
787 .addReg(0)
788 .addExpr(Sym)
789 .addReg(0));
790 }
791
792 const MCSymbol *TlsGetAddr = Ctx.getOrCreateSymbol("___tls_get_addr");
793 if (UseGot) {
794 const MCExpr *Expr =
795 MCSymbolRefExpr::create(TlsGetAddr, MCSymbolRefExpr::VK_GOT, Ctx);
796 EmitAndCountInstruction(MCInstBuilder(X86::CALL32m)
797 .addReg(X86::EBX)
798 .addImm(1)
799 .addReg(0)
800 .addExpr(Expr)
801 .addReg(0));
802 } else {
803 EmitAndCountInstruction(
804 MCInstBuilder(X86::CALLpcrel32)
805 .addExpr(MCSymbolRefExpr::create(TlsGetAddr,
806 MCSymbolRefExpr::VK_PLT, Ctx)));
807 }
808 }
809 }
810
811 /// Emit the largest nop instruction smaller than or equal to \p NumBytes
812 /// bytes. Return the size of nop emitted.
813 static unsigned EmitNop(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
814 const MCSubtargetInfo &STI) {
815 // This works only for 64bit. For 32bit we have to do additional checking if
816 // the CPU supports multi-byte nops.
817 assert(Is64Bit && "EmitNops only supports X86-64");
818
819 unsigned NopSize;
820 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg;
821 IndexReg = Displacement = SegmentReg = 0;
822 BaseReg = X86::RAX;
823 ScaleVal = 1;
824 switch (NumBytes) {
825 case 0:
826 llvm_unreachable("Zero nops?");
827 break;
828 case 1:
829 NopSize = 1;
830 Opc = X86::NOOP;
831 break;
832 case 2:
833 NopSize = 2;
834 Opc = X86::XCHG16ar;
835 break;
836 case 3:
837 NopSize = 3;
838 Opc = X86::NOOPL;
839 break;
840 case 4:
841 NopSize = 4;
842 Opc = X86::NOOPL;
843 Displacement = 8;
844 break;
845 case 5:
846 NopSize = 5;
847 Opc = X86::NOOPL;
848 Displacement = 8;
849 IndexReg = X86::RAX;
850 break;
851 case 6:
852 NopSize = 6;
853 Opc = X86::NOOPW;
854 Displacement = 8;
855 IndexReg = X86::RAX;
856 break;
857 case 7:
858 NopSize = 7;
859 Opc = X86::NOOPL;
860 Displacement = 512;
861 break;
862 case 8:
863 NopSize = 8;
864 Opc = X86::NOOPL;
865 Displacement = 512;
866 IndexReg = X86::RAX;
867 break;
868 case 9:
869 NopSize = 9;
870 Opc = X86::NOOPW;
871 Displacement = 512;
872 IndexReg = X86::RAX;
873 break;
874 default:
875 NopSize = 10;
876 Opc = X86::NOOPW;
877 Displacement = 512;
878 IndexReg = X86::RAX;
879 SegmentReg = X86::CS;
880 break;
881 }
882
883 unsigned NumPrefixes = std::min(NumBytes - NopSize, 5U);
884 NopSize += NumPrefixes;
885 for (unsigned i = 0; i != NumPrefixes; ++i)
886 OS.EmitBytes("\x66");
887
888 switch (Opc) {
889 default: llvm_unreachable("Unexpected opcode");
890 case X86::NOOP:
891 OS.EmitInstruction(MCInstBuilder(Opc), STI);
892 break;
893 case X86::XCHG16ar:
894 OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX).addReg(X86::AX), STI);
895 break;
896 case X86::NOOPL:
897 case X86::NOOPW:
898 OS.EmitInstruction(MCInstBuilder(Opc)
899 .addReg(BaseReg)
900 .addImm(ScaleVal)
901 .addReg(IndexReg)
902 .addImm(Displacement)
903 .addReg(SegmentReg),
904 STI);
905 break;
906 }
907 assert(NopSize <= NumBytes && "We overemitted?");
908 return NopSize;
909 }
910
911 /// Emit the optimal amount of multi-byte nops on X86.
912 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
913 const MCSubtargetInfo &STI) {
914 unsigned NopsToEmit = NumBytes;
915 (void)NopsToEmit;
916 while (NumBytes) {
917 NumBytes -= EmitNop(OS, NumBytes, Is64Bit, STI);
918 assert(NopsToEmit >= NumBytes && "Emitted more than I asked for!");
919 }
920 }
921
922 void X86AsmPrinter::LowerSTATEPOINT(const MachineInstr &MI,
923 X86MCInstLower &MCIL) {
924 assert(Subtarget->is64Bit() && "Statepoint currently only supports X86-64");
925
926 StatepointOpers SOpers(&MI);
927 if (unsigned PatchBytes = SOpers.getNumPatchBytes()) {
928 EmitNops(*OutStreamer, PatchBytes, Subtarget->is64Bit(),
929 getSubtargetInfo());
930 } else {
931 // Lower call target and choose correct opcode
932 const MachineOperand &CallTarget = SOpers.getCallTarget();
933 MCOperand CallTargetMCOp;
934 unsigned CallOpcode;
935 switch (CallTarget.getType()) {
936 case MachineOperand::MO_GlobalAddress:
937 case MachineOperand::MO_ExternalSymbol:
938 CallTargetMCOp = MCIL.LowerSymbolOperand(
939 CallTarget, MCIL.GetSymbolFromOperand(CallTarget));
940 CallOpcode = X86::CALL64pcrel32;
941 // Currently, we only support relative addressing with statepoints.
942 // Otherwise, we'll need a scratch register to hold the target
943 // address. You'll fail asserts during load & relocation if this
944 // symbol is to far away. (TODO: support non-relative addressing)
945 break;
946 case MachineOperand::MO_Immediate:
947 CallTargetMCOp = MCOperand::createImm(CallTarget.getImm());
948 CallOpcode = X86::CALL64pcrel32;
949 // Currently, we only support relative addressing with statepoints.
950 // Otherwise, we'll need a scratch register to hold the target
951 // immediate. You'll fail asserts during load & relocation if this
952 // address is to far away. (TODO: support non-relative addressing)
953 break;
954 case MachineOperand::MO_Register:
955 // FIXME: Add retpoline support and remove this.
956 if (Subtarget->useRetpolineIndirectCalls())
957 report_fatal_error("Lowering register statepoints with retpoline not "
958 "yet implemented.");
959 CallTargetMCOp = MCOperand::createReg(CallTarget.getReg());
960 CallOpcode = X86::CALL64r;
961 break;
962 default:
963 llvm_unreachable("Unsupported operand type in statepoint call target");
964 break;
965 }
966
967 // Emit call
968 MCInst CallInst;
969 CallInst.setOpcode(CallOpcode);
970 CallInst.addOperand(CallTargetMCOp);
971 OutStreamer->EmitInstruction(CallInst, getSubtargetInfo());
972 }
973
974 // Record our statepoint node in the same section used by STACKMAP
975 // and PATCHPOINT
976 SM.recordStatepoint(MI);
977 }
978
979 void X86AsmPrinter::LowerFAULTING_OP(const MachineInstr &FaultingMI,
980 X86MCInstLower &MCIL) {
981 // FAULTING_LOAD_OP <def>, <faltinf type>, <MBB handler>,
982 // <opcode>, <operands>
983
984 Register DefRegister = FaultingMI.getOperand(0).getReg();
985 FaultMaps::FaultKind FK =
986 static_cast<FaultMaps::FaultKind>(FaultingMI.getOperand(1).getImm());
987 MCSymbol *HandlerLabel = FaultingMI.getOperand(2).getMBB()->getSymbol();
988 unsigned Opcode = FaultingMI.getOperand(3).getImm();
989 unsigned OperandsBeginIdx = 4;
990
991 assert(FK < FaultMaps::FaultKindMax && "Invalid Faulting Kind!");
992 FM.recordFaultingOp(FK, HandlerLabel);
993
994 MCInst MI;
995 MI.setOpcode(Opcode);
996
997 if (DefRegister != X86::NoRegister)
998 MI.addOperand(MCOperand::createReg(DefRegister));
999
1000 for (auto I = FaultingMI.operands_begin() + OperandsBeginIdx,
1001 E = FaultingMI.operands_end();
1002 I != E; ++I)
1003 if (auto MaybeOperand = MCIL.LowerMachineOperand(&FaultingMI, *I))
1004 MI.addOperand(MaybeOperand.getValue());
1005
1006 OutStreamer->AddComment("on-fault: " + HandlerLabel->getName());
1007 OutStreamer->EmitInstruction(MI, getSubtargetInfo());
1008 }
1009
1010 void X86AsmPrinter::LowerFENTRY_CALL(const MachineInstr &MI,
1011 X86MCInstLower &MCIL) {
1012 bool Is64Bits = Subtarget->is64Bit();
1013 MCContext &Ctx = OutStreamer->getContext();
1014 MCSymbol *fentry = Ctx.getOrCreateSymbol("__fentry__");
1015 const MCSymbolRefExpr *Op =
1016 MCSymbolRefExpr::create(fentry, MCSymbolRefExpr::VK_None, Ctx);
1017
1018 EmitAndCountInstruction(
1019 MCInstBuilder(Is64Bits ? X86::CALL64pcrel32 : X86::CALLpcrel32)
1020 .addExpr(Op));
1021 }
1022
1023 void X86AsmPrinter::LowerPATCHABLE_OP(const MachineInstr &MI,
1024 X86MCInstLower &MCIL) {
1025 // PATCHABLE_OP minsize, opcode, operands
1026
1027 unsigned MinSize = MI.getOperand(0).getImm();
1028 unsigned Opcode = MI.getOperand(1).getImm();
1029
1030 MCInst MCI;
1031 MCI.setOpcode(Opcode);
1032 for (auto &MO : make_range(MI.operands_begin() + 2, MI.operands_end()))
1033 if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO))
1034 MCI.addOperand(MaybeOperand.getValue());
1035
1036 SmallString<256> Code;
1037 SmallVector<MCFixup, 4> Fixups;
1038 raw_svector_ostream VecOS(Code);
1039 CodeEmitter->encodeInstruction(MCI, VecOS, Fixups, getSubtargetInfo());
1040
1041 if (Code.size() < MinSize) {
1042 if (MinSize == 2 && Opcode == X86::PUSH64r) {
1043 // This is an optimization that lets us get away without emitting a nop in
1044 // many cases.
1045 //
1046 // NB! In some cases the encoding for PUSH64r (e.g. PUSH64r %r9) takes two
1047 // bytes too, so the check on MinSize is important.
1048 MCI.setOpcode(X86::PUSH64rmr);
1049 } else {
1050 unsigned NopSize = EmitNop(*OutStreamer, MinSize, Subtarget->is64Bit(),
1051 getSubtargetInfo());
1052 assert(NopSize == MinSize && "Could not implement MinSize!");
1053 (void)NopSize;
1054 }
1055 }
1056
1057 OutStreamer->EmitInstruction(MCI, getSubtargetInfo());
1058 }
1059
1060 // Lower a stackmap of the form:
1061 // <id>, <shadowBytes>, ...
1062 void X86AsmPrinter::LowerSTACKMAP(const MachineInstr &MI) {
1063 SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
1064 SM.recordStackMap(MI);
1065 unsigned NumShadowBytes = MI.getOperand(1).getImm();
1066 SMShadowTracker.reset(NumShadowBytes);
1067 }
1068
1069 // Lower a patchpoint of the form:
1070 // [<def>], <id>, <numBytes>, <target>, <numArgs>, <cc>, ...
1071 void X86AsmPrinter::LowerPATCHPOINT(const MachineInstr &MI,
1072 X86MCInstLower &MCIL) {
1073 assert(Subtarget->is64Bit() && "Patchpoint currently only supports X86-64");
1074
1075 SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
1076
1077 SM.recordPatchPoint(MI);
1078
1079 PatchPointOpers opers(&MI);
1080 unsigned ScratchIdx = opers.getNextScratchIdx();
1081 unsigned EncodedBytes = 0;
1082 const MachineOperand &CalleeMO = opers.getCallTarget();
1083
1084 // Check for null target. If target is non-null (i.e. is non-zero or is
1085 // symbolic) then emit a call.
1086 if (!(CalleeMO.isImm() && !CalleeMO.getImm())) {
1087 MCOperand CalleeMCOp;
1088 switch (CalleeMO.getType()) {
1089 default:
1090 /// FIXME: Add a verifier check for bad callee types.
1091 llvm_unreachable("Unrecognized callee operand type.");
1092 case MachineOperand::MO_Immediate:
1093 if (CalleeMO.getImm())
1094 CalleeMCOp = MCOperand::createImm(CalleeMO.getImm());
1095 break;
1096 case MachineOperand::MO_ExternalSymbol:
1097 case MachineOperand::MO_GlobalAddress:
1098 CalleeMCOp = MCIL.LowerSymbolOperand(CalleeMO,
1099 MCIL.GetSymbolFromOperand(CalleeMO));
1100 break;
1101 }
1102
1103 // Emit MOV to materialize the target address and the CALL to target.
1104 // This is encoded with 12-13 bytes, depending on which register is used.
1105 Register ScratchReg = MI.getOperand(ScratchIdx).getReg();
1106 if (X86II::isX86_64ExtendedReg(ScratchReg))
1107 EncodedBytes = 13;
1108 else
1109 EncodedBytes = 12;
1110
1111 EmitAndCountInstruction(
1112 MCInstBuilder(X86::MOV64ri).addReg(ScratchReg).addOperand(CalleeMCOp));
1113 // FIXME: Add retpoline support and remove this.
1114 if (Subtarget->useRetpolineIndirectCalls())
1115 report_fatal_error(
1116 "Lowering patchpoint with retpoline not yet implemented.");
1117 EmitAndCountInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg));
1118 }
1119
1120 // Emit padding.
1121 unsigned NumBytes = opers.getNumPatchBytes();
1122 assert(NumBytes >= EncodedBytes &&
1123 "Patchpoint can't request size less than the length of a call.");
1124
1125 EmitNops(*OutStreamer, NumBytes - EncodedBytes, Subtarget->is64Bit(),
1126 getSubtargetInfo());
1127 }
1128
1129 void X86AsmPrinter::LowerPATCHABLE_EVENT_CALL(const MachineInstr &MI,
1130 X86MCInstLower &MCIL) {
1131 assert(Subtarget->is64Bit() && "XRay custom events only supports X86-64");
1132
1133 // We want to emit the following pattern, which follows the x86 calling
1134 // convention to prepare for the trampoline call to be patched in.
1135 //
1136 // .p2align 1, ...
1137 // .Lxray_event_sled_N:
1138 // jmp +N // jump across the instrumentation sled
1139 // ... // set up arguments in register
1140 // callq __xray_CustomEvent@plt // force dependency to symbol
1141 // ...
1142 // <jump here>
1143 //
1144 // After patching, it would look something like:
1145 //
1146 // nopw (2-byte nop)
1147 // ...
1148 // callq __xrayCustomEvent // already lowered
1149 // ...
1150 //
1151 // ---
1152 // First we emit the label and the jump.
1153 auto CurSled = OutContext.createTempSymbol("xray_event_sled_", true);
1154 OutStreamer->AddComment("# XRay Custom Event Log");
1155 OutStreamer->EmitCodeAlignment(2);
1156 OutStreamer->EmitLabel(CurSled);
1157
1158 // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as
1159 // an operand (computed as an offset from the jmp instruction).
1160 // FIXME: Find another less hacky way do force the relative jump.
1161 OutStreamer->EmitBinaryData("\xeb\x0f");
1162
1163 // The default C calling convention will place two arguments into %rcx and
1164 // %rdx -- so we only work with those.
1165 unsigned DestRegs[] = {X86::RDI, X86::RSI};
1166 bool UsedMask[] = {false, false};
1167 // Filled out in loop.
1168 unsigned SrcRegs[] = {0, 0};
1169
1170 // Then we put the operands in the %rdi and %rsi registers. We spill the
1171 // values in the register before we clobber them, and mark them as used in
1172 // UsedMask. In case the arguments are already in the correct register, we use
1173 // emit nops appropriately sized to keep the sled the same size in every
1174 // situation.
1175 for (unsigned I = 0; I < MI.getNumOperands(); ++I)
1176 if (auto Op = MCIL.LowerMachineOperand(&MI, MI.getOperand(I))) {
1177 assert(Op->isReg() && "Only support arguments in registers");
1178 SrcRegs[I] = Op->getReg();
1179 if (SrcRegs[I] != DestRegs[I]) {
1180 UsedMask[I] = true;
1181 EmitAndCountInstruction(
1182 MCInstBuilder(X86::PUSH64r).addReg(DestRegs[I]));
1183 } else {
1184 EmitNops(*OutStreamer, 4, Subtarget->is64Bit(), getSubtargetInfo());
1185 }
1186 }
1187
1188 // Now that the register values are stashed, mov arguments into place.
1189 for (unsigned I = 0; I < MI.getNumOperands(); ++I)
1190 if (SrcRegs[I] != DestRegs[I])
1191 EmitAndCountInstruction(
1192 MCInstBuilder(X86::MOV64rr).addReg(DestRegs[I]).addReg(SrcRegs[I]));
1193
1194 // We emit a hard dependency on the __xray_CustomEvent symbol, which is the
1195 // name of the trampoline to be implemented by the XRay runtime.
1196 auto TSym = OutContext.getOrCreateSymbol("__xray_CustomEvent");
1197 MachineOperand TOp = MachineOperand::CreateMCSymbol(TSym);
1198 if (isPositionIndependent())
1199 TOp.setTargetFlags(X86II::MO_PLT);
1200
1201 // Emit the call instruction.
1202 EmitAndCountInstruction(MCInstBuilder(X86::CALL64pcrel32)
1203 .addOperand(MCIL.LowerSymbolOperand(TOp, TSym)));
1204
1205 // Restore caller-saved and used registers.
1206 for (unsigned I = sizeof UsedMask; I-- > 0;)
1207 if (UsedMask[I])
1208 EmitAndCountInstruction(MCInstBuilder(X86::POP64r).addReg(DestRegs[I]));
1209 else
1210 EmitNops(*OutStreamer, 1, Subtarget->is64Bit(), getSubtargetInfo());
1211
1212 OutStreamer->AddComment("xray custom event end.");
1213
1214 // Record the sled version. Older versions of this sled were spelled
1215 // differently, so we let the runtime handle the different offsets we're
1216 // using.
1217 recordSled(CurSled, MI, SledKind::CUSTOM_EVENT, 1);
1218 }
1219
1220 void X86AsmPrinter::LowerPATCHABLE_TYPED_EVENT_CALL(const MachineInstr &MI,
1221 X86MCInstLower &MCIL) {
1222 assert(Subtarget->is64Bit() && "XRay typed events only supports X86-64");
1223
1224 // We want to emit the following pattern, which follows the x86 calling
1225 // convention to prepare for the trampoline call to be patched in.
1226 //
1227 // .p2align 1, ...
1228 // .Lxray_event_sled_N:
1229 // jmp +N // jump across the instrumentation sled
1230 // ... // set up arguments in register
1231 // callq __xray_TypedEvent@plt // force dependency to symbol
1232 // ...
1233 // <jump here>
1234 //
1235 // After patching, it would look something like:
1236 //
1237 // nopw (2-byte nop)
1238 // ...
1239 // callq __xrayTypedEvent // already lowered
1240 // ...
1241 //
1242 // ---
1243 // First we emit the label and the jump.
1244 auto CurSled = OutContext.createTempSymbol("xray_typed_event_sled_", true);
1245 OutStreamer->AddComment("# XRay Typed Event Log");
1246 OutStreamer->EmitCodeAlignment(2);
1247 OutStreamer->EmitLabel(CurSled);
1248
1249 // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as
1250 // an operand (computed as an offset from the jmp instruction).
1251 // FIXME: Find another less hacky way do force the relative jump.
1252 OutStreamer->EmitBinaryData("\xeb\x14");
1253
1254 // An x86-64 convention may place three arguments into %rcx, %rdx, and R8,
1255 // so we'll work with those. Or we may be called via SystemV, in which case
1256 // we don't have to do any translation.
1257 unsigned DestRegs[] = {X86::RDI, X86::RSI, X86::RDX};
1258 bool UsedMask[] = {false, false, false};
1259
1260 // Will fill out src regs in the loop.
1261 unsigned SrcRegs[] = {0, 0, 0};
1262
1263 // Then we put the operands in the SystemV registers. We spill the values in
1264 // the registers before we clobber them, and mark them as used in UsedMask.
1265 // In case the arguments are already in the correct register, we emit nops
1266 // appropriately sized to keep the sled the same size in every situation.
1267 for (unsigned I = 0; I < MI.getNumOperands(); ++I)
1268 if (auto Op = MCIL.LowerMachineOperand(&MI, MI.getOperand(I))) {
1269 // TODO: Is register only support adequate?
1270 assert(Op->isReg() && "Only supports arguments in registers");
1271 SrcRegs[I] = Op->getReg();
1272 if (SrcRegs[I] != DestRegs[I]) {
1273 UsedMask[I] = true;
1274 EmitAndCountInstruction(
1275 MCInstBuilder(X86::PUSH64r).addReg(DestRegs[I]));
1276 } else {
1277 EmitNops(*OutStreamer, 4, Subtarget->is64Bit(), getSubtargetInfo());
1278 }
1279 }
1280
1281 // In the above loop we only stash all of the destination registers or emit
1282 // nops if the arguments are already in the right place. Doing the actually
1283 // moving is postponed until after all the registers are stashed so nothing
1284 // is clobbers. We've already added nops to account for the size of mov and
1285 // push if the register is in the right place, so we only have to worry about
1286 // emitting movs.
1287 for (unsigned I = 0; I < MI.getNumOperands(); ++I)
1288 if (UsedMask[I])
1289 EmitAndCountInstruction(
1290 MCInstBuilder(X86::MOV64rr).addReg(DestRegs[I]).addReg(SrcRegs[I]));
1291
1292 // We emit a hard dependency on the __xray_TypedEvent symbol, which is the
1293 // name of the trampoline to be implemented by the XRay runtime.
1294 auto TSym = OutContext.getOrCreateSymbol("__xray_TypedEvent");
1295 MachineOperand TOp = MachineOperand::CreateMCSymbol(TSym);
1296 if (isPositionIndependent())
1297 TOp.setTargetFlags(X86II::MO_PLT);
1298
1299 // Emit the call instruction.
1300 EmitAndCountInstruction(MCInstBuilder(X86::CALL64pcrel32)
1301 .addOperand(MCIL.LowerSymbolOperand(TOp, TSym)));
1302
1303 // Restore caller-saved and used registers.
1304 for (unsigned I = sizeof UsedMask; I-- > 0;)
1305 if (UsedMask[I])
1306 EmitAndCountInstruction(MCInstBuilder(X86::POP64r).addReg(DestRegs[I]));
1307 else
1308 EmitNops(*OutStreamer, 1, Subtarget->is64Bit(), getSubtargetInfo());
1309
1310 OutStreamer->AddComment("xray typed event end.");
1311
1312 // Record the sled version.
1313 recordSled(CurSled, MI, SledKind::TYPED_EVENT, 0);
1314 }
1315
1316 void X86AsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI,
1317 X86MCInstLower &MCIL) {
1318 // We want to emit the following pattern:
1319 //
1320 // .p2align 1, ...
1321 // .Lxray_sled_N:
1322 // jmp .tmpN
1323 // # 9 bytes worth of noops
1324 //
1325 // We need the 9 bytes because at runtime, we'd be patching over the full 11
1326 // bytes with the following pattern:
1327 //
1328 // mov %r10, <function id, 32-bit> // 6 bytes
1329 // call <relative offset, 32-bits> // 5 bytes
1330 //
1331 auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
1332 OutStreamer->EmitCodeAlignment(2);
1333 OutStreamer->EmitLabel(CurSled);
1334
1335 // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as
1336 // an operand (computed as an offset from the jmp instruction).
1337 // FIXME: Find another less hacky way do force the relative jump.
1338 OutStreamer->EmitBytes("\xeb\x09");
1339 EmitNops(*OutStreamer, 9, Subtarget->is64Bit(), getSubtargetInfo());
1340 recordSled(CurSled, MI, SledKind::FUNCTION_ENTER);
1341 }
1342
1343 void X86AsmPrinter::LowerPATCHABLE_RET(const MachineInstr &MI,
1344 X86MCInstLower &MCIL) {
1345 // Since PATCHABLE_RET takes the opcode of the return statement as an
1346 // argument, we use that to emit the correct form of the RET that we want.
1347 // i.e. when we see this:
1348 //
1349 // PATCHABLE_RET X86::RET ...
1350 //
1351 // We should emit the RET followed by sleds.
1352 //
1353 // .p2align 1, ...
1354 // .Lxray_sled_N:
1355 // ret # or equivalent instruction
1356 // # 10 bytes worth of noops
1357 //
1358 // This just makes sure that the alignment for the next instruction is 2.
1359 auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
1360 OutStreamer->EmitCodeAlignment(2);
1361 OutStreamer->EmitLabel(CurSled);
1362 unsigned OpCode = MI.getOperand(0).getImm();
1363 MCInst Ret;
1364 Ret.setOpcode(OpCode);
1365 for (auto &MO : make_range(MI.operands_begin() + 1, MI.operands_end()))
1366 if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO))
1367 Ret.addOperand(MaybeOperand.getValue());
1368 OutStreamer->EmitInstruction(Ret, getSubtargetInfo());
1369 EmitNops(*OutStreamer, 10, Subtarget->is64Bit(), getSubtargetInfo());
1370 recordSled(CurSled, MI, SledKind::FUNCTION_EXIT);
1371 }
1372
1373 void X86AsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI,
1374 X86MCInstLower &MCIL) {
1375 // Like PATCHABLE_RET, we have the actual instruction in the operands to this
1376 // instruction so we lower that particular instruction and its operands.
1377 // Unlike PATCHABLE_RET though, we put the sled before the JMP, much like how
1378 // we do it for PATCHABLE_FUNCTION_ENTER. The sled should be very similar to
1379 // the PATCHABLE_FUNCTION_ENTER case, followed by the lowering of the actual
1380 // tail call much like how we have it in PATCHABLE_RET.
1381 auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
1382 OutStreamer->EmitCodeAlignment(2);
1383 OutStreamer->EmitLabel(CurSled);
1384 auto Target = OutContext.createTempSymbol();
1385
1386 // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as
1387 // an operand (computed as an offset from the jmp instruction).
1388 // FIXME: Find another less hacky way do force the relative jump.
1389 OutStreamer->EmitBytes("\xeb\x09");
1390 EmitNops(*OutStreamer, 9, Subtarget->is64Bit(), getSubtargetInfo());
1391 OutStreamer->EmitLabel(Target);
1392 recordSled(CurSled, MI, SledKind::TAIL_CALL);
1393
1394 unsigned OpCode = MI.getOperand(0).getImm();
1395 OpCode = convertTailJumpOpcode(OpCode);
1396 MCInst TC;
1397 TC.setOpcode(OpCode);
1398
1399 // Before emitting the instruction, add a comment to indicate that this is
1400 // indeed a tail call.
1401 OutStreamer->AddComment("TAILCALL");
1402 for (auto &MO : make_range(MI.operands_begin() + 1, MI.operands_end()))
1403 if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO))
1404 TC.addOperand(MaybeOperand.getValue());
1405 OutStreamer->EmitInstruction(TC, getSubtargetInfo());
1406 }
1407
1408 // Returns instruction preceding MBBI in MachineFunction.
1409 // If MBBI is the first instruction of the first basic block, returns null.
1410 static MachineBasicBlock::const_iterator
1411 PrevCrossBBInst(MachineBasicBlock::const_iterator MBBI) {
1412 const MachineBasicBlock *MBB = MBBI->getParent();
1413 while (MBBI == MBB->begin()) {
1414 if (MBB == &MBB->getParent()->front())
1415 return MachineBasicBlock::const_iterator();
1416 MBB = MBB->getPrevNode();
1417 MBBI = MBB->end();
1418 }
1419 --MBBI;
1420 return MBBI;
1421 }
1422
1423 static const Constant *getConstantFromPool(const MachineInstr &MI,
1424 const MachineOperand &Op) {
1425 if (!Op.isCPI() || Op.getOffset() != 0)
1426 return nullptr;
1427
1428 ArrayRef<MachineConstantPoolEntry> Constants =
1429 MI.getParent()->getParent()->getConstantPool()->getConstants();
1430 const MachineConstantPoolEntry &ConstantEntry = Constants[Op.getIndex()];
1431
1432 // Bail if this is a machine constant pool entry, we won't be able to dig out
1433 // anything useful.
1434 if (ConstantEntry.isMachineConstantPoolEntry())
1435 return nullptr;
1436
1437 const Constant *C = ConstantEntry.Val.ConstVal;
1438 assert((!C || ConstantEntry.getType() == C->getType()) &&
1439 "Expected a constant of the same type!");
1440 return C;
1441 }
1442
1443 static std::string getShuffleComment(const MachineInstr *MI, unsigned SrcOp1Idx,
1444 unsigned SrcOp2Idx, ArrayRef<int> Mask) {
1445 std::string Comment;
1446
1447 // Compute the name for a register. This is really goofy because we have
1448 // multiple instruction printers that could (in theory) use different
1449 // names. Fortunately most people use the ATT style (outside of Windows)
1450 // and they actually agree on register naming here. Ultimately, this is
1451 // a comment, and so its OK if it isn't perfect.
1452 auto GetRegisterName = [](unsigned RegNum) -> StringRef {
1453 return X86ATTInstPrinter::getRegisterName(RegNum);
1454 };
1455
1456 const MachineOperand &DstOp = MI->getOperand(0);
1457 const MachineOperand &SrcOp1 = MI->getOperand(SrcOp1Idx);
1458 const MachineOperand &SrcOp2 = MI->getOperand(SrcOp2Idx);
1459
1460 StringRef DstName = DstOp.isReg() ? GetRegisterName(DstOp.getReg()) : "mem";
1461 StringRef Src1Name =
1462 SrcOp1.isReg() ? GetRegisterName(SrcOp1.getReg()) : "mem";
1463 StringRef Src2Name =
1464 SrcOp2.isReg() ? GetRegisterName(SrcOp2.getReg()) : "mem";
1465
1466 // One source operand, fix the mask to print all elements in one span.
1467 SmallVector<int, 8> ShuffleMask(Mask.begin(), Mask.end());
1468 if (Src1Name == Src2Name)
1469 for (int i = 0, e = ShuffleMask.size(); i != e; ++i)
1470 if (ShuffleMask[i] >= e)
1471 ShuffleMask[i] -= e;
1472
1473 raw_string_ostream CS(Comment);
1474 CS << DstName;
1475
1476 // Handle AVX512 MASK/MASXZ write mask comments.
1477 // MASK: zmmX {%kY}
1478 // MASKZ: zmmX {%kY} {z}
1479 if (SrcOp1Idx > 1) {
1480 assert((SrcOp1Idx == 2 || SrcOp1Idx == 3) && "Unexpected writemask");
1481
1482 const MachineOperand &WriteMaskOp = MI->getOperand(SrcOp1Idx - 1);
1483 if (WriteMaskOp.isReg()) {
1484 CS << " {%" << GetRegisterName(WriteMaskOp.getReg()) << "}";
1485
1486 if (SrcOp1Idx == 2) {
1487 CS << " {z}";
1488 }
1489 }
1490 }
1491
1492 CS << " = ";
1493
1494 for (int i = 0, e = ShuffleMask.size(); i != e; ++i) {
1495 if (i != 0)
1496 CS << ",";
1497 if (ShuffleMask[i] == SM_SentinelZero) {
1498 CS << "zero";
1499 continue;
1500 }
1501
1502 // Otherwise, it must come from src1 or src2. Print the span of elements
1503 // that comes from this src.
1504 bool isSrc1 = ShuffleMask[i] < (int)e;
1505 CS << (isSrc1 ? Src1Name : Src2Name) << '[';
1506
1507 bool IsFirst = true;
1508 while (i != e && ShuffleMask[i] != SM_SentinelZero &&
1509 (ShuffleMask[i] < (int)e) == isSrc1) {
1510 if (!IsFirst)
1511 CS << ',';
1512 else
1513 IsFirst = false;
1514 if (ShuffleMask[i] == SM_SentinelUndef)
1515 CS << "u";
1516 else
1517 CS << ShuffleMask[i] % (int)e;
1518 ++i;
1519 }
1520 CS << ']';
1521 --i; // For loop increments element #.
1522 }
1523 CS.flush();
1524
1525 return Comment;
1526 }
1527
1528 static void printConstant(const APInt &Val, raw_ostream &CS) {
1529 if (Val.getBitWidth() <= 64) {
1530 CS << Val.getZExtValue();
1531 } else {
1532 // print multi-word constant as (w0,w1)
1533 CS << "(";
1534 for (int i = 0, N = Val.getNumWords(); i < N; ++i) {
1535 if (i > 0)
1536 CS << ",";
1537 CS << Val.getRawData()[i];
1538 }
1539 CS << ")";
1540 }
1541 }
1542
1543 static void printConstant(const APFloat &Flt, raw_ostream &CS) {
1544 SmallString<32> Str;
1545 // Force scientific notation to distinquish from integers.
1546 Flt.toString(Str, 0, 0);
1547 CS << Str;
1548 }
1549
1550 static void printConstant(const Constant *COp, raw_ostream &CS) {
1551 if (isa<UndefValue>(COp)) {
1552 CS << "u";
1553 } else if (auto *CI = dyn_cast<ConstantInt>(COp)) {
1554 printConstant(CI->getValue(), CS);
1555 } else if (auto *CF = dyn_cast<ConstantFP>(COp)) {
1556 printConstant(CF->getValueAPF(), CS);
1557 } else {
1558 CS << "?";
1559 }
1560 }
1561
1562 void X86AsmPrinter::EmitSEHInstruction(const MachineInstr *MI) {
1563 assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?");
1564 assert(getSubtarget().isOSWindows() && "SEH_ instruction Windows only");
1565
1566 // Use the .cv_fpo directives if we're emitting CodeView on 32-bit x86.
1567 if (EmitFPOData) {
1568 X86TargetStreamer *XTS =
1569 static_cast<X86TargetStreamer *>(OutStreamer->getTargetStreamer());
1570 switch (MI->getOpcode()) {
1571 case X86::SEH_PushReg:
1572 XTS->emitFPOPushReg(MI->getOperand(0).getImm());
1573 break;
1574 case X86::SEH_StackAlloc:
1575 XTS->emitFPOStackAlloc(MI->getOperand(0).getImm());
1576 break;
1577 case X86::SEH_StackAlign:
1578 XTS->emitFPOStackAlign(MI->getOperand(0).getImm());
1579 break;
1580 case X86::SEH_SetFrame:
1581 assert(MI->getOperand(1).getImm() == 0 &&
1582 ".cv_fpo_setframe takes no offset");
1583 XTS->emitFPOSetFrame(MI->getOperand(0).getImm());
1584 break;
1585 case X86::SEH_EndPrologue:
1586 XTS->emitFPOEndPrologue();
1587 break;
1588 case X86::SEH_SaveReg:
1589 case X86::SEH_SaveXMM:
1590 case X86::SEH_PushFrame:
1591 llvm_unreachable("SEH_ directive incompatible with FPO");
1592 break;
1593 default:
1594 llvm_unreachable("expected SEH_ instruction");
1595 }
1596 return;
1597 }
1598
1599 // Otherwise, use the .seh_ directives for all other Windows platforms.
1600 switch (MI->getOpcode()) {
1601 case X86::SEH_PushReg:
1602 OutStreamer->EmitWinCFIPushReg(MI->getOperand(0).getImm());
1603 break;
1604
1605 case X86::SEH_SaveReg:
1606 OutStreamer->EmitWinCFISaveReg(MI->getOperand(0).getImm(),
1607 MI->getOperand(1).getImm());
1608 break;
1609
1610 case X86::SEH_SaveXMM:
1611 OutStreamer->EmitWinCFISaveXMM(MI->getOperand(0).getImm(),
1612 MI->getOperand(1).getImm());
1613 break;
1614
1615 case X86::SEH_StackAlloc:
1616 OutStreamer->EmitWinCFIAllocStack(MI->getOperand(0).getImm());
1617 break;
1618
1619 case X86::SEH_SetFrame:
1620 OutStreamer->EmitWinCFISetFrame(MI->getOperand(0).getImm(),
1621 MI->getOperand(1).getImm());
1622 break;
1623
1624 case X86::SEH_PushFrame:
1625 OutStreamer->EmitWinCFIPushFrame(MI->getOperand(0).getImm());
1626 break;
1627
1628 case X86::SEH_EndPrologue:
1629 OutStreamer->EmitWinCFIEndProlog();
1630 break;
1631
1632 default:
1633 llvm_unreachable("expected SEH_ instruction");
1634 }
1635 }
1636
1637 static unsigned getRegisterWidth(const MCOperandInfo &Info) {
1638 if (Info.RegClass == X86::VR128RegClassID ||
1639 Info.RegClass == X86::VR128XRegClassID)
1640 return 128;
1641 if (Info.RegClass == X86::VR256RegClassID ||
1642 Info.RegClass == X86::VR256XRegClassID)
1643 return 256;
1644 if (Info.RegClass == X86::VR512RegClassID)
1645 return 512;
1646 llvm_unreachable("Unknown register class!");
1647 }
1648
1649 void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
1650 X86MCInstLower MCInstLowering(*MF, *this);
1651 const X86RegisterInfo *RI =
1652 MF->getSubtarget<X86Subtarget>().getRegisterInfo();
1653
1654 // Add a comment about EVEX-2-VEX compression for AVX-512 instrs that
1655 // are compressed from EVEX encoding to VEX encoding.
1656 if (TM.Options.MCOptions.ShowMCEncoding) {
1657 if (MI->getAsmPrinterFlags() & X86::AC_EVEX_2_VEX)
1658 OutStreamer->AddComment("EVEX TO VEX Compression ", false);
1659 }
1660
1661 switch (MI->getOpcode()) {
1662 case TargetOpcode::DBG_VALUE:
1663 llvm_unreachable("Should be handled target independently");
1664
1665 // Emit nothing here but a comment if we can.
1666 case X86::Int_MemBarrier:
1667 OutStreamer->emitRawComment("MEMBARRIER");
1668 return;
1669
1670 case X86::EH_RETURN:
1671 case X86::EH_RETURN64: {
1672 // Lower these as normal, but add some comments.
1673 Register Reg = MI->getOperand(0).getReg();
1674 OutStreamer->AddComment(StringRef("eh_return, addr: %") +
1675 X86ATTInstPrinter::getRegisterName(Reg));
1676 break;
1677 }
1678 case X86::CLEANUPRET: {
1679 // Lower these as normal, but add some comments.
1680 OutStreamer->AddComment("CLEANUPRET");
1681 break;
1682 }
1683
1684 case X86::CATCHRET: {
1685 // Lower these as normal, but add some comments.
1686 OutStreamer->AddComment("CATCHRET");
1687 break;
1688 }
1689
1690 case X86::TAILJMPr:
1691 case X86::TAILJMPm:
1692 case X86::TAILJMPd:
1693 case X86::TAILJMPd_CC:
1694 case X86::TAILJMPr64:
1695 case X86::TAILJMPm64:
1696 case X86::TAILJMPd64:
1697 case X86::TAILJMPd64_CC:
1698 case X86::TAILJMPr64_REX:
1699 case X86::TAILJMPm64_REX:
1700 // Lower these as normal, but add some comments.
1701 OutStreamer->AddComment("TAILCALL");
1702 break;
1703
1704 case X86::TLS_addr32:
1705 case X86::TLS_addr64:
1706 case X86::TLS_base_addr32:
1707 case X86::TLS_base_addr64:
1708 return LowerTlsAddr(MCInstLowering, *MI);
1709
1710 // Loading/storing mask pairs requires two kmov operations. The second one of these
1711 // needs a 2 byte displacement relative to the specified address (with 32 bit spill
1712 // size). The pairs of 1bit masks up to 16 bit masks all use the same spill size,
1713 // they all are stored using MASKPAIR16STORE, loaded using MASKPAIR16LOAD.
1714 //
1715 // The displacement value might wrap around in theory, thus the asserts in both
1716 // cases.
1717 case X86::MASKPAIR16LOAD: {
1718 int64_t Disp = MI->getOperand(1 + X86::AddrDisp).getImm();
1719 assert(Disp >= 0 && Disp <= INT32_MAX - 2 && "Unexpected displacement");
1720 Register Reg = MI->getOperand(0).getReg();
1721 Register Reg0 = RI->getSubReg(Reg, X86::sub_mask_0);
1722 Register Reg1 = RI->getSubReg(Reg, X86::sub_mask_1);
1723
1724 // Load the first mask register
1725 MCInstBuilder MIB = MCInstBuilder(X86::KMOVWkm);
1726 MIB.addReg(Reg0);
1727 for (int i = 0; i < X86::AddrNumOperands; ++i) {
1728 auto Op = MCInstLowering.LowerMachineOperand(MI, MI->getOperand(1 + i));
1729 MIB.addOperand(Op.getValue());
1730 }
1731 EmitAndCountInstruction(MIB);
1732
1733 // Load the second mask register of the pair
1734 MIB = MCInstBuilder(X86::KMOVWkm);
1735 MIB.addReg(Reg1);
1736 for (int i = 0; i < X86::AddrNumOperands; ++i) {
1737 if (i == X86::AddrDisp) {
1738 MIB.addImm(Disp + 2);
1739 } else {
1740 auto Op = MCInstLowering.LowerMachineOperand(MI, MI->getOperand(1 + i));
1741 MIB.addOperand(Op.getValue());
1742 }
1743 }
1744 EmitAndCountInstruction(MIB);
1745 return;
1746 }
1747
1748 case X86::MASKPAIR16STORE: {
1749 int64_t Disp = MI->getOperand(X86::AddrDisp).getImm();
1750 assert(Disp >= 0 && Disp <= INT32_MAX - 2 && "Unexpected displacement");
1751 Register Reg = MI->getOperand(X86::AddrNumOperands).getReg();
1752 Register Reg0 = RI->getSubReg(Reg, X86::sub_mask_0);
1753 Register Reg1 = RI->getSubReg(Reg, X86::sub_mask_1);
1754
1755 // Store the first mask register
1756 MCInstBuilder MIB = MCInstBuilder(X86::KMOVWmk);
1757 for (int i = 0; i < X86::AddrNumOperands; ++i)
1758 MIB.addOperand(MCInstLowering.LowerMachineOperand(MI, MI->getOperand(i)).getValue());
1759 MIB.addReg(Reg0);
1760 EmitAndCountInstruction(MIB);
1761
1762 // Store the second mask register of the pair
1763 MIB = MCInstBuilder(X86::KMOVWmk);
1764 for (int i = 0; i < X86::AddrNumOperands; ++i) {
1765 if (i == X86::AddrDisp) {
1766 MIB.addImm(Disp + 2);
1767 } else {
1768 auto Op = MCInstLowering.LowerMachineOperand(MI, MI->getOperand(0 + i));
1769 MIB.addOperand(Op.getValue());
1770 }
1771 }
1772 MIB.addReg(Reg1);
1773 EmitAndCountInstruction(MIB);
1774 return;
1775 }
1776
1777 case X86::MOVPC32r: {
1778 // This is a pseudo op for a two instruction sequence with a label, which
1779 // looks like:
1780 // call "L1$pb"
1781 // "L1$pb":
1782 // popl %esi
1783
1784 // Emit the call.
1785 MCSymbol *PICBase = MF->getPICBaseSymbol();
1786 // FIXME: We would like an efficient form for this, so we don't have to do a
1787 // lot of extra uniquing.
1788 EmitAndCountInstruction(
1789 MCInstBuilder(X86::CALLpcrel32)
1790 .addExpr(MCSymbolRefExpr::create(PICBase, OutContext)));
1791
1792 const X86FrameLowering *FrameLowering =
1793 MF->getSubtarget<X86Subtarget>().getFrameLowering();
1794 bool hasFP = FrameLowering->hasFP(*MF);
1795
1796 // TODO: This is needed only if we require precise CFA.
1797 bool HasActiveDwarfFrame = OutStreamer->getNumFrameInfos() &&
1798 !OutStreamer->getDwarfFrameInfos().back().End;
1799
1800 int stackGrowth = -RI->getSlotSize();
1801
1802 if (HasActiveDwarfFrame && !hasFP) {
1803 OutStreamer->EmitCFIAdjustCfaOffset(-stackGrowth);
1804 }
1805
1806 // Emit the label.
1807 OutStreamer->EmitLabel(PICBase);
1808
1809 // popl $reg
1810 EmitAndCountInstruction(
1811 MCInstBuilder(X86::POP32r).addReg(MI->getOperand(0).getReg()));
1812
1813 if (HasActiveDwarfFrame && !hasFP) {
1814 OutStreamer->EmitCFIAdjustCfaOffset(stackGrowth);
1815 }
1816 return;
1817 }
1818
1819 case X86::ADD32ri: {
1820 // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri.
1821 if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS)
1822 break;
1823
1824 // Okay, we have something like:
1825 // EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL)
1826
1827 // For this, we want to print something like:
1828 // MYGLOBAL + (. - PICBASE)
1829 // However, we can't generate a ".", so just emit a new label here and refer
1830 // to it.
1831 MCSymbol *DotSym = OutContext.createTempSymbol();
1832 OutStreamer->EmitLabel(DotSym);
1833
1834 // Now that we have emitted the label, lower the complex operand expression.
1835 MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2));
1836
1837 const MCExpr *DotExpr = MCSymbolRefExpr::create(DotSym, OutContext);
1838 const MCExpr *PICBase =
1839 MCSymbolRefExpr::create(MF->getPICBaseSymbol(), OutContext);
1840 DotExpr = MCBinaryExpr::createSub(DotExpr, PICBase, OutContext);
1841
1842 DotExpr = MCBinaryExpr::createAdd(
1843 MCSymbolRefExpr::create(OpSym, OutContext), DotExpr, OutContext);
1844
1845 EmitAndCountInstruction(MCInstBuilder(X86::ADD32ri)
1846 .addReg(MI->getOperand(0).getReg())
1847 .addReg(MI->getOperand(1).getReg())
1848 .addExpr(DotExpr));
1849 return;
1850 }
1851 case TargetOpcode::STATEPOINT:
1852 return LowerSTATEPOINT(*MI, MCInstLowering);
1853
1854 case TargetOpcode::FAULTING_OP:
1855 return LowerFAULTING_OP(*MI, MCInstLowering);
1856
1857 case TargetOpcode::FENTRY_CALL:
1858 return LowerFENTRY_CALL(*MI, MCInstLowering);
1859
1860 case TargetOpcode::PATCHABLE_OP:
1861 return LowerPATCHABLE_OP(*MI, MCInstLowering);
1862
1863 case TargetOpcode::STACKMAP:
1864 return LowerSTACKMAP(*MI);
1865
1866 case TargetOpcode::PATCHPOINT:
1867 return LowerPATCHPOINT(*MI, MCInstLowering);
1868
1869 case TargetOpcode::PATCHABLE_FUNCTION_ENTER:
1870 return LowerPATCHABLE_FUNCTION_ENTER(*MI, MCInstLowering);
1871
1872 case TargetOpcode::PATCHABLE_RET:
1873 return LowerPATCHABLE_RET(*MI, MCInstLowering);
1874
1875 case TargetOpcode::PATCHABLE_TAIL_CALL:
1876 return LowerPATCHABLE_TAIL_CALL(*MI, MCInstLowering);
1877
1878 case TargetOpcode::PATCHABLE_EVENT_CALL:
1879 return LowerPATCHABLE_EVENT_CALL(*MI, MCInstLowering);
1880
1881 case TargetOpcode::PATCHABLE_TYPED_EVENT_CALL:
1882 return LowerPATCHABLE_TYPED_EVENT_CALL(*MI, MCInstLowering);
1883
1884 case X86::MORESTACK_RET:
1885 EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
1886 return;
1887
1888 case X86::MORESTACK_RET_RESTORE_R10:
1889 // Return, then restore R10.
1890 EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
1891 EmitAndCountInstruction(
1892 MCInstBuilder(X86::MOV64rr).addReg(X86::R10).addReg(X86::RAX));
1893 return;
1894
1895 case X86::SEH_PushReg:
1896 case X86::SEH_SaveReg:
1897 case X86::SEH_SaveXMM:
1898 case X86::SEH_StackAlloc:
1899 case X86::SEH_StackAlign:
1900 case X86::SEH_SetFrame:
1901 case X86::SEH_PushFrame:
1902 case X86::SEH_EndPrologue:
1903 EmitSEHInstruction(MI);
1904 return;
1905
1906 case X86::SEH_Epilogue: {
1907 assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?");
1908 MachineBasicBlock::const_iterator MBBI(MI);
1909 // Check if preceded by a call and emit nop if so.
1910 for (MBBI = PrevCrossBBInst(MBBI);
1911 MBBI != MachineBasicBlock::const_iterator();
1912 MBBI = PrevCrossBBInst(MBBI)) {
1913 // Conservatively assume that pseudo instructions don't emit code and keep
1914 // looking for a call. We may emit an unnecessary nop in some cases.
1915 if (!MBBI->isPseudo()) {
1916 if (MBBI->isCall())
1917 EmitAndCountInstruction(MCInstBuilder(X86::NOOP));
1918 break;
1919 }
1920 }
1921 return;
1922 }
1923
1924 // Lower PSHUFB and VPERMILP normally but add a comment if we can find
1925 // a constant shuffle mask. We won't be able to do this at the MC layer
1926 // because the mask isn't an immediate.
1927 case X86::PSHUFBrm:
1928 case X86::VPSHUFBrm:
1929 case X86::VPSHUFBYrm:
1930 case X86::VPSHUFBZ128rm:
1931 case X86::VPSHUFBZ128rmk:
1932 case X86::VPSHUFBZ128rmkz:
1933 case X86::VPSHUFBZ256rm:
1934 case X86::VPSHUFBZ256rmk:
1935 case X86::VPSHUFBZ256rmkz:
1936 case X86::VPSHUFBZrm:
1937 case X86::VPSHUFBZrmk:
1938 case X86::VPSHUFBZrmkz: {
1939 if (!OutStreamer->isVerboseAsm())
1940 break;
1941 unsigned SrcIdx, MaskIdx;
1942 switch (MI->getOpcode()) {
1943 default: llvm_unreachable("Invalid opcode");
1944 case X86::PSHUFBrm:
1945 case X86::VPSHUFBrm:
1946 case X86::VPSHUFBYrm:
1947 case X86::VPSHUFBZ128rm:
1948 case X86::VPSHUFBZ256rm:
1949 case X86::VPSHUFBZrm:
1950 SrcIdx = 1; MaskIdx = 5; break;
1951 case X86::VPSHUFBZ128rmkz:
1952 case X86::VPSHUFBZ256rmkz:
1953 case X86::VPSHUFBZrmkz:
1954 SrcIdx = 2; MaskIdx = 6; break;
1955 case X86::VPSHUFBZ128rmk:
1956 case X86::VPSHUFBZ256rmk:
1957 case X86::VPSHUFBZrmk:
1958 SrcIdx = 3; MaskIdx = 7; break;
1959 }
1960
1961 assert(MI->getNumOperands() >= 6 &&
1962 "We should always have at least 6 operands!");
1963
1964 const MachineOperand &MaskOp = MI->getOperand(MaskIdx);
1965 if (auto *C = getConstantFromPool(*MI, MaskOp)) {
1966 unsigned Width = getRegisterWidth(MI->getDesc().OpInfo[0]);
1967 SmallVector<int, 64> Mask;
1968 DecodePSHUFBMask(C, Width, Mask);
1969 if (!Mask.empty())
1970 OutStreamer->AddComment(getShuffleComment(MI, SrcIdx, SrcIdx, Mask));
1971 }
1972 break;
1973 }
1974
1975 case X86::VPERMILPSrm:
1976 case X86::VPERMILPSYrm:
1977 case X86::VPERMILPSZ128rm:
1978 case X86::VPERMILPSZ128rmk:
1979 case X86::VPERMILPSZ128rmkz:
1980 case X86::VPERMILPSZ256rm:
1981 case X86::VPERMILPSZ256rmk:
1982 case X86::VPERMILPSZ256rmkz:
1983 case X86::VPERMILPSZrm:
1984 case X86::VPERMILPSZrmk:
1985 case X86::VPERMILPSZrmkz:
1986 case X86::VPERMILPDrm:
1987 case X86::VPERMILPDYrm:
1988 case X86::VPERMILPDZ128rm:
1989 case X86::VPERMILPDZ128rmk:
1990 case X86::VPERMILPDZ128rmkz:
1991 case X86::VPERMILPDZ256rm:
1992 case X86::VPERMILPDZ256rmk:
1993 case X86::VPERMILPDZ256rmkz:
1994 case X86::VPERMILPDZrm:
1995 case X86::VPERMILPDZrmk:
1996 case X86::VPERMILPDZrmkz: {
1997 if (!OutStreamer->isVerboseAsm())
1998 break;
1999 unsigned SrcIdx, MaskIdx;
2000 unsigned ElSize;
2001 switch (MI->getOpcode()) {
2002 default: llvm_unreachable("Invalid opcode");
2003 case X86::VPERMILPSrm:
2004 case X86::VPERMILPSYrm:
2005 case X86::VPERMILPSZ128rm:
2006 case X86::VPERMILPSZ256rm:
2007 case X86::VPERMILPSZrm:
2008 SrcIdx = 1; MaskIdx = 5; ElSize = 32; break;
2009 case X86::VPERMILPSZ128rmkz:
2010 case X86::VPERMILPSZ256rmkz:
2011 case X86::VPERMILPSZrmkz:
2012 SrcIdx = 2; MaskIdx = 6; ElSize = 32; break;
2013 case X86::VPERMILPSZ128rmk:
2014 case X86::VPERMILPSZ256rmk:
2015 case X86::VPERMILPSZrmk:
2016 SrcIdx = 3; MaskIdx = 7; ElSize = 32; break;
2017 case X86::VPERMILPDrm:
2018 case X86::VPERMILPDYrm:
2019 case X86::VPERMILPDZ128rm:
2020 case X86::VPERMILPDZ256rm:
2021 case X86::VPERMILPDZrm:
2022 SrcIdx = 1; MaskIdx = 5; ElSize = 64; break;
2023 case X86::VPERMILPDZ128rmkz:
2024 case X86::VPERMILPDZ256rmkz:
2025 case X86::VPERMILPDZrmkz:
2026 SrcIdx = 2; MaskIdx = 6; ElSize = 64; break;
2027 case X86::VPERMILPDZ128rmk:
2028 case X86::VPERMILPDZ256rmk:
2029 case X86::VPERMILPDZrmk:
2030 SrcIdx = 3; MaskIdx = 7; ElSize = 64; break;
2031 }
2032
2033 assert(MI->getNumOperands() >= 6 &&
2034 "We should always have at least 6 operands!");
2035
2036 const MachineOperand &MaskOp = MI->getOperand(MaskIdx);
2037 if (auto *C = getConstantFromPool(*MI, MaskOp)) {
2038 unsigned Width = getRegisterWidth(MI->getDesc().OpInfo[0]);
2039 SmallVector<int, 16> Mask;
2040 DecodeVPERMILPMask(C, ElSize, Width, Mask);
2041 if (!Mask.empty())
2042 OutStreamer->AddComment(getShuffleComment(MI, SrcIdx, SrcIdx, Mask));
2043 }
2044 break;
2045 }
2046
2047 case X86::VPERMIL2PDrm:
2048 case X86::VPERMIL2PSrm:
2049 case X86::VPERMIL2PDYrm:
2050 case X86::VPERMIL2PSYrm: {
2051 if (!OutStreamer->isVerboseAsm())
2052 break;
2053 assert(MI->getNumOperands() >= 8 &&
2054 "We should always have at least 8 operands!");
2055
2056 const MachineOperand &CtrlOp = MI->getOperand(MI->getNumOperands() - 1);
2057 if (!CtrlOp.isImm())
2058 break;
2059
2060 unsigned ElSize;
2061 switch (MI->getOpcode()) {
2062 default: llvm_unreachable("Invalid opcode");
2063 case X86::VPERMIL2PSrm: case X86::VPERMIL2PSYrm: ElSize = 32; break;
2064 case X86::VPERMIL2PDrm: case X86::VPERMIL2PDYrm: ElSize = 64; break;
2065 }
2066
2067 const MachineOperand &MaskOp = MI->getOperand(6);
2068 if (auto *C = getConstantFromPool(*MI, MaskOp)) {
2069 unsigned Width = getRegisterWidth(MI->getDesc().OpInfo[0]);
2070 SmallVector<int, 16> Mask;
2071 DecodeVPERMIL2PMask(C, (unsigned)CtrlOp.getImm(), ElSize, Width, Mask);
2072 if (!Mask.empty())
2073 OutStreamer->AddComment(getShuffleComment(MI, 1, 2, Mask));
2074 }
2075 break;
2076 }
2077
2078 case X86::VPPERMrrm: {
2079 if (!OutStreamer->isVerboseAsm())
2080 break;
2081 assert(MI->getNumOperands() >= 7 &&
2082 "We should always have at least 7 operands!");
2083
2084 const MachineOperand &MaskOp = MI->getOperand(6);
2085 if (auto *C = getConstantFromPool(*MI, MaskOp)) {
2086 unsigned Width = getRegisterWidth(MI->getDesc().OpInfo[0]);
2087 SmallVector<int, 16> Mask;
2088 DecodeVPPERMMask(C, Width, Mask);
2089 if (!Mask.empty())
2090 OutStreamer->AddComment(getShuffleComment(MI, 1, 2, Mask));
2091 }
2092 break;
2093 }
2094
2095 case X86::MMX_MOVQ64rm: {
2096 if (!OutStreamer->isVerboseAsm())
2097 break;
2098 if (MI->getNumOperands() <= 4)
2099 break;
2100 if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) {
2101 std::string Comment;
2102 raw_string_ostream CS(Comment);
2103 const MachineOperand &DstOp = MI->getOperand(0);
2104 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = ";
2105 if (auto *CF = dyn_cast<ConstantFP>(C)) {
2106 CS << "0x" << CF->getValueAPF().bitcastToAPInt().toString(16, false);
2107 OutStreamer->AddComment(CS.str());
2108 }
2109 }
2110 break;
2111 }
2112
2113 #define MOV_CASE(Prefix, Suffix) \
2114 case X86::Prefix##MOVAPD##Suffix##rm: \
2115 case X86::Prefix##MOVAPS##Suffix##rm: \
2116 case X86::Prefix##MOVUPD##Suffix##rm: \
2117 case X86::Prefix##MOVUPS##Suffix##rm: \
2118 case X86::Prefix##MOVDQA##Suffix##rm: \
2119 case X86::Prefix##MOVDQU##Suffix##rm:
2120
2121 #define MOV_AVX512_CASE(Suffix) \
2122 case X86::VMOVDQA64##Suffix##rm: \
2123 case X86::VMOVDQA32##Suffix##rm: \
2124 case X86::VMOVDQU64##Suffix##rm: \
2125 case X86::VMOVDQU32##Suffix##rm: \
2126 case X86::VMOVDQU16##Suffix##rm: \
2127 case X86::VMOVDQU8##Suffix##rm: \
2128 case X86::VMOVAPS##Suffix##rm: \
2129 case X86::VMOVAPD##Suffix##rm: \
2130 case X86::VMOVUPS##Suffix##rm: \
2131 case X86::VMOVUPD##Suffix##rm:
2132
2133 #define CASE_ALL_MOV_RM() \
2134 MOV_CASE(, ) /* SSE */ \
2135 MOV_CASE(V, ) /* AVX-128 */ \
2136 MOV_CASE(V, Y) /* AVX-256 */ \
2137 MOV_AVX512_CASE(Z) \
2138 MOV_AVX512_CASE(Z256) \
2139 MOV_AVX512_CASE(Z128)
2140
2141 // For loads from a constant pool to a vector register, print the constant
2142 // loaded.
2143 CASE_ALL_MOV_RM()
2144 case X86::VBROADCASTF128:
2145 case X86::VBROADCASTI128:
2146 case X86::VBROADCASTF32X4Z256rm:
2147 case X86::VBROADCASTF32X4rm:
2148 case X86::VBROADCASTF32X8rm:
2149 case X86::VBROADCASTF64X2Z128rm:
2150 case X86::VBROADCASTF64X2rm:
2151 case X86::VBROADCASTF64X4rm:
2152 case X86::VBROADCASTI32X4Z256rm:
2153 case X86::VBROADCASTI32X4rm:
2154 case X86::VBROADCASTI32X8rm:
2155 case X86::VBROADCASTI64X2Z128rm:
2156 case X86::VBROADCASTI64X2rm:
2157 case X86::VBROADCASTI64X4rm:
2158 if (!OutStreamer->isVerboseAsm())
2159 break;
2160 if (MI->getNumOperands() <= 4)
2161 break;
2162 if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) {
2163 int NumLanes = 1;
2164 // Override NumLanes for the broadcast instructions.
2165 switch (MI->getOpcode()) {
2166 case X86::VBROADCASTF128: NumLanes = 2; break;
2167 case X86::VBROADCASTI128: NumLanes = 2; break;
2168 case X86::VBROADCASTF32X4Z256rm: NumLanes = 2; break;
2169 case X86::VBROADCASTF32X4rm: NumLanes = 4; break;
2170 case X86::VBROADCASTF32X8rm: NumLanes = 2; break;
2171 case X86::VBROADCASTF64X2Z128rm: NumLanes = 2; break;
2172 case X86::VBROADCASTF64X2rm: NumLanes = 4; break;
2173 case X86::VBROADCASTF64X4rm: NumLanes = 2; break;
2174 case X86::VBROADCASTI32X4Z256rm: NumLanes = 2; break;
2175 case X86::VBROADCASTI32X4rm: NumLanes = 4; break;
2176 case X86::VBROADCASTI32X8rm: NumLanes = 2; break;
2177 case X86::VBROADCASTI64X2Z128rm: NumLanes = 2; break;
2178 case X86::VBROADCASTI64X2rm: NumLanes = 4; break;
2179 case X86::VBROADCASTI64X4rm: NumLanes = 2; break;
2180 }
2181
2182 std::string Comment;
2183 raw_string_ostream CS(Comment);
2184 const MachineOperand &DstOp = MI->getOperand(0);
2185 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = ";
2186 if (auto *CDS = dyn_cast<ConstantDataSequential>(C)) {
2187 CS << "[";
2188 for (int l = 0; l != NumLanes; ++l) {
2189 for (int i = 0, NumElements = CDS->getNumElements(); i < NumElements;
2190 ++i) {
2191 if (i != 0 || l != 0)
2192 CS << ",";
2193 if (CDS->getElementType()->isIntegerTy())
2194 printConstant(CDS->getElementAsAPInt(i), CS);
2195 else if (CDS->getElementType()->isHalfTy() ||
2196 CDS->getElementType()->isFloatTy() ||
2197 CDS->getElementType()->isDoubleTy())
2198 printConstant(CDS->getElementAsAPFloat(i), CS);
2199 else
2200 CS << "?";
2201 }
2202 }
2203 CS << "]";
2204 OutStreamer->AddComment(CS.str());
2205 } else if (auto *CV = dyn_cast<ConstantVector>(C)) {
2206 CS << "<";
2207 for (int l = 0; l != NumLanes; ++l) {
2208 for (int i = 0, NumOperands = CV->getNumOperands(); i < NumOperands;
2209 ++i) {
2210 if (i != 0 || l != 0)
2211 CS << ",";
2212 printConstant(CV->getOperand(i), CS);
2213 }
2214 }
2215 CS << ">";
2216 OutStreamer->AddComment(CS.str());
2217 }
2218 }
2219 break;
2220 case X86::MOVDDUPrm:
2221 case X86::VMOVDDUPrm:
2222 case X86::VMOVDDUPZ128rm:
2223 case X86::VBROADCASTSSrm:
2224 case X86::VBROADCASTSSYrm:
2225 case X86::VBROADCASTSSZ128m:
2226 case X86::VBROADCASTSSZ256m:
2227 case X86::VBROADCASTSSZm:
2228 case X86::VBROADCASTSDYrm:
2229 case X86::VBROADCASTSDZ256m:
2230 case X86::VBROADCASTSDZm:
2231 case X86::VPBROADCASTBrm:
2232 case X86::VPBROADCASTBYrm:
2233 case X86::VPBROADCASTBZ128m:
2234 case X86::VPBROADCASTBZ256m:
2235 case X86::VPBROADCASTBZm:
2236 case X86::VPBROADCASTDrm:
2237 case X86::VPBROADCASTDYrm:
2238 case X86::VPBROADCASTDZ128m:
2239 case X86::VPBROADCASTDZ256m:
2240 case X86::VPBROADCASTDZm:
2241 case X86::VPBROADCASTQrm:
2242 case X86::VPBROADCASTQYrm:
2243 case X86::VPBROADCASTQZ128m:
2244 case X86::VPBROADCASTQZ256m:
2245 case X86::VPBROADCASTQZm:
2246 case X86::VPBROADCASTWrm:
2247 case X86::VPBROADCASTWYrm:
2248 case X86::VPBROADCASTWZ128m:
2249 case X86::VPBROADCASTWZ256m:
2250 case X86::VPBROADCASTWZm:
2251 if (!OutStreamer->isVerboseAsm())
2252 break;
2253 if (MI->getNumOperands() <= 4)
2254 break;
2255 if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) {
2256 int NumElts;
2257 switch (MI->getOpcode()) {
2258 default: llvm_unreachable("Invalid opcode");
2259 case X86::MOVDDUPrm: NumElts = 2; break;
2260 case X86::VMOVDDUPrm: NumElts = 2; break;
2261 case X86::VMOVDDUPZ128rm: NumElts = 2; break;
2262 case X86::VBROADCASTSSrm: NumElts = 4; break;
2263 case X86::VBROADCASTSSYrm: NumElts = 8; break;
2264 case X86::VBROADCASTSSZ128m: NumElts = 4; break;
2265 case X86::VBROADCASTSSZ256m: NumElts = 8; break;
2266 case X86::VBROADCASTSSZm: NumElts = 16; break;
2267 case X86::VBROADCASTSDYrm: NumElts = 4; break;
2268 case X86::VBROADCASTSDZ256m: NumElts = 4; break;
2269 case X86::VBROADCASTSDZm: NumElts = 8; break;
2270 case X86::VPBROADCASTBrm: NumElts = 16; break;
2271 case X86::VPBROADCASTBYrm: NumElts = 32; break;
2272 case X86::VPBROADCASTBZ128m: NumElts = 16; break;
2273 case X86::VPBROADCASTBZ256m: NumElts = 32; break;
2274 case X86::VPBROADCASTBZm: NumElts = 64; break;
2275 case X86::VPBROADCASTDrm: NumElts = 4; break;
2276 case X86::VPBROADCASTDYrm: NumElts = 8; break;
2277 case X86::VPBROADCASTDZ128m: NumElts = 4; break;
2278 case X86::VPBROADCASTDZ256m: NumElts = 8; break;
2279 case X86::VPBROADCASTDZm: NumElts = 16; break;
2280 case X86::VPBROADCASTQrm: NumElts = 2; break;
2281 case X86::VPBROADCASTQYrm: NumElts = 4; break;
2282 case X86::VPBROADCASTQZ128m: NumElts = 2; break;
2283 case X86::VPBROADCASTQZ256m: NumElts = 4; break;
2284 case X86::VPBROADCASTQZm: NumElts = 8; break;
2285 case X86::VPBROADCASTWrm: NumElts = 8; break;
2286 case X86::VPBROADCASTWYrm: NumElts = 16; break;
2287 case X86::VPBROADCASTWZ128m: NumElts = 8; break;
2288 case X86::VPBROADCASTWZ256m: NumElts = 16; break;
2289 case X86::VPBROADCASTWZm: NumElts = 32; break;
2290 }
2291
2292 std::string Comment;
2293 raw_string_ostream CS(Comment);
2294 const MachineOperand &DstOp = MI->getOperand(0);
2295 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = ";
2296 CS << "[";
2297 for (int i = 0; i != NumElts; ++i) {
2298 if (i != 0)
2299 CS << ",";
2300 printConstant(C, CS);
2301 }
2302 CS << "]";
2303 OutStreamer->AddComment(CS.str());
2304 }
2305 }
2306
2307 MCInst TmpInst;
2308 MCInstLowering.Lower(MI, TmpInst);
2309
2310 // Stackmap shadows cannot include branch targets, so we can count the bytes
2311 // in a call towards the shadow, but must ensure that the no thread returns
2312 // in to the stackmap shadow. The only way to achieve this is if the call
2313 // is at the end of the shadow.
2314 if (MI->isCall()) {
2315 // Count then size of the call towards the shadow
2316 SMShadowTracker.count(TmpInst, getSubtargetInfo(), CodeEmitter.get());
2317 // Then flush the shadow so that we fill with nops before the call, not
2318 // after it.
2319 SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
2320 // Then emit the call
2321 OutStreamer->EmitInstruction(TmpInst, getSubtargetInfo());
2322 return;
2323 }
2324
2325 EmitAndCountInstruction(TmpInst);
2326 }
The LLVM Project is a collection of modular and reusable compiler and toolchain technologies.