| blob | cc51b10fee18429e9678fa1cfd4b0ff9ae3ab0e0 |
1 ; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
2 ; RUN: | FileCheck %s -check-prefix=ILP32-LP64
3 ; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
4 ; RUN: | FileCheck %s -check-prefix=ILP32-LP64
5 ; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d -verify-machineinstrs < %s \
6 ; RUN: | FileCheck %s -check-prefix=ILP32D-LP64D
7 ; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64d -verify-machineinstrs < %s \
8 ; RUN: | FileCheck %s -check-prefix=ILP32D-LP64D
10 @var = global [32 x double] zeroinitializer
12 ; All floating point registers are temporaries for the ilp32 and lp64 ABIs.
13 ; fs0-fs11 are callee-saved for the ilp32f, ilp32d, lp64f, and lp64d ABIs.
15 ; This function tests that RISCVRegisterInfo::getCalleeSavedRegs returns
16 ; something appropriate.
18 define void @callee() nounwind {
19 ; ILP32-LP64-LABEL: callee:
20 ; ILP32-LP64: # %bb.0:
21 ; ILP32-LP64-NEXT: lui a0, %hi(var)
22 ; ILP32-LP64-NEXT: addi a1, a0, %lo(var)
23 ; ILP32-LP64-NEXT: fld ft0, %lo(var)(a0)
24 ; ILP32-LP64-NEXT: fld ft1, 8(a1)
25 ; ILP32-LP64-NEXT: fld ft2, 16(a1)
26 ; ILP32-LP64-NEXT: fld ft3, 24(a1)
27 ; ILP32-LP64-NEXT: fld ft4, 32(a1)
28 ; ILP32-LP64-NEXT: fld ft5, 40(a1)
29 ; ILP32-LP64-NEXT: fld ft6, 48(a1)
30 ; ILP32-LP64-NEXT: fld ft7, 56(a1)
31 ; ILP32-LP64-NEXT: fld fa0, 64(a1)
32 ; ILP32-LP64-NEXT: fld fa1, 72(a1)
33 ; ILP32-LP64-NEXT: fld fa2, 80(a1)
34 ; ILP32-LP64-NEXT: fld fa3, 88(a1)
35 ; ILP32-LP64-NEXT: fld fa4, 96(a1)
36 ; ILP32-LP64-NEXT: fld fa5, 104(a1)
37 ; ILP32-LP64-NEXT: fld fa6, 112(a1)
38 ; ILP32-LP64-NEXT: fld fa7, 120(a1)
39 ; ILP32-LP64-NEXT: fld ft8, 128(a1)
40 ; ILP32-LP64-NEXT: fld ft9, 136(a1)
41 ; ILP32-LP64-NEXT: fld ft10, 144(a1)
42 ; ILP32-LP64-NEXT: fld ft11, 152(a1)
43 ; ILP32-LP64-NEXT: fld fs0, 160(a1)
44 ; ILP32-LP64-NEXT: fld fs1, 168(a1)
45 ; ILP32-LP64-NEXT: fld fs2, 176(a1)
46 ; ILP32-LP64-NEXT: fld fs3, 184(a1)
47 ; ILP32-LP64-NEXT: fld fs4, 192(a1)
48 ; ILP32-LP64-NEXT: fld fs5, 200(a1)
49 ; ILP32-LP64-NEXT: fld fs6, 208(a1)
50 ; ILP32-LP64-NEXT: fld fs7, 216(a1)
51 ; ILP32-LP64-NEXT: fld fs8, 224(a1)
52 ; ILP32-LP64-NEXT: fld fs9, 232(a1)
53 ; ILP32-LP64-NEXT: fld fs10, 240(a1)
54 ; ILP32-LP64-NEXT: fld fs11, 248(a1)
55 ; ILP32-LP64-NEXT: fsd fs11, 248(a1)
56 ; ILP32-LP64-NEXT: fsd fs10, 240(a1)
57 ; ILP32-LP64-NEXT: fsd fs9, 232(a1)
58 ; ILP32-LP64-NEXT: fsd fs8, 224(a1)
59 ; ILP32-LP64-NEXT: fsd fs7, 216(a1)
60 ; ILP32-LP64-NEXT: fsd fs6, 208(a1)
61 ; ILP32-LP64-NEXT: fsd fs5, 200(a1)
62 ; ILP32-LP64-NEXT: fsd fs4, 192(a1)
63 ; ILP32-LP64-NEXT: fsd fs3, 184(a1)
64 ; ILP32-LP64-NEXT: fsd fs2, 176(a1)
65 ; ILP32-LP64-NEXT: fsd fs1, 168(a1)
66 ; ILP32-LP64-NEXT: fsd fs0, 160(a1)
67 ; ILP32-LP64-NEXT: fsd ft11, 152(a1)
68 ; ILP32-LP64-NEXT: fsd ft10, 144(a1)
69 ; ILP32-LP64-NEXT: fsd ft9, 136(a1)
70 ; ILP32-LP64-NEXT: fsd ft8, 128(a1)
71 ; ILP32-LP64-NEXT: fsd fa7, 120(a1)
72 ; ILP32-LP64-NEXT: fsd fa6, 112(a1)
73 ; ILP32-LP64-NEXT: fsd fa5, 104(a1)
74 ; ILP32-LP64-NEXT: fsd fa4, 96(a1)
75 ; ILP32-LP64-NEXT: fsd fa3, 88(a1)
76 ; ILP32-LP64-NEXT: fsd fa2, 80(a1)
77 ; ILP32-LP64-NEXT: fsd fa1, 72(a1)
78 ; ILP32-LP64-NEXT: fsd fa0, 64(a1)
79 ; ILP32-LP64-NEXT: fsd ft7, 56(a1)
80 ; ILP32-LP64-NEXT: fsd ft6, 48(a1)
81 ; ILP32-LP64-NEXT: fsd ft5, 40(a1)
82 ; ILP32-LP64-NEXT: fsd ft4, 32(a1)
83 ; ILP32-LP64-NEXT: fsd ft3, 24(a1)
84 ; ILP32-LP64-NEXT: fsd ft2, 16(a1)
85 ; ILP32-LP64-NEXT: fsd ft1, 8(a1)
86 ; ILP32-LP64-NEXT: fsd ft0, %lo(var)(a0)
87 ; ILP32-LP64-NEXT: ret
88 ;
89 ; ILP32D-LP64D-LABEL: callee:
90 ; ILP32D-LP64D: # %bb.0:
91 ; ILP32D-LP64D-NEXT: addi sp, sp, -96
92 ; ILP32D-LP64D-NEXT: fsd fs0, 88(sp)
93 ; ILP32D-LP64D-NEXT: fsd fs1, 80(sp)
94 ; ILP32D-LP64D-NEXT: fsd fs2, 72(sp)
95 ; ILP32D-LP64D-NEXT: fsd fs3, 64(sp)
96 ; ILP32D-LP64D-NEXT: fsd fs4, 56(sp)
97 ; ILP32D-LP64D-NEXT: fsd fs5, 48(sp)
98 ; ILP32D-LP64D-NEXT: fsd fs6, 40(sp)
99 ; ILP32D-LP64D-NEXT: fsd fs7, 32(sp)
100 ; ILP32D-LP64D-NEXT: fsd fs8, 24(sp)
101 ; ILP32D-LP64D-NEXT: fsd fs9, 16(sp)
102 ; ILP32D-LP64D-NEXT: fsd fs10, 8(sp)
103 ; ILP32D-LP64D-NEXT: fsd fs11, 0(sp)
104 ; ILP32D-LP64D-NEXT: lui a0, %hi(var)
105 ; ILP32D-LP64D-NEXT: addi a1, a0, %lo(var)
106 %val = load [32 x double], [32 x double]* @var
107 store volatile [32 x double] %val, [32 x double]* @var
108 ret void
109 }
111 ; This function tests that RISCVRegisterInfo::getCallPreservedMask returns
112 ; something appropriate.
113 ;
114 ; For the soft float ABIs, no floating point registers are preserved, and
115 ; codegen will use only ft0 in the body of caller. For the 'f' and 'd ABIs,
116 ; fs0-fs11 are preserved across calls.
118 define void @caller() nounwind {
119 ; ILP32-LP64-LABEL: caller:
120 ; ILP32-LP64-NOT: ft{{[1-9][0-9]*}}
121 ; ILP32-LP64-NOT: fs{{[0-9]+}}
122 ; ILP32-LP64-NOT: fa{{[0-9]+}}
123 ; ILP32-LP64: call callee
124 ; ILP32-LP64-NOT: ft{{[1-9][0-9]*}}
125 ; ILP32-LP64-NOT: fs{{[0-9]+}}
126 ; ILP32-LP64-NOT: fa{{[0-9]+}}
127 ; ILP32-LP64: ret
128 ;
129 ; ILP32F-LP64D-LABEL: caller:
130 ; ILP32D-LP64D: fld fs8, 160(s1)
131 ; ILP32D-LP64D-NEXT: fld fs9, 168(s1)
132 ; ILP32D-LP64D-NEXT: fld fs10, 176(s1)
133 ; ILP32D-LP64D-NEXT: fld fs11, 184(s1)
134 ; ILP32D-LP64D-NEXT: fld fs0, 192(s1)
135 ; ILP32D-LP64D-NEXT: fld fs1, 200(s1)
136 ; ILP32D-LP64D-NEXT: fld fs2, 208(s1)
137 ; ILP32D-LP64D-NEXT: fld fs3, 216(s1)
138 ; ILP32D-LP64D-NEXT: fld fs4, 224(s1)
139 ; ILP32D-LP64D-NEXT: fld fs5, 232(s1)
140 ; ILP32D-LP64D-NEXT: fld fs6, 240(s1)
141 ; ILP32D-LP64D-NEXT: fld fs7, 248(s1)
142 ; ILP32D-LP64D-NEXT: call callee
143 ; ILP32D-LP64D-NEXT: fsd fs7, 248(s1)
144 ; ILP32D-LP64D-NEXT: fsd fs6, 240(s1)
145 ; ILP32D-LP64D-NEXT: fsd fs5, 232(s1)
146 ; ILP32D-LP64D-NEXT: fsd fs4, 224(s1)
147 ; ILP32D-LP64D-NEXT: fsd fs3, 216(s1)
148 ; ILP32D-LP64D-NEXT: fsd fs2, 208(s1)
149 ; ILP32D-LP64D-NEXT: fsd fs1, 200(s1)
150 ; ILP32D-LP64D-NEXT: fsd fs0, 192(s1)
151 ; ILP32D-LP64D-NEXT: fsd fs11, 184(s1)
152 ; ILP32D-LP64D-NEXT: fsd fs10, 176(s1)
153 ; ILP32D-LP64D-NEXT: fsd fs9, 168(s1)
154 ; ILP32D-LP64D-NEXT: fsd fs8, 160(s1)
155 ; ILP32D-LP64D-NEXT: fld ft0, {{[0-9]+}}(sp)
156 %val = load [32 x double], [32 x double]* @var
157 call void @callee()
158 store volatile [32 x double] %val, [32 x double]* @var
159 ret void
160 }