1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX12-SDAG %s
3 ; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX12-GISEL %s
5 define amdgpu_ps float @test_fmaximum_f32_vv(float %a, float %b) {
6 ; GCN-LABEL: test_fmaximum_f32_vv:
8 ; GCN-NEXT: v_maximum_f32 v0, v0, v1
9 ; GCN-NEXT: ; return to shader part epilog
10 %val = call float @llvm.maximum.f32(float %a, float %b)
14 define amdgpu_ps float @test_fmaximum_f32_ss(float inreg %a, float inreg %b) {
15 ; GCN-LABEL: test_fmaximum_f32_ss:
17 ; GCN-NEXT: s_maximum_f32 s0, s0, s1
18 ; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
19 ; GCN-NEXT: v_mov_b32_e32 v0, s0
20 ; GCN-NEXT: ; return to shader part epilog
21 %val = call float @llvm.maximum.f32(float %a, float %b)
25 define amdgpu_ps float @test_fmaximum_f32_vs(float %a, float inreg %b) {
26 ; GCN-LABEL: test_fmaximum_f32_vs:
28 ; GCN-NEXT: v_maximum_f32 v0, v0, s0
29 ; GCN-NEXT: ; return to shader part epilog
30 %val = call float @llvm.maximum.f32(float %a, float %b)
34 define amdgpu_ps float @test_fmaximum_nnan_f32(float %a, float %b) {
35 ; GCN-LABEL: test_fmaximum_nnan_f32:
37 ; GCN-NEXT: v_maximum_f32 v0, v0, v1
38 ; GCN-NEXT: ; return to shader part epilog
39 %val = call nnan float @llvm.maximum.f32(float %a, float %b)
43 define amdgpu_ps <2 x float> @test_fmaximum_v2f32(<2 x float> %a, <2 x float> %b) {
44 ; GCN-LABEL: test_fmaximum_v2f32:
46 ; GCN-NEXT: v_maximum_f32 v0, v0, v2
47 ; GCN-NEXT: v_maximum_f32 v1, v1, v3
48 ; GCN-NEXT: ; return to shader part epilog
49 %val = call <2 x float> @llvm.maximum.v2f32(<2 x float> %a, <2 x float> %b)
53 define amdgpu_ps <2 x float> @test_fmaximum_v2f32_ss(<2 x float> inreg %a, <2 x float> inreg %b) {
54 ; GCN-LABEL: test_fmaximum_v2f32_ss:
56 ; GCN-NEXT: s_maximum_f32 s0, s0, s2
57 ; GCN-NEXT: s_maximum_f32 s1, s1, s3
58 ; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
59 ; GCN-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
60 ; GCN-NEXT: ; return to shader part epilog
61 %val = call <2 x float> @llvm.maximum.v2f32(<2 x float> %a, <2 x float> %b)
65 define amdgpu_ps <3 x float> @test_fmaximum_v3f32(<3 x float> %a, <3 x float> %b) {
66 ; GCN-LABEL: test_fmaximum_v3f32:
68 ; GCN-NEXT: v_maximum_f32 v0, v0, v3
69 ; GCN-NEXT: v_maximum_f32 v1, v1, v4
70 ; GCN-NEXT: v_maximum_f32 v2, v2, v5
71 ; GCN-NEXT: ; return to shader part epilog
72 %val = call <3 x float> @llvm.maximum.v3f32(<3 x float> %a, <3 x float> %b)
76 define amdgpu_ps <4 x float> @test_fmaximum_v4f32(<4 x float> %a, <4 x float> %b) {
77 ; GCN-LABEL: test_fmaximum_v4f32:
79 ; GCN-NEXT: v_maximum_f32 v0, v0, v4
80 ; GCN-NEXT: v_maximum_f32 v1, v1, v5
81 ; GCN-NEXT: v_maximum_f32 v2, v2, v6
82 ; GCN-NEXT: v_maximum_f32 v3, v3, v7
83 ; GCN-NEXT: ; return to shader part epilog
84 %val = call <4 x float> @llvm.maximum.v4f32(<4 x float> %a, <4 x float> %b)
88 define amdgpu_ps <16 x float> @test_fmaximum_v16f32(<16 x float> %a, <16 x float> %b) {
89 ; GCN-LABEL: test_fmaximum_v16f32:
91 ; GCN-NEXT: v_maximum_f32 v0, v0, v16
92 ; GCN-NEXT: v_maximum_f32 v1, v1, v17
93 ; GCN-NEXT: v_maximum_f32 v2, v2, v18
94 ; GCN-NEXT: v_maximum_f32 v3, v3, v19
95 ; GCN-NEXT: v_maximum_f32 v4, v4, v20
96 ; GCN-NEXT: v_maximum_f32 v5, v5, v21
97 ; GCN-NEXT: v_maximum_f32 v6, v6, v22
98 ; GCN-NEXT: v_maximum_f32 v7, v7, v23
99 ; GCN-NEXT: v_maximum_f32 v8, v8, v24
100 ; GCN-NEXT: v_maximum_f32 v9, v9, v25
101 ; GCN-NEXT: v_maximum_f32 v10, v10, v26
102 ; GCN-NEXT: v_maximum_f32 v11, v11, v27
103 ; GCN-NEXT: v_maximum_f32 v12, v12, v28
104 ; GCN-NEXT: v_maximum_f32 v13, v13, v29
105 ; GCN-NEXT: v_maximum_f32 v14, v14, v30
106 ; GCN-NEXT: v_maximum_f32 v15, v15, v31
107 ; GCN-NEXT: ; return to shader part epilog
108 %val = call <16 x float> @llvm.maximum.v16f32(<16 x float> %a, <16 x float> %b)
109 ret <16 x float> %val
112 define amdgpu_ps half @test_fmaximum_f16_vv(half %a, half %b) {
113 ; GCN-LABEL: test_fmaximum_f16_vv:
115 ; GCN-NEXT: v_maximum_f16 v0, v0, v1
116 ; GCN-NEXT: ; return to shader part epilog
117 %val = call half @llvm.maximum.f16(half %a, half %b)
121 define amdgpu_ps half @test_fmaximum_f16_ss(half inreg %a, half inreg %b) {
122 ; GCN-LABEL: test_fmaximum_f16_ss:
124 ; GCN-NEXT: s_maximum_f16 s0, s0, s1
125 ; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
126 ; GCN-NEXT: v_mov_b32_e32 v0, s0
127 ; GCN-NEXT: ; return to shader part epilog
128 %val = call half @llvm.maximum.f16(half %a, half %b)
132 define amdgpu_ps <2 x half> @test_fmaximum_v2f16_vv(<2 x half> %a, <2 x half> %b) {
133 ; GCN-LABEL: test_fmaximum_v2f16_vv:
135 ; GCN-NEXT: v_pk_maximum_f16 v0, v0, v1
136 ; GCN-NEXT: ; return to shader part epilog
137 %val = call <2 x half> @llvm.maximum.v2f16(<2 x half> %a, <2 x half> %b)
141 define amdgpu_ps <2 x half> @test_fmaximum_v2f16_ss(<2 x half> inreg %a, <2 x half> inreg %b) {
142 ; GCN-LABEL: test_fmaximum_v2f16_ss:
144 ; GCN-NEXT: v_pk_maximum_f16 v0, s0, s1
145 ; GCN-NEXT: ; return to shader part epilog
146 %val = call <2 x half> @llvm.maximum.v2f16(<2 x half> %a, <2 x half> %b)
150 define amdgpu_ps <3 x half> @test_fmaximum_v3f16_vv(<3 x half> %a, <3 x half> %b) {
151 ; GCN-LABEL: test_fmaximum_v3f16_vv:
153 ; GCN-NEXT: v_pk_maximum_f16 v0, v0, v2
154 ; GCN-NEXT: v_maximum_f16 v1, v1, v3
155 ; GCN-NEXT: ; return to shader part epilog
156 %val = call <3 x half> @llvm.maximum.v3f16(<3 x half> %a, <3 x half> %b)
160 define amdgpu_ps <3 x half> @test_fmaximum_v3f16_ss(<3 x half> inreg %a, <3 x half> inreg %b) {
161 ; GCN-LABEL: test_fmaximum_v3f16_ss:
163 ; GCN-NEXT: v_pk_maximum_f16 v0, s0, s2
164 ; GCN-NEXT: s_maximum_f16 s0, s1, s3
165 ; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
166 ; GCN-NEXT: v_mov_b32_e32 v1, s0
167 ; GCN-NEXT: ; return to shader part epilog
168 %val = call <3 x half> @llvm.maximum.v3f16(<3 x half> %a, <3 x half> %b)
172 define amdgpu_ps <4 x half> @test_fmaximum_v4f16(<4 x half> %a, <4 x half> %b) {
173 ; GCN-LABEL: test_fmaximum_v4f16:
175 ; GCN-NEXT: v_pk_maximum_f16 v0, v0, v2
176 ; GCN-NEXT: v_pk_maximum_f16 v1, v1, v3
177 ; GCN-NEXT: ; return to shader part epilog
178 %val = call <4 x half> @llvm.maximum.v4f16(<4 x half> %a, <4 x half> %b)
182 define amdgpu_ps <4 x half> @test_fmaximum_v4f16_ss(<4 x half> inreg %a, <4 x half> inreg %b) {
183 ; GCN-LABEL: test_fmaximum_v4f16_ss:
185 ; GCN-NEXT: v_pk_maximum_f16 v0, s0, s2
186 ; GCN-NEXT: v_pk_maximum_f16 v1, s1, s3
187 ; GCN-NEXT: ; return to shader part epilog
188 %val = call <4 x half> @llvm.maximum.v4f16(<4 x half> %a, <4 x half> %b)
192 define amdgpu_ps <2 x float> @test_fmaximum_f64_vv(double %a, double %b) {
193 ; GCN-LABEL: test_fmaximum_f64_vv:
195 ; GCN-NEXT: v_maximum_f64 v[0:1], v[0:1], v[2:3]
196 ; GCN-NEXT: ; return to shader part epilog
197 %val = call double @llvm.maximum.f64(double %a, double %b)
198 %ret = bitcast double %val to <2 x float>
202 define amdgpu_ps <2 x float> @test_fmaximum_f64_ss(double inreg %a, double inreg %b) {
203 ; GCN-LABEL: test_fmaximum_f64_ss:
205 ; GCN-NEXT: v_maximum_f64 v[0:1], s[0:1], s[2:3]
206 ; GCN-NEXT: ; return to shader part epilog
207 %val = call double @llvm.maximum.f64(double %a, double %b)
208 %ret = bitcast double %val to <2 x float>
212 define amdgpu_ps <4 x float> @test_fmaximum_v2f64_ss(<2 x double> inreg %a, <2 x double> inreg %b) {
213 ; GCN-LABEL: test_fmaximum_v2f64_ss:
215 ; GCN-NEXT: v_maximum_f64 v[0:1], s[0:1], s[4:5]
216 ; GCN-NEXT: v_maximum_f64 v[2:3], s[2:3], s[6:7]
217 ; GCN-NEXT: ; return to shader part epilog
218 %val = call <2 x double> @llvm.maximum.v2f64(<2 x double> %a, <2 x double> %b)
219 %ret = bitcast <2 x double> %val to <4 x float>
223 define amdgpu_ps <8 x float> @test_fmaximum_v4f64(<4 x double> %a, <4 x double> %b) {
224 ; GCN-LABEL: test_fmaximum_v4f64:
226 ; GCN-NEXT: v_maximum_f64 v[0:1], v[0:1], v[8:9]
227 ; GCN-NEXT: v_maximum_f64 v[2:3], v[2:3], v[10:11]
228 ; GCN-NEXT: v_maximum_f64 v[4:5], v[4:5], v[12:13]
229 ; GCN-NEXT: v_maximum_f64 v[6:7], v[6:7], v[14:15]
230 ; GCN-NEXT: ; return to shader part epilog
231 %val = call <4 x double> @llvm.maximum.v4f64(<4 x double> %a, <4 x double> %b)
232 %ret = bitcast <4 x double> %val to <8 x float>
236 define amdgpu_ps <8 x float> @test_fmaximum_v4f64_ss(<4 x double> inreg %a, <4 x double> inreg %b) {
237 ; GCN-LABEL: test_fmaximum_v4f64_ss:
239 ; GCN-NEXT: v_maximum_f64 v[0:1], s[0:1], s[8:9]
240 ; GCN-NEXT: v_maximum_f64 v[2:3], s[2:3], s[10:11]
241 ; GCN-NEXT: v_maximum_f64 v[4:5], s[4:5], s[12:13]
242 ; GCN-NEXT: v_maximum_f64 v[6:7], s[6:7], s[14:15]
243 ; GCN-NEXT: ; return to shader part epilog
244 %val = call <4 x double> @llvm.maximum.v4f64(<4 x double> %a, <4 x double> %b)
245 %ret = bitcast <4 x double> %val to <8 x float>
249 define amdgpu_kernel void @fmaximumi_f32_move_to_valu(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) {
250 ; GCN-LABEL: fmaximumi_f32_move_to_valu:
252 ; GCN-NEXT: s_clause 0x1
253 ; GCN-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
254 ; GCN-NEXT: s_load_b64 s[0:1], s[0:1], 0x34
255 ; GCN-NEXT: v_mov_b32_e32 v0, 0
256 ; GCN-NEXT: s_wait_kmcnt 0x0
257 ; GCN-NEXT: global_load_b32 v1, v0, s[6:7] scope:SCOPE_SYS
258 ; GCN-NEXT: s_wait_loadcnt 0x0
259 ; GCN-NEXT: global_load_b32 v2, v0, s[0:1] scope:SCOPE_SYS
260 ; GCN-NEXT: s_wait_loadcnt 0x0
261 ; GCN-NEXT: v_maximum_f32 v1, v1, v2
262 ; GCN-NEXT: global_store_b32 v0, v1, s[4:5]
264 ; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
266 %a = load volatile float, ptr addrspace(1) %aptr, align 4
267 %b = load volatile float, ptr addrspace(1) %bptr, align 4
268 %v = call float @llvm.maximum.f32(float %a, float %b)
269 store float %v, ptr addrspace(1) %out, align 4
273 define amdgpu_kernel void @fmaximum_f16_move_to_valu(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) {
274 ; GCN-LABEL: fmaximum_f16_move_to_valu:
276 ; GCN-NEXT: s_clause 0x1
277 ; GCN-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
278 ; GCN-NEXT: s_load_b64 s[0:1], s[0:1], 0x34
279 ; GCN-NEXT: v_mov_b32_e32 v0, 0
280 ; GCN-NEXT: s_wait_kmcnt 0x0
281 ; GCN-NEXT: global_load_u16 v1, v0, s[6:7] scope:SCOPE_SYS
282 ; GCN-NEXT: s_wait_loadcnt 0x0
283 ; GCN-NEXT: global_load_u16 v2, v0, s[0:1] scope:SCOPE_SYS
284 ; GCN-NEXT: s_wait_loadcnt 0x0
285 ; GCN-NEXT: v_maximum_f16 v1, v1, v2
286 ; GCN-NEXT: global_store_b16 v0, v1, s[4:5]
288 ; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
290 %a = load volatile half, ptr addrspace(1) %aptr, align 4
291 %b = load volatile half, ptr addrspace(1) %bptr, align 4
292 %v = call half @llvm.maximum.f16(half %a, half %b)
293 store half %v, ptr addrspace(1) %out, align 4
297 declare float @llvm.maximum.f32(float, float)
298 declare <2 x float> @llvm.maximum.v2f32(<2 x float>, <2 x float>)
299 declare <3 x float> @llvm.maximum.v3f32(<3 x float>, <3 x float>)
300 declare <4 x float> @llvm.maximum.v4f32(<4 x float>, <4 x float>)
301 declare <16 x float> @llvm.maximum.v16f32(<16 x float>, <16 x float>)
302 declare half @llvm.maximum.f16(half, half)
303 declare <2 x half> @llvm.maximum.v2f16(<2 x half>, <2 x half>)
304 declare <3 x half> @llvm.maximum.v3f16(<3 x half>, <3 x half>)
305 declare <4 x half> @llvm.maximum.v4f16(<4 x half>, <4 x half>)
306 declare double @llvm.maximum.f64(double, double)
307 declare <2 x double> @llvm.maximum.v2f64(<2 x double>, <2 x double>)
308 declare <4 x double> @llvm.maximum.v4f64(<4 x double>, <4 x double>)
309 ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
310 ; GFX12-GISEL: {{.*}}