| blob | 36e78975cdb015777ca493b9f2ca8b4e170b0acb |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,SI,GCN-SDAG,SI-SDAG %s
3 ; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,SI,GCN-GISEL,SI-GISEL %s
4 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,VI,GCN-SDAG,VI-SDAG %s
5 ; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,VI,GCN-GISEL,VI-GISEL %s
6 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX900,GCN-SDAG,GFX900-SDAG %s
7 ; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX900,GCN-GISEL,GFX900-GISEL %s
9 ; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 %s
10 ; RUN: llc -mtriple=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM %s
12 define amdgpu_kernel void @s_exp2_f32(ptr addrspace(1) %out, float %in) {
13 ; SI-SDAG-LABEL: s_exp2_f32:
14 ; SI-SDAG: ; %bb.0:
15 ; SI-SDAG-NEXT: s_load_dword s2, s[0:1], 0xb
16 ; SI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
17 ; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
18 ; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
19 ; SI-SDAG-NEXT: s_mov_b32 s3, 0xf000
20 ; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
21 ; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
22 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc
23 ; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42800000
24 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
25 ; SI-SDAG-NEXT: v_add_f32_e32 v1, s2, v1
26 ; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1
27 ; SI-SDAG-NEXT: s_mov_b32 s2, -1
28 ; SI-SDAG-NEXT: v_mul_f32_e32 v0, v1, v0
29 ; SI-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
30 ; SI-SDAG-NEXT: s_endpgm
31 ;
32 ; SI-GISEL-LABEL: s_exp2_f32:
33 ; SI-GISEL: ; %bb.0:
34 ; SI-GISEL-NEXT: s_load_dword s2, s[0:1], 0xb
35 ; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
36 ; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
37 ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42800000
38 ; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
39 ; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
40 ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
41 ; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
42 ; SI-GISEL-NEXT: v_add_f32_e32 v0, s2, v0
43 ; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
44 ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000
45 ; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
46 ; SI-GISEL-NEXT: s_mov_b32 s2, -1
47 ; SI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
48 ; SI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
49 ; SI-GISEL-NEXT: s_endpgm
50 ;
51 ; VI-SDAG-LABEL: s_exp2_f32:
52 ; VI-SDAG: ; %bb.0:
53 ; VI-SDAG-NEXT: s_load_dword s2, s[0:1], 0x2c
54 ; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
55 ; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
56 ; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
57 ; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
58 ; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
59 ; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc
60 ; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42800000
61 ; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
62 ; VI-SDAG-NEXT: v_add_f32_e32 v1, s2, v1
63 ; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
64 ; VI-SDAG-NEXT: v_mul_f32_e32 v2, v1, v0
65 ; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
66 ; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
67 ; VI-SDAG-NEXT: flat_store_dword v[0:1], v2
68 ; VI-SDAG-NEXT: s_endpgm
69 ;
70 ; VI-GISEL-LABEL: s_exp2_f32:
71 ; VI-GISEL: ; %bb.0:
72 ; VI-GISEL-NEXT: s_load_dword s2, s[0:1], 0x2c
73 ; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
74 ; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
75 ; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42800000
76 ; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
77 ; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
78 ; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
79 ; VI-GISEL-NEXT: v_add_f32_e32 v0, s2, v0
80 ; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0
81 ; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000
82 ; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
83 ; VI-GISEL-NEXT: v_mul_f32_e32 v2, v0, v1
84 ; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
85 ; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
86 ; VI-GISEL-NEXT: flat_store_dword v[0:1], v2
87 ; VI-GISEL-NEXT: s_endpgm
88 ;
89 ; GFX900-SDAG-LABEL: s_exp2_f32:
90 ; GFX900-SDAG: ; %bb.0:
91 ; GFX900-SDAG-NEXT: s_load_dword s4, s[0:1], 0x2c
92 ; GFX900-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
93 ; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
94 ; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
95 ; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0
96 ; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0)
97 ; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0
98 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc
99 ; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x42800000
100 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
101 ; GFX900-SDAG-NEXT: v_add_f32_e32 v1, s4, v1
102 ; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v1
103 ; GFX900-SDAG-NEXT: v_mul_f32_e32 v0, v1, v0
104 ; GFX900-SDAG-NEXT: global_store_dword v2, v0, s[2:3]
105 ; GFX900-SDAG-NEXT: s_endpgm
106 ;
107 ; GFX900-GISEL-LABEL: s_exp2_f32:
108 ; GFX900-GISEL: ; %bb.0:
109 ; GFX900-GISEL-NEXT: s_load_dword s2, s[0:1], 0x2c
110 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
111 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42800000
112 ; GFX900-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
113 ; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
114 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
115 ; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
116 ; GFX900-GISEL-NEXT: v_add_f32_e32 v0, s2, v0
117 ; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0
118 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000
119 ; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
120 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
121 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0
122 ; GFX900-GISEL-NEXT: global_store_dword v1, v0, s[0:1]
123 ; GFX900-GISEL-NEXT: s_endpgm
124 ;
125 ; R600-LABEL: s_exp2_f32:
126 ; R600: ; %bb.0:
127 ; R600-NEXT: ALU 10, @4, KC0[CB0:0-32], KC1[]
128 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
129 ; R600-NEXT: CF_END
130 ; R600-NEXT: PAD
131 ; R600-NEXT: ALU clause starting at 4:
132 ; R600-NEXT: SETGT * T0.W, literal.x, KC0[2].Z,
133 ; R600-NEXT: -1023672320(-1.260000e+02), 0(0.000000e+00)
134 ; R600-NEXT: CNDE * T1.W, PV.W, 0.0, literal.x,
135 ; R600-NEXT: 1115684864(6.400000e+01), 0(0.000000e+00)
136 ; R600-NEXT: ADD T1.W, KC0[2].Z, PV.W,
137 ; R600-NEXT: CNDE * T0.W, T0.W, 1.0, literal.x,
138 ; R600-NEXT: 528482304(5.421011e-20), 0(0.000000e+00)
139 ; R600-NEXT: EXP_IEEE * T0.X, PV.W,
140 ; R600-NEXT: MUL_IEEE T0.X, PS, T0.W,
141 ; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
142 ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
143 ;
144 ; CM-LABEL: s_exp2_f32:
145 ; CM: ; %bb.0:
146 ; CM-NEXT: ALU 13, @4, KC0[CB0:0-32], KC1[]
147 ; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X
148 ; CM-NEXT: CF_END
149 ; CM-NEXT: PAD
150 ; CM-NEXT: ALU clause starting at 4:
151 ; CM-NEXT: SETGT * T0.W, literal.x, KC0[2].Z,
152 ; CM-NEXT: -1023672320(-1.260000e+02), 0(0.000000e+00)
153 ; CM-NEXT: CNDE * T1.W, PV.W, 0.0, literal.x,
154 ; CM-NEXT: 1115684864(6.400000e+01), 0(0.000000e+00)
155 ; CM-NEXT: CNDE T0.Z, T0.W, 1.0, literal.x,
156 ; CM-NEXT: ADD * T0.W, KC0[2].Z, PV.W,
157 ; CM-NEXT: 528482304(5.421011e-20), 0(0.000000e+00)
158 ; CM-NEXT: EXP_IEEE T0.X, T0.W,
159 ; CM-NEXT: EXP_IEEE T0.Y (MASKED), T0.W,
160 ; CM-NEXT: EXP_IEEE T0.Z (MASKED), T0.W,
161 ; CM-NEXT: EXP_IEEE * T0.W (MASKED), T0.W,
162 ; CM-NEXT: MUL_IEEE * T0.X, PV.X, T0.Z,
163 ; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
164 ; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
165 %result = call float @llvm.exp2.f32(float %in)
166 store float %result, ptr addrspace(1) %out
167 ret void
168 }
170 ; FIXME: We should be able to merge these packets together on Cayman so we
171 ; have a maximum of 4 instructions.
172 define amdgpu_kernel void @s_exp2_v2f32(ptr addrspace(1) %out, <2 x float> %in) {
173 ; SI-SDAG-LABEL: s_exp2_v2f32:
174 ; SI-SDAG: ; %bb.0:
175 ; SI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
176 ; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
177 ; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
178 ; SI-SDAG-NEXT: v_mov_b32_e32 v3, 0x42800000
179 ; SI-SDAG-NEXT: s_mov_b32 s7, 0xf000
180 ; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
181 ; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
182 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v1, vcc
183 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v3, vcc
184 ; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
185 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc
186 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
187 ; SI-SDAG-NEXT: v_add_f32_e32 v4, s3, v4
188 ; SI-SDAG-NEXT: v_add_f32_e32 v1, s2, v1
189 ; SI-SDAG-NEXT: v_exp_f32_e32 v4, v4
190 ; SI-SDAG-NEXT: v_exp_f32_e32 v3, v1
191 ; SI-SDAG-NEXT: s_mov_b32 s6, -1
192 ; SI-SDAG-NEXT: s_mov_b32 s4, s0
193 ; SI-SDAG-NEXT: s_mov_b32 s5, s1
194 ; SI-SDAG-NEXT: v_mul_f32_e32 v1, v4, v2
195 ; SI-SDAG-NEXT: v_mul_f32_e32 v0, v3, v0
196 ; SI-SDAG-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
197 ; SI-SDAG-NEXT: s_endpgm
198 ;
199 ; SI-GISEL-LABEL: s_exp2_v2f32:
200 ; SI-GISEL: ; %bb.0:
201 ; SI-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
202 ; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
203 ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42800000
204 ; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x1f800000
205 ; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
206 ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
207 ; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v0
208 ; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v1, vcc
209 ; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v1, s[0:1]
210 ; SI-GISEL-NEXT: v_add_f32_e32 v3, s6, v3
211 ; SI-GISEL-NEXT: v_add_f32_e32 v0, s7, v0
212 ; SI-GISEL-NEXT: v_exp_f32_e32 v3, v3
213 ; SI-GISEL-NEXT: v_exp_f32_e32 v1, v0
214 ; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v2, vcc
215 ; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, v2, s[0:1]
216 ; SI-GISEL-NEXT: v_mul_f32_e32 v0, v3, v0
217 ; SI-GISEL-NEXT: v_mul_f32_e32 v1, v1, v2
218 ; SI-GISEL-NEXT: s_mov_b32 s6, -1
219 ; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000
220 ; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
221 ; SI-GISEL-NEXT: s_endpgm
222 ;
223 ; VI-SDAG-LABEL: s_exp2_v2f32:
224 ; VI-SDAG: ; %bb.0:
225 ; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
226 ; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
227 ; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
228 ; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
229 ; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
230 ; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
231 ; VI-SDAG-NEXT: v_cndmask_b32_e32 v3, 1.0, v1, vcc
232 ; VI-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v2, vcc
233 ; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
234 ; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc
235 ; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
236 ; VI-SDAG-NEXT: v_add_f32_e32 v4, s3, v4
237 ; VI-SDAG-NEXT: v_add_f32_e32 v1, s2, v1
238 ; VI-SDAG-NEXT: v_exp_f32_e32 v4, v4
239 ; VI-SDAG-NEXT: v_exp_f32_e32 v2, v1
240 ; VI-SDAG-NEXT: v_mul_f32_e32 v1, v4, v3
241 ; VI-SDAG-NEXT: v_mul_f32_e32 v0, v2, v0
242 ; VI-SDAG-NEXT: v_mov_b32_e32 v3, s1
243 ; VI-SDAG-NEXT: v_mov_b32_e32 v2, s0
244 ; VI-SDAG-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
245 ; VI-SDAG-NEXT: s_endpgm
246 ;
247 ; VI-GISEL-LABEL: s_exp2_v2f32:
248 ; VI-GISEL: ; %bb.0:
249 ; VI-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
250 ; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
251 ; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42800000
252 ; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x1f800000
253 ; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
254 ; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
255 ; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v0
256 ; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v1, vcc
257 ; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v1, s[0:1]
258 ; VI-GISEL-NEXT: v_add_f32_e32 v3, s6, v3
259 ; VI-GISEL-NEXT: v_add_f32_e32 v0, s7, v0
260 ; VI-GISEL-NEXT: v_exp_f32_e32 v3, v3
261 ; VI-GISEL-NEXT: v_exp_f32_e32 v1, v0
262 ; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v2, vcc
263 ; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, v2, s[0:1]
264 ; VI-GISEL-NEXT: v_mul_f32_e32 v0, v3, v0
265 ; VI-GISEL-NEXT: v_mul_f32_e32 v1, v1, v2
266 ; VI-GISEL-NEXT: v_mov_b32_e32 v2, s4
267 ; VI-GISEL-NEXT: v_mov_b32_e32 v3, s5
268 ; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
269 ; VI-GISEL-NEXT: s_endpgm
270 ;
271 ; GFX900-SDAG-LABEL: s_exp2_v2f32:
272 ; GFX900-SDAG: ; %bb.0:
273 ; GFX900-SDAG-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
274 ; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
275 ; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
276 ; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
277 ; GFX900-SDAG-NEXT: v_mov_b32_e32 v5, 0
278 ; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0)
279 ; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
280 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, 1.0, v1, vcc
281 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v2, vcc
282 ; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
283 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc
284 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
285 ; GFX900-SDAG-NEXT: v_add_f32_e32 v4, s3, v4
286 ; GFX900-SDAG-NEXT: v_add_f32_e32 v1, s2, v1
287 ; GFX900-SDAG-NEXT: v_exp_f32_e32 v4, v4
288 ; GFX900-SDAG-NEXT: v_exp_f32_e32 v2, v1
289 ; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, v4, v3
290 ; GFX900-SDAG-NEXT: v_mul_f32_e32 v0, v2, v0
291 ; GFX900-SDAG-NEXT: global_store_dwordx2 v5, v[0:1], s[0:1]
292 ; GFX900-SDAG-NEXT: s_endpgm
293 ;
294 ; GFX900-GISEL-LABEL: s_exp2_v2f32:
295 ; GFX900-GISEL: ; %bb.0:
296 ; GFX900-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
297 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
298 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42800000
299 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x1f800000
300 ; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
301 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
302 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v0
303 ; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v1, vcc
304 ; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v1, s[0:1]
305 ; GFX900-GISEL-NEXT: v_add_f32_e32 v3, s6, v3
306 ; GFX900-GISEL-NEXT: v_add_f32_e32 v0, s7, v0
307 ; GFX900-GISEL-NEXT: v_exp_f32_e32 v3, v3
308 ; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v0
309 ; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v2, vcc
310 ; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, v2, s[0:1]
311 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, v3, v0
312 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, v1, v2
313 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0
314 ; GFX900-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5]
315 ; GFX900-GISEL-NEXT: s_endpgm
316 ;
317 ; R600-LABEL: s_exp2_v2f32:
318 ; R600: ; %bb.0:
319 ; R600-NEXT: ALU 18, @4, KC0[CB0:0-32], KC1[]
320 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
321 ; R600-NEXT: CF_END
322 ; R600-NEXT: PAD
323 ; R600-NEXT: ALU clause starting at 4:
324 ; R600-NEXT: SETGT T0.W, literal.x, KC0[3].X,
325 ; R600-NEXT: SETGT * T1.W, literal.x, KC0[2].W,
326 ; R600-NEXT: -1023672320(-1.260000e+02), 0(0.000000e+00)
327 ; R600-NEXT: CNDE * T2.W, PV.W, 0.0, literal.x,
328 ; R600-NEXT: 1115684864(6.400000e+01), 0(0.000000e+00)
329 ; R600-NEXT: ADD T2.W, KC0[3].X, PV.W,
330 ; R600-NEXT: CNDE * T3.W, T1.W, 0.0, literal.x,
331 ; R600-NEXT: 1115684864(6.400000e+01), 0(0.000000e+00)
332 ; R600-NEXT: ADD T0.Z, KC0[2].W, PS,
333 ; R600-NEXT: CNDE T0.W, T0.W, 1.0, literal.x,
334 ; R600-NEXT: EXP_IEEE * T0.X, PV.W,
335 ; R600-NEXT: 528482304(5.421011e-20), 0(0.000000e+00)
336 ; R600-NEXT: MUL_IEEE T0.Y, PS, PV.W,
337 ; R600-NEXT: CNDE T0.W, T1.W, 1.0, literal.x,
338 ; R600-NEXT: EXP_IEEE * T0.X, PV.Z,
339 ; R600-NEXT: 528482304(5.421011e-20), 0(0.000000e+00)
340 ; R600-NEXT: MUL_IEEE T0.X, PS, PV.W,
341 ; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
342 ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
343 ;
344 ; CM-LABEL: s_exp2_v2f32:
345 ; CM: ; %bb.0:
346 ; CM-NEXT: ALU 23, @4, KC0[CB0:0-32], KC1[]
347 ; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1, T0.X
348 ; CM-NEXT: CF_END
349 ; CM-NEXT: PAD
350 ; CM-NEXT: ALU clause starting at 4:
351 ; CM-NEXT: SETGT * T0.W, literal.x, KC0[3].X,
352 ; CM-NEXT: -1023672320(-1.260000e+02), 0(0.000000e+00)
353 ; CM-NEXT: CNDE T0.Z, PV.W, 0.0, literal.x,
354 ; CM-NEXT: SETGT * T1.W, literal.y, KC0[2].W,
355 ; CM-NEXT: 1115684864(6.400000e+01), -1023672320(-1.260000e+02)
356 ; CM-NEXT: CNDE T0.Y, PV.W, 0.0, literal.x,
357 ; CM-NEXT: CNDE T1.Z, T0.W, 1.0, literal.y,
358 ; CM-NEXT: ADD * T0.W, KC0[3].X, PV.Z,
359 ; CM-NEXT: 1115684864(6.400000e+01), 528482304(5.421011e-20)
360 ; CM-NEXT: EXP_IEEE T0.X, T0.W,
361 ; CM-NEXT: EXP_IEEE T0.Y (MASKED), T0.W,
362 ; CM-NEXT: EXP_IEEE T0.Z (MASKED), T0.W,
363 ; CM-NEXT: EXP_IEEE * T0.W (MASKED), T0.W,
364 ; CM-NEXT: MUL_IEEE T1.Y, PV.X, T1.Z,
365 ; CM-NEXT: CNDE T0.Z, T1.W, 1.0, literal.x,
366 ; CM-NEXT: ADD * T0.W, KC0[2].W, T0.Y,
367 ; CM-NEXT: 528482304(5.421011e-20), 0(0.000000e+00)
368 ; CM-NEXT: EXP_IEEE T0.X, T0.W,
369 ; CM-NEXT: EXP_IEEE T0.Y (MASKED), T0.W,
370 ; CM-NEXT: EXP_IEEE T0.Z (MASKED), T0.W,
371 ; CM-NEXT: EXP_IEEE * T0.W (MASKED), T0.W,
372 ; CM-NEXT: MUL_IEEE * T1.X, PV.X, T0.Z,
373 ; CM-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,
374 ; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
375 %result = call <2 x float> @llvm.exp2.v2f32(<2 x float> %in)
376 store <2 x float> %result, ptr addrspace(1) %out
377 ret void
378 }
380 define amdgpu_kernel void @s_exp2_v3f32(ptr addrspace(1) %out, <3 x float> %in) {
381 ; SI-SDAG-LABEL: s_exp2_v3f32:
382 ; SI-SDAG: ; %bb.0:
383 ; SI-SDAG-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xd
384 ; SI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
385 ; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
386 ; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
387 ; SI-SDAG-NEXT: v_mov_b32_e32 v3, 0x42800000
388 ; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
389 ; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s5, v0
390 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v1, vcc
391 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v3, vcc
392 ; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0
393 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v5, 1.0, v1, vcc
394 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v6, 0, v3, vcc
395 ; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
396 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
397 ; SI-SDAG-NEXT: v_add_f32_e32 v4, s5, v4
398 ; SI-SDAG-NEXT: v_add_f32_e32 v0, s6, v0
399 ; SI-SDAG-NEXT: v_exp_f32_e32 v4, v4
400 ; SI-SDAG-NEXT: v_add_f32_e32 v6, s4, v6
401 ; SI-SDAG-NEXT: v_exp_f32_e32 v3, v0
402 ; SI-SDAG-NEXT: v_exp_f32_e32 v6, v6
403 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v7, 1.0, v1, vcc
404 ; SI-SDAG-NEXT: s_mov_b32 s3, 0xf000
405 ; SI-SDAG-NEXT: s_mov_b32 s2, -1
406 ; SI-SDAG-NEXT: v_mul_f32_e32 v1, v4, v2
407 ; SI-SDAG-NEXT: v_mul_f32_e32 v2, v3, v7
408 ; SI-SDAG-NEXT: v_mul_f32_e32 v0, v6, v5
409 ; SI-SDAG-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:8
410 ; SI-SDAG-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
411 ; SI-SDAG-NEXT: s_endpgm
412 ;
413 ; SI-GISEL-LABEL: s_exp2_v3f32:
414 ; SI-GISEL: ; %bb.0:
415 ; SI-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xd
416 ; SI-GISEL-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x9
417 ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
418 ; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
419 ; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x1f800000
420 ; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
421 ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v1
422 ; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
423 ; SI-GISEL-NEXT: v_add_f32_e32 v0, s4, v0
424 ; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
425 ; SI-GISEL-NEXT: v_cndmask_b32_e32 v4, 1.0, v3, vcc
426 ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s5, v1
427 ; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s6, v1
428 ; SI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v4
429 ; SI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v2, vcc
430 ; SI-GISEL-NEXT: v_add_f32_e32 v4, s5, v4
431 ; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v2, s[0:1]
432 ; SI-GISEL-NEXT: v_exp_f32_e32 v4, v4
433 ; SI-GISEL-NEXT: v_add_f32_e32 v1, s6, v1
434 ; SI-GISEL-NEXT: v_exp_f32_e32 v2, v1
435 ; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v3, vcc
436 ; SI-GISEL-NEXT: v_mul_f32_e32 v1, v4, v1
437 ; SI-GISEL-NEXT: v_cndmask_b32_e64 v3, 1.0, v3, s[0:1]
438 ; SI-GISEL-NEXT: s_mov_b32 s10, -1
439 ; SI-GISEL-NEXT: s_mov_b32 s11, 0xf000
440 ; SI-GISEL-NEXT: v_mul_f32_e32 v2, v2, v3
441 ; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
442 ; SI-GISEL-NEXT: buffer_store_dword v2, off, s[8:11], 0 offset:8
443 ; SI-GISEL-NEXT: s_endpgm
444 ;
445 ; VI-SDAG-LABEL: s_exp2_v3f32:
446 ; VI-SDAG: ; %bb.0:
447 ; VI-SDAG-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
448 ; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
449 ; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
450 ; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
451 ; VI-SDAG-NEXT: v_mov_b32_e32 v3, 0x42800000
452 ; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
453 ; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
454 ; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v1, vcc
455 ; VI-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v3, vcc
456 ; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s5, v0
457 ; VI-SDAG-NEXT: v_cndmask_b32_e32 v5, 1.0, v1, vcc
458 ; VI-SDAG-NEXT: v_cndmask_b32_e32 v6, 0, v3, vcc
459 ; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0
460 ; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc
461 ; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
462 ; VI-SDAG-NEXT: v_add_f32_e32 v4, s6, v4
463 ; VI-SDAG-NEXT: v_add_f32_e32 v1, s4, v1
464 ; VI-SDAG-NEXT: v_exp_f32_e32 v4, v4
465 ; VI-SDAG-NEXT: v_add_f32_e32 v6, s5, v6
466 ; VI-SDAG-NEXT: v_exp_f32_e32 v3, v1
467 ; VI-SDAG-NEXT: v_exp_f32_e32 v6, v6
468 ; VI-SDAG-NEXT: v_mul_f32_e32 v2, v4, v2
469 ; VI-SDAG-NEXT: v_mul_f32_e32 v0, v3, v0
470 ; VI-SDAG-NEXT: v_mov_b32_e32 v4, s1
471 ; VI-SDAG-NEXT: v_mul_f32_e32 v1, v6, v5
472 ; VI-SDAG-NEXT: v_mov_b32_e32 v3, s0
473 ; VI-SDAG-NEXT: flat_store_dwordx3 v[3:4], v[0:2]
474 ; VI-SDAG-NEXT: s_endpgm
475 ;
476 ; VI-GISEL-LABEL: s_exp2_v3f32:
477 ; VI-GISEL: ; %bb.0:
478 ; VI-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
479 ; VI-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
480 ; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
481 ; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
482 ; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x1f800000
483 ; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
484 ; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v1
485 ; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
486 ; VI-GISEL-NEXT: v_add_f32_e32 v0, s4, v0
487 ; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0
488 ; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 1.0, v3, vcc
489 ; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s5, v1
490 ; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s6, v1
491 ; VI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v4
492 ; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v2, vcc
493 ; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v2, s[0:1]
494 ; VI-GISEL-NEXT: v_add_f32_e32 v4, s5, v4
495 ; VI-GISEL-NEXT: v_add_f32_e32 v1, s6, v1
496 ; VI-GISEL-NEXT: v_exp_f32_e32 v4, v4
497 ; VI-GISEL-NEXT: v_exp_f32_e32 v2, v1
498 ; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v3, vcc
499 ; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, 1.0, v3, s[0:1]
500 ; VI-GISEL-NEXT: v_mul_f32_e32 v1, v4, v1
501 ; VI-GISEL-NEXT: v_mul_f32_e32 v2, v2, v3
502 ; VI-GISEL-NEXT: v_mov_b32_e32 v4, s3
503 ; VI-GISEL-NEXT: v_mov_b32_e32 v3, s2
504 ; VI-GISEL-NEXT: flat_store_dwordx3 v[3:4], v[0:2]
505 ; VI-GISEL-NEXT: s_endpgm
506 ;
507 ; GFX900-SDAG-LABEL: s_exp2_v3f32:
508 ; GFX900-SDAG: ; %bb.0:
509 ; GFX900-SDAG-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
510 ; GFX900-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
511 ; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
512 ; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
513 ; GFX900-SDAG-NEXT: v_mov_b32_e32 v3, 0x42800000
514 ; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0)
515 ; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
516 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v1, vcc
517 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v3, vcc
518 ; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s5, v0
519 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v5, 1.0, v1, vcc
520 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v6, 0, v3, vcc
521 ; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0
522 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc
523 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
524 ; GFX900-SDAG-NEXT: v_add_f32_e32 v4, s6, v4
525 ; GFX900-SDAG-NEXT: v_add_f32_e32 v6, s5, v6
526 ; GFX900-SDAG-NEXT: v_add_f32_e32 v1, s4, v1
527 ; GFX900-SDAG-NEXT: v_exp_f32_e32 v4, v4
528 ; GFX900-SDAG-NEXT: v_exp_f32_e32 v6, v6
529 ; GFX900-SDAG-NEXT: v_exp_f32_e32 v3, v1
530 ; GFX900-SDAG-NEXT: v_mov_b32_e32 v7, 0
531 ; GFX900-SDAG-NEXT: v_mul_f32_e32 v2, v4, v2
532 ; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, v6, v5
533 ; GFX900-SDAG-NEXT: v_mul_f32_e32 v0, v3, v0
534 ; GFX900-SDAG-NEXT: global_store_dwordx3 v7, v[0:2], s[2:3]
535 ; GFX900-SDAG-NEXT: s_endpgm
536 ;
537 ; GFX900-GISEL-LABEL: s_exp2_v3f32:
538 ; GFX900-GISEL: ; %bb.0:
539 ; GFX900-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
540 ; GFX900-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
541 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
542 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
543 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x1f800000
544 ; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
545 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v1
546 ; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
547 ; GFX900-GISEL-NEXT: v_add_f32_e32 v0, s4, v0
548 ; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0
549 ; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v4, 1.0, v3, vcc
550 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s5, v1
551 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s6, v1
552 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, v0, v4
553 ; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v2, vcc
554 ; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v2, s[0:1]
555 ; GFX900-GISEL-NEXT: v_add_f32_e32 v4, s5, v4
556 ; GFX900-GISEL-NEXT: v_add_f32_e32 v1, s6, v1
557 ; GFX900-GISEL-NEXT: v_exp_f32_e32 v4, v4
558 ; GFX900-GISEL-NEXT: v_exp_f32_e32 v2, v1
559 ; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v3, vcc
560 ; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v3, 1.0, v3, s[0:1]
561 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, v4, v1
562 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, v2, v3
563 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0
564 ; GFX900-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[2:3]
565 ; GFX900-GISEL-NEXT: s_endpgm
566 ;
567 ; R600-LABEL: s_exp2_v3f32:
568 ; R600: ; %bb.0:
569 ; R600-NEXT: ALU 29, @4, KC0[CB0:0-32], KC1[]
570 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.X, T3.X, 0
571 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XY, T0.X, 1
572 ; R600-NEXT: CF_END
573 ; R600-NEXT: ALU clause starting at 4:
574 ; R600-NEXT: SETGT T0.W, literal.x, KC0[3].Z,
575 ; R600-NEXT: SETGT * T1.W, literal.x, KC0[3].Y,
576 ; R600-NEXT: -1023672320(-1.260000e+02), 0(0.000000e+00)
577 ; R600-NEXT: CNDE * T2.W, PV.W, 0.0, literal.x,
578 ; R600-NEXT: 1115684864(6.400000e+01), 0(0.000000e+00)
579 ; R600-NEXT: ADD T2.W, KC0[3].Z, PV.W,
580 ; R600-NEXT: CNDE * T3.W, T1.W, 0.0, literal.x,
581 ; R600-NEXT: 1115684864(6.400000e+01), 0(0.000000e+00)
582 ; R600-NEXT: ADD T0.Y, KC0[3].Y, PS,
583 ; R600-NEXT: SETGT T0.Z, literal.x, KC0[3].W,
584 ; R600-NEXT: CNDE T0.W, T0.W, 1.0, literal.y,
585 ; R600-NEXT: EXP_IEEE * T0.X, PV.W,
586 ; R600-NEXT: -1023672320(-1.260000e+02), 528482304(5.421011e-20)
587 ; R600-NEXT: MUL_IEEE T1.Y, PS, PV.W,
588 ; R600-NEXT: CNDE T1.Z, PV.Z, 0.0, literal.x,
589 ; R600-NEXT: CNDE T0.W, T1.W, 1.0, literal.y,
590 ; R600-NEXT: EXP_IEEE * T0.X, PV.Y,
591 ; R600-NEXT: 1115684864(6.400000e+01), 528482304(5.421011e-20)
592 ; R600-NEXT: MUL_IEEE T1.X, PS, PV.W,
593 ; R600-NEXT: ADD T0.W, KC0[3].W, PV.Z,
594 ; R600-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,
595 ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
596 ; R600-NEXT: CNDE T1.W, T0.Z, 1.0, literal.x,
597 ; R600-NEXT: EXP_IEEE * T0.Y, PV.W,
598 ; R600-NEXT: 528482304(5.421011e-20), 0(0.000000e+00)
599 ; R600-NEXT: MUL_IEEE T2.X, PS, PV.W,
600 ; R600-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,
601 ; R600-NEXT: 8(1.121039e-44), 0(0.000000e+00)
602 ; R600-NEXT: LSHR * T3.X, PV.W, literal.x,
603 ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
604 ;
605 ; CM-LABEL: s_exp2_v3f32:
606 ; CM: ; %bb.0:
607 ; CM-NEXT: ALU 35, @4, KC0[CB0:0-32], KC1[]
608 ; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T3.X
609 ; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T2.X
610 ; CM-NEXT: CF_END
611 ; CM-NEXT: ALU clause starting at 4:
612 ; CM-NEXT: SETGT * T0.W, literal.x, KC0[3].W,
613 ; CM-NEXT: -1023672320(-1.260000e+02), 0(0.000000e+00)
614 ; CM-NEXT: CNDE T0.Y, PV.W, 0.0, literal.x,
615 ; CM-NEXT: SETGT T0.Z, literal.y, KC0[3].Z,
616 ; CM-NEXT: SETGT * T1.W, literal.y, KC0[3].Y,
617 ; CM-NEXT: 1115684864(6.400000e+01), -1023672320(-1.260000e+02)
618 ; CM-NEXT: CNDE T0.X, PV.W, 0.0, literal.x,
619 ; CM-NEXT: CNDE T1.Y, PV.Z, 0.0, literal.x,
620 ; CM-NEXT: CNDE T1.Z, T0.W, 1.0, literal.y,
621 ; CM-NEXT: ADD * T0.W, KC0[3].W, PV.Y,
622 ; CM-NEXT: 1115684864(6.400000e+01), 528482304(5.421011e-20)
623 ; CM-NEXT: EXP_IEEE T0.X (MASKED), T0.W,
624 ; CM-NEXT: EXP_IEEE T0.Y, T0.W,
625 ; CM-NEXT: EXP_IEEE T0.Z (MASKED), T0.W,
626 ; CM-NEXT: EXP_IEEE * T0.W (MASKED), T0.W,
627 ; CM-NEXT: MUL_IEEE T1.X, PV.Y, T1.Z,
628 ; CM-NEXT: CNDE T0.Y, T0.Z, 1.0, literal.x,
629 ; CM-NEXT: ADD_INT T0.Z, KC0[2].Y, literal.y,
630 ; CM-NEXT: ADD * T0.W, KC0[3].Z, T1.Y,
631 ; CM-NEXT: 528482304(5.421011e-20), 8(1.121039e-44)
632 ; CM-NEXT: EXP_IEEE T0.X (MASKED), T0.W,
633 ; CM-NEXT: EXP_IEEE T0.Y (MASKED), T0.W,
634 ; CM-NEXT: EXP_IEEE T0.Z (MASKED), T0.W,
635 ; CM-NEXT: EXP_IEEE * T0.W, T0.W,
636 ; CM-NEXT: LSHR T2.X, T0.Z, literal.x,
637 ; CM-NEXT: MUL_IEEE T0.Y, PV.W, T0.Y,
638 ; CM-NEXT: CNDE T0.Z, T1.W, 1.0, literal.y,
639 ; CM-NEXT: ADD * T0.W, KC0[3].Y, T0.X,
640 ; CM-NEXT: 2(2.802597e-45), 528482304(5.421011e-20)
641 ; CM-NEXT: EXP_IEEE T0.X, T0.W,
642 ; CM-NEXT: EXP_IEEE T0.Y (MASKED), T0.W,
643 ; CM-NEXT: EXP_IEEE T0.Z (MASKED), T0.W,
644 ; CM-NEXT: EXP_IEEE * T0.W (MASKED), T0.W,
645 ; CM-NEXT: MUL_IEEE * T0.X, PV.X, T0.Z,
646 ; CM-NEXT: LSHR * T3.X, KC0[2].Y, literal.x,
647 ; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
648 %result = call <3 x float> @llvm.exp2.v3f32(<3 x float> %in)
649 store <3 x float> %result, ptr addrspace(1) %out
650 ret void
651 }
653 ; FIXME: We should be able to merge these packets together on Cayman so we
654 ; have a maximum of 4 instructions.
655 define amdgpu_kernel void @s_exp2_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
656 ; SI-SDAG-LABEL: s_exp2_v4f32:
657 ; SI-SDAG: ; %bb.0:
658 ; SI-SDAG-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
659 ; SI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
660 ; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
661 ; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
662 ; SI-SDAG-NEXT: v_mov_b32_e32 v3, 0x42800000
663 ; SI-SDAG-NEXT: s_mov_b32 s7, 0xf000
664 ; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
665 ; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
666 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v1, vcc
667 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v3, vcc
668 ; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
669 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v5, 1.0, v1, vcc
670 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v6, 0, v3, vcc
671 ; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
672 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v7, 1.0, v1, vcc
673 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v8, 0, v3, vcc
674 ; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
675 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc
676 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
677 ; SI-SDAG-NEXT: v_add_f32_e32 v4, s3, v4
678 ; SI-SDAG-NEXT: v_add_f32_e32 v6, s2, v6
679 ; SI-SDAG-NEXT: v_add_f32_e32 v8, s1, v8
680 ; SI-SDAG-NEXT: v_add_f32_e32 v1, s0, v1
681 ; SI-SDAG-NEXT: v_exp_f32_e32 v4, v4
682 ; SI-SDAG-NEXT: v_exp_f32_e32 v6, v6
683 ; SI-SDAG-NEXT: v_exp_f32_e32 v8, v8
684 ; SI-SDAG-NEXT: v_exp_f32_e32 v9, v1
685 ; SI-SDAG-NEXT: s_mov_b32 s6, -1
686 ; SI-SDAG-NEXT: v_mul_f32_e32 v3, v4, v2
687 ; SI-SDAG-NEXT: v_mul_f32_e32 v2, v6, v5
688 ; SI-SDAG-NEXT: v_mul_f32_e32 v1, v8, v7
689 ; SI-SDAG-NEXT: v_mul_f32_e32 v0, v9, v0
690 ; SI-SDAG-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
691 ; SI-SDAG-NEXT: s_endpgm
692 ;
693 ; SI-GISEL-LABEL: s_exp2_v4f32:
694 ; SI-GISEL: ; %bb.0:
695 ; SI-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xd
696 ; SI-GISEL-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x9
697 ; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2fc0000
698 ; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x42800000
699 ; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0x1f800000
700 ; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
701 ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v2
702 ; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
703 ; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s5, v2
704 ; SI-GISEL-NEXT: v_add_f32_e32 v0, s4, v0
705 ; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[0:1]
706 ; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
707 ; SI-GISEL-NEXT: v_add_f32_e32 v1, s5, v1
708 ; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1
709 ; SI-GISEL-NEXT: v_cndmask_b32_e32 v5, 1.0, v4, vcc
710 ; SI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v5
711 ; SI-GISEL-NEXT: v_cndmask_b32_e64 v5, 1.0, v4, s[0:1]
712 ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v2
713 ; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v2
714 ; SI-GISEL-NEXT: v_mul_f32_e32 v1, v1, v5
715 ; SI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v3, vcc
716 ; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v3, s[0:1]
717 ; SI-GISEL-NEXT: v_add_f32_e32 v5, s6, v5
718 ; SI-GISEL-NEXT: v_add_f32_e32 v2, s7, v2
719 ; SI-GISEL-NEXT: v_exp_f32_e32 v5, v5
720 ; SI-GISEL-NEXT: v_exp_f32_e32 v3, v2
721 ; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 1.0, v4, vcc
722 ; SI-GISEL-NEXT: v_cndmask_b32_e64 v4, 1.0, v4, s[0:1]
723 ; SI-GISEL-NEXT: v_mul_f32_e32 v2, v5, v2
724 ; SI-GISEL-NEXT: v_mul_f32_e32 v3, v3, v4
725 ; SI-GISEL-NEXT: s_mov_b32 s10, -1
726 ; SI-GISEL-NEXT: s_mov_b32 s11, 0xf000
727 ; SI-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
728 ; SI-GISEL-NEXT: s_endpgm
729 ;
730 ; VI-SDAG-LABEL: s_exp2_v4f32:
731 ; VI-SDAG: ; %bb.0:
732 ; VI-SDAG-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
733 ; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
734 ; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
735 ; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
736 ; VI-SDAG-NEXT: v_mov_b32_e32 v3, 0x42800000
737 ; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
738 ; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s7, v0
739 ; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v1, vcc
740 ; VI-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v3, vcc
741 ; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
742 ; VI-SDAG-NEXT: v_cndmask_b32_e32 v5, 1.0, v1, vcc
743 ; VI-SDAG-NEXT: v_cndmask_b32_e32 v6, 0, v3, vcc
744 ; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s5, v0
745 ; VI-SDAG-NEXT: v_cndmask_b32_e32 v7, 1.0, v1, vcc
746 ; VI-SDAG-NEXT: v_cndmask_b32_e32 v8, 0, v3, vcc
747 ; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0
748 ; VI-SDAG-NEXT: v_add_f32_e32 v4, s7, v4
749 ; VI-SDAG-NEXT: v_add_f32_e32 v6, s6, v6
750 ; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc
751 ; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
752 ; VI-SDAG-NEXT: v_exp_f32_e32 v4, v4
753 ; VI-SDAG-NEXT: v_exp_f32_e32 v6, v6
754 ; VI-SDAG-NEXT: v_add_f32_e32 v8, s5, v8
755 ; VI-SDAG-NEXT: v_add_f32_e32 v1, s4, v1
756 ; VI-SDAG-NEXT: v_exp_f32_e32 v8, v8
757 ; VI-SDAG-NEXT: v_exp_f32_e32 v9, v1
758 ; VI-SDAG-NEXT: v_mul_f32_e32 v3, v4, v2
759 ; VI-SDAG-NEXT: v_mul_f32_e32 v2, v6, v5
760 ; VI-SDAG-NEXT: v_mov_b32_e32 v5, s1
761 ; VI-SDAG-NEXT: v_mul_f32_e32 v1, v8, v7
762 ; VI-SDAG-NEXT: v_mul_f32_e32 v0, v9, v0
763 ; VI-SDAG-NEXT: v_mov_b32_e32 v4, s0
764 ; VI-SDAG-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
765 ; VI-SDAG-NEXT: s_endpgm
766 ;
767 ; VI-GISEL-LABEL: s_exp2_v4f32:
768 ; VI-GISEL: ; %bb.0:
769 ; VI-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
770 ; VI-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
771 ; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2fc0000
772 ; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x42800000
773 ; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x1f800000
774 ; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
775 ; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v2
776 ; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
777 ; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s5, v2
778 ; VI-GISEL-NEXT: v_add_f32_e32 v0, s4, v0
779 ; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[0:1]
780 ; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0
781 ; VI-GISEL-NEXT: v_add_f32_e32 v1, s5, v1
782 ; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
783 ; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, 1.0, v4, vcc
784 ; VI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v5
785 ; VI-GISEL-NEXT: v_cndmask_b32_e64 v5, 1.0, v4, s[0:1]
786 ; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v2
787 ; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v2
788 ; VI-GISEL-NEXT: v_mul_f32_e32 v1, v1, v5
789 ; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v3, vcc
790 ; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v3, s[0:1]
791 ; VI-GISEL-NEXT: v_add_f32_e32 v5, s6, v5
792 ; VI-GISEL-NEXT: v_add_f32_e32 v2, s7, v2
793 ; VI-GISEL-NEXT: v_exp_f32_e32 v5, v5
794 ; VI-GISEL-NEXT: v_exp_f32_e32 v3, v2
795 ; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 1.0, v4, vcc
796 ; VI-GISEL-NEXT: v_cndmask_b32_e64 v4, 1.0, v4, s[0:1]
797 ; VI-GISEL-NEXT: v_mul_f32_e32 v2, v5, v2
798 ; VI-GISEL-NEXT: v_mul_f32_e32 v3, v3, v4
799 ; VI-GISEL-NEXT: v_mov_b32_e32 v5, s3
800 ; VI-GISEL-NEXT: v_mov_b32_e32 v4, s2
801 ; VI-GISEL-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
802 ; VI-GISEL-NEXT: s_endpgm
803 ;
804 ; GFX900-SDAG-LABEL: s_exp2_v4f32:
805 ; GFX900-SDAG: ; %bb.0:
806 ; GFX900-SDAG-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
807 ; GFX900-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
808 ; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
809 ; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
810 ; GFX900-SDAG-NEXT: v_mov_b32_e32 v3, 0x42800000
811 ; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0)
812 ; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s7, v0
813 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v1, vcc
814 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v3, vcc
815 ; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
816 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v6, 1.0, v1, vcc
817 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v7, 0, v3, vcc
818 ; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s5, v0
819 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v8, 1.0, v1, vcc
820 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v9, 0, v3, vcc
821 ; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0
822 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc
823 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
824 ; GFX900-SDAG-NEXT: v_add_f32_e32 v5, s7, v5
825 ; GFX900-SDAG-NEXT: v_add_f32_e32 v7, s6, v7
826 ; GFX900-SDAG-NEXT: v_add_f32_e32 v9, s5, v9
827 ; GFX900-SDAG-NEXT: v_add_f32_e32 v1, s4, v1
828 ; GFX900-SDAG-NEXT: v_exp_f32_e32 v5, v5
829 ; GFX900-SDAG-NEXT: v_exp_f32_e32 v7, v7
830 ; GFX900-SDAG-NEXT: v_exp_f32_e32 v9, v9
831 ; GFX900-SDAG-NEXT: v_exp_f32_e32 v10, v1
832 ; GFX900-SDAG-NEXT: v_mov_b32_e32 v4, 0
833 ; GFX900-SDAG-NEXT: v_mul_f32_e32 v3, v5, v2
834 ; GFX900-SDAG-NEXT: v_mul_f32_e32 v2, v7, v6
835 ; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, v9, v8
836 ; GFX900-SDAG-NEXT: v_mul_f32_e32 v0, v10, v0
837 ; GFX900-SDAG-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3]
838 ; GFX900-SDAG-NEXT: s_endpgm
839 ;
840 ; GFX900-GISEL-LABEL: s_exp2_v4f32:
841 ; GFX900-GISEL: ; %bb.0:
842 ; GFX900-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
843 ; GFX900-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
844 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2fc0000
845 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x42800000
846 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0x1f800000
847 ; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
848 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v2
849 ; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
850 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s5, v2
851 ; GFX900-GISEL-NEXT: v_add_f32_e32 v0, s4, v0
852 ; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[0:1]
853 ; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0
854 ; GFX900-GISEL-NEXT: v_add_f32_e32 v1, s5, v1
855 ; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v1
856 ; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, 1.0, v4, vcc
857 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, v0, v5
858 ; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v5, 1.0, v4, s[0:1]
859 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v2
860 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v2
861 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, v1, v5
862 ; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v3, vcc
863 ; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v3, s[0:1]
864 ; GFX900-GISEL-NEXT: v_add_f32_e32 v5, s6, v5
865 ; GFX900-GISEL-NEXT: v_add_f32_e32 v2, s7, v2
866 ; GFX900-GISEL-NEXT: v_exp_f32_e32 v5, v5
867 ; GFX900-GISEL-NEXT: v_exp_f32_e32 v3, v2
868 ; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 1.0, v4, vcc
869 ; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v4, 1.0, v4, s[0:1]
870 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, v5, v2
871 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v3, v3, v4
872 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
873 ; GFX900-GISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3]
874 ; GFX900-GISEL-NEXT: s_endpgm
875 ;
876 ; R600-LABEL: s_exp2_v4f32:
877 ; R600: ; %bb.0:
878 ; R600-NEXT: ALU 33, @4, KC0[CB0:0-32], KC1[]
879 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
880 ; R600-NEXT: CF_END
881 ; R600-NEXT: PAD
882 ; R600-NEXT: ALU clause starting at 4:
883 ; R600-NEXT: SETGT T0.W, literal.x, KC0[4].X,
884 ; R600-NEXT: SETGT * T1.W, literal.x, KC0[3].W,
885 ; R600-NEXT: -1023672320(-1.260000e+02), 0(0.000000e+00)
886 ; R600-NEXT: CNDE * T2.W, PV.W, 0.0, literal.x,
887 ; R600-NEXT: 1115684864(6.400000e+01), 0(0.000000e+00)
888 ; R600-NEXT: ADD T0.Z, KC0[4].X, PV.W,
889 ; R600-NEXT: SETGT T2.W, literal.x, KC0[3].Z,
890 ; R600-NEXT: CNDE * T3.W, T1.W, 0.0, literal.y,
891 ; R600-NEXT: -1023672320(-1.260000e+02), 1115684864(6.400000e+01)
892 ; R600-NEXT: ADD T0.X, KC0[3].W, PS,
893 ; R600-NEXT: CNDE T0.Y, T0.W, 1.0, literal.x,
894 ; R600-NEXT: SETGT T1.Z, literal.y, KC0[3].Y,
895 ; R600-NEXT: CNDE T0.W, PV.W, 0.0, literal.z,
896 ; R600-NEXT: EXP_IEEE * T0.Z, PV.Z,
897 ; R600-NEXT: 528482304(5.421011e-20), -1023672320(-1.260000e+02)
898 ; R600-NEXT: 1115684864(6.400000e+01), 0(0.000000e+00)
899 ; R600-NEXT: ADD T1.X, KC0[3].Z, PV.W,
900 ; R600-NEXT: CNDE T1.Y, T1.W, 1.0, literal.x,
901 ; R600-NEXT: CNDE T2.Z, PV.Z, 0.0, literal.y,
902 ; R600-NEXT: MUL_IEEE T0.W, PS, PV.Y,
903 ; R600-NEXT: EXP_IEEE * T0.X, PV.X,
904 ; R600-NEXT: 528482304(5.421011e-20), 1115684864(6.400000e+01)
905 ; R600-NEXT: ADD T2.Y, KC0[3].Y, PV.Z,
906 ; R600-NEXT: MUL_IEEE T0.Z, PS, PV.Y,
907 ; R600-NEXT: CNDE T1.W, T2.W, 1.0, literal.x,
908 ; R600-NEXT: EXP_IEEE * T0.X, PV.X,
909 ; R600-NEXT: 528482304(5.421011e-20), 0(0.000000e+00)
910 ; R600-NEXT: MUL_IEEE T0.Y, PS, PV.W,
911 ; R600-NEXT: CNDE T1.W, T1.Z, 1.0, literal.x,
912 ; R600-NEXT: EXP_IEEE * T0.X, PV.Y,
913 ; R600-NEXT: 528482304(5.421011e-20), 0(0.000000e+00)
914 ; R600-NEXT: MUL_IEEE T0.X, PS, PV.W,
915 ; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
916 ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
917 ;
918 ; CM-LABEL: s_exp2_v4f32:
919 ; CM: ; %bb.0:
920 ; CM-NEXT: ALU 43, @4, KC0[CB0:0-32], KC1[]
921 ; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T1.X
922 ; CM-NEXT: CF_END
923 ; CM-NEXT: PAD
924 ; CM-NEXT: ALU clause starting at 4:
925 ; CM-NEXT: SETGT * T0.W, literal.x, KC0[4].X,
926 ; CM-NEXT: -1023672320(-1.260000e+02), 0(0.000000e+00)
927 ; CM-NEXT: CNDE T0.Y, PV.W, 0.0, literal.x,
928 ; CM-NEXT: SETGT T0.Z, literal.y, KC0[3].W,
929 ; CM-NEXT: SETGT * T1.W, literal.y, KC0[3].Z,
930 ; CM-NEXT: 1115684864(6.400000e+01), -1023672320(-1.260000e+02)
931 ; CM-NEXT: CNDE T0.X, PV.W, 0.0, literal.x,
932 ; CM-NEXT: CNDE T1.Y, T0.W, 1.0, literal.y,
933 ; CM-NEXT: CNDE T1.Z, PV.Z, 0.0, literal.x,
934 ; CM-NEXT: ADD * T0.W, KC0[4].X, PV.Y,
935 ; CM-NEXT: 1115684864(6.400000e+01), 528482304(5.421011e-20)
936 ; CM-NEXT: EXP_IEEE T0.X (MASKED), T0.W,
937 ; CM-NEXT: EXP_IEEE T0.Y, T0.W,
938 ; CM-NEXT: EXP_IEEE T0.Z (MASKED), T0.W,
939 ; CM-NEXT: EXP_IEEE * T0.W (MASKED), T0.W,
940 ; CM-NEXT: CNDE T1.X, T0.Z, 1.0, literal.x,
941 ; CM-NEXT: SETGT T2.Y, literal.y, KC0[3].Y,
942 ; CM-NEXT: ADD T0.Z, KC0[3].W, T1.Z,
943 ; CM-NEXT: MUL_IEEE * T0.W, PV.Y, T1.Y,
944 ; CM-NEXT: 528482304(5.421011e-20), -1023672320(-1.260000e+02)
945 ; CM-NEXT: EXP_IEEE T0.X (MASKED), T0.Z,
946 ; CM-NEXT: EXP_IEEE T0.Y, T0.Z,
947 ; CM-NEXT: EXP_IEEE T0.Z (MASKED), T0.Z,
948 ; CM-NEXT: EXP_IEEE * T0.W (MASKED), T0.Z,
949 ; CM-NEXT: CNDE T2.X, T2.Y, 0.0, literal.x,
950 ; CM-NEXT: CNDE T1.Y, T1.W, 1.0, literal.y,
951 ; CM-NEXT: MUL_IEEE T0.Z, PV.Y, T1.X,
952 ; CM-NEXT: ADD * T1.W, KC0[3].Z, T0.X, BS:VEC_021/SCL_122
953 ; CM-NEXT: 1115684864(6.400000e+01), 528482304(5.421011e-20)
954 ; CM-NEXT: EXP_IEEE T0.X, T1.W,
955 ; CM-NEXT: EXP_IEEE T0.Y (MASKED), T1.W,
956 ; CM-NEXT: EXP_IEEE T0.Z (MASKED), T1.W,
957 ; CM-NEXT: EXP_IEEE * T0.W (MASKED), T1.W,
958 ; CM-NEXT: MUL_IEEE T0.Y, PV.X, T1.Y,
959 ; CM-NEXT: CNDE T1.Z, T2.Y, 1.0, literal.x,
960 ; CM-NEXT: ADD * T1.W, KC0[3].Y, T2.X,
961 ; CM-NEXT: 528482304(5.421011e-20), 0(0.000000e+00)
962 ; CM-NEXT: EXP_IEEE T0.X, T1.W,
963 ; CM-NEXT: EXP_IEEE T0.Y (MASKED), T1.W,
964 ; CM-NEXT: EXP_IEEE T0.Z (MASKED), T1.W,
965 ; CM-NEXT: EXP_IEEE * T0.W (MASKED), T1.W,
966 ; CM-NEXT: MUL_IEEE * T0.X, PV.X, T1.Z,
967 ; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
968 ; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
969 %result = call <4 x float> @llvm.exp2.v4f32(<4 x float> %in)
970 store <4 x float> %result, ptr addrspace(1) %out
971 ret void
972 }
974 define float @v_exp2_f32(float %in) {
975 ; GCN-SDAG-LABEL: v_exp2_f32:
976 ; GCN-SDAG: ; %bb.0:
977 ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
978 ; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc2fc0000
979 ; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
980 ; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
981 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
982 ; GCN-SDAG-NEXT: v_add_f32_e32 v0, v0, v2
983 ; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0
984 ; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
985 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
986 ; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1
987 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
988 ;
989 ; GCN-GISEL-LABEL: v_exp2_f32:
990 ; GCN-GISEL: ; %bb.0:
991 ; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
992 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
993 ; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
994 ; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
995 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
996 ; GCN-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
997 ; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
998 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000
999 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1000 ; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
1001 ; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]
1002 ;
1003 ; R600-LABEL: v_exp2_f32:
1004 ; R600: ; %bb.0:
1005 ; R600-NEXT: CF_END
1006 ; R600-NEXT: PAD
1007 ;
1008 ; CM-LABEL: v_exp2_f32:
1009 ; CM: ; %bb.0:
1010 ; CM-NEXT: CF_END
1011 ; CM-NEXT: PAD
1012 %result = call float @llvm.exp2.f32(float %in)
1013 ret float %result
1014 }
1016 define float @v_exp2_fabs_f32(float %in) {
1017 ; GCN-SDAG-LABEL: v_exp2_fabs_f32:
1018 ; GCN-SDAG: ; %bb.0:
1019 ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1020 ; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc2fc0000
1021 ; GCN-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
1022 ; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
1023 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
1024 ; GCN-SDAG-NEXT: v_add_f32_e64 v0, |v0|, v2
1025 ; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0
1026 ; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
1027 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1028 ; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1
1029 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
1030 ;
1031 ; GCN-GISEL-LABEL: v_exp2_fabs_f32:
1032 ; GCN-GISEL: ; %bb.0:
1033 ; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1034 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
1035 ; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
1036 ; GCN-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
1037 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
1038 ; GCN-GISEL-NEXT: v_add_f32_e64 v0, |v0|, v1
1039 ; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
1040 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000
1041 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1042 ; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
1043 ; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]
1044 ;
1045 ; R600-LABEL: v_exp2_fabs_f32:
1046 ; R600: ; %bb.0:
1047 ; R600-NEXT: CF_END
1048 ; R600-NEXT: PAD
1049 ;
1050 ; CM-LABEL: v_exp2_fabs_f32:
1051 ; CM: ; %bb.0:
1052 ; CM-NEXT: CF_END
1053 ; CM-NEXT: PAD
1054 %fabs = call float @llvm.fabs.f32(float %in)
1055 %result = call float @llvm.exp2.f32(float %fabs)
1056 ret float %result
1057 }
1059 define float @v_exp2_fneg_fabs_f32(float %in) {
1060 ; GCN-SDAG-LABEL: v_exp2_fneg_fabs_f32:
1061 ; GCN-SDAG: ; %bb.0:
1062 ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1063 ; GCN-SDAG-NEXT: s_mov_b32 s4, 0x42fc0000
1064 ; GCN-SDAG-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, s4
1065 ; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
1066 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
1067 ; GCN-SDAG-NEXT: v_sub_f32_e64 v0, v2, |v0|
1068 ; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0
1069 ; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
1070 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1071 ; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1
1072 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
1073 ;
1074 ; GCN-GISEL-LABEL: v_exp2_fneg_fabs_f32:
1075 ; GCN-GISEL: ; %bb.0:
1076 ; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1077 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
1078 ; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
1079 ; GCN-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -|v0|, v1
1080 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
1081 ; GCN-GISEL-NEXT: v_sub_f32_e64 v0, v1, |v0|
1082 ; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
1083 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000
1084 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1085 ; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
1086 ; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]
1087 ;
1088 ; R600-LABEL: v_exp2_fneg_fabs_f32:
1089 ; R600: ; %bb.0:
1090 ; R600-NEXT: CF_END
1091 ; R600-NEXT: PAD
1092 ;
1093 ; CM-LABEL: v_exp2_fneg_fabs_f32:
1094 ; CM: ; %bb.0:
1095 ; CM-NEXT: CF_END
1096 ; CM-NEXT: PAD
1097 %fabs = call float @llvm.fabs.f32(float %in)
1098 %fneg.fabs = fneg float %fabs
1099 %result = call float @llvm.exp2.f32(float %fneg.fabs)
1100 ret float %result
1101 }
1103 define float @v_exp2_fneg_f32(float %in) {
1104 ; GCN-SDAG-LABEL: v_exp2_fneg_f32:
1105 ; GCN-SDAG: ; %bb.0:
1106 ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1107 ; GCN-SDAG-NEXT: s_mov_b32 s4, 0x42fc0000
1108 ; GCN-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0
1109 ; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
1110 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
1111 ; GCN-SDAG-NEXT: v_sub_f32_e32 v0, v2, v0
1112 ; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0
1113 ; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
1114 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1115 ; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1
1116 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
1117 ;
1118 ; GCN-GISEL-LABEL: v_exp2_fneg_f32:
1119 ; GCN-GISEL: ; %bb.0:
1120 ; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1121 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
1122 ; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
1123 ; GCN-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -v0, v1
1124 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
1125 ; GCN-GISEL-NEXT: v_sub_f32_e32 v0, v1, v0
1126 ; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
1127 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000
1128 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1129 ; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
1130 ; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]
1131 ;
1132 ; R600-LABEL: v_exp2_fneg_f32:
1133 ; R600: ; %bb.0:
1134 ; R600-NEXT: CF_END
1135 ; R600-NEXT: PAD
1136 ;
1137 ; CM-LABEL: v_exp2_fneg_f32:
1138 ; CM: ; %bb.0:
1139 ; CM-NEXT: CF_END
1140 ; CM-NEXT: PAD
1141 %fneg = fneg float %in
1142 %result = call float @llvm.exp2.f32(float %fneg)
1143 ret float %result
1144 }
1146 define float @v_exp2_f32_fast(float %in) {
1147 ; GCN-SDAG-LABEL: v_exp2_f32_fast:
1148 ; GCN-SDAG: ; %bb.0:
1149 ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1150 ; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc2fc0000
1151 ; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
1152 ; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
1153 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
1154 ; GCN-SDAG-NEXT: v_add_f32_e32 v0, v0, v2
1155 ; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0
1156 ; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
1157 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1158 ; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1
1159 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
1160 ;
1161 ; GCN-GISEL-LABEL: v_exp2_f32_fast:
1162 ; GCN-GISEL: ; %bb.0:
1163 ; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1164 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
1165 ; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
1166 ; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
1167 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
1168 ; GCN-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
1169 ; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
1170 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000
1171 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1172 ; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
1173 ; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]
1174 ;
1175 ; R600-LABEL: v_exp2_f32_fast:
1176 ; R600: ; %bb.0:
1177 ; R600-NEXT: CF_END
1178 ; R600-NEXT: PAD
1179 ;
1180 ; CM-LABEL: v_exp2_f32_fast:
1181 ; CM: ; %bb.0:
1182 ; CM-NEXT: CF_END
1183 ; CM-NEXT: PAD
1184 %result = call fast float @llvm.exp2.f32(float %in)
1185 ret float %result
1186 }
1188 define float @v_exp2_f32_unsafe_math_attr(float %in) "unsafe-fp-math"="true" {
1189 ; GCN-SDAG-LABEL: v_exp2_f32_unsafe_math_attr:
1190 ; GCN-SDAG: ; %bb.0:
1191 ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1192 ; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc2fc0000
1193 ; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
1194 ; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
1195 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
1196 ; GCN-SDAG-NEXT: v_add_f32_e32 v0, v0, v2
1197 ; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0
1198 ; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
1199 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1200 ; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1
1201 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
1202 ;
1203 ; GCN-GISEL-LABEL: v_exp2_f32_unsafe_math_attr:
1204 ; GCN-GISEL: ; %bb.0:
1205 ; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1206 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
1207 ; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
1208 ; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
1209 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
1210 ; GCN-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
1211 ; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
1212 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000
1213 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1214 ; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
1215 ; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]
1216 ;
1217 ; R600-LABEL: v_exp2_f32_unsafe_math_attr:
1218 ; R600: ; %bb.0:
1219 ; R600-NEXT: CF_END
1220 ; R600-NEXT: PAD
1221 ;
1222 ; CM-LABEL: v_exp2_f32_unsafe_math_attr:
1223 ; CM: ; %bb.0:
1224 ; CM-NEXT: CF_END
1225 ; CM-NEXT: PAD
1226 %result = call float @llvm.exp2.f32(float %in)
1227 ret float %result
1228 }
1230 define float @v_exp2_f32_approx_fn_attr(float %in) "approx-func-fp-math"="true" {
1231 ; GCN-SDAG-LABEL: v_exp2_f32_approx_fn_attr:
1232 ; GCN-SDAG: ; %bb.0:
1233 ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1234 ; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc2fc0000
1235 ; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
1236 ; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
1237 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
1238 ; GCN-SDAG-NEXT: v_add_f32_e32 v0, v0, v2
1239 ; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0
1240 ; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
1241 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1242 ; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1
1243 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
1244 ;
1245 ; GCN-GISEL-LABEL: v_exp2_f32_approx_fn_attr:
1246 ; GCN-GISEL: ; %bb.0:
1247 ; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1248 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
1249 ; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
1250 ; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
1251 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
1252 ; GCN-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
1253 ; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
1254 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000
1255 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1256 ; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
1257 ; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]
1258 ;
1259 ; R600-LABEL: v_exp2_f32_approx_fn_attr:
1260 ; R600: ; %bb.0:
1261 ; R600-NEXT: CF_END
1262 ; R600-NEXT: PAD
1263 ;
1264 ; CM-LABEL: v_exp2_f32_approx_fn_attr:
1265 ; CM: ; %bb.0:
1266 ; CM-NEXT: CF_END
1267 ; CM-NEXT: PAD
1268 %result = call float @llvm.exp2.f32(float %in)
1269 ret float %result
1270 }
1272 define float @v_exp2_f32_ninf(float %in) {
1273 ; GCN-SDAG-LABEL: v_exp2_f32_ninf:
1274 ; GCN-SDAG: ; %bb.0:
1275 ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1276 ; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc2fc0000
1277 ; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
1278 ; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
1279 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
1280 ; GCN-SDAG-NEXT: v_add_f32_e32 v0, v0, v2
1281 ; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0
1282 ; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
1283 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1284 ; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1
1285 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
1286 ;
1287 ; GCN-GISEL-LABEL: v_exp2_f32_ninf:
1288 ; GCN-GISEL: ; %bb.0:
1289 ; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1290 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
1291 ; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
1292 ; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
1293 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
1294 ; GCN-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
1295 ; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
1296 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000
1297 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1298 ; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
1299 ; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]
1300 ;
1301 ; R600-LABEL: v_exp2_f32_ninf:
1302 ; R600: ; %bb.0:
1303 ; R600-NEXT: CF_END
1304 ; R600-NEXT: PAD
1305 ;
1306 ; CM-LABEL: v_exp2_f32_ninf:
1307 ; CM: ; %bb.0:
1308 ; CM-NEXT: CF_END
1309 ; CM-NEXT: PAD
1310 %result = call ninf float @llvm.exp2.f32(float %in)
1311 ret float %result
1312 }
1314 define float @v_exp2_f32_afn(float %in) {
1315 ; GCN-SDAG-LABEL: v_exp2_f32_afn:
1316 ; GCN-SDAG: ; %bb.0:
1317 ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1318 ; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc2fc0000
1319 ; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
1320 ; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
1321 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
1322 ; GCN-SDAG-NEXT: v_add_f32_e32 v0, v0, v2
1323 ; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0
1324 ; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
1325 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1326 ; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1
1327 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
1328 ;
1329 ; GCN-GISEL-LABEL: v_exp2_f32_afn:
1330 ; GCN-GISEL: ; %bb.0:
1331 ; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1332 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
1333 ; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
1334 ; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
1335 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
1336 ; GCN-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
1337 ; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
1338 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000
1339 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1340 ; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
1341 ; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]
1342 ;
1343 ; R600-LABEL: v_exp2_f32_afn:
1344 ; R600: ; %bb.0:
1345 ; R600-NEXT: CF_END
1346 ; R600-NEXT: PAD
1347 ;
1348 ; CM-LABEL: v_exp2_f32_afn:
1349 ; CM: ; %bb.0:
1350 ; CM-NEXT: CF_END
1351 ; CM-NEXT: PAD
1352 %result = call afn float @llvm.exp2.f32(float %in)
1353 ret float %result
1354 }
1356 define float @v_exp2_f32_afn_daz(float %in) #0 {
1357 ; GCN-LABEL: v_exp2_f32_afn_daz:
1358 ; GCN: ; %bb.0:
1359 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1360 ; GCN-NEXT: v_exp_f32_e32 v0, v0
1361 ; GCN-NEXT: s_setpc_b64 s[30:31]
1362 ;
1363 ; R600-LABEL: v_exp2_f32_afn_daz:
1364 ; R600: ; %bb.0:
1365 ; R600-NEXT: CF_END
1366 ; R600-NEXT: PAD
1367 ;
1368 ; CM-LABEL: v_exp2_f32_afn_daz:
1369 ; CM: ; %bb.0:
1370 ; CM-NEXT: CF_END
1371 ; CM-NEXT: PAD
1372 %result = call afn float @llvm.exp2.f32(float %in)
1373 ret float %result
1374 }
1376 define float @v_exp2_f32_afn_dynamic(float %in) #1 {
1377 ; GCN-SDAG-LABEL: v_exp2_f32_afn_dynamic:
1378 ; GCN-SDAG: ; %bb.0:
1379 ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1380 ; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc2fc0000
1381 ; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
1382 ; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
1383 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
1384 ; GCN-SDAG-NEXT: v_add_f32_e32 v0, v0, v2
1385 ; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0
1386 ; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
1387 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1388 ; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1
1389 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
1390 ;
1391 ; GCN-GISEL-LABEL: v_exp2_f32_afn_dynamic:
1392 ; GCN-GISEL: ; %bb.0:
1393 ; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1394 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
1395 ; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
1396 ; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
1397 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
1398 ; GCN-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
1399 ; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
1400 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000
1401 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1402 ; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
1403 ; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]
1404 ;
1405 ; R600-LABEL: v_exp2_f32_afn_dynamic:
1406 ; R600: ; %bb.0:
1407 ; R600-NEXT: CF_END
1408 ; R600-NEXT: PAD
1409 ;
1410 ; CM-LABEL: v_exp2_f32_afn_dynamic:
1411 ; CM: ; %bb.0:
1412 ; CM-NEXT: CF_END
1413 ; CM-NEXT: PAD
1414 %result = call afn float @llvm.exp2.f32(float %in)
1415 ret float %result
1416 }
1418 define float @v_fabs_exp2_f32_afn(float %in) {
1419 ; GCN-SDAG-LABEL: v_fabs_exp2_f32_afn:
1420 ; GCN-SDAG: ; %bb.0:
1421 ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1422 ; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc2fc0000
1423 ; GCN-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
1424 ; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
1425 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
1426 ; GCN-SDAG-NEXT: v_add_f32_e64 v0, |v0|, v2
1427 ; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0
1428 ; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
1429 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1430 ; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1
1431 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
1432 ;
1433 ; GCN-GISEL-LABEL: v_fabs_exp2_f32_afn:
1434 ; GCN-GISEL: ; %bb.0:
1435 ; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1436 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
1437 ; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
1438 ; GCN-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
1439 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
1440 ; GCN-GISEL-NEXT: v_add_f32_e64 v0, |v0|, v1
1441 ; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
1442 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000
1443 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1444 ; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
1445 ; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]
1446 ;
1447 ; R600-LABEL: v_fabs_exp2_f32_afn:
1448 ; R600: ; %bb.0:
1449 ; R600-NEXT: CF_END
1450 ; R600-NEXT: PAD
1451 ;
1452 ; CM-LABEL: v_fabs_exp2_f32_afn:
1453 ; CM: ; %bb.0:
1454 ; CM-NEXT: CF_END
1455 ; CM-NEXT: PAD
1456 %fabs = call float @llvm.fabs.f32(float %in)
1457 %result = call afn float @llvm.exp2.f32(float %fabs)
1458 ret float %result
1459 }
1461 define float @v_exp2_f32_daz(float %in) #0 {
1462 ; GCN-LABEL: v_exp2_f32_daz:
1463 ; GCN: ; %bb.0:
1464 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1465 ; GCN-NEXT: v_exp_f32_e32 v0, v0
1466 ; GCN-NEXT: s_setpc_b64 s[30:31]
1467 ;
1468 ; R600-LABEL: v_exp2_f32_daz:
1469 ; R600: ; %bb.0:
1470 ; R600-NEXT: CF_END
1471 ; R600-NEXT: PAD
1472 ;
1473 ; CM-LABEL: v_exp2_f32_daz:
1474 ; CM: ; %bb.0:
1475 ; CM-NEXT: CF_END
1476 ; CM-NEXT: PAD
1477 %result = call float @llvm.exp2.f32(float %in)
1478 ret float %result
1479 }
1481 define float @v_exp2_f32_nnan(float %in) {
1482 ; GCN-SDAG-LABEL: v_exp2_f32_nnan:
1483 ; GCN-SDAG: ; %bb.0:
1484 ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1485 ; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc2fc0000
1486 ; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
1487 ; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
1488 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
1489 ; GCN-SDAG-NEXT: v_add_f32_e32 v0, v0, v2
1490 ; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0
1491 ; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
1492 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1493 ; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1
1494 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
1495 ;
1496 ; GCN-GISEL-LABEL: v_exp2_f32_nnan:
1497 ; GCN-GISEL: ; %bb.0:
1498 ; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1499 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
1500 ; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
1501 ; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
1502 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
1503 ; GCN-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
1504 ; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
1505 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000
1506 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1507 ; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
1508 ; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]
1509 ;
1510 ; R600-LABEL: v_exp2_f32_nnan:
1511 ; R600: ; %bb.0:
1512 ; R600-NEXT: CF_END
1513 ; R600-NEXT: PAD
1514 ;
1515 ; CM-LABEL: v_exp2_f32_nnan:
1516 ; CM: ; %bb.0:
1517 ; CM-NEXT: CF_END
1518 ; CM-NEXT: PAD
1519 %result = call nnan float @llvm.exp2.f32(float %in)
1520 ret float %result
1521 }
1523 define float @v_exp2_f32_nnan_daz(float %in) #0 {
1524 ; GCN-LABEL: v_exp2_f32_nnan_daz:
1525 ; GCN: ; %bb.0:
1526 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1527 ; GCN-NEXT: v_exp_f32_e32 v0, v0
1528 ; GCN-NEXT: s_setpc_b64 s[30:31]
1529 ;
1530 ; R600-LABEL: v_exp2_f32_nnan_daz:
1531 ; R600: ; %bb.0:
1532 ; R600-NEXT: CF_END
1533 ; R600-NEXT: PAD
1534 ;
1535 ; CM-LABEL: v_exp2_f32_nnan_daz:
1536 ; CM: ; %bb.0:
1537 ; CM-NEXT: CF_END
1538 ; CM-NEXT: PAD
1539 %result = call nnan float @llvm.exp2.f32(float %in)
1540 ret float %result
1541 }
1543 define float @v_exp2_f32_nnan_dynamic(float %in) #1 {
1544 ; GCN-SDAG-LABEL: v_exp2_f32_nnan_dynamic:
1545 ; GCN-SDAG: ; %bb.0:
1546 ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1547 ; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc2fc0000
1548 ; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
1549 ; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
1550 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
1551 ; GCN-SDAG-NEXT: v_add_f32_e32 v0, v0, v2
1552 ; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0
1553 ; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
1554 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1555 ; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1
1556 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
1557 ;
1558 ; GCN-GISEL-LABEL: v_exp2_f32_nnan_dynamic:
1559 ; GCN-GISEL: ; %bb.0:
1560 ; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1561 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
1562 ; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
1563 ; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
1564 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
1565 ; GCN-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
1566 ; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
1567 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000
1568 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1569 ; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
1570 ; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]
1571 ;
1572 ; R600-LABEL: v_exp2_f32_nnan_dynamic:
1573 ; R600: ; %bb.0:
1574 ; R600-NEXT: CF_END
1575 ; R600-NEXT: PAD
1576 ;
1577 ; CM-LABEL: v_exp2_f32_nnan_dynamic:
1578 ; CM: ; %bb.0:
1579 ; CM-NEXT: CF_END
1580 ; CM-NEXT: PAD
1581 %result = call nnan float @llvm.exp2.f32(float %in)
1582 ret float %result
1583 }
1585 define float @v_exp2_f32_ninf_daz(float %in) #0 {
1586 ; GCN-LABEL: v_exp2_f32_ninf_daz:
1587 ; GCN: ; %bb.0:
1588 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1589 ; GCN-NEXT: v_exp_f32_e32 v0, v0
1590 ; GCN-NEXT: s_setpc_b64 s[30:31]
1591 ;
1592 ; R600-LABEL: v_exp2_f32_ninf_daz:
1593 ; R600: ; %bb.0:
1594 ; R600-NEXT: CF_END
1595 ; R600-NEXT: PAD
1596 ;
1597 ; CM-LABEL: v_exp2_f32_ninf_daz:
1598 ; CM: ; %bb.0:
1599 ; CM-NEXT: CF_END
1600 ; CM-NEXT: PAD
1601 %result = call ninf float @llvm.exp2.f32(float %in)
1602 ret float %result
1603 }
1605 define float @v_exp2_f32_ninf_dynamic(float %in) #1 {
1606 ; GCN-SDAG-LABEL: v_exp2_f32_ninf_dynamic:
1607 ; GCN-SDAG: ; %bb.0:
1608 ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1609 ; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc2fc0000
1610 ; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
1611 ; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
1612 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
1613 ; GCN-SDAG-NEXT: v_add_f32_e32 v0, v0, v2
1614 ; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0
1615 ; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
1616 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1617 ; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1
1618 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
1619 ;
1620 ; GCN-GISEL-LABEL: v_exp2_f32_ninf_dynamic:
1621 ; GCN-GISEL: ; %bb.0:
1622 ; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1623 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
1624 ; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
1625 ; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
1626 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
1627 ; GCN-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
1628 ; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
1629 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000
1630 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1631 ; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
1632 ; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]
1633 ;
1634 ; R600-LABEL: v_exp2_f32_ninf_dynamic:
1635 ; R600: ; %bb.0:
1636 ; R600-NEXT: CF_END
1637 ; R600-NEXT: PAD
1638 ;
1639 ; CM-LABEL: v_exp2_f32_ninf_dynamic:
1640 ; CM: ; %bb.0:
1641 ; CM-NEXT: CF_END
1642 ; CM-NEXT: PAD
1643 %result = call ninf float @llvm.exp2.f32(float %in)
1644 ret float %result
1645 }
1647 define float @v_exp2_f32_nnan_ninf(float %in) {
1648 ; GCN-SDAG-LABEL: v_exp2_f32_nnan_ninf:
1649 ; GCN-SDAG: ; %bb.0:
1650 ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1651 ; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc2fc0000
1652 ; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
1653 ; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
1654 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
1655 ; GCN-SDAG-NEXT: v_add_f32_e32 v0, v0, v2
1656 ; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0
1657 ; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
1658 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1659 ; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1
1660 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
1661 ;
1662 ; GCN-GISEL-LABEL: v_exp2_f32_nnan_ninf:
1663 ; GCN-GISEL: ; %bb.0:
1664 ; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1665 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
1666 ; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
1667 ; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
1668 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
1669 ; GCN-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
1670 ; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
1671 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000
1672 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1673 ; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
1674 ; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]
1675 ;
1676 ; R600-LABEL: v_exp2_f32_nnan_ninf:
1677 ; R600: ; %bb.0:
1678 ; R600-NEXT: CF_END
1679 ; R600-NEXT: PAD
1680 ;
1681 ; CM-LABEL: v_exp2_f32_nnan_ninf:
1682 ; CM: ; %bb.0:
1683 ; CM-NEXT: CF_END
1684 ; CM-NEXT: PAD
1685 %result = call nnan ninf float @llvm.exp2.f32(float %in)
1686 ret float %result
1687 }
1689 define float @v_exp2_f32_nnan_ninf_daz(float %in) #0 {
1690 ; GCN-LABEL: v_exp2_f32_nnan_ninf_daz:
1691 ; GCN: ; %bb.0:
1692 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1693 ; GCN-NEXT: v_exp_f32_e32 v0, v0
1694 ; GCN-NEXT: s_setpc_b64 s[30:31]
1695 ;
1696 ; R600-LABEL: v_exp2_f32_nnan_ninf_daz:
1697 ; R600: ; %bb.0:
1698 ; R600-NEXT: CF_END
1699 ; R600-NEXT: PAD
1700 ;
1701 ; CM-LABEL: v_exp2_f32_nnan_ninf_daz:
1702 ; CM: ; %bb.0:
1703 ; CM-NEXT: CF_END
1704 ; CM-NEXT: PAD
1705 %result = call nnan ninf float @llvm.exp2.f32(float %in)
1706 ret float %result
1707 }
1709 define float @v_exp2_f32_nnan_ninf_dynamic(float %in) #1 {
1710 ; GCN-SDAG-LABEL: v_exp2_f32_nnan_ninf_dynamic:
1711 ; GCN-SDAG: ; %bb.0:
1712 ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1713 ; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc2fc0000
1714 ; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
1715 ; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
1716 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
1717 ; GCN-SDAG-NEXT: v_add_f32_e32 v0, v0, v2
1718 ; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0
1719 ; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
1720 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1721 ; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1
1722 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
1723 ;
1724 ; GCN-GISEL-LABEL: v_exp2_f32_nnan_ninf_dynamic:
1725 ; GCN-GISEL: ; %bb.0:
1726 ; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1727 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
1728 ; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
1729 ; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
1730 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
1731 ; GCN-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
1732 ; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
1733 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000
1734 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1735 ; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
1736 ; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]
1737 ;
1738 ; R600-LABEL: v_exp2_f32_nnan_ninf_dynamic:
1739 ; R600: ; %bb.0:
1740 ; R600-NEXT: CF_END
1741 ; R600-NEXT: PAD
1742 ;
1743 ; CM-LABEL: v_exp2_f32_nnan_ninf_dynamic:
1744 ; CM: ; %bb.0:
1745 ; CM-NEXT: CF_END
1746 ; CM-NEXT: PAD
1747 %result = call nnan ninf float @llvm.exp2.f32(float %in)
1748 ret float %result
1749 }
1751 define float @v_exp2_f32_fast_daz(float %in) #0 {
1752 ; GCN-LABEL: v_exp2_f32_fast_daz:
1753 ; GCN: ; %bb.0:
1754 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1755 ; GCN-NEXT: v_exp_f32_e32 v0, v0
1756 ; GCN-NEXT: s_setpc_b64 s[30:31]
1757 ;
1758 ; R600-LABEL: v_exp2_f32_fast_daz:
1759 ; R600: ; %bb.0:
1760 ; R600-NEXT: CF_END
1761 ; R600-NEXT: PAD
1762 ;
1763 ; CM-LABEL: v_exp2_f32_fast_daz:
1764 ; CM: ; %bb.0:
1765 ; CM-NEXT: CF_END
1766 ; CM-NEXT: PAD
1767 %result = call fast float @llvm.exp2.f32(float %in)
1768 ret float %result
1769 }
1771 define float @v_exp2_f32_dynamic_mode(float %in) #1 {
1772 ; GCN-SDAG-LABEL: v_exp2_f32_dynamic_mode:
1773 ; GCN-SDAG: ; %bb.0:
1774 ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1775 ; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc2fc0000
1776 ; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
1777 ; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
1778 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
1779 ; GCN-SDAG-NEXT: v_add_f32_e32 v0, v0, v2
1780 ; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0
1781 ; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
1782 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1783 ; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1
1784 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
1785 ;
1786 ; GCN-GISEL-LABEL: v_exp2_f32_dynamic_mode:
1787 ; GCN-GISEL: ; %bb.0:
1788 ; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1789 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
1790 ; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
1791 ; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
1792 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
1793 ; GCN-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
1794 ; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
1795 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000
1796 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1797 ; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
1798 ; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]
1799 ;
1800 ; R600-LABEL: v_exp2_f32_dynamic_mode:
1801 ; R600: ; %bb.0:
1802 ; R600-NEXT: CF_END
1803 ; R600-NEXT: PAD
1804 ;
1805 ; CM-LABEL: v_exp2_f32_dynamic_mode:
1806 ; CM: ; %bb.0:
1807 ; CM-NEXT: CF_END
1808 ; CM-NEXT: PAD
1809 %result = call float @llvm.exp2.f32(float %in)
1810 ret float %result
1811 }
1813 define float @v_exp2_f32_undef() {
1814 ; GCN-SDAG-LABEL: v_exp2_f32_undef:
1815 ; GCN-SDAG: ; %bb.0:
1816 ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1817 ; GCN-SDAG-NEXT: v_exp_f32_e32 v0, 0x7fc00000
1818 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
1819 ;
1820 ; GCN-GISEL-LABEL: v_exp2_f32_undef:
1821 ; GCN-GISEL: ; %bb.0:
1822 ; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1823 ; GCN-GISEL-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
1824 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x42800000
1825 ; GCN-GISEL-NEXT: v_add_f32_e32 v1, s4, v1
1826 ; GCN-GISEL-NEXT: v_add_f32_e64 v2, s4, 0
1827 ; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0
1828 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
1829 ; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
1830 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000
1831 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1832 ; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
1833 ; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]
1834 ;
1835 ; R600-LABEL: v_exp2_f32_undef:
1836 ; R600: ; %bb.0:
1837 ; R600-NEXT: CF_END
1838 ; R600-NEXT: PAD
1839 ;
1840 ; CM-LABEL: v_exp2_f32_undef:
1841 ; CM: ; %bb.0:
1842 ; CM-NEXT: CF_END
1843 ; CM-NEXT: PAD
1844 %result = call float @llvm.exp2.f32(float undef)
1845 ret float %result
1846 }
1848 define float @v_exp2_f32_0() {
1849 ; GCN-LABEL: v_exp2_f32_0:
1850 ; GCN: ; %bb.0:
1851 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1852 ; GCN-NEXT: v_mov_b32_e32 v0, 1.0
1853 ; GCN-NEXT: s_setpc_b64 s[30:31]
1854 ;
1855 ; R600-LABEL: v_exp2_f32_0:
1856 ; R600: ; %bb.0:
1857 ; R600-NEXT: CF_END
1858 ; R600-NEXT: PAD
1859 ;
1860 ; CM-LABEL: v_exp2_f32_0:
1861 ; CM: ; %bb.0:
1862 ; CM-NEXT: CF_END
1863 ; CM-NEXT: PAD
1864 ; GFX89-SDAG-LABEL: v_exp2_f32_0:
1865 ; GFX89-SDAG: ; %bb.0:
1866 ; GFX89-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1867 ; GFX89-SDAG-NEXT: v_log_f32_e32 v0, 0
1868 ; GFX89-SDAG-NEXT: s_setpc_b64 s[30:31]
1869 ; GFX89-GISEL-LABEL: v_exp2_f32_0:
1870 ; GFX89-GISEL: ; %bb.0:
1871 ; GFX89-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1872 ; GFX89-GISEL-NEXT: v_mov_b32_e32 v0, 0xff800000
1873 ; GFX89-GISEL-NEXT: s_setpc_b64 s[30:31]
1874 %result = call float @llvm.exp2.f32(float 0.0)
1875 ret float %result
1876 }
1878 define float @v_exp2_f32_from_fpext_f16(i16 %src.i) {
1879 ; GCN-LABEL: v_exp2_f32_from_fpext_f16:
1880 ; GCN: ; %bb.0:
1881 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1882 ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0
1883 ; GCN-NEXT: v_exp_f32_e32 v0, v0
1884 ; GCN-NEXT: s_setpc_b64 s[30:31]
1885 ;
1886 ; R600-LABEL: v_exp2_f32_from_fpext_f16:
1887 ; R600: ; %bb.0:
1888 ; R600-NEXT: CF_END
1889 ; R600-NEXT: PAD
1890 ;
1891 ; CM-LABEL: v_exp2_f32_from_fpext_f16:
1892 ; CM: ; %bb.0:
1893 ; CM-NEXT: CF_END
1894 ; CM-NEXT: PAD
1895 %src = bitcast i16 %src.i to half
1896 %fpext = fpext half %src to float
1897 %result = call float @llvm.exp2.f32(float %fpext)
1898 ret float %result
1899 }
1901 define float @v_exp2_f32_from_fpext_math_f16(i16 %src0.i, i16 %src1.i) {
1902 ; SI-SDAG-LABEL: v_exp2_f32_from_fpext_math_f16:
1903 ; SI-SDAG: ; %bb.0:
1904 ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1905 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
1906 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1
1907 ; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2fc0000
1908 ; SI-SDAG-NEXT: v_add_f32_e32 v0, v0, v1
1909 ; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42800000
1910 ; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
1911 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
1912 ; SI-SDAG-NEXT: v_add_f32_e32 v0, v0, v1
1913 ; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0
1914 ; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
1915 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1916 ; SI-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1
1917 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
1918 ;
1919 ; SI-GISEL-LABEL: v_exp2_f32_from_fpext_math_f16:
1920 ; SI-GISEL: ; %bb.0:
1921 ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1922 ; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
1923 ; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1
1924 ; SI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
1925 ; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
1926 ; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
1927 ; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
1928 ; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
1929 ;
1930 ; VI-LABEL: v_exp2_f32_from_fpext_math_f16:
1931 ; VI: ; %bb.0:
1932 ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1933 ; VI-NEXT: v_add_f16_e32 v0, v0, v1
1934 ; VI-NEXT: v_cvt_f32_f16_e32 v0, v0
1935 ; VI-NEXT: v_exp_f32_e32 v0, v0
1936 ; VI-NEXT: s_setpc_b64 s[30:31]
1937 ;
1938 ; GFX900-LABEL: v_exp2_f32_from_fpext_math_f16:
1939 ; GFX900: ; %bb.0:
1940 ; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1941 ; GFX900-NEXT: v_add_f16_e32 v0, v0, v1
1942 ; GFX900-NEXT: v_cvt_f32_f16_e32 v0, v0
1943 ; GFX900-NEXT: v_exp_f32_e32 v0, v0
1944 ; GFX900-NEXT: s_setpc_b64 s[30:31]
1945 ;
1946 ; R600-LABEL: v_exp2_f32_from_fpext_math_f16:
1947 ; R600: ; %bb.0:
1948 ; R600-NEXT: CF_END
1949 ; R600-NEXT: PAD
1950 ;
1951 ; CM-LABEL: v_exp2_f32_from_fpext_math_f16:
1952 ; CM: ; %bb.0:
1953 ; CM-NEXT: CF_END
1954 ; CM-NEXT: PAD
1955 ; GFX89-LABEL: v_exp2_f32_from_fpext_math_f16:
1956 ; GFX89: ; %bb.0:
1957 ; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1958 ; GFX89-NEXT: v_add_f16_e32 v0, v0, v1
1959 ; GFX89-NEXT: v_cvt_f32_f16_e32 v0, v0
1960 ; GFX89-NEXT: v_log_f32_e32 v0, v0
1961 ; GFX89-NEXT: s_setpc_b64 s[30:31]
1962 %src0 = bitcast i16 %src0.i to half
1963 %src1 = bitcast i16 %src1.i to half
1964 %fadd = fadd half %src0, %src1
1965 %fpext = fpext half %fadd to float
1966 %result = call float @llvm.exp2.f32(float %fpext)
1967 ret float %result
1968 }
1970 define float @v_exp2_f32_from_fpext_bf16(bfloat %src) {
1971 ; SI-LABEL: v_exp2_f32_from_fpext_bf16:
1972 ; SI: ; %bb.0:
1973 ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1974 ; SI-NEXT: s_mov_b32 s4, 0xc2fc0000
1975 ; SI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
1976 ; SI-NEXT: v_mov_b32_e32 v2, 0x42800000
1977 ; SI-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
1978 ; SI-NEXT: v_add_f32_e32 v0, v0, v2
1979 ; SI-NEXT: v_exp_f32_e32 v0, v0
1980 ; SI-NEXT: v_mov_b32_e32 v1, 0x1f800000
1981 ; SI-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1982 ; SI-NEXT: v_mul_f32_e32 v0, v0, v1
1983 ; SI-NEXT: s_setpc_b64 s[30:31]
1984 ;
1985 ; VI-LABEL: v_exp2_f32_from_fpext_bf16:
1986 ; VI: ; %bb.0:
1987 ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1988 ; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
1989 ; VI-NEXT: s_mov_b32 s4, 0xc2fc0000
1990 ; VI-NEXT: v_mov_b32_e32 v1, 0x42800000
1991 ; VI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
1992 ; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
1993 ; VI-NEXT: v_add_f32_e32 v0, v0, v1
1994 ; VI-NEXT: v_exp_f32_e32 v0, v0
1995 ; VI-NEXT: v_mov_b32_e32 v1, 0x1f800000
1996 ; VI-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1997 ; VI-NEXT: v_mul_f32_e32 v0, v0, v1
1998 ; VI-NEXT: s_setpc_b64 s[30:31]
1999 ;
2000 ; GFX900-LABEL: v_exp2_f32_from_fpext_bf16:
2001 ; GFX900: ; %bb.0:
2002 ; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2003 ; GFX900-NEXT: v_lshlrev_b32_e32 v0, 16, v0
2004 ; GFX900-NEXT: s_mov_b32 s4, 0xc2fc0000
2005 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
2006 ; GFX900-NEXT: v_mov_b32_e32 v2, 0x42800000
2007 ; GFX900-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
2008 ; GFX900-NEXT: v_add_f32_e32 v0, v0, v2
2009 ; GFX900-NEXT: v_exp_f32_e32 v0, v0
2010 ; GFX900-NEXT: v_mov_b32_e32 v1, 0x1f800000
2011 ; GFX900-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
2012 ; GFX900-NEXT: v_mul_f32_e32 v0, v0, v1
2013 ; GFX900-NEXT: s_setpc_b64 s[30:31]
2014 ;
2015 ; R600-LABEL: v_exp2_f32_from_fpext_bf16:
2016 ; R600: ; %bb.0:
2017 ; R600-NEXT: CF_END
2018 ; R600-NEXT: PAD
2019 ;
2020 ; CM-LABEL: v_exp2_f32_from_fpext_bf16:
2021 ; CM: ; %bb.0:
2022 ; CM-NEXT: CF_END
2023 ; CM-NEXT: PAD
2024 ; GFX89-SDAG-LABEL: v_exp2_f32_from_fpext_bf16:
2025 ; GFX89-SDAG: ; %bb.0:
2026 ; GFX89-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2027 ; GFX89-SDAG-NEXT: v_log_f32_e32 v0, v0
2028 ; GFX89-SDAG-NEXT: s_setpc_b64 s[30:31]
2029 ; GFX89-GISEL-LABEL: v_exp2_f32_from_fpext_bf16:
2030 ; GFX89-GISEL: ; %bb.0:
2031 ; GFX89-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2032 ; GFX89-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
2033 ; GFX89-GISEL-NEXT: v_log_f32_e32 v0, v0
2034 ; GFX89-GISEL-NEXT: s_setpc_b64 s[30:31]
2035 %fpext = fpext bfloat %src to float
2036 %result = call float @llvm.exp2.f32(float %fpext)
2037 ret float %result
2038 }
2040 ; FIXME: Fold out fp16_to_fp (FP_TO_FP16) on no-f16 targets
2041 define half @v_exp2_f16(half %in) {
2042 ; SI-SDAG-LABEL: v_exp2_f16:
2043 ; SI-SDAG: ; %bb.0:
2044 ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2045 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2046 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
2047 ; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0
2048 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2049 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
2050 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
2051 ;
2052 ; SI-GISEL-LABEL: v_exp2_f16:
2053 ; SI-GISEL: ; %bb.0:
2054 ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2055 ; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
2056 ; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
2057 ; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
2058 ; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
2059 ;
2060 ; VI-LABEL: v_exp2_f16:
2061 ; VI: ; %bb.0:
2062 ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2063 ; VI-NEXT: v_exp_f16_e32 v0, v0
2064 ; VI-NEXT: s_setpc_b64 s[30:31]
2065 ;
2066 ; GFX900-LABEL: v_exp2_f16:
2067 ; GFX900: ; %bb.0:
2068 ; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2069 ; GFX900-NEXT: v_exp_f16_e32 v0, v0
2070 ; GFX900-NEXT: s_setpc_b64 s[30:31]
2071 ;
2072 ; R600-LABEL: v_exp2_f16:
2073 ; R600: ; %bb.0:
2074 ; R600-NEXT: CF_END
2075 ; R600-NEXT: PAD
2076 ;
2077 ; CM-LABEL: v_exp2_f16:
2078 ; CM: ; %bb.0:
2079 ; CM-NEXT: CF_END
2080 ; CM-NEXT: PAD
2081 ; GFX89-LABEL: v_exp2_f16:
2082 ; GFX89: ; %bb.0:
2083 ; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2084 ; GFX89-NEXT: v_log_f16_e32 v0, v0
2085 ; GFX89-NEXT: s_setpc_b64 s[30:31]
2086 %result = call half @llvm.exp2.f16(half %in)
2087 ret half %result
2088 }
2090 define half @v_exp2_fabs_f16(half %in) {
2091 ; SI-SDAG-LABEL: v_exp2_fabs_f16:
2092 ; SI-SDAG: ; %bb.0:
2093 ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2094 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2095 ; SI-SDAG-NEXT: v_cvt_f32_f16_e64 v0, |v0|
2096 ; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0
2097 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2098 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
2099 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
2100 ;
2101 ; SI-GISEL-LABEL: v_exp2_fabs_f16:
2102 ; SI-GISEL: ; %bb.0:
2103 ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2104 ; SI-GISEL-NEXT: v_cvt_f32_f16_e64 v0, |v0|
2105 ; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
2106 ; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
2107 ; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
2108 ;
2109 ; VI-LABEL: v_exp2_fabs_f16:
2110 ; VI: ; %bb.0:
2111 ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2112 ; VI-NEXT: v_exp_f16_e64 v0, |v0|
2113 ; VI-NEXT: s_setpc_b64 s[30:31]
2114 ;
2115 ; GFX900-LABEL: v_exp2_fabs_f16:
2116 ; GFX900: ; %bb.0:
2117 ; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2118 ; GFX900-NEXT: v_exp_f16_e64 v0, |v0|
2119 ; GFX900-NEXT: s_setpc_b64 s[30:31]
2120 ;
2121 ; R600-LABEL: v_exp2_fabs_f16:
2122 ; R600: ; %bb.0:
2123 ; R600-NEXT: CF_END
2124 ; R600-NEXT: PAD
2125 ;
2126 ; CM-LABEL: v_exp2_fabs_f16:
2127 ; CM: ; %bb.0:
2128 ; CM-NEXT: CF_END
2129 ; CM-NEXT: PAD
2130 ; GFX89-LABEL: v_exp2_fabs_f16:
2131 ; GFX89: ; %bb.0:
2132 ; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2133 ; GFX89-NEXT: v_log_f16_e64 v0, |v0|
2134 ; GFX89-NEXT: s_setpc_b64 s[30:31]
2135 %fabs = call half @llvm.fabs.f16(half %in)
2136 %result = call half @llvm.exp2.f16(half %fabs)
2137 ret half %result
2138 }
2140 define half @v_exp2_fneg_fabs_f16(half %in) {
2141 ; SI-SDAG-LABEL: v_exp2_fneg_fabs_f16:
2142 ; SI-SDAG: ; %bb.0:
2143 ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2144 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2145 ; SI-SDAG-NEXT: v_cvt_f32_f16_e64 v0, -|v0|
2146 ; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0
2147 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2148 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
2149 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
2150 ;
2151 ; SI-GISEL-LABEL: v_exp2_fneg_fabs_f16:
2152 ; SI-GISEL: ; %bb.0:
2153 ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2154 ; SI-GISEL-NEXT: v_cvt_f32_f16_e64 v0, -|v0|
2155 ; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
2156 ; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
2157 ; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
2158 ;
2159 ; VI-LABEL: v_exp2_fneg_fabs_f16:
2160 ; VI: ; %bb.0:
2161 ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2162 ; VI-NEXT: v_exp_f16_e64 v0, -|v0|
2163 ; VI-NEXT: s_setpc_b64 s[30:31]
2164 ;
2165 ; GFX900-LABEL: v_exp2_fneg_fabs_f16:
2166 ; GFX900: ; %bb.0:
2167 ; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2168 ; GFX900-NEXT: v_exp_f16_e64 v0, -|v0|
2169 ; GFX900-NEXT: s_setpc_b64 s[30:31]
2170 ;
2171 ; R600-LABEL: v_exp2_fneg_fabs_f16:
2172 ; R600: ; %bb.0:
2173 ; R600-NEXT: CF_END
2174 ; R600-NEXT: PAD
2175 ;
2176 ; CM-LABEL: v_exp2_fneg_fabs_f16:
2177 ; CM: ; %bb.0:
2178 ; CM-NEXT: CF_END
2179 ; CM-NEXT: PAD
2180 ; GFX89-LABEL: v_exp2_fneg_fabs_f16:
2181 ; GFX89: ; %bb.0:
2182 ; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2183 ; GFX89-NEXT: v_log_f16_e64 v0, -|v0|
2184 ; GFX89-NEXT: s_setpc_b64 s[30:31]
2185 %fabs = call half @llvm.fabs.f16(half %in)
2186 %fneg.fabs = fneg half %fabs
2187 %result = call half @llvm.exp2.f16(half %fneg.fabs)
2188 ret half %result
2189 }
2191 define half @v_exp2_fneg_f16(half %in) {
2192 ; SI-SDAG-LABEL: v_exp2_fneg_f16:
2193 ; SI-SDAG: ; %bb.0:
2194 ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2195 ; SI-SDAG-NEXT: v_cvt_f16_f32_e64 v0, -v0
2196 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
2197 ; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0
2198 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2199 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
2200 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
2201 ;
2202 ; SI-GISEL-LABEL: v_exp2_fneg_f16:
2203 ; SI-GISEL: ; %bb.0:
2204 ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2205 ; SI-GISEL-NEXT: v_cvt_f32_f16_e64 v0, -v0
2206 ; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
2207 ; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
2208 ; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
2209 ;
2210 ; VI-LABEL: v_exp2_fneg_f16:
2211 ; VI: ; %bb.0:
2212 ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2213 ; VI-NEXT: v_exp_f16_e64 v0, -v0
2214 ; VI-NEXT: s_setpc_b64 s[30:31]
2215 ;
2216 ; GFX900-LABEL: v_exp2_fneg_f16:
2217 ; GFX900: ; %bb.0:
2218 ; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2219 ; GFX900-NEXT: v_exp_f16_e64 v0, -v0
2220 ; GFX900-NEXT: s_setpc_b64 s[30:31]
2221 ;
2222 ; R600-LABEL: v_exp2_fneg_f16:
2223 ; R600: ; %bb.0:
2224 ; R600-NEXT: CF_END
2225 ; R600-NEXT: PAD
2226 ;
2227 ; CM-LABEL: v_exp2_fneg_f16:
2228 ; CM: ; %bb.0:
2229 ; CM-NEXT: CF_END
2230 ; CM-NEXT: PAD
2231 ; GFX89-LABEL: v_exp2_fneg_f16:
2232 ; GFX89: ; %bb.0:
2233 ; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2234 ; GFX89-NEXT: v_log_f16_e64 v0, -v0
2235 ; GFX89-NEXT: s_setpc_b64 s[30:31]
2236 %fneg = fneg half %in
2237 %result = call half @llvm.exp2.f16(half %fneg)
2238 ret half %result
2239 }
2241 define half @v_exp2_f16_fast(half %in) {
2242 ; SI-SDAG-LABEL: v_exp2_f16_fast:
2243 ; SI-SDAG: ; %bb.0:
2244 ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2245 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2246 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
2247 ; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0
2248 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2249 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
2250 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
2251 ;
2252 ; SI-GISEL-LABEL: v_exp2_f16_fast:
2253 ; SI-GISEL: ; %bb.0:
2254 ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2255 ; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
2256 ; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
2257 ; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
2258 ; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
2259 ;
2260 ; VI-LABEL: v_exp2_f16_fast:
2261 ; VI: ; %bb.0:
2262 ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2263 ; VI-NEXT: v_exp_f16_e32 v0, v0
2264 ; VI-NEXT: s_setpc_b64 s[30:31]
2265 ;
2266 ; GFX900-LABEL: v_exp2_f16_fast:
2267 ; GFX900: ; %bb.0:
2268 ; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2269 ; GFX900-NEXT: v_exp_f16_e32 v0, v0
2270 ; GFX900-NEXT: s_setpc_b64 s[30:31]
2271 ;
2272 ; R600-LABEL: v_exp2_f16_fast:
2273 ; R600: ; %bb.0:
2274 ; R600-NEXT: CF_END
2275 ; R600-NEXT: PAD
2276 ;
2277 ; CM-LABEL: v_exp2_f16_fast:
2278 ; CM: ; %bb.0:
2279 ; CM-NEXT: CF_END
2280 ; CM-NEXT: PAD
2281 ; GFX89-LABEL: v_exp2_f16_fast:
2282 ; GFX89: ; %bb.0:
2283 ; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2284 ; GFX89-NEXT: v_log_f16_e32 v0, v0
2285 ; GFX89-NEXT: s_setpc_b64 s[30:31]
2286 %result = call fast half @llvm.exp2.f16(half %in)
2287 ret half %result
2288 }
2290 define <2 x half> @v_exp2_v2f16(<2 x half> %in) {
2291 ; SI-SDAG-LABEL: v_exp2_v2f16:
2292 ; SI-SDAG: ; %bb.0:
2293 ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2294 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2295 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1
2296 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
2297 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1
2298 ; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0
2299 ; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1
2300 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2301 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1
2302 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
2303 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1
2304 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
2305 ;
2306 ; SI-GISEL-LABEL: v_exp2_v2f16:
2307 ; SI-GISEL: ; %bb.0:
2308 ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2309 ; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
2310 ; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1
2311 ; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
2312 ; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1
2313 ; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
2314 ; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1
2315 ; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
2316 ;
2317 ; VI-SDAG-LABEL: v_exp2_v2f16:
2318 ; VI-SDAG: ; %bb.0:
2319 ; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2320 ; VI-SDAG-NEXT: v_exp_f16_sdwa v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1
2321 ; VI-SDAG-NEXT: v_exp_f16_e32 v0, v0
2322 ; VI-SDAG-NEXT: v_or_b32_e32 v0, v0, v1
2323 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
2324 ;
2325 ; VI-GISEL-LABEL: v_exp2_v2f16:
2326 ; VI-GISEL: ; %bb.0:
2327 ; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2328 ; VI-GISEL-NEXT: v_exp_f16_e32 v1, v0
2329 ; VI-GISEL-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1
2330 ; VI-GISEL-NEXT: v_or_b32_e32 v0, v1, v0
2331 ; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
2332 ;
2333 ; GFX900-SDAG-LABEL: v_exp2_v2f16:
2334 ; GFX900-SDAG: ; %bb.0:
2335 ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2336 ; GFX900-SDAG-NEXT: v_exp_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
2337 ; GFX900-SDAG-NEXT: v_exp_f16_e32 v0, v0
2338 ; GFX900-SDAG-NEXT: v_pack_b32_f16 v0, v0, v1
2339 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
2340 ;
2341 ; GFX900-GISEL-LABEL: v_exp2_v2f16:
2342 ; GFX900-GISEL: ; %bb.0:
2343 ; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2344 ; GFX900-GISEL-NEXT: v_exp_f16_e32 v1, v0
2345 ; GFX900-GISEL-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
2346 ; GFX900-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v1
2347 ; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
2348 ;
2349 ; R600-LABEL: v_exp2_v2f16:
2350 ; R600: ; %bb.0:
2351 ; R600-NEXT: CF_END
2352 ; R600-NEXT: PAD
2353 ;
2354 ; CM-LABEL: v_exp2_v2f16:
2355 ; CM: ; %bb.0:
2356 ; CM-NEXT: CF_END
2357 ; CM-NEXT: PAD
2358 %result = call <2 x half> @llvm.exp2.v2f16(<2 x half> %in)
2359 ret <2 x half> %result
2360 }
2362 define <2 x half> @v_exp2_fabs_v2f16(<2 x half> %in) {
2363 ; SI-SDAG-LABEL: v_exp2_fabs_v2f16:
2364 ; SI-SDAG: ; %bb.0:
2365 ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2366 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2367 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1
2368 ; SI-SDAG-NEXT: v_cvt_f32_f16_e64 v0, |v0|
2369 ; SI-SDAG-NEXT: v_cvt_f32_f16_e64 v1, |v1|
2370 ; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0
2371 ; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1
2372 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2373 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1
2374 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
2375 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1
2376 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
2377 ;
2378 ; SI-GISEL-LABEL: v_exp2_fabs_v2f16:
2379 ; SI-GISEL: ; %bb.0:
2380 ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2381 ; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
2382 ; SI-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
2383 ; SI-GISEL-NEXT: v_or_b32_e32 v0, v1, v0
2384 ; SI-GISEL-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
2385 ; SI-GISEL-NEXT: v_lshrrev_b32_e32 v1, 16, v0
2386 ; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
2387 ; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1
2388 ; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
2389 ; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1
2390 ; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
2391 ; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1
2392 ; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
2393 ;
2394 ; VI-SDAG-LABEL: v_exp2_fabs_v2f16:
2395 ; VI-SDAG: ; %bb.0:
2396 ; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2397 ; VI-SDAG-NEXT: v_exp_f16_sdwa v1, |v0| dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1
2398 ; VI-SDAG-NEXT: v_exp_f16_e64 v0, |v0|
2399 ; VI-SDAG-NEXT: v_or_b32_e32 v0, v0, v1
2400 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
2401 ;
2402 ; VI-GISEL-LABEL: v_exp2_fabs_v2f16:
2403 ; VI-GISEL: ; %bb.0:
2404 ; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2405 ; VI-GISEL-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
2406 ; VI-GISEL-NEXT: v_exp_f16_e32 v1, v0
2407 ; VI-GISEL-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1
2408 ; VI-GISEL-NEXT: v_or_b32_e32 v0, v1, v0
2409 ; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
2410 ;
2411 ; GFX900-SDAG-LABEL: v_exp2_fabs_v2f16:
2412 ; GFX900-SDAG: ; %bb.0:
2413 ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2414 ; GFX900-SDAG-NEXT: v_exp_f16_sdwa v1, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
2415 ; GFX900-SDAG-NEXT: v_exp_f16_e64 v0, |v0|
2416 ; GFX900-SDAG-NEXT: v_pack_b32_f16 v0, v0, v1
2417 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
2418 ;
2419 ; GFX900-GISEL-LABEL: v_exp2_fabs_v2f16:
2420 ; GFX900-GISEL: ; %bb.0:
2421 ; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2422 ; GFX900-GISEL-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
2423 ; GFX900-GISEL-NEXT: v_exp_f16_e32 v1, v0
2424 ; GFX900-GISEL-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
2425 ; GFX900-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v1
2426 ; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
2427 ;
2428 ; R600-LABEL: v_exp2_fabs_v2f16:
2429 ; R600: ; %bb.0:
2430 ; R600-NEXT: CF_END
2431 ; R600-NEXT: PAD
2432 ;
2433 ; CM-LABEL: v_exp2_fabs_v2f16:
2434 ; CM: ; %bb.0:
2435 ; CM-NEXT: CF_END
2436 ; CM-NEXT: PAD
2437 %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %in)
2438 %result = call <2 x half> @llvm.exp2.v2f16(<2 x half> %fabs)
2439 ret <2 x half> %result
2440 }
2442 define <2 x half> @v_exp2_fneg_fabs_v2f16(<2 x half> %in) {
2443 ; SI-SDAG-LABEL: v_exp2_fneg_fabs_v2f16:
2444 ; SI-SDAG: ; %bb.0:
2445 ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2446 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1
2447 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2448 ; SI-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v1
2449 ; SI-SDAG-NEXT: v_or_b32_e32 v0, v0, v1
2450 ; SI-SDAG-NEXT: v_or_b32_e32 v0, 0x80008000, v0
2451 ; SI-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
2452 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
2453 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1
2454 ; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0
2455 ; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1
2456 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2457 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1
2458 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
2459 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1
2460 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
2461 ;
2462 ; SI-GISEL-LABEL: v_exp2_fneg_fabs_v2f16:
2463 ; SI-GISEL: ; %bb.0:
2464 ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2465 ; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
2466 ; SI-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
2467 ; SI-GISEL-NEXT: v_or_b32_e32 v0, v1, v0
2468 ; SI-GISEL-NEXT: v_or_b32_e32 v0, 0x80008000, v0
2469 ; SI-GISEL-NEXT: v_lshrrev_b32_e32 v1, 16, v0
2470 ; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
2471 ; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1
2472 ; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
2473 ; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1
2474 ; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
2475 ; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1
2476 ; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
2477 ;
2478 ; VI-SDAG-LABEL: v_exp2_fneg_fabs_v2f16:
2479 ; VI-SDAG: ; %bb.0:
2480 ; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2481 ; VI-SDAG-NEXT: v_exp_f16_sdwa v1, -|v0| dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1
2482 ; VI-SDAG-NEXT: v_exp_f16_e64 v0, -|v0|
2483 ; VI-SDAG-NEXT: v_or_b32_e32 v0, v0, v1
2484 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
2485 ;
2486 ; VI-GISEL-LABEL: v_exp2_fneg_fabs_v2f16:
2487 ; VI-GISEL: ; %bb.0:
2488 ; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2489 ; VI-GISEL-NEXT: v_or_b32_e32 v0, 0x80008000, v0
2490 ; VI-GISEL-NEXT: v_exp_f16_e32 v1, v0
2491 ; VI-GISEL-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1
2492 ; VI-GISEL-NEXT: v_or_b32_e32 v0, v1, v0
2493 ; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
2494 ;
2495 ; GFX900-SDAG-LABEL: v_exp2_fneg_fabs_v2f16:
2496 ; GFX900-SDAG: ; %bb.0:
2497 ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2498 ; GFX900-SDAG-NEXT: v_exp_f16_sdwa v1, -|v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
2499 ; GFX900-SDAG-NEXT: v_exp_f16_e64 v0, -|v0|
2500 ; GFX900-SDAG-NEXT: v_pack_b32_f16 v0, v0, v1
2501 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
2502 ;
2503 ; GFX900-GISEL-LABEL: v_exp2_fneg_fabs_v2f16:
2504 ; GFX900-GISEL: ; %bb.0:
2505 ; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2506 ; GFX900-GISEL-NEXT: v_or_b32_e32 v0, 0x80008000, v0
2507 ; GFX900-GISEL-NEXT: v_exp_f16_e32 v1, v0
2508 ; GFX900-GISEL-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
2509 ; GFX900-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v1
2510 ; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
2511 ;
2512 ; R600-LABEL: v_exp2_fneg_fabs_v2f16:
2513 ; R600: ; %bb.0:
2514 ; R600-NEXT: CF_END
2515 ; R600-NEXT: PAD
2516 ;
2517 ; CM-LABEL: v_exp2_fneg_fabs_v2f16:
2518 ; CM: ; %bb.0:
2519 ; CM-NEXT: CF_END
2520 ; CM-NEXT: PAD
2521 %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %in)
2522 %fneg.fabs = fneg <2 x half> %fabs
2523 %result = call <2 x half> @llvm.exp2.v2f16(<2 x half> %fneg.fabs)
2524 ret <2 x half> %result
2525 }
2527 define <2 x half> @v_exp2_fneg_v2f16(<2 x half> %in) {
2528 ; SI-SDAG-LABEL: v_exp2_fneg_v2f16:
2529 ; SI-SDAG: ; %bb.0:
2530 ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2531 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1
2532 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2533 ; SI-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v1
2534 ; SI-SDAG-NEXT: v_or_b32_e32 v0, v0, v1
2535 ; SI-SDAG-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
2536 ; SI-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
2537 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
2538 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1
2539 ; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0
2540 ; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1
2541 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2542 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1
2543 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
2544 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1
2545 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
2546 ;
2547 ; SI-GISEL-LABEL: v_exp2_fneg_v2f16:
2548 ; SI-GISEL: ; %bb.0:
2549 ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2550 ; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
2551 ; SI-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
2552 ; SI-GISEL-NEXT: v_or_b32_e32 v0, v1, v0
2553 ; SI-GISEL-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
2554 ; SI-GISEL-NEXT: v_lshrrev_b32_e32 v1, 16, v0
2555 ; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
2556 ; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1
2557 ; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
2558 ; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1
2559 ; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
2560 ; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1
2561 ; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
2562 ;
2563 ; VI-SDAG-LABEL: v_exp2_fneg_v2f16:
2564 ; VI-SDAG: ; %bb.0:
2565 ; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2566 ; VI-SDAG-NEXT: v_exp_f16_sdwa v1, -v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1
2567 ; VI-SDAG-NEXT: v_exp_f16_e64 v0, -v0
2568 ; VI-SDAG-NEXT: v_or_b32_e32 v0, v0, v1
2569 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
2570 ;
2571 ; VI-GISEL-LABEL: v_exp2_fneg_v2f16:
2572 ; VI-GISEL: ; %bb.0:
2573 ; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2574 ; VI-GISEL-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
2575 ; VI-GISEL-NEXT: v_exp_f16_e32 v1, v0
2576 ; VI-GISEL-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1
2577 ; VI-GISEL-NEXT: v_or_b32_e32 v0, v1, v0
2578 ; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
2579 ;
2580 ; GFX900-SDAG-LABEL: v_exp2_fneg_v2f16:
2581 ; GFX900-SDAG: ; %bb.0:
2582 ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2583 ; GFX900-SDAG-NEXT: v_exp_f16_sdwa v1, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
2584 ; GFX900-SDAG-NEXT: v_exp_f16_e64 v0, -v0
2585 ; GFX900-SDAG-NEXT: v_pack_b32_f16 v0, v0, v1
2586 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
2587 ;
2588 ; GFX900-GISEL-LABEL: v_exp2_fneg_v2f16:
2589 ; GFX900-GISEL: ; %bb.0:
2590 ; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2591 ; GFX900-GISEL-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
2592 ; GFX900-GISEL-NEXT: v_exp_f16_e32 v1, v0
2593 ; GFX900-GISEL-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
2594 ; GFX900-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v1
2595 ; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
2596 ;
2597 ; R600-LABEL: v_exp2_fneg_v2f16:
2598 ; R600: ; %bb.0:
2599 ; R600-NEXT: CF_END
2600 ; R600-NEXT: PAD
2601 ;
2602 ; CM-LABEL: v_exp2_fneg_v2f16:
2603 ; CM: ; %bb.0:
2604 ; CM-NEXT: CF_END
2605 ; CM-NEXT: PAD
2606 %fneg = fneg <2 x half> %in
2607 %result = call <2 x half> @llvm.exp2.v2f16(<2 x half> %fneg)
2608 ret <2 x half> %result
2609 }
2611 define <2 x half> @v_exp2_v2f16_fast(<2 x half> %in) {
2612 ; SI-SDAG-LABEL: v_exp2_v2f16_fast:
2613 ; SI-SDAG: ; %bb.0:
2614 ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2615 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2616 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1
2617 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
2618 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1
2619 ; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0
2620 ; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1
2621 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2622 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1
2623 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
2624 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1
2625 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
2626 ;
2627 ; SI-GISEL-LABEL: v_exp2_v2f16_fast:
2628 ; SI-GISEL: ; %bb.0:
2629 ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2630 ; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
2631 ; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1
2632 ; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
2633 ; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1
2634 ; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
2635 ; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1
2636 ; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
2637 ;
2638 ; VI-SDAG-LABEL: v_exp2_v2f16_fast:
2639 ; VI-SDAG: ; %bb.0:
2640 ; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2641 ; VI-SDAG-NEXT: v_exp_f16_sdwa v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1
2642 ; VI-SDAG-NEXT: v_exp_f16_e32 v0, v0
2643 ; VI-SDAG-NEXT: v_or_b32_e32 v0, v0, v1
2644 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
2645 ;
2646 ; VI-GISEL-LABEL: v_exp2_v2f16_fast:
2647 ; VI-GISEL: ; %bb.0:
2648 ; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2649 ; VI-GISEL-NEXT: v_exp_f16_e32 v1, v0
2650 ; VI-GISEL-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1
2651 ; VI-GISEL-NEXT: v_or_b32_e32 v0, v1, v0
2652 ; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
2653 ;
2654 ; GFX900-SDAG-LABEL: v_exp2_v2f16_fast:
2655 ; GFX900-SDAG: ; %bb.0:
2656 ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2657 ; GFX900-SDAG-NEXT: v_exp_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
2658 ; GFX900-SDAG-NEXT: v_exp_f16_e32 v0, v0
2659 ; GFX900-SDAG-NEXT: v_pack_b32_f16 v0, v0, v1
2660 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
2661 ;
2662 ; GFX900-GISEL-LABEL: v_exp2_v2f16_fast:
2663 ; GFX900-GISEL: ; %bb.0:
2664 ; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2665 ; GFX900-GISEL-NEXT: v_exp_f16_e32 v1, v0
2666 ; GFX900-GISEL-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
2667 ; GFX900-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v1
2668 ; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
2669 ;
2670 ; R600-LABEL: v_exp2_v2f16_fast:
2671 ; R600: ; %bb.0:
2672 ; R600-NEXT: CF_END
2673 ; R600-NEXT: PAD
2674 ;
2675 ; CM-LABEL: v_exp2_v2f16_fast:
2676 ; CM: ; %bb.0:
2677 ; CM-NEXT: CF_END
2678 ; CM-NEXT: PAD
2679 %result = call fast <2 x half> @llvm.exp2.v2f16(<2 x half> %in)
2680 ret <2 x half> %result
2681 }
2683 define <3 x half> @v_exp_v3f16(<3 x half> %in) {
2684 ; SI-SDAG-LABEL: v_exp_v3f16:
2685 ; SI-SDAG: ; %bb.0:
2686 ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2687 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2688 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1
2689 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v2, v2
2690 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
2691 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1
2692 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v2, v2
2693 ; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0
2694 ; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1
2695 ; SI-SDAG-NEXT: v_exp_f32_e32 v2, v2
2696 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2697 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1
2698 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v2, v2
2699 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
2700 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1
2701 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v2, v2
2702 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
2703 ;
2704 ; SI-GISEL-LABEL: v_exp_v3f16:
2705 ; SI-GISEL: ; %bb.0:
2706 ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2707 ; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
2708 ; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1
2709 ; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v2, v2
2710 ; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
2711 ; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1
2712 ; SI-GISEL-NEXT: v_exp_f32_e32 v2, v2
2713 ; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
2714 ; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1
2715 ; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v2, v2
2716 ; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
2717 ;
2718 ; VI-SDAG-LABEL: v_exp_v3f16:
2719 ; VI-SDAG: ; %bb.0:
2720 ; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2721 ; VI-SDAG-NEXT: v_exp_f16_sdwa v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1
2722 ; VI-SDAG-NEXT: v_exp_f16_e32 v0, v0
2723 ; VI-SDAG-NEXT: v_exp_f16_e32 v1, v1
2724 ; VI-SDAG-NEXT: v_or_b32_e32 v0, v0, v2
2725 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
2726 ;
2727 ; VI-GISEL-LABEL: v_exp_v3f16:
2728 ; VI-GISEL: ; %bb.0:
2729 ; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2730 ; VI-GISEL-NEXT: v_exp_f16_e32 v2, v0
2731 ; VI-GISEL-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1
2732 ; VI-GISEL-NEXT: v_exp_f16_e32 v1, v1
2733 ; VI-GISEL-NEXT: v_or_b32_e32 v0, v2, v0
2734 ; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
2735 ;
2736 ; GFX900-SDAG-LABEL: v_exp_v3f16:
2737 ; GFX900-SDAG: ; %bb.0:
2738 ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2739 ; GFX900-SDAG-NEXT: v_exp_f16_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
2740 ; GFX900-SDAG-NEXT: v_exp_f16_e32 v0, v0
2741 ; GFX900-SDAG-NEXT: v_exp_f16_e32 v1, v1
2742 ; GFX900-SDAG-NEXT: v_pack_b32_f16 v0, v0, v2
2743 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
2744 ;
2745 ; GFX900-GISEL-LABEL: v_exp_v3f16:
2746 ; GFX900-GISEL: ; %bb.0:
2747 ; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2748 ; GFX900-GISEL-NEXT: v_exp_f16_e32 v2, v0
2749 ; GFX900-GISEL-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
2750 ; GFX900-GISEL-NEXT: v_exp_f16_e32 v1, v1
2751 ; GFX900-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v2
2752 ; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
2753 ;
2754 ; R600-LABEL: v_exp_v3f16:
2755 ; R600: ; %bb.0:
2756 ; R600-NEXT: CF_END
2757 ; R600-NEXT: PAD
2758 ;
2759 ; CM-LABEL: v_exp_v3f16:
2760 ; CM: ; %bb.0:
2761 ; CM-NEXT: CF_END
2762 ; CM-NEXT: PAD
2763 %result = call <3 x half> @llvm.exp2.v3f16(<3 x half> %in)
2764 ret <3 x half> %result
2765 }
2767 define <3 x half> @v_exp2_v3f16_afn(<3 x half> %in) {
2768 ; SI-SDAG-LABEL: v_exp2_v3f16_afn:
2769 ; SI-SDAG: ; %bb.0:
2770 ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2771 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2772 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1
2773 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v2, v2
2774 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
2775 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1
2776 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v2, v2
2777 ; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0
2778 ; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1
2779 ; SI-SDAG-NEXT: v_exp_f32_e32 v2, v2
2780 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2781 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1
2782 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v2, v2
2783 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
2784 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1
2785 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v2, v2
2786 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
2787 ;
2788 ; SI-GISEL-LABEL: v_exp2_v3f16_afn:
2789 ; SI-GISEL: ; %bb.0:
2790 ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2791 ; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
2792 ; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1
2793 ; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v2, v2
2794 ; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
2795 ; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1
2796 ; SI-GISEL-NEXT: v_exp_f32_e32 v2, v2
2797 ; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
2798 ; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1
2799 ; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v2, v2
2800 ; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
2801 ;
2802 ; VI-SDAG-LABEL: v_exp2_v3f16_afn:
2803 ; VI-SDAG: ; %bb.0:
2804 ; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2805 ; VI-SDAG-NEXT: v_exp_f16_sdwa v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1
2806 ; VI-SDAG-NEXT: v_exp_f16_e32 v0, v0
2807 ; VI-SDAG-NEXT: v_exp_f16_e32 v1, v1
2808 ; VI-SDAG-NEXT: v_or_b32_e32 v0, v0, v2
2809 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
2810 ;
2811 ; VI-GISEL-LABEL: v_exp2_v3f16_afn:
2812 ; VI-GISEL: ; %bb.0:
2813 ; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2814 ; VI-GISEL-NEXT: v_exp_f16_e32 v2, v0
2815 ; VI-GISEL-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1
2816 ; VI-GISEL-NEXT: v_exp_f16_e32 v1, v1
2817 ; VI-GISEL-NEXT: v_or_b32_e32 v0, v2, v0
2818 ; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
2819 ;
2820 ; GFX900-SDAG-LABEL: v_exp2_v3f16_afn:
2821 ; GFX900-SDAG: ; %bb.0:
2822 ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2823 ; GFX900-SDAG-NEXT: v_exp_f16_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
2824 ; GFX900-SDAG-NEXT: v_exp_f16_e32 v0, v0
2825 ; GFX900-SDAG-NEXT: v_exp_f16_e32 v1, v1
2826 ; GFX900-SDAG-NEXT: v_pack_b32_f16 v0, v0, v2
2827 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
2828 ;
2829 ; GFX900-GISEL-LABEL: v_exp2_v3f16_afn:
2830 ; GFX900-GISEL: ; %bb.0:
2831 ; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2832 ; GFX900-GISEL-NEXT: v_exp_f16_e32 v2, v0
2833 ; GFX900-GISEL-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
2834 ; GFX900-GISEL-NEXT: v_exp_f16_e32 v1, v1
2835 ; GFX900-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v2
2836 ; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
2837 ;
2838 ; R600-LABEL: v_exp2_v3f16_afn:
2839 ; R600: ; %bb.0:
2840 ; R600-NEXT: CF_END
2841 ; R600-NEXT: PAD
2842 ;
2843 ; CM-LABEL: v_exp2_v3f16_afn:
2844 ; CM: ; %bb.0:
2845 ; CM-NEXT: CF_END
2846 ; CM-NEXT: PAD
2847 %result = call afn <3 x half> @llvm.exp2.v3f16(<3 x half> %in)
2848 ret <3 x half> %result
2849 }
2851 define float @v_exp2_f32_contract(float %in) {
2852 ; GCN-SDAG-LABEL: v_exp2_f32_contract:
2853 ; GCN-SDAG: ; %bb.0:
2854 ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2855 ; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc2fc0000
2856 ; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
2857 ; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
2858 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
2859 ; GCN-SDAG-NEXT: v_add_f32_e32 v0, v0, v2
2860 ; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0
2861 ; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
2862 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
2863 ; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1
2864 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
2865 ;
2866 ; GCN-GISEL-LABEL: v_exp2_f32_contract:
2867 ; GCN-GISEL: ; %bb.0:
2868 ; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2869 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
2870 ; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
2871 ; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
2872 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
2873 ; GCN-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
2874 ; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
2875 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000
2876 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
2877 ; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
2878 ; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]
2879 ;
2880 ; R600-LABEL: v_exp2_f32_contract:
2881 ; R600: ; %bb.0:
2882 ; R600-NEXT: CF_END
2883 ; R600-NEXT: PAD
2884 ;
2885 ; CM-LABEL: v_exp2_f32_contract:
2886 ; CM: ; %bb.0:
2887 ; CM-NEXT: CF_END
2888 ; CM-NEXT: PAD
2889 %result = call contract float @llvm.exp2.f32(float %in)
2890 ret float %result
2891 }
2893 define float @v_exp2_f32_contract_daz(float %in) #0 {
2894 ; GCN-LABEL: v_exp2_f32_contract_daz:
2895 ; GCN: ; %bb.0:
2896 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2897 ; GCN-NEXT: v_exp_f32_e32 v0, v0
2898 ; GCN-NEXT: s_setpc_b64 s[30:31]
2899 ;
2900 ; R600-LABEL: v_exp2_f32_contract_daz:
2901 ; R600: ; %bb.0:
2902 ; R600-NEXT: CF_END
2903 ; R600-NEXT: PAD
2904 ;
2905 ; CM-LABEL: v_exp2_f32_contract_daz:
2906 ; CM: ; %bb.0:
2907 ; CM-NEXT: CF_END
2908 ; CM-NEXT: PAD
2909 %result = call contract float @llvm.exp2.f32(float %in)
2910 ret float %result
2911 }
2913 define float @v_exp2_f32_contract_nnan_ninf(float %in) {
2914 ; GCN-SDAG-LABEL: v_exp2_f32_contract_nnan_ninf:
2915 ; GCN-SDAG: ; %bb.0:
2916 ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2917 ; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc2fc0000
2918 ; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
2919 ; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
2920 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
2921 ; GCN-SDAG-NEXT: v_add_f32_e32 v0, v0, v2
2922 ; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0
2923 ; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
2924 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
2925 ; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1
2926 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
2927 ;
2928 ; GCN-GISEL-LABEL: v_exp2_f32_contract_nnan_ninf:
2929 ; GCN-GISEL: ; %bb.0:
2930 ; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2931 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
2932 ; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
2933 ; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
2934 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
2935 ; GCN-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
2936 ; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
2937 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000
2938 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
2939 ; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
2940 ; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]
2941 ;
2942 ; R600-LABEL: v_exp2_f32_contract_nnan_ninf:
2943 ; R600: ; %bb.0:
2944 ; R600-NEXT: CF_END
2945 ; R600-NEXT: PAD
2946 ;
2947 ; CM-LABEL: v_exp2_f32_contract_nnan_ninf:
2948 ; CM: ; %bb.0:
2949 ; CM-NEXT: CF_END
2950 ; CM-NEXT: PAD
2951 %result = call contract nnan ninf float @llvm.exp2.f32(float %in)
2952 ret float %result
2953 }
2955 declare float @llvm.fabs.f32(float) #2
2956 declare float @llvm.exp2.f32(float) #2
2957 declare <2 x float> @llvm.exp2.v2f32(<2 x float>) #2
2958 declare <3 x float> @llvm.exp2.v3f32(<3 x float>) #2
2959 declare <4 x float> @llvm.exp2.v4f32(<4 x float>) #2
2960 declare half @llvm.fabs.f16(half) #2
2961 declare half @llvm.exp2.f16(half) #2
2962 declare <2 x half> @llvm.exp2.v2f16(<2 x half>) #2
2963 declare <2 x half> @llvm.fabs.v2f16(<2 x half>) #2
2964 declare <3 x half> @llvm.exp2.v3f16(<3 x half>) #2
2966 attributes #0 = { "denormal-fp-math-f32"="ieee,preserve-sign" }
2967 attributes #1 = { "denormal-fp-math-f32"="dynamic,dynamic" }
2968 attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }