1 //===-- ARMHazardRecognizer.h - ARM Hazard Recognizers ----------*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines hazard recognizers for scheduling ARM functions.
11 //===----------------------------------------------------------------------===//
13 #ifndef LLVM_LIB_TARGET_ARM_ARMHAZARDRECOGNIZER_H
14 #define LLVM_LIB_TARGET_ARM_ARMHAZARDRECOGNIZER_H
16 #include "ARMBaseInstrInfo.h"
17 #include "llvm/ADT/BitmaskEnum.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
20 #include "llvm/Support/DataTypes.h"
22 #include <initializer_list>
27 class MachineFunction
;
31 // Hazards related to FP MLx instructions
32 class ARMHazardRecognizerFPMLx
: public ScheduleHazardRecognizer
{
33 MachineInstr
*LastMI
= nullptr;
34 unsigned FpMLxStalls
= 0;
37 ARMHazardRecognizerFPMLx() : ScheduleHazardRecognizer() { MaxLookAhead
= 1; }
39 HazardType
getHazardType(SUnit
*SU
, int Stalls
) override
;
40 void Reset() override
;
41 void EmitInstruction(SUnit
*SU
) override
;
42 void AdvanceCycle() override
;
43 void RecedeCycle() override
;
46 // Hazards related to bank conflicts
47 class ARMBankConflictHazardRecognizer
: public ScheduleHazardRecognizer
{
48 SmallVector
<MachineInstr
*, 8> Accesses
;
49 const MachineFunction
&MF
;
52 bool AssumeITCMBankConflict
;
55 ARMBankConflictHazardRecognizer(const ScheduleDAG
*DAG
, int64_t DDM
,
57 HazardType
getHazardType(SUnit
*SU
, int Stalls
) override
;
58 void Reset() override
;
59 void EmitInstruction(SUnit
*SU
) override
;
60 void AdvanceCycle() override
;
61 void RecedeCycle() override
;
64 inline HazardType
CheckOffsets(unsigned O0
, unsigned O1
);
67 } // end namespace llvm