llvm/lib/Target/PowerPC/PPCInstrInfo.h

   1 //===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file contains the PowerPC implementation of the TargetInstrInfo class.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #ifndef LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
  14 #define LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
  15
  16 #include "PPCRegisterInfo.h"
  17 #include "llvm/CodeGen/TargetInstrInfo.h"
  18
  19 #define GET_INSTRINFO_HEADER
  20 #include "PPCGenInstrInfo.inc"
  21
  22 namespace llvm {
  23
  24 /// PPCII - This namespace holds all of the PowerPC target-specific
  25 /// per-instruction flags.  These must match the corresponding definitions in
  26 /// PPC.td and PPCInstrFormats.td.
  27 namespace PPCII {
  28 enum {
  29   // PPC970 Instruction Flags.  These flags describe the characteristics of the
  30   // PowerPC 970 (aka G5) dispatch groups and how they are formed out of
  31   // raw machine instructions.
  32
  33   /// PPC970_First - This instruction starts a new dispatch group, so it will
  34   /// always be the first one in the group.
  35   PPC970_First = 0x1,
  36
  37   /// PPC970_Single - This instruction starts a new dispatch group and
  38   /// terminates it, so it will be the sole instruction in the group.
  39   PPC970_Single = 0x2,
  40
  41   /// PPC970_Cracked - This instruction is cracked into two pieces, requiring
  42   /// two dispatch pipes to be available to issue.
  43   PPC970_Cracked = 0x4,
  44
  45   /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that
  46   /// an instruction is issued to.
  47   PPC970_Shift = 3,
  48   PPC970_Mask = 0x07 << PPC970_Shift
  49 };
  50 enum PPC970_Unit {
  51   /// These are the various PPC970 execution unit pipelines.  Each instruction
  52   /// is one of these.
  53   PPC970_Pseudo = 0 << PPC970_Shift,   // Pseudo instruction
  54   PPC970_FXU    = 1 << PPC970_Shift,   // Fixed Point (aka Integer/ALU) Unit
  55   PPC970_LSU    = 2 << PPC970_Shift,   // Load Store Unit
  56   PPC970_FPU    = 3 << PPC970_Shift,   // Floating Point Unit
  57   PPC970_CRU    = 4 << PPC970_Shift,   // Control Register Unit
  58   PPC970_VALU   = 5 << PPC970_Shift,   // Vector ALU
  59   PPC970_VPERM  = 6 << PPC970_Shift,   // Vector Permute Unit
  60   PPC970_BRU    = 7 << PPC970_Shift    // Branch Unit
  61 };
  62
  63 enum {
  64   /// Shift count to bypass PPC970 flags
  65   NewDef_Shift = 6,
  66
  67   /// This instruction is an X-Form memory operation.
  68   XFormMemOp = 0x1 << NewDef_Shift,
  69   /// This instruction is prefixed.
  70   Prefixed = 0x1 << (NewDef_Shift+1)
  71 };
  72 } // end namespace PPCII
  73
  74 // Instructions that have an immediate form might be convertible to that
  75 // form if the correct input is a result of a load immediate. In order to
  76 // know whether the transformation is special, we might need to know some
  77 // of the details of the two forms.
  78 struct ImmInstrInfo {
  79   // Is the immediate field in the immediate form signed or unsigned?
  80   uint64_t SignedImm : 1;
  81   // Does the immediate need to be a multiple of some value?
  82   uint64_t ImmMustBeMultipleOf : 5;
  83   // Is R0/X0 treated specially by the original r+r instruction?
  84   // If so, in which operand?
  85   uint64_t ZeroIsSpecialOrig : 3;
  86   // Is R0/X0 treated specially by the new r+i instruction?
  87   // If so, in which operand?
  88   uint64_t ZeroIsSpecialNew : 3;
  89   // Is the operation commutative?
  90   uint64_t IsCommutative : 1;
  91   // The operand number to check for add-immediate def.
  92   uint64_t OpNoForForwarding : 3;
  93   // The operand number for the immediate.
  94   uint64_t ImmOpNo : 3;
  95   // The opcode of the new instruction.
  96   uint64_t ImmOpcode : 16;
  97   // The size of the immediate.
  98   uint64_t ImmWidth : 5;
  99   // The immediate should be truncated to N bits.
 100   uint64_t TruncateImmTo : 5;
 101   // Is the instruction summing the operand
 102   uint64_t IsSummingOperands : 1;
 103 };
 104
 105 // Information required to convert an instruction to just a materialized
 106 // immediate.
 107 struct LoadImmediateInfo {
 108   unsigned Imm : 16;
 109   unsigned Is64Bit : 1;
 110   unsigned SetCR : 1;
 111 };
 112
 113 // Index into the OpcodesForSpill array.
 114 enum SpillOpcodeKey {
 115   SOK_Int4Spill,
 116   SOK_Int8Spill,
 117   SOK_Float8Spill,
 118   SOK_Float4Spill,
 119   SOK_CRSpill,
 120   SOK_CRBitSpill,
 121   SOK_VRVectorSpill,
 122   SOK_VSXVectorSpill,
 123   SOK_VectorFloat8Spill,
 124   SOK_VectorFloat4Spill,
 125   SOK_SpillToVSR,
 126   SOK_PairedVecSpill,
 127   SOK_AccumulatorSpill,
 128   SOK_UAccumulatorSpill,
 129   SOK_SPESpill,
 130   SOK_PairedG8Spill,
 131   SOK_LastOpcodeSpill // This must be last on the enum.
 132 };
 133
 134 // Define list of load and store spill opcodes.
 135 #define NoInstr PPC::INSTRUCTION_LIST_END
 136 #define Pwr8LoadOpcodes                                                        \
 137   {                                                                            \
 138     PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR,                    \
 139         PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXVD2X, PPC::LXSDX, PPC::LXSSPX,    \
 140         PPC::SPILLTOVSR_LD, NoInstr, NoInstr, NoInstr, PPC::EVLDD,             \
 141         PPC::RESTORE_QUADWORD                                                  \
 142   }
 143
 144 #define Pwr9LoadOpcodes                                                        \
 145   {                                                                            \
 146     PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR,                    \
 147         PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64,                \
 148         PPC::DFLOADf32, PPC::SPILLTOVSR_LD, NoInstr, NoInstr, NoInstr,         \
 149         NoInstr, PPC::RESTORE_QUADWORD                                         \
 150   }
 151
 152 #define Pwr10LoadOpcodes                                                       \
 153   {                                                                            \
 154     PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR,                    \
 155         PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64,                \
 156         PPC::DFLOADf32, PPC::SPILLTOVSR_LD, PPC::LXVP, PPC::RESTORE_ACC,       \
 157         PPC::RESTORE_UACC, NoInstr, PPC::RESTORE_QUADWORD                      \
 158   }
 159
 160 #define Pwr8StoreOpcodes                                                       \
 161   {                                                                            \
 162     PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \
 163         PPC::STVX, PPC::STXVD2X, PPC::STXSDX, PPC::STXSSPX,                    \
 164         PPC::SPILLTOVSR_ST, NoInstr, NoInstr, NoInstr, PPC::EVSTDD,            \
 165         PPC::SPILL_QUADWORD                                                    \
 166   }
 167
 168 #define Pwr9StoreOpcodes                                                       \
 169   {                                                                            \
 170     PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \
 171         PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32,                \
 172         PPC::SPILLTOVSR_ST, NoInstr, NoInstr, NoInstr, NoInstr,                \
 173         PPC::SPILL_QUADWORD                                                    \
 174   }
 175
 176 #define Pwr10StoreOpcodes                                                      \
 177   {                                                                            \
 178     PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \
 179         PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32,                \
 180         PPC::SPILLTOVSR_ST, PPC::STXVP, PPC::SPILL_ACC, PPC::SPILL_UACC,       \
 181         NoInstr, PPC::SPILL_QUADWORD                                           \
 182   }
 183
 184 // Initialize arrays for load and store spill opcodes on supported subtargets.
 185 #define StoreOpcodesForSpill                                                   \
 186   { Pwr8StoreOpcodes, Pwr9StoreOpcodes, Pwr10StoreOpcodes }
 187 #define LoadOpcodesForSpill                                                    \
 188   { Pwr8LoadOpcodes, Pwr9LoadOpcodes, Pwr10LoadOpcodes }
 189
 190 class PPCSubtarget;
 191 class PPCInstrInfo : public PPCGenInstrInfo {
 192   PPCSubtarget &Subtarget;
 193   const PPCRegisterInfo RI;
 194   const unsigned StoreSpillOpcodesArray[3][SOK_LastOpcodeSpill] =
 195       StoreOpcodesForSpill;
 196   const unsigned LoadSpillOpcodesArray[3][SOK_LastOpcodeSpill] =
 197       LoadOpcodesForSpill;
 198
 199   void StoreRegToStackSlot(MachineFunction &MF, unsigned SrcReg, bool isKill,
 200                            int FrameIdx, const TargetRegisterClass *RC,
 201                            SmallVectorImpl<MachineInstr *> &NewMIs) const;
 202   void LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL,
 203                             unsigned DestReg, int FrameIdx,
 204                             const TargetRegisterClass *RC,
 205                             SmallVectorImpl<MachineInstr *> &NewMIs) const;
 206
 207   // Replace the instruction with single LI if possible. \p DefMI must be LI or
 208   // LI8.
 209   bool simplifyToLI(MachineInstr &MI, MachineInstr &DefMI,
 210                     unsigned OpNoForForwarding, MachineInstr **KilledDef) const;
 211   // If the inst is imm-form and its register operand is produced by a ADDI, put
 212   // the imm into the inst directly and remove the ADDI if possible.
 213   bool transformToNewImmFormFedByAdd(MachineInstr &MI, MachineInstr &DefMI,
 214                                      unsigned OpNoForForwarding) const;
 215   // If the inst is x-form and has imm-form and one of its operand is produced
 216   // by a LI, put the imm into the inst directly and remove the LI if possible.
 217   bool transformToImmFormFedByLI(MachineInstr &MI, const ImmInstrInfo &III,
 218                                  unsigned ConstantOpNo,
 219                                  MachineInstr &DefMI) const;
 220   // If the inst is x-form and has imm-form and one of its operand is produced
 221   // by an add-immediate, try to transform it when possible.
 222   bool transformToImmFormFedByAdd(MachineInstr &MI, const ImmInstrInfo &III,
 223                                   unsigned ConstantOpNo, MachineInstr &DefMI,
 224                                   bool KillDefMI) const;
 225   // Try to find that, if the instruction 'MI' contains any operand that
 226   // could be forwarded from some inst that feeds it. If yes, return the
 227   // Def of that operand. And OpNoForForwarding is the operand index in
 228   // the 'MI' for that 'Def'. If we see another use of this Def between
 229   // the Def and the MI, SeenIntermediateUse becomes 'true'.
 230   MachineInstr *getForwardingDefMI(MachineInstr &MI,
 231                                    unsigned &OpNoForForwarding,
 232                                    bool &SeenIntermediateUse) const;
 233
 234   // Can the user MI have it's source at index \p OpNoForForwarding
 235   // forwarded from an add-immediate that feeds it?
 236   bool isUseMIElgibleForForwarding(MachineInstr &MI, const ImmInstrInfo &III,
 237                                    unsigned OpNoForForwarding) const;
 238   bool isDefMIElgibleForForwarding(MachineInstr &DefMI,
 239                                    const ImmInstrInfo &III,
 240                                    MachineOperand *&ImmMO,
 241                                    MachineOperand *&RegMO) const;
 242   bool isImmElgibleForForwarding(const MachineOperand &ImmMO,
 243                                  const MachineInstr &DefMI,
 244                                  const ImmInstrInfo &III,
 245                                  int64_t &Imm,
 246                                  int64_t BaseImm = 0) const;
 247   bool isRegElgibleForForwarding(const MachineOperand &RegMO,
 248                                  const MachineInstr &DefMI,
 249                                  const MachineInstr &MI, bool KillDefMI,
 250                                  bool &IsFwdFeederRegKilled) const;
 251   unsigned getSpillTarget() const;
 252   const unsigned *getStoreOpcodesForSpillArray() const;
 253   const unsigned *getLoadOpcodesForSpillArray() const;
 254   unsigned getSpillIndex(const TargetRegisterClass *RC) const;
 255   int16_t getFMAOpIdxInfo(unsigned Opcode) const;
 256   void reassociateFMA(MachineInstr &Root, MachineCombinerPattern Pattern,
 257                       SmallVectorImpl<MachineInstr *> &InsInstrs,
 258                       SmallVectorImpl<MachineInstr *> &DelInstrs,
 259                       DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
 260   bool isLoadFromConstantPool(MachineInstr *I) const;
 261   Register
 262   generateLoadForNewConst(unsigned Idx, MachineInstr *MI, Type *Ty,
 263                           SmallVectorImpl<MachineInstr *> &InsInstrs) const;
 264   const Constant *getConstantFromConstantPool(MachineInstr *I) const;
 265   virtual void anchor();
 266
 267 protected:
 268   /// Commutes the operands in the given instruction.
 269   /// The commutable operands are specified by their indices OpIdx1 and OpIdx2.
 270   ///
 271   /// Do not call this method for a non-commutable instruction or for
 272   /// non-commutable pair of operand indices OpIdx1 and OpIdx2.
 273   /// Even though the instruction is commutable, the method may still
 274   /// fail to commute the operands, null pointer is returned in such cases.
 275   ///
 276   /// For example, we can commute rlwimi instructions, but only if the
 277   /// rotate amt is zero.  We also have to munge the immediates a bit.
 278   MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
 279                                        unsigned OpIdx1,
 280                                        unsigned OpIdx2) const override;
 281
 282 public:
 283   explicit PPCInstrInfo(PPCSubtarget &STI);
 284
 285   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
 286   /// such, whenever a client has an instance of instruction info, it should
 287   /// always be able to get register info as well (through this method).
 288   ///
 289   const PPCRegisterInfo &getRegisterInfo() const { return RI; }
 290
 291   bool isXFormMemOp(unsigned Opcode) const {
 292     return get(Opcode).TSFlags & PPCII::XFormMemOp;
 293   }
 294   bool isPrefixed(unsigned Opcode) const {
 295     return get(Opcode).TSFlags & PPCII::Prefixed;
 296   }
 297
 298   static bool isSameClassPhysRegCopy(unsigned Opcode) {
 299     unsigned CopyOpcodes[] = {PPC::OR,        PPC::OR8,   PPC::FMR,
 300                               PPC::VOR,       PPC::XXLOR, PPC::XXLORf,
 301                               PPC::XSCPSGNDP, PPC::MCRF,  PPC::CROR,
 302                               PPC::EVOR,      -1U};
 303     for (int i = 0; CopyOpcodes[i] != -1U; i++)
 304       if (Opcode == CopyOpcodes[i])
 305         return true;
 306     return false;
 307   }
 308
 309   ScheduleHazardRecognizer *
 310   CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
 311                                const ScheduleDAG *DAG) const override;
 312   ScheduleHazardRecognizer *
 313   CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
 314                                      const ScheduleDAG *DAG) const override;
 315
 316   unsigned getInstrLatency(const InstrItineraryData *ItinData,
 317                            const MachineInstr &MI,
 318                            unsigned *PredCost = nullptr) const override;
 319
 320   int getOperandLatency(const InstrItineraryData *ItinData,
 321                         const MachineInstr &DefMI, unsigned DefIdx,
 322                         const MachineInstr &UseMI,
 323                         unsigned UseIdx) const override;
 324   int getOperandLatency(const InstrItineraryData *ItinData,
 325                         SDNode *DefNode, unsigned DefIdx,
 326                         SDNode *UseNode, unsigned UseIdx) const override {
 327     return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx,
 328                                               UseNode, UseIdx);
 329   }
 330
 331   bool hasLowDefLatency(const TargetSchedModel &SchedModel,
 332                         const MachineInstr &DefMI,
 333                         unsigned DefIdx) const override {
 334     // Machine LICM should hoist all instructions in low-register-pressure
 335     // situations; none are sufficiently free to justify leaving in a loop
 336     // body.
 337     return false;
 338   }
 339
 340   bool useMachineCombiner() const override {
 341     return true;
 342   }
 343
 344   /// When getMachineCombinerPatterns() finds patterns, this function generates
 345   /// the instructions that could replace the original code sequence
 346   void genAlternativeCodeSequence(
 347       MachineInstr &Root, MachineCombinerPattern Pattern,
 348       SmallVectorImpl<MachineInstr *> &InsInstrs,
 349       SmallVectorImpl<MachineInstr *> &DelInstrs,
 350       DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
 351
 352   /// Return true when there is potentially a faster code sequence for a fma
 353   /// chain ending in \p Root. All potential patterns are output in the \p
 354   /// P array.
 355   bool getFMAPatterns(MachineInstr &Root,
 356                       SmallVectorImpl<MachineCombinerPattern> &P,
 357                       bool DoRegPressureReduce) const;
 358
 359   /// Return true when there is potentially a faster code sequence
 360   /// for an instruction chain ending in <Root>. All potential patterns are
 361   /// output in the <Pattern> array.
 362   bool getMachineCombinerPatterns(MachineInstr &Root,
 363                                   SmallVectorImpl<MachineCombinerPattern> &P,
 364                                   bool DoRegPressureReduce) const override;
 365
 366   /// On PowerPC, we leverage machine combiner pass to reduce register pressure
 367   /// when the register pressure is high for one BB.
 368   /// Return true if register pressure for \p MBB is high and ABI is supported
 369   /// to reduce register pressure. Otherwise return false.
 370   bool
 371   shouldReduceRegisterPressure(MachineBasicBlock *MBB,
 372                                RegisterClassInfo *RegClassInfo) const override;
 373
 374   /// Fixup the placeholders we put in genAlternativeCodeSequence() for
 375   /// MachineCombiner.
 376   void
 377   finalizeInsInstrs(MachineInstr &Root, MachineCombinerPattern &P,
 378                     SmallVectorImpl<MachineInstr *> &InsInstrs) const override;
 379
 380   bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
 381
 382   /// On PowerPC, we try to reassociate FMA chain which will increase
 383   /// instruction size. Set extension resource length limit to 1 for edge case.
 384   /// Resource Length is calculated by scaled resource usage in getCycles().
 385   /// Because of the division in getCycles(), it returns different cycles due to
 386   /// legacy scaled resource usage. So new resource length may be same with
 387   /// legacy or 1 bigger than legacy.
 388   /// We need to execlude the 1 bigger case even the resource length is not
 389   /// perserved for more FMA chain reassociations on PowerPC.
 390   int getExtendResourceLenLimit() const override { return 1; }
 391
 392   void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
 393                              MachineInstr &NewMI1,
 394                              MachineInstr &NewMI2) const override;
 395
 396   void setSpecialOperandAttr(MachineInstr &MI, uint16_t Flags) const override;
 397
 398   bool isCoalescableExtInstr(const MachineInstr &MI,
 399                              Register &SrcReg, Register &DstReg,
 400                              unsigned &SubIdx) const override;
 401   unsigned isLoadFromStackSlot(const MachineInstr &MI,
 402                                int &FrameIndex) const override;
 403   bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
 404                                          AAResults *AA) const override;
 405   unsigned isStoreToStackSlot(const MachineInstr &MI,
 406                               int &FrameIndex) const override;
 407
 408   bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
 409                              unsigned &SrcOpIdx2) const override;
 410
 411   void insertNoop(MachineBasicBlock &MBB,
 412                   MachineBasicBlock::iterator MI) const override;
 413
 414
 415   // Branch analysis.
 416   bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
 417                      MachineBasicBlock *&FBB,
 418                      SmallVectorImpl<MachineOperand> &Cond,
 419                      bool AllowModify) const override;
 420   unsigned removeBranch(MachineBasicBlock &MBB,
 421                         int *BytesRemoved = nullptr) const override;
 422   unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
 423                         MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
 424                         const DebugLoc &DL,
 425                         int *BytesAdded = nullptr) const override;
 426
 427   // Select analysis.
 428   bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
 429                        Register, Register, Register, int &, int &,
 430                        int &) const override;
 431   void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
 432                     const DebugLoc &DL, Register DstReg,
 433                     ArrayRef<MachineOperand> Cond, Register TrueReg,
 434                     Register FalseReg) const override;
 435
 436   void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
 437                    const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
 438                    bool KillSrc) const override;
 439
 440   void storeRegToStackSlot(MachineBasicBlock &MBB,
 441                            MachineBasicBlock::iterator MBBI,
 442                            Register SrcReg, bool isKill, int FrameIndex,
 443                            const TargetRegisterClass *RC,
 444                            const TargetRegisterInfo *TRI) const override;
 445
 446   // Emits a register spill without updating the register class for vector
 447   // registers. This ensures that when we spill a vector register the
 448   // element order in the register is the same as it was in memory.
 449   void storeRegToStackSlotNoUpd(MachineBasicBlock &MBB,
 450                                 MachineBasicBlock::iterator MBBI,
 451                                 unsigned SrcReg, bool isKill, int FrameIndex,
 452                                 const TargetRegisterClass *RC,
 453                                 const TargetRegisterInfo *TRI) const;
 454
 455   void loadRegFromStackSlot(MachineBasicBlock &MBB,
 456                             MachineBasicBlock::iterator MBBI,
 457                             Register DestReg, int FrameIndex,
 458                             const TargetRegisterClass *RC,
 459                             const TargetRegisterInfo *TRI) const override;
 460
 461   // Emits a register reload without updating the register class for vector
 462   // registers. This ensures that when we reload a vector register the
 463   // element order in the register is the same as it was in memory.
 464   void loadRegFromStackSlotNoUpd(MachineBasicBlock &MBB,
 465                                  MachineBasicBlock::iterator MBBI,
 466                                  unsigned DestReg, int FrameIndex,
 467                                  const TargetRegisterClass *RC,
 468                                  const TargetRegisterInfo *TRI) const;
 469
 470   unsigned getStoreOpcodeForSpill(const TargetRegisterClass *RC) const;
 471
 472   unsigned getLoadOpcodeForSpill(const TargetRegisterClass *RC) const;
 473
 474   bool
 475   reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
 476
 477   bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg,
 478                      MachineRegisterInfo *MRI) const override;
 479
 480   bool onlyFoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
 481                          Register Reg) const;
 482
 483   // If conversion by predication (only supported by some branch instructions).
 484   // All of the profitability checks always return true; it is always
 485   // profitable to use the predicated branches.
 486   bool isProfitableToIfCvt(MachineBasicBlock &MBB,
 487                           unsigned NumCycles, unsigned ExtraPredCycles,
 488                           BranchProbability Probability) const override {
 489     return true;
 490   }
 491
 492   bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
 493                            unsigned NumT, unsigned ExtraT,
 494                            MachineBasicBlock &FMBB,
 495                            unsigned NumF, unsigned ExtraF,
 496                            BranchProbability Probability) const override;
 497
 498   bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
 499                                  BranchProbability Probability) const override {
 500     return true;
 501   }
 502
 503   bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
 504                                  MachineBasicBlock &FMBB) const override {
 505     return false;
 506   }
 507
 508   // Predication support.
 509   bool isPredicated(const MachineInstr &MI) const override;
 510
 511   bool isSchedulingBoundary(const MachineInstr &MI,
 512                             const MachineBasicBlock *MBB,
 513                             const MachineFunction &MF) const override;
 514
 515   bool PredicateInstruction(MachineInstr &MI,
 516                             ArrayRef<MachineOperand> Pred) const override;
 517
 518   bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
 519                          ArrayRef<MachineOperand> Pred2) const override;
 520
 521   bool ClobbersPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred,
 522                          bool SkipDead) const override;
 523
 524   // Comparison optimization.
 525
 526   bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
 527                       Register &SrcReg2, int &Mask, int &Value) const override;
 528
 529   bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
 530                             Register SrcReg2, int Mask, int Value,
 531                             const MachineRegisterInfo *MRI) const override;
 532
 533
 534   /// Return true if get the base operand, byte offset of an instruction and
 535   /// the memory width. Width is the size of memory that is being
 536   /// loaded/stored (e.g. 1, 2, 4, 8).
 537   bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt,
 538                                     const MachineOperand *&BaseOp,
 539                                     int64_t &Offset, unsigned &Width,
 540                                     const TargetRegisterInfo *TRI) const;
 541
 542   /// Get the base operand and byte offset of an instruction that reads/writes
 543   /// memory.
 544   bool getMemOperandsWithOffsetWidth(
 545       const MachineInstr &LdSt,
 546       SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
 547       bool &OffsetIsScalable, unsigned &Width,
 548       const TargetRegisterInfo *TRI) const override;
 549
 550   /// Returns true if the two given memory operations should be scheduled
 551   /// adjacent.
 552   bool shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1,
 553                            ArrayRef<const MachineOperand *> BaseOps2,
 554                            unsigned NumLoads, unsigned NumBytes) const override;
 555
 556   /// Return true if two MIs access different memory addresses and false
 557   /// otherwise
 558   bool
 559   areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
 560                                   const MachineInstr &MIb) const override;
 561
 562   /// GetInstSize - Return the number of bytes of code the specified
 563   /// instruction may be.  This returns the maximum number of bytes.
 564   ///
 565   unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
 566
 567   MCInst getNop() const override;
 568
 569   std::pair<unsigned, unsigned>
 570   decomposeMachineOperandsTargetFlags(unsigned TF) const override;
 571
 572   ArrayRef<std::pair<unsigned, const char *>>
 573   getSerializableDirectMachineOperandTargetFlags() const override;
 574
 575   ArrayRef<std::pair<unsigned, const char *>>
 576   getSerializableBitmaskMachineOperandTargetFlags() const override;
 577
 578   // Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction.
 579   bool expandVSXMemPseudo(MachineInstr &MI) const;
 580
 581   // Lower pseudo instructions after register allocation.
 582   bool expandPostRAPseudo(MachineInstr &MI) const override;
 583
 584   static bool isVFRegister(unsigned Reg) {
 585     return Reg >= PPC::VF0 && Reg <= PPC::VF31;
 586   }
 587   static bool isVRRegister(unsigned Reg) {
 588     return Reg >= PPC::V0 && Reg <= PPC::V31;
 589   }
 590   const TargetRegisterClass *updatedRC(const TargetRegisterClass *RC) const;
 591   static int getRecordFormOpcode(unsigned Opcode);
 592
 593   bool isTOCSaveMI(const MachineInstr &MI) const;
 594
 595   bool isSignOrZeroExtended(const MachineInstr &MI, bool SignExt,
 596                             const unsigned PhiDepth) const;
 597
 598   /// Return true if the output of the instruction is always a sign-extended,
 599   /// i.e. 0 to 31-th bits are same as 32-th bit.
 600   bool isSignExtended(const MachineInstr &MI, const unsigned depth = 0) const {
 601     return isSignOrZeroExtended(MI, true, depth);
 602   }
 603
 604   /// Return true if the output of the instruction is always zero-extended,
 605   /// i.e. 0 to 31-th bits are all zeros
 606   bool isZeroExtended(const MachineInstr &MI, const unsigned depth = 0) const {
 607    return isSignOrZeroExtended(MI, false, depth);
 608   }
 609
 610   bool convertToImmediateForm(MachineInstr &MI,
 611                               MachineInstr **KilledDef = nullptr) const;
 612   bool foldFrameOffset(MachineInstr &MI) const;
 613   bool combineRLWINM(MachineInstr &MI, MachineInstr **ToErase = nullptr) const;
 614   bool isADDIInstrEligibleForFolding(MachineInstr &ADDIMI, int64_t &Imm) const;
 615   bool isADDInstrEligibleForFolding(MachineInstr &ADDMI) const;
 616   bool isImmInstrEligibleForFolding(MachineInstr &MI, unsigned &BaseReg,
 617                                     unsigned &XFormOpcode,
 618                                     int64_t &OffsetOfImmInstr,
 619                                     ImmInstrInfo &III) const;
 620   bool isValidToBeChangedReg(MachineInstr *ADDMI, unsigned Index,
 621                              MachineInstr *&ADDIMI, int64_t &OffsetAddi,
 622                              int64_t OffsetImm) const;
 623
 624   /// Fixup killed/dead flag for register \p RegNo between instructions [\p
 625   /// StartMI, \p EndMI]. Some pre-RA or post-RA transformations may violate
 626   /// register killed/dead flags semantics, this function can be called to fix
 627   /// up. Before calling this function,
 628   /// 1. Ensure that \p RegNo liveness is killed after instruction \p EndMI.
 629   /// 2. Ensure that there is no new definition between (\p StartMI, \p EndMI)
 630   ///    and possible definition for \p RegNo is \p StartMI or \p EndMI. For
 631   ///    pre-RA cases, definition may be \p StartMI through COPY, \p StartMI
 632   ///    will be adjust to true definition.
 633   /// 3. We can do accurate fixup for the case when all instructions between
 634   ///    [\p StartMI, \p EndMI] are in same basic block.
 635   /// 4. For the case when \p StartMI and \p EndMI are not in same basic block,
 636   ///    we conservatively clear kill flag for all uses of \p RegNo for pre-RA
 637   ///    and for post-RA, we give an assertion as without reaching definition
 638   ///    analysis post-RA, \p StartMI and \p EndMI are hard to keep right.
 639   void fixupIsDeadOrKill(MachineInstr *StartMI, MachineInstr *EndMI,
 640                          unsigned RegNo) const;
 641   void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const;
 642   void replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo,
 643                                   int64_t Imm) const;
 644
 645   bool instrHasImmForm(unsigned Opc, bool IsVFReg, ImmInstrInfo &III,
 646                        bool PostRA) const;
 647
 648   // In PostRA phase, try to find instruction defines \p Reg before \p MI.
 649   // \p SeenIntermediate is set to true if uses between DefMI and \p MI exist.
 650   MachineInstr *getDefMIPostRA(unsigned Reg, MachineInstr &MI,
 651                                bool &SeenIntermediateUse) const;
 652
 653   /// getRegNumForOperand - some operands use different numbering schemes
 654   /// for the same registers. For example, a VSX instruction may have any of
 655   /// vs0-vs63 allocated whereas an Altivec instruction could only have
 656   /// vs32-vs63 allocated (numbered as v0-v31). This function returns the actual
 657   /// register number needed for the opcode/operand number combination.
 658   /// The operand number argument will be useful when we need to extend this
 659   /// to instructions that use both Altivec and VSX numbering (for different
 660   /// operands).
 661   static unsigned getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg,
 662                                       unsigned OpNo) {
 663     int16_t regClass = Desc.OpInfo[OpNo].RegClass;
 664     switch (regClass) {
 665       // We store F0-F31, VF0-VF31 in MCOperand and it should be F0-F31,
 666       // VSX32-VSX63 during encoding/disassembling
 667       case PPC::VSSRCRegClassID:
 668       case PPC::VSFRCRegClassID:
 669         if (isVFRegister(Reg))
 670           return PPC::VSX32 + (Reg - PPC::VF0);
 671         break;
 672       // We store VSL0-VSL31, V0-V31 in MCOperand and it should be VSL0-VSL31,
 673       // VSX32-VSX63 during encoding/disassembling
 674       case PPC::VSRCRegClassID:
 675         if (isVRRegister(Reg))
 676           return PPC::VSX32 + (Reg - PPC::V0);
 677         break;
 678       // Other RegClass doesn't need mapping
 679       default:
 680         break;
 681     }
 682     return Reg;
 683   }
 684
 685   /// Check \p Opcode is BDNZ (Decrement CTR and branch if it is still nonzero).
 686   bool isBDNZ(unsigned Opcode) const;
 687
 688   /// Find the hardware loop instruction used to set-up the specified loop.
 689   /// On PPC, we have two instructions used to set-up the hardware loop
 690   /// (MTCTRloop, MTCTR8loop) with corresponding endloop (BDNZ, BDNZ8)
 691   /// instructions to indicate the end of a loop.
 692   MachineInstr *
 693   findLoopInstr(MachineBasicBlock &PreHeader,
 694                 SmallPtrSet<MachineBasicBlock *, 8> &Visited) const;
 695
 696   /// Analyze loop L, which must be a single-basic-block loop, and if the
 697   /// conditions can be understood enough produce a PipelinerLoopInfo object.
 698   std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
 699   analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override;
 700 };
 701
 702 }
 703
 704 #endif