llvm/lib/Target/RISCV/CMakeLists.txt

   1 add_llvm_component_group(RISCV)
   2
   3 set(LLVM_TARGET_DEFINITIONS RISCV.td)
   4
   5 tablegen(LLVM RISCVGenAsmMatcher.inc -gen-asm-matcher)
   6 tablegen(LLVM RISCVGenAsmWriter.inc -gen-asm-writer)
   7 tablegen(LLVM RISCVGenCompressInstEmitter.inc -gen-compress-inst-emitter)
   8 tablegen(LLVM RISCVGenDAGISel.inc -gen-dag-isel)
   9 tablegen(LLVM RISCVGenDisassemblerTables.inc -gen-disassembler)
  10 tablegen(LLVM RISCVGenGlobalISel.inc -gen-global-isel)
  11 tablegen(LLVM RISCVGenInstrInfo.inc -gen-instr-info)
  12 tablegen(LLVM RISCVGenMCCodeEmitter.inc -gen-emitter)
  13 tablegen(LLVM RISCVGenMCPseudoLowering.inc -gen-pseudo-lowering)
  14 tablegen(LLVM RISCVGenRegisterBank.inc -gen-register-bank)
  15 tablegen(LLVM RISCVGenRegisterInfo.inc -gen-register-info)
  16 tablegen(LLVM RISCVGenSearchableTables.inc -gen-searchable-tables)
  17 tablegen(LLVM RISCVGenSubtargetInfo.inc -gen-subtarget)
  18
  19 add_public_tablegen_target(RISCVCommonTableGen)
  20
  21 add_llvm_target(RISCVCodeGen
  22   RISCVAsmPrinter.cpp
  23   RISCVCallLowering.cpp
  24   RISCVExpandAtomicPseudoInsts.cpp
  25   RISCVExpandPseudoInsts.cpp
  26   RISCVFrameLowering.cpp
  27   RISCVInsertVSETVLI.cpp
  28   RISCVInstrInfo.cpp
  29   RISCVInstructionSelector.cpp
  30   RISCVISelDAGToDAG.cpp
  31   RISCVISelLowering.cpp
  32   RISCVLegalizerInfo.cpp
  33   RISCVMCInstLower.cpp
  34   RISCVMergeBaseOffset.cpp
  35   RISCVRegisterBankInfo.cpp
  36   RISCVRegisterInfo.cpp
  37   RISCVSubtarget.cpp
  38   RISCVTargetMachine.cpp
  39   RISCVTargetObjectFile.cpp
  40   RISCVTargetTransformInfo.cpp
  41
  42   LINK_COMPONENTS
  43   Analysis
  44   AsmPrinter
  45   Core
  46   CodeGen
  47   MC
  48   RISCVDesc
  49   RISCVInfo
  50   SelectionDAG
  51   Support
  52   Target
  53   GlobalISel
  54
  55   ADD_TO_COMPONENT
  56   RISCV
  57   )
  58
  59 add_subdirectory(AsmParser)
  60 add_subdirectory(Disassembler)
  61 add_subdirectory(MCTargetDesc)
  62 add_subdirectory(TargetInfo)