llvm/lib/Target/X86/X86SchedSkylakeClient.td

   1 //=- X86SchedSkylake.td - X86 Skylake Client Scheduling ------*- tablegen -*-=//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines the machine model for Skylake Client to support
  10 // instruction scheduling and other instruction cost heuristics.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 def SkylakeClientModel : SchedMachineModel {
  15   // All x86 instructions are modeled as a single micro-op, and SKylake can
  16   // decode 6 instructions per cycle.
  17   let IssueWidth = 6;
  18   let MicroOpBufferSize = 224; // Based on the reorder buffer.
  19   let LoadLatency = 5;
  20   let MispredictPenalty = 14;
  21
  22   // Based on the LSD (loop-stream detector) queue size and benchmarking data.
  23   let LoopMicroOpBufferSize = 50;
  24
  25   // This flag is set to allow the scheduler to assign a default model to
  26   // unrecognized opcodes.
  27   let CompleteModel = 0;
  28 }
  29
  30 let SchedModel = SkylakeClientModel in {
  31
  32 // Skylake Client can issue micro-ops to 8 different ports in one cycle.
  33
  34 // Ports 0, 1, 5, and 6 handle all computation.
  35 // Port 4 gets the data half of stores. Store data can be available later than
  36 // the store address, but since we don't model the latency of stores, we can
  37 // ignore that.
  38 // Ports 2 and 3 are identical. They handle loads and the address half of
  39 // stores. Port 7 can handle address calculations.
  40 def SKLPort0 : ProcResource<1>;
  41 def SKLPort1 : ProcResource<1>;
  42 def SKLPort2 : ProcResource<1>;
  43 def SKLPort3 : ProcResource<1>;
  44 def SKLPort4 : ProcResource<1>;
  45 def SKLPort5 : ProcResource<1>;
  46 def SKLPort6 : ProcResource<1>;
  47 def SKLPort7 : ProcResource<1>;
  48
  49 // Many micro-ops are capable of issuing on multiple ports.
  50 def SKLPort01  : ProcResGroup<[SKLPort0, SKLPort1]>;
  51 def SKLPort23  : ProcResGroup<[SKLPort2, SKLPort3]>;
  52 def SKLPort237 : ProcResGroup<[SKLPort2, SKLPort3, SKLPort7]>;
  53 def SKLPort04  : ProcResGroup<[SKLPort0, SKLPort4]>;
  54 def SKLPort05  : ProcResGroup<[SKLPort0, SKLPort5]>;
  55 def SKLPort06  : ProcResGroup<[SKLPort0, SKLPort6]>;
  56 def SKLPort15  : ProcResGroup<[SKLPort1, SKLPort5]>;
  57 def SKLPort16  : ProcResGroup<[SKLPort1, SKLPort6]>;
  58 def SKLPort56  : ProcResGroup<[SKLPort5, SKLPort6]>;
  59 def SKLPort015 : ProcResGroup<[SKLPort0, SKLPort1, SKLPort5]>;
  60 def SKLPort056 : ProcResGroup<[SKLPort0, SKLPort5, SKLPort6]>;
  61 def SKLPort0156: ProcResGroup<[SKLPort0, SKLPort1, SKLPort5, SKLPort6]>;
  62
  63 def SKLDivider : ProcResource<1>; // Integer division issued on port 0.
  64 // FP division and sqrt on port 0.
  65 def SKLFPDivider : ProcResource<1>;
  66
  67 // 60 Entry Unified Scheduler
  68 def SKLPortAny : ProcResGroup<[SKLPort0, SKLPort1, SKLPort2, SKLPort3, SKLPort4,
  69                               SKLPort5, SKLPort6, SKLPort7]> {
  70   let BufferSize=60;
  71 }
  72
  73 // Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 5
  74 // cycles after the memory operand.
  75 def : ReadAdvance<ReadAfterLd, 5>;
  76
  77 // Vector loads are 5/6/7 cycles, so ReadAfterVec*Ld registers needn't be available
  78 // until 5/6/7 cycles after the memory operand.
  79 def : ReadAdvance<ReadAfterVecLd, 5>;
  80 def : ReadAdvance<ReadAfterVecXLd, 6>;
  81 def : ReadAdvance<ReadAfterVecYLd, 7>;
  82
  83 def : ReadAdvance<ReadInt2Fpu, 0>;
  84
  85 // Many SchedWrites are defined in pairs with and without a folded load.
  86 // Instructions with folded loads are usually micro-fused, so they only appear
  87 // as two micro-ops when queued in the reservation station.
  88 // This multiclass defines the resource usage for variants with and without
  89 // folded loads.
  90 multiclass SKLWriteResPair<X86FoldableSchedWrite SchedRW,
  91                           list<ProcResourceKind> ExePorts,
  92                           int Lat, list<int> Res = [1], int UOps = 1,
  93                           int LoadLat = 5> {
  94   // Register variant is using a single cycle on ExePort.
  95   def : WriteRes<SchedRW, ExePorts> {
  96     let Latency = Lat;
  97     let ResourceCycles = Res;
  98     let NumMicroOps = UOps;
  99   }
 100
 101   // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to
 102   // the latency (default = 5).
 103   def : WriteRes<SchedRW.Folded, !listconcat([SKLPort23], ExePorts)> {
 104     let Latency = !add(Lat, LoadLat);
 105     let ResourceCycles = !listconcat([1], Res);
 106     let NumMicroOps = !add(UOps, 1);
 107   }
 108 }
 109
 110 // A folded store needs a cycle on port 4 for the store data, and an extra port
 111 // 2/3/7 cycle to recompute the address.
 112 def : WriteRes<WriteRMW, [SKLPort237,SKLPort4]>;
 113
 114 // Arithmetic.
 115 defm : SKLWriteResPair<WriteALU,    [SKLPort0156], 1>; // Simple integer ALU op.
 116 defm : SKLWriteResPair<WriteADC,    [SKLPort06],   1>; // Integer ALU + flags op.
 117
 118 // Integer multiplication.
 119 defm : SKLWriteResPair<WriteIMul8,     [SKLPort1],   3>;
 120 defm : SKLWriteResPair<WriteIMul16,    [SKLPort1,SKLPort06,SKLPort0156], 4, [1,1,2], 4>;
 121 defm : X86WriteRes<WriteIMul16Imm,     [SKLPort1,SKLPort0156], 4, [1,1], 2>;
 122 defm : X86WriteRes<WriteIMul16ImmLd,   [SKLPort1,SKLPort0156,SKLPort23], 8, [1,1,1], 3>;
 123 defm : SKLWriteResPair<WriteIMul16Reg, [SKLPort1],   3>;
 124 defm : SKLWriteResPair<WriteIMul32,    [SKLPort1,SKLPort06,SKLPort0156], 4, [1,1,1], 3>;
 125 defm : SKLWriteResPair<WriteMULX32,    [SKLPort1,SKLPort06,SKLPort0156], 4, [1,1,1], 3>;
 126 defm : SKLWriteResPair<WriteIMul32Imm, [SKLPort1],   3>;
 127 defm : SKLWriteResPair<WriteIMul32Reg, [SKLPort1],   3>;
 128 defm : SKLWriteResPair<WriteIMul64,    [SKLPort1,SKLPort5], 4, [1,1], 2>;
 129 defm : SKLWriteResPair<WriteMULX64,    [SKLPort1,SKLPort5], 4, [1,1], 2>;
 130 defm : SKLWriteResPair<WriteIMul64Imm, [SKLPort1],   3>;
 131 defm : SKLWriteResPair<WriteIMul64Reg, [SKLPort1],   3>;
 132 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
 133
 134 defm : X86WriteRes<WriteBSWAP32,    [SKLPort15], 1, [1], 1>;
 135 defm : X86WriteRes<WriteBSWAP64,    [SKLPort06, SKLPort15], 2, [1,1], 2>;
 136 defm : X86WriteRes<WriteCMPXCHG,[SKLPort06, SKLPort0156], 5, [2,3], 5>;
 137 defm : X86WriteRes<WriteCMPXCHGRMW,[SKLPort23,SKLPort06,SKLPort0156,SKLPort237,SKLPort4], 8, [1,2,1,1,1], 6>;
 138 defm : X86WriteRes<WriteXCHG, [SKLPort0156], 2, [3], 3>;
 139
 140 // TODO: Why isn't the SKLDivider used?
 141 defm : SKLWriteResPair<WriteDiv8,   [SKLPort0,SKLDivider], 25, [1,10], 1, 4>;
 142 defm : X86WriteRes<WriteDiv16,      [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156], 76, [7,2,8,3,1,11], 32>;
 143 defm : X86WriteRes<WriteDiv32,      [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156], 76, [7,2,8,3,1,11], 32>;
 144 defm : X86WriteRes<WriteDiv64,      [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156], 76, [7,2,8,3,1,11], 32>;
 145 defm : X86WriteRes<WriteDiv16Ld,    [SKLPort0,SKLPort23,SKLDivider], 29, [1,1,10], 2>;
 146 defm : X86WriteRes<WriteDiv32Ld,    [SKLPort0,SKLPort23,SKLDivider], 29, [1,1,10], 2>;
 147 defm : X86WriteRes<WriteDiv64Ld,    [SKLPort0,SKLPort23,SKLDivider], 29, [1,1,10], 2>;
 148
 149 defm : X86WriteRes<WriteIDiv8,    [SKLPort0,SKLDivider], 25, [1,10], 1>;
 150 defm : X86WriteRes<WriteIDiv16,   [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156], 102, [4,2,4,8,14,34], 66>;
 151 defm : X86WriteRes<WriteIDiv32,   [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156], 102, [4,2,4,8,14,34], 66>;
 152 defm : X86WriteRes<WriteIDiv64,   [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156], 102, [4,2,4,8,14,34], 66>;
 153 defm : X86WriteRes<WriteIDiv8Ld,  [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>;
 154 defm : X86WriteRes<WriteIDiv16Ld, [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>;
 155 defm : X86WriteRes<WriteIDiv32Ld, [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>;
 156 defm : X86WriteRes<WriteIDiv64Ld, [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>;
 157
 158 defm : SKLWriteResPair<WriteCRC32, [SKLPort1], 3>;
 159
 160 def : WriteRes<WriteLEA, [SKLPort15]>; // LEA instructions can't fold loads.
 161
 162 defm : SKLWriteResPair<WriteCMOV,  [SKLPort06], 1, [1], 1>; // Conditional move.
 163 defm : X86WriteRes<WriteFCMOV, [SKLPort1], 3, [1], 1>; // x87 conditional move.
 164 def  : WriteRes<WriteSETCC, [SKLPort06]>; // Setcc.
 165 def  : WriteRes<WriteSETCCStore, [SKLPort06,SKLPort4,SKLPort237]> {
 166   let Latency = 2;
 167   let NumMicroOps = 3;
 168 }
 169
 170 defm : X86WriteRes<WriteLAHFSAHF,        [SKLPort06], 1, [1], 1>;
 171 defm : X86WriteRes<WriteBitTest,         [SKLPort06], 1, [1], 1>;
 172 defm : X86WriteRes<WriteBitTestImmLd,    [SKLPort06,SKLPort23], 6, [1,1], 2>;
 173 defm : X86WriteRes<WriteBitTestRegLd,    [SKLPort0156,SKLPort23], 6, [1,1], 2>;
 174 defm : X86WriteRes<WriteBitTestSet,      [SKLPort06], 1, [1], 1>;
 175 defm : X86WriteRes<WriteBitTestSetImmLd, [SKLPort06,SKLPort23], 5, [1,1], 3>;
 176 defm : X86WriteRes<WriteBitTestSetRegLd, [SKLPort0156,SKLPort23], 5, [1,1], 2>;
 177
 178 // Bit counts.
 179 defm : SKLWriteResPair<WriteBSF, [SKLPort1], 3>;
 180 defm : SKLWriteResPair<WriteBSR, [SKLPort1], 3>;
 181 defm : SKLWriteResPair<WriteLZCNT,          [SKLPort1], 3>;
 182 defm : SKLWriteResPair<WriteTZCNT,          [SKLPort1], 3>;
 183 defm : SKLWriteResPair<WritePOPCNT,         [SKLPort1], 3>;
 184
 185 // Integer shifts and rotates.
 186 defm : SKLWriteResPair<WriteShift,    [SKLPort06],  1>;
 187 defm : SKLWriteResPair<WriteShiftCL,  [SKLPort06],  3, [3], 3>;
 188 defm : SKLWriteResPair<WriteRotate,   [SKLPort06],  1, [1], 1>;
 189 defm : SKLWriteResPair<WriteRotateCL, [SKLPort06],  3, [3], 3>;
 190
 191 // SHLD/SHRD.
 192 defm : X86WriteRes<WriteSHDrri, [SKLPort1], 3, [1], 1>;
 193 defm : X86WriteRes<WriteSHDrrcl,[SKLPort1,SKLPort06,SKLPort0156], 6, [1, 2, 1], 4>;
 194 defm : X86WriteRes<WriteSHDmri, [SKLPort1,SKLPort23,SKLPort237,SKLPort0156], 9, [1, 1, 1, 1], 4>;
 195 defm : X86WriteRes<WriteSHDmrcl,[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort0156], 11, [1, 1, 1, 2, 1], 6>;
 196
 197 // BMI1 BEXTR/BLS, BMI2 BZHI
 198 defm : SKLWriteResPair<WriteBEXTR, [SKLPort06,SKLPort15], 2, [1,1], 2>;
 199 defm : SKLWriteResPair<WriteBLS,   [SKLPort15], 1>;
 200 defm : SKLWriteResPair<WriteBZHI,  [SKLPort15], 1>;
 201
 202 // Loads, stores, and moves, not folded with other operations.
 203 defm : X86WriteRes<WriteLoad,    [SKLPort23], 5, [1], 1>;
 204 defm : X86WriteRes<WriteStore,   [SKLPort237, SKLPort4], 1, [1,1], 1>;
 205 defm : X86WriteRes<WriteStoreNT, [SKLPort237, SKLPort4], 1, [1,1], 2>;
 206 defm : X86WriteRes<WriteMove,    [SKLPort0156], 1, [1], 1>;
 207
 208 // Model the effect of clobbering the read-write mask operand of the GATHER operation.
 209 // Does not cost anything by itself, only has latency, matching that of the WriteLoad,
 210 defm : X86WriteRes<WriteVecMaskedGatherWriteback, [], 5, [], 0>;
 211
 212 // Idioms that clear a register, like xorps %xmm0, %xmm0.
 213 // These can often bypass execution ports completely.
 214 def : WriteRes<WriteZero,  []>;
 215
 216 // Branches don't produce values, so they have no latency, but they still
 217 // consume resources. Indirect branches can fold loads.
 218 defm : SKLWriteResPair<WriteJump,  [SKLPort06],   1>;
 219
 220 // Floating point. This covers both scalar and vector operations.
 221 defm : X86WriteRes<WriteFLD0,          [SKLPort05], 1, [1], 1>;
 222 defm : X86WriteRes<WriteFLD1,          [SKLPort05], 1, [2], 2>;
 223 defm : X86WriteRes<WriteFLDC,          [SKLPort05], 1, [2], 2>;
 224 defm : X86WriteRes<WriteFLoad,         [SKLPort23], 5, [1], 1>;
 225 defm : X86WriteRes<WriteFLoadX,        [SKLPort23], 6, [1], 1>;
 226 defm : X86WriteRes<WriteFLoadY,        [SKLPort23], 7, [1], 1>;
 227 defm : X86WriteRes<WriteFMaskedLoad,   [SKLPort23,SKLPort015], 7, [1,1], 2>;
 228 defm : X86WriteRes<WriteFMaskedLoadY,  [SKLPort23,SKLPort015], 8, [1,1], 2>;
 229 defm : X86WriteRes<WriteFStore,        [SKLPort237,SKLPort4], 1, [1,1], 2>;
 230 defm : X86WriteRes<WriteFStoreX,       [SKLPort237,SKLPort4], 1, [1,1], 2>;
 231 defm : X86WriteRes<WriteFStoreY,       [SKLPort237,SKLPort4], 1, [1,1], 2>;
 232 defm : X86WriteRes<WriteFStoreNT,      [SKLPort237,SKLPort4], 1, [1,1], 2>;
 233 defm : X86WriteRes<WriteFStoreNTX,     [SKLPort237,SKLPort4], 1, [1,1], 2>;
 234 defm : X86WriteRes<WriteFStoreNTY,     [SKLPort237,SKLPort4], 1, [1,1], 2>;
 235
 236 defm : X86WriteRes<WriteFMaskedStore32,  [SKLPort237,SKLPort0], 2, [1,1], 2>;
 237 defm : X86WriteRes<WriteFMaskedStore32Y, [SKLPort237,SKLPort0], 2, [1,1], 2>;
 238 defm : X86WriteRes<WriteFMaskedStore64,  [SKLPort237,SKLPort0], 2, [1,1], 2>;
 239 defm : X86WriteRes<WriteFMaskedStore64Y, [SKLPort237,SKLPort0], 2, [1,1], 2>;
 240
 241 defm : X86WriteRes<WriteFMove,         [SKLPort015], 1, [1], 1>;
 242 defm : X86WriteRes<WriteFMoveX,        [SKLPort015], 1, [1], 1>;
 243 defm : X86WriteRes<WriteFMoveY,        [SKLPort015], 1, [1], 1>;
 244 defm : X86WriteRes<WriteEMMS,          [SKLPort05,SKLPort0156], 10, [9,1], 10>;
 245
 246 defm : SKLWriteResPair<WriteFAdd,     [SKLPort01],  4, [1], 1, 5>; // Floating point add/sub.
 247 defm : SKLWriteResPair<WriteFAddX,    [SKLPort01],  4, [1], 1, 6>;
 248 defm : SKLWriteResPair<WriteFAddY,    [SKLPort01],  4, [1], 1, 7>;
 249 defm : X86WriteResPairUnsupported<WriteFAddZ>;
 250 defm : SKLWriteResPair<WriteFAdd64,   [SKLPort01],  4, [1], 1, 5>; // Floating point double add/sub.
 251 defm : SKLWriteResPair<WriteFAdd64X,  [SKLPort01],  4, [1], 1, 6>;
 252 defm : SKLWriteResPair<WriteFAdd64Y,  [SKLPort01],  4, [1], 1, 7>;
 253 defm : X86WriteResPairUnsupported<WriteFAdd64Z>;
 254
 255 defm : SKLWriteResPair<WriteFCmp,     [SKLPort01],  4, [1], 1, 5>; // Floating point compare.
 256 defm : SKLWriteResPair<WriteFCmpX,    [SKLPort01],  4, [1], 1, 6>;
 257 defm : SKLWriteResPair<WriteFCmpY,    [SKLPort01],  4, [1], 1, 7>;
 258 defm : X86WriteResPairUnsupported<WriteFCmpZ>;
 259 defm : SKLWriteResPair<WriteFCmp64,   [SKLPort01],  4, [1], 1, 5>; // Floating point double compare.
 260 defm : SKLWriteResPair<WriteFCmp64X,  [SKLPort01],  4, [1], 1, 6>;
 261 defm : SKLWriteResPair<WriteFCmp64Y,  [SKLPort01],  4, [1], 1, 7>;
 262 defm : X86WriteResPairUnsupported<WriteFCmp64Z>;
 263
 264 defm : SKLWriteResPair<WriteFCom,      [SKLPort0],  2>; // Floating point compare to flags (X87).
 265 defm : SKLWriteResPair<WriteFComX,     [SKLPort0],  2>; // Floating point compare to flags (SSE).
 266
 267 defm : SKLWriteResPair<WriteFMul,     [SKLPort01],  4, [1], 1, 5>; // Floating point multiplication.
 268 defm : SKLWriteResPair<WriteFMulX,    [SKLPort01],  4, [1], 1, 6>;
 269 defm : SKLWriteResPair<WriteFMulY,    [SKLPort01],  4, [1], 1, 7>;
 270 defm : X86WriteResPairUnsupported<WriteFMulZ>;
 271 defm : SKLWriteResPair<WriteFMul64,   [SKLPort01],  4, [1], 1, 5>; // Floating point double multiplication.
 272 defm : SKLWriteResPair<WriteFMul64X,  [SKLPort01],  4, [1], 1, 6>;
 273 defm : SKLWriteResPair<WriteFMul64Y,  [SKLPort01],  4, [1], 1, 7>;
 274 defm : X86WriteResPairUnsupported<WriteFMul64Z>;
 275
 276 defm : SKLWriteResPair<WriteFDiv,     [SKLPort0,SKLFPDivider], 11, [1,3], 1, 5>; // Floating point division.
 277 //defm : SKLWriteResPair<WriteFDivX,    [SKLPort0,SKLFPDivider], 11, [1,3], 1, 6>;
 278 defm : SKLWriteResPair<WriteFDivY,    [SKLPort0,SKLFPDivider], 11, [1,5], 1, 7>;
 279 defm : X86WriteResPairUnsupported<WriteFDivZ>;
 280 //defm : SKLWriteResPair<WriteFDiv64,   [SKLPort0,SKLFPDivider], 14, [1,3], 1, 5>; // Floating point double division.
 281 //defm : SKLWriteResPair<WriteFDiv64X,  [SKLPort0,SKLFPDivider], 14, [1,3], 1, 6>;
 282 //defm : SKLWriteResPair<WriteFDiv64Y,  [SKLPort0,SKLFPDivider], 14, [1,5], 1, 7>;
 283 defm : X86WriteResPairUnsupported<WriteFDiv64Z>;
 284
 285 defm : SKLWriteResPair<WriteFSqrt,    [SKLPort0,SKLFPDivider], 12, [1,3], 1, 5>; // Floating point square root.
 286 defm : SKLWriteResPair<WriteFSqrtX,   [SKLPort0,SKLFPDivider], 12, [1,3], 1, 6>;
 287 defm : SKLWriteResPair<WriteFSqrtY,   [SKLPort0,SKLFPDivider], 12, [1,6], 1, 7>;
 288 defm : X86WriteResPairUnsupported<WriteFSqrtZ>;
 289 defm : SKLWriteResPair<WriteFSqrt64,  [SKLPort0,SKLFPDivider], 18, [1,6], 1, 5>; // Floating point double square root.
 290 defm : SKLWriteResPair<WriteFSqrt64X, [SKLPort0,SKLFPDivider], 18, [1,6], 1, 6>;
 291 defm : SKLWriteResPair<WriteFSqrt64Y, [SKLPort0,SKLFPDivider], 18, [1,12],1, 7>;
 292 defm : X86WriteResPairUnsupported<WriteFSqrt64Z>;
 293 defm : SKLWriteResPair<WriteFSqrt80,  [SKLPort0,SKLFPDivider], 21, [1,7]>; // Floating point long double square root.
 294
 295 defm : SKLWriteResPair<WriteFRcp,   [SKLPort0], 4, [1], 1, 5>; // Floating point reciprocal estimate.
 296 defm : SKLWriteResPair<WriteFRcpX,  [SKLPort0], 4, [1], 1, 6>;
 297 defm : SKLWriteResPair<WriteFRcpY,  [SKLPort0], 4, [1], 1, 7>;
 298 defm : X86WriteResPairUnsupported<WriteFRcpZ>;
 299
 300 defm : SKLWriteResPair<WriteFRsqrt, [SKLPort0], 4, [1], 1, 5>; // Floating point reciprocal square root estimate.
 301 defm : SKLWriteResPair<WriteFRsqrtX,[SKLPort0], 4, [1], 1, 6>;
 302 defm : SKLWriteResPair<WriteFRsqrtY,[SKLPort0], 4, [1], 1, 7>;
 303 defm : X86WriteResPairUnsupported<WriteFRsqrtZ>;
 304
 305 defm : SKLWriteResPair<WriteFMA,    [SKLPort01], 4, [1], 1, 5>; // Fused Multiply Add.
 306 defm : SKLWriteResPair<WriteFMAX,   [SKLPort01], 4, [1], 1, 6>;
 307 defm : SKLWriteResPair<WriteFMAY,   [SKLPort01], 4, [1], 1, 7>;
 308 defm : X86WriteResPairUnsupported<WriteFMAZ>;
 309 defm : SKLWriteResPair<WriteDPPD,   [SKLPort5,SKLPort01],  9, [1,2], 3, 6>; // Floating point double dot product.
 310 defm : SKLWriteResPair<WriteDPPS,   [SKLPort5,SKLPort01], 13, [1,3], 4, 6>;
 311 defm : SKLWriteResPair<WriteDPPSY,  [SKLPort5,SKLPort01], 13, [1,3], 4, 7>;
 312 defm : X86WriteResPairUnsupported<WriteDPPSZ>;
 313 defm : SKLWriteResPair<WriteFSign,   [SKLPort0], 1>; // Floating point fabs/fchs.
 314 defm : SKLWriteResPair<WriteFRnd,     [SKLPort01], 8, [2], 2, 6>; // Floating point rounding.
 315 defm : SKLWriteResPair<WriteFRndY,    [SKLPort01], 8, [2], 2, 7>;
 316 defm : X86WriteResPairUnsupported<WriteFRndZ>;
 317 defm : SKLWriteResPair<WriteFLogic,  [SKLPort015], 1, [1], 1, 6>; // Floating point and/or/xor logicals.
 318 defm : SKLWriteResPair<WriteFLogicY, [SKLPort015], 1, [1], 1, 7>;
 319 defm : X86WriteResPairUnsupported<WriteFLogicZ>;
 320 defm : SKLWriteResPair<WriteFTest,   [SKLPort0], 2, [1], 1, 6>; // Floating point TEST instructions.
 321 defm : SKLWriteResPair<WriteFTestY,  [SKLPort0], 2, [1], 1, 7>;
 322 defm : X86WriteResPairUnsupported<WriteFTestZ>;
 323 defm : SKLWriteResPair<WriteFShuffle,  [SKLPort5], 1, [1], 1, 6>; // Floating point vector shuffles.
 324 defm : SKLWriteResPair<WriteFShuffleY, [SKLPort5], 1, [1], 1, 7>;
 325 defm : X86WriteResPairUnsupported<WriteFShuffleZ>;
 326 defm : SKLWriteResPair<WriteFVarShuffle,  [SKLPort5], 1, [1], 1, 6>; // Floating point vector shuffles.
 327 defm : SKLWriteResPair<WriteFVarShuffleY, [SKLPort5], 1, [1], 1, 7>;
 328 defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>;
 329 defm : SKLWriteResPair<WriteFBlend,  [SKLPort015], 1, [1], 1, 6>; // Floating point vector blends.
 330 defm : SKLWriteResPair<WriteFBlendY, [SKLPort015], 1, [1], 1, 7>;
 331 defm : X86WriteResPairUnsupported<WriteFBlendZ>;
 332 defm : SKLWriteResPair<WriteFVarBlend, [SKLPort015], 2, [2], 2, 6>; // Fp vector variable blends.
 333 defm : SKLWriteResPair<WriteFVarBlendY,[SKLPort015], 2, [2], 2, 7>;
 334 defm : X86WriteResPairUnsupported<WriteFVarBlendZ>;
 335
 336 // FMA Scheduling helper class.
 337 // class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }
 338
 339 // Vector integer operations.
 340 defm : X86WriteRes<WriteVecLoad,         [SKLPort23], 5, [1], 1>;
 341 defm : X86WriteRes<WriteVecLoadX,        [SKLPort23], 6, [1], 1>;
 342 defm : X86WriteRes<WriteVecLoadY,        [SKLPort23], 7, [1], 1>;
 343 defm : X86WriteRes<WriteVecLoadNT,       [SKLPort23], 6, [1], 1>;
 344 defm : X86WriteRes<WriteVecLoadNTY,      [SKLPort23], 7, [1], 1>;
 345 defm : X86WriteRes<WriteVecMaskedLoad,   [SKLPort23,SKLPort015], 7, [1,1], 2>;
 346 defm : X86WriteRes<WriteVecMaskedLoadY,  [SKLPort23,SKLPort015], 8, [1,1], 2>;
 347 defm : X86WriteRes<WriteVecStore,        [SKLPort237,SKLPort4], 1, [1,1], 2>;
 348 defm : X86WriteRes<WriteVecStoreX,       [SKLPort237,SKLPort4], 1, [1,1], 2>;
 349 defm : X86WriteRes<WriteVecStoreY,       [SKLPort237,SKLPort4], 1, [1,1], 2>;
 350 defm : X86WriteRes<WriteVecStoreNT,      [SKLPort237,SKLPort4], 1, [1,1], 2>;
 351 defm : X86WriteRes<WriteVecStoreNTY,     [SKLPort237,SKLPort4], 1, [1,1], 2>;
 352 defm : X86WriteRes<WriteVecMaskedStore32,  [SKLPort237,SKLPort0], 2, [1,1], 2>;
 353 defm : X86WriteRes<WriteVecMaskedStore32Y, [SKLPort237,SKLPort0], 2, [1,1], 2>;
 354 defm : X86WriteRes<WriteVecMaskedStore64,  [SKLPort237,SKLPort0], 2, [1,1], 2>;
 355 defm : X86WriteRes<WriteVecMaskedStore64Y, [SKLPort237,SKLPort0], 2, [1,1], 2>;
 356 defm : X86WriteRes<WriteVecMove,         [SKLPort05],  1, [1], 1>;
 357 defm : X86WriteRes<WriteVecMoveX,        [SKLPort015], 1, [1], 1>;
 358 defm : X86WriteRes<WriteVecMoveY,        [SKLPort015], 1, [1], 1>;
 359 defm : X86WriteRes<WriteVecMoveToGpr,    [SKLPort0], 2, [1], 1>;
 360 defm : X86WriteRes<WriteVecMoveFromGpr,  [SKLPort5], 1, [1], 1>;
 361
 362 defm : SKLWriteResPair<WriteVecALU,   [SKLPort05], 1, [1], 1, 5>; // Vector integer ALU op, no logicals.
 363 defm : SKLWriteResPair<WriteVecALUX,  [SKLPort01], 1, [1], 1, 6>;
 364 defm : SKLWriteResPair<WriteVecALUY,  [SKLPort01], 1, [1], 1, 7>;
 365 defm : X86WriteResPairUnsupported<WriteVecALUZ>;
 366 defm : SKLWriteResPair<WriteVecLogic, [SKLPort05],  1, [1], 1, 5>; // Vector integer and/or/xor.
 367 defm : SKLWriteResPair<WriteVecLogicX,[SKLPort015], 1, [1], 1, 6>;
 368 defm : SKLWriteResPair<WriteVecLogicY,[SKLPort015], 1, [1], 1, 7>;
 369 defm : X86WriteResPairUnsupported<WriteVecLogicZ>;
 370 defm : SKLWriteResPair<WriteVecTest,  [SKLPort0,SKLPort5], 3, [1,1], 2, 6>; // Vector integer TEST instructions.
 371 defm : SKLWriteResPair<WriteVecTestY, [SKLPort0,SKLPort5], 3, [1,1], 2, 7>;
 372 defm : X86WriteResPairUnsupported<WriteVecTestZ>;
 373 defm : SKLWriteResPair<WriteVecIMul,  [SKLPort0] ,  5, [1], 1, 5>; // Vector integer multiply.
 374 defm : SKLWriteResPair<WriteVecIMulX, [SKLPort01],  5, [1], 1, 6>;
 375 defm : SKLWriteResPair<WriteVecIMulY, [SKLPort01],  5, [1], 1, 7>;
 376 defm : X86WriteResPairUnsupported<WriteVecIMulZ>;
 377 defm : SKLWriteResPair<WritePMULLD,   [SKLPort01], 10, [2], 2, 6>; // Vector PMULLD.
 378 defm : SKLWriteResPair<WritePMULLDY,  [SKLPort01], 10, [2], 2, 7>;
 379 defm : X86WriteResPairUnsupported<WritePMULLDZ>;
 380 defm : SKLWriteResPair<WriteShuffle,  [SKLPort5], 1, [1], 1, 5>; // Vector shuffles.
 381 defm : SKLWriteResPair<WriteShuffleX, [SKLPort5], 1, [1], 1, 6>;
 382 defm : SKLWriteResPair<WriteShuffleY, [SKLPort5], 1, [1], 1, 7>;
 383 defm : X86WriteResPairUnsupported<WriteShuffleZ>;
 384 defm : SKLWriteResPair<WriteVarShuffle,  [SKLPort5], 1, [1], 1, 5>; // Vector shuffles.
 385 defm : SKLWriteResPair<WriteVarShuffleX, [SKLPort5], 1, [1], 1, 6>;
 386 defm : SKLWriteResPair<WriteVarShuffleY, [SKLPort5], 1, [1], 1, 7>;
 387 defm : X86WriteResPairUnsupported<WriteVarShuffleZ>;
 388 defm : SKLWriteResPair<WriteBlend,  [SKLPort5], 1, [1], 1, 6>; // Vector blends.
 389 defm : SKLWriteResPair<WriteBlendY, [SKLPort5], 1, [1], 1, 7>;
 390 defm : X86WriteResPairUnsupported<WriteBlendZ>;
 391 defm : SKLWriteResPair<WriteVarBlend,  [SKLPort015], 2, [2], 2, 6>; // Vector variable blends.
 392 defm : SKLWriteResPair<WriteVarBlendY, [SKLPort015], 2, [2], 2, 6>;
 393 defm : X86WriteResPairUnsupported<WriteVarBlendZ>;
 394 defm : SKLWriteResPair<WriteMPSAD,  [SKLPort5], 4, [2], 2, 6>; // Vector MPSAD.
 395 defm : SKLWriteResPair<WriteMPSADY, [SKLPort5], 4, [2], 2, 7>;
 396 defm : X86WriteResPairUnsupported<WriteMPSADZ>;
 397 defm : SKLWriteResPair<WritePSADBW,  [SKLPort5], 3, [1], 1, 5>; // Vector PSADBW.
 398 defm : SKLWriteResPair<WritePSADBWX, [SKLPort5], 3, [1], 1, 6>;
 399 defm : SKLWriteResPair<WritePSADBWY, [SKLPort5], 3, [1], 1, 7>;
 400 defm : X86WriteResPairUnsupported<WritePSADBWZ>;
 401 defm : SKLWriteResPair<WritePHMINPOS, [SKLPort01], 4, [1], 1, 6>; // Vector PHMINPOS.
 402
 403 // Vector integer shifts.
 404 defm : SKLWriteResPair<WriteVecShift,     [SKLPort0], 1, [1], 1, 5>;
 405 defm : X86WriteRes<WriteVecShiftX,        [SKLPort5,SKLPort01],  2, [1,1], 2>;
 406 defm : X86WriteRes<WriteVecShiftY,        [SKLPort5,SKLPort01],  4, [1,1], 2>;
 407 defm : X86WriteRes<WriteVecShiftXLd,      [SKLPort01,SKLPort23], 7, [1,1], 2>;
 408 defm : X86WriteRes<WriteVecShiftYLd,      [SKLPort01,SKLPort23], 8, [1,1], 2>;
 409 defm : X86WriteResPairUnsupported<WriteVecShiftZ>;
 410
 411 defm : SKLWriteResPair<WriteVecShiftImm,  [SKLPort0],  1, [1], 1, 5>; // Vector integer immediate shifts.
 412 defm : SKLWriteResPair<WriteVecShiftImmX, [SKLPort01], 1, [1], 1, 6>;
 413 defm : SKLWriteResPair<WriteVecShiftImmY, [SKLPort01], 1, [1], 1, 7>;
 414 defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>;
 415 defm : SKLWriteResPair<WriteVarVecShift,  [SKLPort01], 1, [1], 1, 6>; // Variable vector shifts.
 416 defm : SKLWriteResPair<WriteVarVecShiftY, [SKLPort01], 1, [1], 1, 7>;
 417 defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>;
 418
 419 // Vector insert/extract operations.
 420 def : WriteRes<WriteVecInsert, [SKLPort5]> {
 421   let Latency = 2;
 422   let NumMicroOps = 2;
 423   let ResourceCycles = [2];
 424 }
 425 def : WriteRes<WriteVecInsertLd, [SKLPort5,SKLPort23]> {
 426   let Latency = 6;
 427   let NumMicroOps = 2;
 428 }
 429 def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>;
 430
 431 def : WriteRes<WriteVecExtract, [SKLPort0,SKLPort5]> {
 432   let Latency = 3;
 433   let NumMicroOps = 2;
 434 }
 435 def : WriteRes<WriteVecExtractSt, [SKLPort4,SKLPort5,SKLPort237]> {
 436   let Latency = 2;
 437   let NumMicroOps = 3;
 438 }
 439
 440 // Conversion between integer and float.
 441 defm : SKLWriteResPair<WriteCvtSS2I,   [SKLPort1], 3>;
 442 defm : SKLWriteResPair<WriteCvtPS2I,   [SKLPort1], 3>;
 443 defm : SKLWriteResPair<WriteCvtPS2IY,  [SKLPort1], 3>;
 444 defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>;
 445 defm : SKLWriteResPair<WriteCvtSD2I,   [SKLPort1], 3>;
 446 defm : SKLWriteResPair<WriteCvtPD2I,   [SKLPort1], 3>;
 447 defm : SKLWriteResPair<WriteCvtPD2IY,  [SKLPort1], 3>;
 448 defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>;
 449
 450 defm : SKLWriteResPair<WriteCvtI2SS,   [SKLPort1], 4>;
 451 defm : SKLWriteResPair<WriteCvtI2PS,   [SKLPort1], 4>;
 452 defm : SKLWriteResPair<WriteCvtI2PSY,  [SKLPort1], 4>;
 453 defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>;
 454 defm : SKLWriteResPair<WriteCvtI2SD,   [SKLPort1], 4>;
 455 defm : SKLWriteResPair<WriteCvtI2PD,   [SKLPort1], 4>;
 456 defm : SKLWriteResPair<WriteCvtI2PDY,  [SKLPort1], 4>;
 457 defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>;
 458
 459 defm : SKLWriteResPair<WriteCvtSS2SD,  [SKLPort1], 3>;
 460 defm : SKLWriteResPair<WriteCvtPS2PD,  [SKLPort1], 3>;
 461 defm : SKLWriteResPair<WriteCvtPS2PDY, [SKLPort1], 3>;
 462 defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>;
 463 defm : SKLWriteResPair<WriteCvtSD2SS,  [SKLPort1], 3>;
 464 defm : SKLWriteResPair<WriteCvtPD2PS,  [SKLPort1], 3>;
 465 defm : SKLWriteResPair<WriteCvtPD2PSY, [SKLPort1], 3>;
 466 defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>;
 467
 468 defm : X86WriteRes<WriteCvtPH2PS,    [SKLPort5,SKLPort015],  5, [1,1], 2>;
 469 defm : X86WriteRes<WriteCvtPH2PSY,    [SKLPort5,SKLPort01],  7, [1,1], 2>;
 470 defm : X86WriteResUnsupported<WriteCvtPH2PSZ>;
 471 defm : X86WriteRes<WriteCvtPH2PSLd,  [SKLPort23,SKLPort01],  9, [1,1], 2>;
 472 defm : X86WriteRes<WriteCvtPH2PSYLd, [SKLPort23,SKLPort01], 10, [1,1], 2>;
 473 defm : X86WriteResUnsupported<WriteCvtPH2PSZLd>;
 474
 475 defm : X86WriteRes<WriteCvtPS2PH,                       [SKLPort5,SKLPort015], 5, [1,1], 2>;
 476 defm : X86WriteRes<WriteCvtPS2PHY,                       [SKLPort5,SKLPort01], 7, [1,1], 2>;
 477 defm : X86WriteResUnsupported<WriteCvtPS2PHZ>;
 478 defm : X86WriteRes<WriteCvtPS2PHSt,  [SKLPort4,SKLPort5,SKLPort237,SKLPort01], 6, [1,1,1,1], 4>;
 479 defm : X86WriteRes<WriteCvtPS2PHYSt, [SKLPort4,SKLPort5,SKLPort237,SKLPort01], 8, [1,1,1,1], 4>;
 480 defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>;
 481
 482 // Strings instructions.
 483
 484 // Packed Compare Implicit Length Strings, Return Mask
 485 def : WriteRes<WritePCmpIStrM, [SKLPort0]> {
 486   let Latency = 10;
 487   let NumMicroOps = 3;
 488   let ResourceCycles = [3];
 489 }
 490 def : WriteRes<WritePCmpIStrMLd, [SKLPort0, SKLPort23]> {
 491   let Latency = 16;
 492   let NumMicroOps = 4;
 493   let ResourceCycles = [3,1];
 494 }
 495
 496 // Packed Compare Explicit Length Strings, Return Mask
 497 def : WriteRes<WritePCmpEStrM, [SKLPort0, SKLPort5, SKLPort015, SKLPort0156]> {
 498   let Latency = 19;
 499   let NumMicroOps = 9;
 500   let ResourceCycles = [4,3,1,1];
 501 }
 502 def : WriteRes<WritePCmpEStrMLd, [SKLPort0, SKLPort5,SKLPort23, SKLPort015, SKLPort0156]> {
 503   let Latency = 25;
 504   let NumMicroOps = 10;
 505   let ResourceCycles = [4,3,1,1,1];
 506 }
 507
 508 // Packed Compare Implicit Length Strings, Return Index
 509 def : WriteRes<WritePCmpIStrI, [SKLPort0]> {
 510   let Latency = 10;
 511   let NumMicroOps = 3;
 512   let ResourceCycles = [3];
 513 }
 514 def : WriteRes<WritePCmpIStrILd, [SKLPort0, SKLPort23]> {
 515   let Latency = 16;
 516   let NumMicroOps = 4;
 517   let ResourceCycles = [3,1];
 518 }
 519
 520 // Packed Compare Explicit Length Strings, Return Index
 521 def : WriteRes<WritePCmpEStrI, [SKLPort0, SKLPort5, SKLPort0156]> {
 522   let Latency = 18;
 523   let NumMicroOps = 8;
 524   let ResourceCycles = [4,3,1];
 525 }
 526 def : WriteRes<WritePCmpEStrILd, [SKLPort0, SKLPort5, SKLPort23, SKLPort0156]> {
 527   let Latency = 24;
 528   let NumMicroOps = 9;
 529   let ResourceCycles = [4,3,1,1];
 530 }
 531
 532 // MOVMSK Instructions.
 533 def : WriteRes<WriteFMOVMSK,    [SKLPort0]> { let Latency = 2; }
 534 def : WriteRes<WriteVecMOVMSK,  [SKLPort0]> { let Latency = 2; }
 535 def : WriteRes<WriteVecMOVMSKY, [SKLPort0]> { let Latency = 2; }
 536 def : WriteRes<WriteMMXMOVMSK,  [SKLPort0]> { let Latency = 2; }
 537
 538 // AES instructions.
 539 def : WriteRes<WriteAESDecEnc, [SKLPort0]> { // Decryption, encryption.
 540   let Latency = 4;
 541   let NumMicroOps = 1;
 542   let ResourceCycles = [1];
 543 }
 544 def : WriteRes<WriteAESDecEncLd, [SKLPort0, SKLPort23]> {
 545   let Latency = 10;
 546   let NumMicroOps = 2;
 547   let ResourceCycles = [1,1];
 548 }
 549
 550 def : WriteRes<WriteAESIMC, [SKLPort0]> { // InvMixColumn.
 551   let Latency = 8;
 552   let NumMicroOps = 2;
 553   let ResourceCycles = [2];
 554 }
 555 def : WriteRes<WriteAESIMCLd, [SKLPort0, SKLPort23]> {
 556   let Latency = 14;
 557   let NumMicroOps = 3;
 558   let ResourceCycles = [2,1];
 559 }
 560
 561 def : WriteRes<WriteAESKeyGen, [SKLPort0, SKLPort5, SKLPort015]> { // Key Generation.
 562   let Latency = 20;
 563   let NumMicroOps = 11;
 564   let ResourceCycles = [3,6,2];
 565 }
 566 def : WriteRes<WriteAESKeyGenLd, [SKLPort0, SKLPort5, SKLPort23, SKLPort015]> {
 567   let Latency = 25;
 568   let NumMicroOps = 11;
 569   let ResourceCycles = [3,6,1,1];
 570 }
 571
 572 // Carry-less multiplication instructions.
 573 def : WriteRes<WriteCLMul, [SKLPort5]> {
 574   let Latency = 6;
 575   let NumMicroOps = 1;
 576   let ResourceCycles = [1];
 577 }
 578 def : WriteRes<WriteCLMulLd, [SKLPort5, SKLPort23]> {
 579   let Latency = 12;
 580   let NumMicroOps = 2;
 581   let ResourceCycles = [1,1];
 582 }
 583
 584 // Catch-all for expensive system instructions.
 585 def : WriteRes<WriteSystem,     [SKLPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;
 586
 587 // AVX2.
 588 defm : SKLWriteResPair<WriteFShuffle256, [SKLPort5], 3, [1], 1, 7>; // Fp 256-bit width vector shuffles.
 589 defm : SKLWriteResPair<WriteFVarShuffle256, [SKLPort5], 3, [1], 1, 7>; // Fp 256-bit width vector variable shuffles.
 590 defm : SKLWriteResPair<WriteShuffle256, [SKLPort5], 3, [1], 1, 7>;  // 256-bit width vector shuffles.
 591 defm : SKLWriteResPair<WriteVPMOV256, [SKLPort5], 3, [1], 1, 7>;  // 256-bit width packed vector width-changing move.
 592 defm : SKLWriteResPair<WriteVarShuffle256, [SKLPort5], 3, [1], 1, 7>;  // 256-bit width vector variable shuffles.
 593
 594 // Old microcoded instructions that nobody use.
 595 def : WriteRes<WriteMicrocoded, [SKLPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
 596
 597 // Fence instructions.
 598 def : WriteRes<WriteFence,  [SKLPort23, SKLPort4]>;
 599
 600 // Load/store MXCSR.
 601 def : WriteRes<WriteLDMXCSR, [SKLPort0,SKLPort23,SKLPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
 602 def : WriteRes<WriteSTMXCSR, [SKLPort4,SKLPort5,SKLPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
 603
 604 // Nop, not very useful expect it provides a model for nops!
 605 def : WriteRes<WriteNop, []>;
 606
 607 ////////////////////////////////////////////////////////////////////////////////
 608 // Horizontal add/sub  instructions.
 609 ////////////////////////////////////////////////////////////////////////////////
 610
 611 defm : SKLWriteResPair<WriteFHAdd,  [SKLPort5,SKLPort01], 6, [2,1], 3, 6>;
 612 defm : SKLWriteResPair<WriteFHAddY, [SKLPort5,SKLPort01], 6, [2,1], 3, 7>;
 613 defm : SKLWriteResPair<WritePHAdd,  [SKLPort5,SKLPort05],  3, [2,1], 3, 5>;
 614 defm : SKLWriteResPair<WritePHAddX, [SKLPort5,SKLPort015], 3, [2,1], 3, 6>;
 615 defm : SKLWriteResPair<WritePHAddY, [SKLPort5,SKLPort015], 3, [2,1], 3, 7>;
 616
 617 // Remaining instrs.
 618
 619 def SKLWriteResGroup1 : SchedWriteRes<[SKLPort0]> {
 620   let Latency = 1;
 621   let NumMicroOps = 1;
 622   let ResourceCycles = [1];
 623 }
 624 def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PADDS(B|W)irr",
 625                                             "MMX_PADDUS(B|W)irr",
 626                                             "MMX_PAVG(B|W)irr",
 627                                             "MMX_PCMPEQ(B|D|W)irr",
 628                                             "MMX_PCMPGT(B|D|W)irr",
 629                                             "MMX_P(MAX|MIN)SWirr",
 630                                             "MMX_P(MAX|MIN)UBirr",
 631                                             "MMX_PSUBS(B|W)irr",
 632                                             "MMX_PSUBUS(B|W)irr")>;
 633
 634 def SKLWriteResGroup3 : SchedWriteRes<[SKLPort5]> {
 635   let Latency = 1;
 636   let NumMicroOps = 1;
 637   let ResourceCycles = [1];
 638 }
 639 def: InstRW<[SKLWriteResGroup3], (instregex "COM(P?)_FST0r",
 640                                             "UCOM_F(P?)r")>;
 641
 642 def SKLWriteResGroup4 : SchedWriteRes<[SKLPort6]> {
 643   let Latency = 1;
 644   let NumMicroOps = 1;
 645   let ResourceCycles = [1];
 646 }
 647 def: InstRW<[SKLWriteResGroup4], (instregex "JMP(16|32|64)r")>;
 648
 649 def SKLWriteResGroup6 : SchedWriteRes<[SKLPort05]> {
 650   let Latency = 1;
 651   let NumMicroOps = 1;
 652   let ResourceCycles = [1];
 653 }
 654 def: InstRW<[SKLWriteResGroup6], (instrs FINCSTP, FNOP)>;
 655
 656 def SKLWriteResGroup7 : SchedWriteRes<[SKLPort06]> {
 657   let Latency = 1;
 658   let NumMicroOps = 1;
 659   let ResourceCycles = [1];
 660 }
 661 def: InstRW<[SKLWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>;
 662
 663 def SKLWriteResGroup8 : SchedWriteRes<[SKLPort15]> {
 664   let Latency = 1;
 665   let NumMicroOps = 1;
 666   let ResourceCycles = [1];
 667 }
 668 def: InstRW<[SKLWriteResGroup8], (instregex "ANDN(32|64)rr")>;
 669
 670 def SKLWriteResGroup9 : SchedWriteRes<[SKLPort015]> {
 671   let Latency = 1;
 672   let NumMicroOps = 1;
 673   let ResourceCycles = [1];
 674 }
 675 def: InstRW<[SKLWriteResGroup9], (instregex "(V?)PADD(B|D|Q|W)(Y?)rr",
 676                                             "VPBLENDD(Y?)rri")>;
 677
 678 def SKLWriteResGroup10 : SchedWriteRes<[SKLPort0156]> {
 679   let Latency = 1;
 680   let NumMicroOps = 1;
 681   let ResourceCycles = [1];
 682 }
 683 def: InstRW<[SKLWriteResGroup10], (instrs CBW, CWDE, CDQE,
 684                                           CMC, STC,
 685                                           SGDT64m,
 686                                           SIDT64m,
 687                                           SMSW16m,
 688                                           STRm,
 689                                           SYSCALL)>;
 690
 691 def SKLWriteResGroup11 : SchedWriteRes<[SKLPort4,SKLPort237]> {
 692   let Latency = 1;
 693   let NumMicroOps = 2;
 694   let ResourceCycles = [1,1];
 695 }
 696 def: InstRW<[SKLWriteResGroup11], (instrs FBSTPm, VMPTRSTm)>;
 697 def: InstRW<[SKLWriteResGroup11], (instregex "ST_FP(32|64|80)m")>;
 698
 699 def SKLWriteResGroup13 : SchedWriteRes<[SKLPort5]> {
 700   let Latency = 2;
 701   let NumMicroOps = 2;
 702   let ResourceCycles = [2];
 703 }
 704 def: InstRW<[SKLWriteResGroup13], (instrs MMX_MOVQ2DQrr)>;
 705
 706 def SKLWriteResGroup14 : SchedWriteRes<[SKLPort05]> {
 707   let Latency = 2;
 708   let NumMicroOps = 2;
 709   let ResourceCycles = [2];
 710 }
 711 def: InstRW<[SKLWriteResGroup14], (instrs FDECSTP,
 712                                           MMX_MOVDQ2Qrr)>;
 713
 714 def SKLWriteResGroup17 : SchedWriteRes<[SKLPort0156]> {
 715   let Latency = 2;
 716   let NumMicroOps = 2;
 717   let ResourceCycles = [2];
 718 }
 719 def: InstRW<[SKLWriteResGroup17], (instrs LFENCE,
 720                                           WAIT,
 721                                           XGETBV)>;
 722
 723 def SKLWriteResGroup20 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
 724   let Latency = 2;
 725   let NumMicroOps = 2;
 726   let ResourceCycles = [1,1];
 727 }
 728 def: InstRW<[SKLWriteResGroup20], (instregex "CLFLUSH")>;
 729
 730 def SKLWriteResGroup21 : SchedWriteRes<[SKLPort237,SKLPort0156]> {
 731   let Latency = 2;
 732   let NumMicroOps = 2;
 733   let ResourceCycles = [1,1];
 734 }
 735 def: InstRW<[SKLWriteResGroup21], (instrs SFENCE)>;
 736
 737 def SKLWriteResGroup23 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
 738   let Latency = 2;
 739   let NumMicroOps = 2;
 740   let ResourceCycles = [1,1];
 741 }
 742 def: InstRW<[SKLWriteResGroup23], (instrs CWD,
 743                                           JCXZ, JECXZ, JRCXZ,
 744                                           ADC8i8, SBB8i8,
 745                                           ADC16i16, SBB16i16,
 746                                           ADC32i32, SBB32i32,
 747                                           ADC64i32, SBB64i32)>;
 748
 749 def SKLWriteResGroup25 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237]> {
 750   let Latency = 2;
 751   let NumMicroOps = 3;
 752   let ResourceCycles = [1,1,1];
 753 }
 754 def: InstRW<[SKLWriteResGroup25], (instrs FNSTCW16m)>;
 755
 756 def SKLWriteResGroup27 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort15]> {
 757   let Latency = 2;
 758   let NumMicroOps = 3;
 759   let ResourceCycles = [1,1,1];
 760 }
 761 def: InstRW<[SKLWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>;
 762
 763 def SKLWriteResGroup28 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> {
 764   let Latency = 2;
 765   let NumMicroOps = 3;
 766   let ResourceCycles = [1,1,1];
 767 }
 768 def: InstRW<[SKLWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8,
 769                                           STOSB, STOSL, STOSQ, STOSW)>;
 770 def: InstRW<[SKLWriteResGroup28], (instregex "PUSH(16|32|64)rmr")>;
 771
 772 def SKLWriteResGroup29 : SchedWriteRes<[SKLPort1]> {
 773   let Latency = 3;
 774   let NumMicroOps = 1;
 775   let ResourceCycles = [1];
 776 }
 777 def: InstRW<[SKLWriteResGroup29], (instregex "PDEP(32|64)rr",
 778                                              "PEXT(32|64)rr")>;
 779
 780 def SKLWriteResGroup30 : SchedWriteRes<[SKLPort5]> {
 781   let Latency = 3;
 782   let NumMicroOps = 1;
 783   let ResourceCycles = [1];
 784 }
 785 def: InstRW<[SKLWriteResGroup30], (instregex "(ADD|SUB|SUBR)_(FPrST0|FST0r|FrST0)",
 786                                              "VPBROADCAST(B|W)rr")>;
 787
 788 def SKLWriteResGroup32 : SchedWriteRes<[SKLPort0,SKLPort0156]> {
 789   let Latency = 3;
 790   let NumMicroOps = 2;
 791   let ResourceCycles = [1,1];
 792 }
 793 def: InstRW<[SKLWriteResGroup32], (instrs FNSTSW16r)>;
 794
 795 def SKLWriteResGroup35 : SchedWriteRes<[SKLPort0,SKLPort5]> {
 796   let Latency = 3;
 797   let NumMicroOps = 3;
 798   let ResourceCycles = [1,2];
 799 }
 800 def: InstRW<[SKLWriteResGroup35], (instregex "MMX_PH(ADD|SUB)SWrr")>;
 801
 802 def SKLWriteResGroup36 : SchedWriteRes<[SKLPort5,SKLPort01]> {
 803   let Latency = 3;
 804   let NumMicroOps = 3;
 805   let ResourceCycles = [2,1];
 806 }
 807 def: InstRW<[SKLWriteResGroup36], (instregex "(V?)PHADDSW(Y?)rr",
 808                                              "(V?)PHSUBSW(Y?)rr")>;
 809
 810 def SKLWriteResGroup39 : SchedWriteRes<[SKLPort5,SKLPort0156]> {
 811   let Latency = 3;
 812   let NumMicroOps = 3;
 813   let ResourceCycles = [2,1];
 814 }
 815 def: InstRW<[SKLWriteResGroup39], (instrs MMX_PACKSSDWirr,
 816                                           MMX_PACKSSWBirr,
 817                                           MMX_PACKUSWBirr)>;
 818
 819 def SKLWriteResGroup40 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
 820   let Latency = 3;
 821   let NumMicroOps = 3;
 822   let ResourceCycles = [1,2];
 823 }
 824 def: InstRW<[SKLWriteResGroup40], (instregex "CLD")>;
 825
 826 def SKLWriteResGroup41 : SchedWriteRes<[SKLPort237,SKLPort0156]> {
 827   let Latency = 3;
 828   let NumMicroOps = 3;
 829   let ResourceCycles = [1,2];
 830 }
 831 def: InstRW<[SKLWriteResGroup41], (instrs MFENCE)>;
 832
 833 def SKLWriteResGroup42 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
 834   let Latency = 3;
 835   let NumMicroOps = 3;
 836   let ResourceCycles = [1,2];
 837 }
 838 def: InstRW<[SKLWriteResGroup42], (instregex "RCL(8|16|32|64)r(1|i)",
 839                                              "RCR(8|16|32|64)r(1|i)")>;
 840
 841 def SKLWriteResGroup43 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort237]> {
 842   let Latency = 3;
 843   let NumMicroOps = 3;
 844   let ResourceCycles = [1,1,1];
 845 }
 846 def: InstRW<[SKLWriteResGroup43], (instrs FNSTSWm)>;
 847
 848 def SKLWriteResGroup45 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237,SKLPort0156]> {
 849   let Latency = 3;
 850   let NumMicroOps = 4;
 851   let ResourceCycles = [1,1,1,1];
 852 }
 853 def: InstRW<[SKLWriteResGroup45], (instregex "CALL(16|32|64)r")>;
 854
 855 def SKLWriteResGroup46 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06,SKLPort0156]> {
 856   let Latency = 3;
 857   let NumMicroOps = 4;
 858   let ResourceCycles = [1,1,1,1];
 859 }
 860 def: InstRW<[SKLWriteResGroup46], (instrs CALL64pcrel32)>;
 861
 862 def SKLWriteResGroup47 : SchedWriteRes<[SKLPort0]> {
 863   let Latency = 4;
 864   let NumMicroOps = 1;
 865   let ResourceCycles = [1];
 866 }
 867 def: InstRW<[SKLWriteResGroup47], (instregex "MUL_(FPrST0|FST0r|FrST0)")>;
 868
 869 def SKLWriteResGroup48 : SchedWriteRes<[SKLPort01]> {
 870   let Latency = 4;
 871   let NumMicroOps = 1;
 872   let ResourceCycles = [1];
 873 }
 874 def: InstRW<[SKLWriteResGroup48], (instregex "(V?)CVTDQ2PS(Y?)rr",
 875                                              "(V?)CVT(T?)PS2DQ(Y?)rr")>;
 876
 877 def SKLWriteResGroup53 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237]> {
 878   let Latency = 4;
 879   let NumMicroOps = 3;
 880   let ResourceCycles = [1,1,1];
 881 }
 882 def: InstRW<[SKLWriteResGroup53], (instregex "IST(T?)_FP(16|32|64)m",
 883                                              "IST_F(16|32)m")>;
 884
 885 def SKLWriteResGroup54 : SchedWriteRes<[SKLPort0156]> {
 886   let Latency = 4;
 887   let NumMicroOps = 4;
 888   let ResourceCycles = [4];
 889 }
 890 def: InstRW<[SKLWriteResGroup54], (instrs FNCLEX)>;
 891
 892 def SKLWriteResGroup55 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
 893   let Latency = 4;
 894   let NumMicroOps = 4;
 895   let ResourceCycles = [1,3];
 896 }
 897 def: InstRW<[SKLWriteResGroup55], (instrs PAUSE)>;
 898
 899 def SKLWriteResGroup56 : SchedWriteRes<[]> {
 900   let Latency = 0;
 901   let NumMicroOps = 4;
 902   let ResourceCycles = [];
 903 }
 904 def: InstRW<[SKLWriteResGroup56], (instrs VZEROUPPER)>;
 905
 906 def SKLWriteResGroup57 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort0156]> {
 907   let Latency = 4;
 908   let NumMicroOps = 4;
 909   let ResourceCycles = [1,1,2];
 910 }
 911 def: InstRW<[SKLWriteResGroup57], (instregex "LAR(16|32|64)rr")>;
 912
 913 def SKLWriteResGroup58 : SchedWriteRes<[SKLPort23]> {
 914   let Latency = 5;
 915   let NumMicroOps = 1;
 916   let ResourceCycles = [1];
 917 }
 918 def: InstRW<[SKLWriteResGroup58], (instregex "MOVSX(16|32|64)rm(8|16|32)",
 919                                              "MOVZX(16|32|64)rm(8|16)",
 920                                              "(V?)MOVDDUPrm")>; // TODO: Should this be SKLWriteResGroup67?
 921
 922 def SKLWriteResGroup59 : SchedWriteRes<[SKLPort0,SKLPort5]> {
 923   let Latency = 5;
 924   let NumMicroOps = 2;
 925   let ResourceCycles = [1,1];
 926 }
 927 def: InstRW<[SKLWriteResGroup59], (instrs MMX_CVTPI2PDirr,
 928                                           CVTDQ2PDrr,
 929                                           VCVTDQ2PDrr)>;
 930
 931 def SKLWriteResGroup60 : SchedWriteRes<[SKLPort5,SKLPort015]> {
 932   let Latency = 5;
 933   let NumMicroOps = 2;
 934   let ResourceCycles = [1,1];
 935 }
 936 def: InstRW<[SKLWriteResGroup60], (instregex "MMX_CVT(T?)PD2PIirr",
 937                                              "MMX_CVT(T?)PS2PIirr",
 938                                              "(V?)CVT(T?)PD2DQrr",
 939                                              "(V?)CVTPD2PSrr",
 940                                              "(V?)CVTPS2PDrr",
 941                                              "(V?)CVTSD2SSrr",
 942                                              "(V?)CVTSI642SDrr",
 943                                              "(V?)CVTSI2SDrr",
 944                                              "(V?)CVTSI2SSrr",
 945                                              "(V?)CVTSS2SDrr")>;
 946
 947 def SKLWriteResGroup61 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06]> {
 948   let Latency = 5;
 949   let NumMicroOps = 3;
 950   let ResourceCycles = [1,1,1];
 951 }
 952 def: InstRW<[SKLWriteResGroup61], (instregex "STR(16|32|64)r")>;
 953
 954 def SKLWriteResGroup63 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
 955   let Latency = 5;
 956   let NumMicroOps = 5;
 957   let ResourceCycles = [1,4];
 958 }
 959 def: InstRW<[SKLWriteResGroup63], (instrs XSETBV)>;
 960
 961 def SKLWriteResGroup65 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> {
 962   let Latency = 5;
 963   let NumMicroOps = 6;
 964   let ResourceCycles = [1,1,4];
 965 }
 966 def: InstRW<[SKLWriteResGroup65], (instregex "PUSHF(16|64)")>;
 967
 968 def SKLWriteResGroup67 : SchedWriteRes<[SKLPort23]> {
 969   let Latency = 6;
 970   let NumMicroOps = 1;
 971   let ResourceCycles = [1];
 972 }
 973 def: InstRW<[SKLWriteResGroup67], (instrs VBROADCASTSSrm,
 974                                           VPBROADCASTDrm,
 975                                           VPBROADCASTQrm)>;
 976 def: InstRW<[SKLWriteResGroup67], (instregex "(V?)MOVSHDUPrm",
 977                                              "(V?)MOVSLDUPrm")>;
 978
 979 def SKLWriteResGroup68 : SchedWriteRes<[SKLPort0]> {
 980   let Latency = 6;
 981   let NumMicroOps = 2;
 982   let ResourceCycles = [2];
 983 }
 984 def: InstRW<[SKLWriteResGroup68], (instrs MMX_CVTPI2PSirr)>;
 985
 986 def SKLWriteResGroup69 : SchedWriteRes<[SKLPort0,SKLPort23]> {
 987   let Latency = 6;
 988   let NumMicroOps = 2;
 989   let ResourceCycles = [1,1];
 990 }
 991 def: InstRW<[SKLWriteResGroup69], (instrs MMX_PADDSBirm,
 992                                           MMX_PADDSWirm,
 993                                           MMX_PADDUSBirm,
 994                                           MMX_PADDUSWirm,
 995                                           MMX_PAVGBirm,
 996                                           MMX_PAVGWirm,
 997                                           MMX_PCMPEQBirm,
 998                                           MMX_PCMPEQDirm,
 999                                           MMX_PCMPEQWirm,
1000                                           MMX_PCMPGTBirm,
1001                                           MMX_PCMPGTDirm,
1002                                           MMX_PCMPGTWirm,
1003                                           MMX_PMAXSWirm,
1004                                           MMX_PMAXUBirm,
1005                                           MMX_PMINSWirm,
1006                                           MMX_PMINUBirm,
1007                                           MMX_PSUBSBirm,
1008                                           MMX_PSUBSWirm,
1009                                           MMX_PSUBUSBirm,
1010                                           MMX_PSUBUSWirm)>;
1011
1012 def SKLWriteResGroup70 : SchedWriteRes<[SKLPort0,SKLPort01]> {
1013   let Latency = 6;
1014   let NumMicroOps = 2;
1015   let ResourceCycles = [1,1];
1016 }
1017 def: InstRW<[SKLWriteResGroup70], (instregex "(V?)CVTSS2SI(64)?rr",
1018                                              "(V?)CVT(T?)SD2SI(64)?rr")>;
1019
1020 def SKLWriteResGroup72 : SchedWriteRes<[SKLPort6,SKLPort23]> {
1021   let Latency = 6;
1022   let NumMicroOps = 2;
1023   let ResourceCycles = [1,1];
1024 }
1025 def: InstRW<[SKLWriteResGroup72], (instrs FARJMP64m)>;
1026 def: InstRW<[SKLWriteResGroup72], (instregex "JMP(16|32|64)m")>;
1027
1028 def SKLWriteResGroup75 : SchedWriteRes<[SKLPort23,SKLPort15]> {
1029   let Latency = 6;
1030   let NumMicroOps = 2;
1031   let ResourceCycles = [1,1];
1032 }
1033 def: InstRW<[SKLWriteResGroup75], (instregex "ANDN(32|64)rm",
1034                                              "MOVBE(16|32|64)rm")>;
1035
1036 def SKLWriteResGroup76 : SchedWriteRes<[SKLPort23,SKLPort0156]> {
1037   let Latency = 6;
1038   let NumMicroOps = 2;
1039   let ResourceCycles = [1,1];
1040 }
1041 def: InstRW<[SKLWriteResGroup76], (instrs POP16r, POP32r, POP64r)>;
1042 def: InstRW<[SKLWriteResGroup76], (instregex "POP(16|32|64)rmr")>;
1043
1044 def SKLWriteResGroup78 : SchedWriteRes<[SKLPort5,SKLPort01]> {
1045   let Latency = 6;
1046   let NumMicroOps = 3;
1047   let ResourceCycles = [2,1];
1048 }
1049 def: InstRW<[SKLWriteResGroup78], (instregex "(V?)CVTSI642SSrr")>;
1050
1051 def SKLWriteResGroup80 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06,SKLPort0156]> {
1052   let Latency = 6;
1053   let NumMicroOps = 4;
1054   let ResourceCycles = [1,1,1,1];
1055 }
1056 def: InstRW<[SKLWriteResGroup80], (instregex "SLDT(16|32|64)r")>;
1057
1058 def SKLWriteResGroup82 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
1059   let Latency = 6;
1060   let NumMicroOps = 4;
1061   let ResourceCycles = [1,1,1,1];
1062 }
1063 def: InstRW<[SKLWriteResGroup82], (instregex "SAR(8|16|32|64)m(1|i)",
1064                                              "SHL(8|16|32|64)m(1|i)",
1065                                              "SHR(8|16|32|64)m(1|i)")>;
1066
1067 def SKLWriteResGroup83 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {
1068   let Latency = 6;
1069   let NumMicroOps = 4;
1070   let ResourceCycles = [1,1,1,1];
1071 }
1072 def: InstRW<[SKLWriteResGroup83], (instregex "POP(16|32|64)rmm",
1073                                              "PUSH(16|32|64)rmm")>;
1074
1075 def SKLWriteResGroup84 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
1076   let Latency = 6;
1077   let NumMicroOps = 6;
1078   let ResourceCycles = [1,5];
1079 }
1080 def: InstRW<[SKLWriteResGroup84], (instrs STD)>;
1081
1082 def SKLWriteResGroup85 : SchedWriteRes<[SKLPort23]> {
1083   let Latency = 7;
1084   let NumMicroOps = 1;
1085   let ResourceCycles = [1];
1086 }
1087 def: InstRW<[SKLWriteResGroup85], (instregex "LD_F(32|64|80)m")>;
1088 def: InstRW<[SKLWriteResGroup85], (instrs VBROADCASTF128,
1089                                           VBROADCASTI128,
1090                                           VBROADCASTSDYrm,
1091                                           VBROADCASTSSYrm,
1092                                           VMOVDDUPYrm,
1093                                           VMOVSHDUPYrm,
1094                                           VMOVSLDUPYrm,
1095                                           VPBROADCASTDYrm,
1096                                           VPBROADCASTQYrm)>;
1097
1098 def SKLWriteResGroup86 : SchedWriteRes<[SKLPort0,SKLPort5]> {
1099   let Latency = 7;
1100   let NumMicroOps = 2;
1101   let ResourceCycles = [1,1];
1102 }
1103 def: InstRW<[SKLWriteResGroup86], (instrs VCVTDQ2PDYrr)>;
1104
1105 def SKLWriteResGroup88 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1106   let Latency = 6;
1107   let NumMicroOps = 2;
1108   let ResourceCycles = [1,1];
1109 }
1110 def: InstRW<[SKLWriteResGroup88], (instregex "(V?)PMOV(SX|ZX)BDrm",
1111                                              "(V?)PMOV(SX|ZX)BQrm",
1112                                              "(V?)PMOV(SX|ZX)BWrm",
1113                                              "(V?)PMOV(SX|ZX)DQrm",
1114                                              "(V?)PMOV(SX|ZX)WDrm",
1115                                              "(V?)PMOV(SX|ZX)WQrm")>;
1116
1117 def SKLWriteResGroup89 : SchedWriteRes<[SKLPort5,SKLPort01]> {
1118   let Latency = 7;
1119   let NumMicroOps = 2;
1120   let ResourceCycles = [1,1];
1121 }
1122 def: InstRW<[SKLWriteResGroup89], (instrs VCVTPD2PSYrr,
1123                                           VCVTPS2PDYrr,
1124                                           VCVTPD2DQYrr,
1125                                           VCVTTPD2DQYrr)>;
1126
1127 def SKLWriteResGroup91 : SchedWriteRes<[SKLPort23,SKLPort015]> {
1128   let Latency = 7;
1129   let NumMicroOps = 2;
1130   let ResourceCycles = [1,1];
1131 }
1132 def: InstRW<[SKLWriteResGroup91], (instrs VINSERTF128rm,
1133                                           VINSERTI128rm,
1134                                           VPBLENDDrmi)>;
1135 def: InstRW<[SKLWriteResGroup91, ReadAfterVecXLd],
1136                                   (instregex "(V?)PADD(B|D|Q|W)rm",
1137                                              "(V?)PSUB(B|D|Q|W)rm")>;
1138
1139 def SKLWriteResGroup92 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1140   let Latency = 7;
1141   let NumMicroOps = 3;
1142   let ResourceCycles = [2,1];
1143 }
1144 def: InstRW<[SKLWriteResGroup92], (instrs MMX_PACKSSDWirm,
1145                                           MMX_PACKSSWBirm,
1146                                           MMX_PACKUSWBirm)>;
1147
1148 def SKLWriteResGroup94 : SchedWriteRes<[SKLPort23,SKLPort0156]> {
1149   let Latency = 7;
1150   let NumMicroOps = 3;
1151   let ResourceCycles = [1,2];
1152 }
1153 def: InstRW<[SKLWriteResGroup94], (instrs LEAVE, LEAVE64,
1154                                           SCASB, SCASL, SCASQ, SCASW)>;
1155
1156 def SKLWriteResGroup95 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort01]> {
1157   let Latency = 7;
1158   let NumMicroOps = 3;
1159   let ResourceCycles = [1,1,1];
1160 }
1161 def: InstRW<[SKLWriteResGroup95], (instregex "(V?)CVTTSS2SI(64)?rr")>;
1162
1163 def SKLWriteResGroup96 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05]> {
1164   let Latency = 7;
1165   let NumMicroOps = 3;
1166   let ResourceCycles = [1,1,1];
1167 }
1168 def: InstRW<[SKLWriteResGroup96], (instrs FLDCW16m)>;
1169
1170 def SKLWriteResGroup98 : SchedWriteRes<[SKLPort6,SKLPort23,SKLPort0156]> {
1171   let Latency = 7;
1172   let NumMicroOps = 3;
1173   let ResourceCycles = [1,1,1];
1174 }
1175 def: InstRW<[SKLWriteResGroup98], (instrs LRETQ, RETQ)>;
1176
1177 def SKLWriteResGroup100 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
1178   let Latency = 7;
1179   let NumMicroOps = 5;
1180   let ResourceCycles = [1,1,1,2];
1181 }
1182 def: InstRW<[SKLWriteResGroup100], (instregex "ROL(8|16|32|64)m(1|i)",
1183                                               "ROR(8|16|32|64)m(1|i)")>;
1184
1185 def SKLWriteResGroup100_1 : SchedWriteRes<[SKLPort06]> {
1186   let Latency = 2;
1187   let NumMicroOps = 2;
1188   let ResourceCycles = [2];
1189 }
1190 def: InstRW<[SKLWriteResGroup100_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1,
1191                                              ROR8r1, ROR16r1, ROR32r1, ROR64r1)>;
1192
1193 def SKLWriteResGroup101 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {
1194   let Latency = 7;
1195   let NumMicroOps = 5;
1196   let ResourceCycles = [1,1,1,2];
1197 }
1198 def: InstRW<[SKLWriteResGroup101], (instregex "XADD(8|16|32|64)rm")>;
1199
1200 def SKLWriteResGroup102 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
1201   let Latency = 7;
1202   let NumMicroOps = 5;
1203   let ResourceCycles = [1,1,1,1,1];
1204 }
1205 def: InstRW<[SKLWriteResGroup102], (instregex "CALL(16|32|64)m")>;
1206 def: InstRW<[SKLWriteResGroup102], (instrs FARCALL64m)>;
1207
1208 def SKLWriteResGroup103 : SchedWriteRes<[SKLPort6,SKLPort06,SKLPort15,SKLPort0156]> {
1209   let Latency = 7;
1210   let NumMicroOps = 7;
1211   let ResourceCycles = [1,3,1,2];
1212 }
1213 def: InstRW<[SKLWriteResGroup103], (instrs LOOP)>;
1214
1215 def SKLWriteResGroup107 : SchedWriteRes<[SKLPort1,SKLPort23]> {
1216   let Latency = 8;
1217   let NumMicroOps = 2;
1218   let ResourceCycles = [1,1];
1219 }
1220 def: InstRW<[SKLWriteResGroup107], (instregex "PDEP(32|64)rm",
1221                                               "PEXT(32|64)rm")>;
1222
1223 def SKLWriteResGroup108 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1224   let Latency = 8;
1225   let NumMicroOps = 2;
1226   let ResourceCycles = [1,1];
1227 }
1228 def: InstRW<[SKLWriteResGroup108], (instregex "FCOM(P?)(32|64)m")>;
1229 def: InstRW<[SKLWriteResGroup108], (instrs VPBROADCASTBYrm,
1230                                            VPBROADCASTWYrm,
1231                                            VPMOVSXBDYrm,
1232                                            VPMOVSXBQYrm,
1233                                            VPMOVSXWQYrm)>;
1234
1235 def SKLWriteResGroup110 : SchedWriteRes<[SKLPort23,SKLPort015]> {
1236   let Latency = 8;
1237   let NumMicroOps = 2;
1238   let ResourceCycles = [1,1];
1239 }
1240 def: InstRW<[SKLWriteResGroup110], (instrs VPBLENDDYrmi)>;
1241 def: InstRW<[SKLWriteResGroup110, ReadAfterVecYLd],
1242                                    (instregex "VPADD(B|D|Q|W)Yrm",
1243                                               "VPSUB(B|D|Q|W)Yrm")>;
1244
1245 def SKLWriteResGroup112 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1246   let Latency = 8;
1247   let NumMicroOps = 4;
1248   let ResourceCycles = [1,2,1];
1249 }
1250 def: InstRW<[SKLWriteResGroup112], (instregex "MMX_PH(ADD|SUB)SWrm")>;
1251
1252 def SKLWriteResGroup116 : SchedWriteRes<[SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1253   let Latency = 8;
1254   let NumMicroOps = 5;
1255   let ResourceCycles = [1,1,1,2];
1256 }
1257 def: InstRW<[SKLWriteResGroup116], (instregex "RCL(8|16|32|64)m(1|i)",
1258                                               "RCR(8|16|32|64)m(1|i)")>;
1259
1260 def SKLWriteResGroup117 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
1261   let Latency = 8;
1262   let NumMicroOps = 6;
1263   let ResourceCycles = [1,1,1,3];
1264 }
1265 def: InstRW<[SKLWriteResGroup117], (instregex "ROL(8|16|32|64)mCL",
1266                                               "ROR(8|16|32|64)mCL",
1267                                               "SAR(8|16|32|64)mCL",
1268                                               "SHL(8|16|32|64)mCL",
1269                                               "SHR(8|16|32|64)mCL")>;
1270
1271 def SKLWriteResGroup119 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1272   let Latency = 8;
1273   let NumMicroOps = 6;
1274   let ResourceCycles = [1,1,1,2,1];
1275 }
1276 def: SchedAlias<WriteADCRMW, SKLWriteResGroup119>;
1277
1278 def SKLWriteResGroup120 : SchedWriteRes<[SKLPort0,SKLPort23]> {
1279   let Latency = 9;
1280   let NumMicroOps = 2;
1281   let ResourceCycles = [1,1];
1282 }
1283 def: InstRW<[SKLWriteResGroup120], (instrs MMX_CVTPI2PSirm)>;
1284
1285 def SKLWriteResGroup121 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1286   let Latency = 9;
1287   let NumMicroOps = 2;
1288   let ResourceCycles = [1,1];
1289 }
1290 def: InstRW<[SKLWriteResGroup121], (instrs PCMPGTQrm,
1291                                            VPCMPGTQrm,
1292                                            VPMOVSXBWYrm,
1293                                            VPMOVSXDQYrm,
1294                                            VPMOVSXWDYrm,
1295                                            VPMOVZXWDYrm)>;
1296
1297 def SKLWriteResGroup123 : SchedWriteRes<[SKLPort23,SKLPort01]> {
1298   let Latency = 9;
1299   let NumMicroOps = 2;
1300   let ResourceCycles = [1,1];
1301 }
1302 def: InstRW<[SKLWriteResGroup123], (instregex "MMX_CVT(T?)PS2PIirm",
1303                                               "(V?)CVTPS2PDrm")>;
1304
1305 def SKLWriteResGroup128 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {
1306   let Latency = 9;
1307   let NumMicroOps = 4;
1308   let ResourceCycles = [2,1,1];
1309 }
1310 def: InstRW<[SKLWriteResGroup128], (instregex "(V?)PHADDSWrm",
1311                                               "(V?)PHSUBSWrm")>;
1312
1313 def SKLWriteResGroup131 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> {
1314   let Latency = 9;
1315   let NumMicroOps = 5;
1316   let ResourceCycles = [1,2,1,1];
1317 }
1318 def: InstRW<[SKLWriteResGroup131], (instregex "LAR(16|32|64)rm",
1319                                               "LSL(16|32|64)rm")>;
1320
1321 def SKLWriteResGroup133 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1322   let Latency = 10;
1323   let NumMicroOps = 2;
1324   let ResourceCycles = [1,1];
1325 }
1326 def: InstRW<[SKLWriteResGroup133], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
1327                                               "ILD_F(16|32|64)m")>;
1328 def: InstRW<[SKLWriteResGroup133], (instrs VPCMPGTQYrm)>;
1329
1330 def SKLWriteResGroup134 : SchedWriteRes<[SKLPort01,SKLPort23]> {
1331   let Latency = 10;
1332   let NumMicroOps = 2;
1333   let ResourceCycles = [1,1];
1334 }
1335 def: InstRW<[SKLWriteResGroup134], (instregex "(V?)CVTDQ2PSrm",
1336                                               "(V?)CVTPS2DQrm",
1337                                               "(V?)CVTSS2SDrm",
1338                                               "(V?)CVTTPS2DQrm")>;
1339
1340 def SKLWriteResGroup138 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1341   let Latency = 10;
1342   let NumMicroOps = 3;
1343   let ResourceCycles = [1,1,1];
1344 }
1345 def: InstRW<[SKLWriteResGroup138], (instrs MMX_CVTPI2PDirm)>;
1346
1347 def SKLWriteResGroup139 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort01]> {
1348   let Latency = 10;
1349   let NumMicroOps = 3;
1350   let ResourceCycles = [1,1,1];
1351 }
1352 def: InstRW<[SKLWriteResGroup139], (instregex "(V?)CVTSD2SSrm")>;
1353
1354 def SKLWriteResGroup140 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {
1355   let Latency = 10;
1356   let NumMicroOps = 4;
1357   let ResourceCycles = [2,1,1];
1358 }
1359 def: InstRW<[SKLWriteResGroup140], (instrs VPHADDSWYrm,
1360                                            VPHSUBSWYrm)>;
1361
1362 def SKLWriteResGroup143 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1363   let Latency = 10;
1364   let NumMicroOps = 8;
1365   let ResourceCycles = [1,1,1,1,1,3];
1366 }
1367 def: InstRW<[SKLWriteResGroup143], (instregex "XCHG(8|16|32|64)rm")>;
1368
1369 def SKLWriteResGroup145 : SchedWriteRes<[SKLPort0,SKLFPDivider]> {
1370   let Latency = 11;
1371   let NumMicroOps = 1;
1372   let ResourceCycles = [1,3];
1373 }
1374 def : SchedAlias<WriteFDivX, SKLWriteResGroup145>; // TODO - convert to ZnWriteResFpuPair
1375
1376 def SKLWriteResGroup146 : SchedWriteRes<[SKLPort0,SKLPort23]> {
1377   let Latency = 11;
1378   let NumMicroOps = 2;
1379   let ResourceCycles = [1,1];
1380 }
1381 def: InstRW<[SKLWriteResGroup146], (instregex "MUL_F(32|64)m")>;
1382
1383 def SKLWriteResGroup147 : SchedWriteRes<[SKLPort01,SKLPort23]> {
1384   let Latency = 11;
1385   let NumMicroOps = 2;
1386   let ResourceCycles = [1,1];
1387 }
1388 def: InstRW<[SKLWriteResGroup147], (instrs VCVTDQ2PSYrm,
1389                                            VCVTPS2PDYrm,
1390                                            VCVTPS2DQYrm,
1391                                            VCVTTPS2DQYrm)>;
1392
1393 def SKLWriteResGroup149 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1394   let Latency = 11;
1395   let NumMicroOps = 3;
1396   let ResourceCycles = [2,1];
1397 }
1398 def: InstRW<[SKLWriteResGroup149], (instregex "FICOM(P?)(16|32)m")>;
1399
1400 def SKLWriteResGroup150 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1401   let Latency = 11;
1402   let NumMicroOps = 3;
1403   let ResourceCycles = [1,1,1];
1404 }
1405 def: InstRW<[SKLWriteResGroup150], (instregex "(V?)CVTDQ2PDrm")>;
1406
1407 def SKLWriteResGroup151 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort01]> {
1408   let Latency = 11;
1409   let NumMicroOps = 3;
1410   let ResourceCycles = [1,1,1];
1411 }
1412 def: InstRW<[SKLWriteResGroup151], (instregex "(V?)CVTSS2SI64rm",
1413                                               "(V?)CVT(T?)SD2SI(64)?rm",
1414                                               "VCVTTSS2SI64rm",
1415                                               "(V?)CVT(T?)SS2SIrm")>;
1416
1417 def SKLWriteResGroup152 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort01]> {
1418   let Latency = 11;
1419   let NumMicroOps = 3;
1420   let ResourceCycles = [1,1,1];
1421 }
1422 def: InstRW<[SKLWriteResGroup152], (instrs CVTPD2PSrm,
1423                                            CVTPD2DQrm,
1424                                            CVTTPD2DQrm,
1425                                            MMX_CVTPD2PIirm,
1426                                            MMX_CVTTPD2PIirm)>;
1427
1428 def SKLWriteResGroup154 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
1429   let Latency = 11;
1430   let NumMicroOps = 7;
1431   let ResourceCycles = [2,3,2];
1432 }
1433 def: InstRW<[SKLWriteResGroup154], (instregex "RCL(16|32|64)rCL",
1434                                               "RCR(16|32|64)rCL")>;
1435
1436 def SKLWriteResGroup155 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> {
1437   let Latency = 11;
1438   let NumMicroOps = 9;
1439   let ResourceCycles = [1,5,1,2];
1440 }
1441 def: InstRW<[SKLWriteResGroup155], (instrs RCL8rCL)>;
1442
1443 def SKLWriteResGroup156 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
1444   let Latency = 11;
1445   let NumMicroOps = 11;
1446   let ResourceCycles = [2,9];
1447 }
1448 def: InstRW<[SKLWriteResGroup156], (instrs LOOPE, LOOPNE)>;
1449
1450 def SKLWriteResGroup160 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort01]> {
1451   let Latency = 12;
1452   let NumMicroOps = 4;
1453   let ResourceCycles = [1,1,1,1];
1454 }
1455 def: InstRW<[SKLWriteResGroup160], (instregex "CVTTSS2SI64rm")>;
1456
1457 def SKLWriteResGroup162 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1458   let Latency = 13;
1459   let NumMicroOps = 3;
1460   let ResourceCycles = [2,1];
1461 }
1462 def: InstRW<[SKLWriteResGroup162], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>;
1463
1464 def SKLWriteResGroup163 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1465   let Latency = 13;
1466   let NumMicroOps = 3;
1467   let ResourceCycles = [1,1,1];
1468 }
1469 def: InstRW<[SKLWriteResGroup163], (instrs VCVTDQ2PDYrm)>;
1470
1471 def SKLWriteResGroup166 : SchedWriteRes<[SKLPort0,SKLFPDivider]> {
1472   let Latency = 14;
1473   let NumMicroOps = 1;
1474   let ResourceCycles = [1,3];
1475 }
1476 def : SchedAlias<WriteFDiv64,  SKLWriteResGroup166>; // TODO - convert to ZnWriteResFpuPair
1477 def : SchedAlias<WriteFDiv64X, SKLWriteResGroup166>; // TODO - convert to ZnWriteResFpuPair
1478
1479 def SKLWriteResGroup166_1 : SchedWriteRes<[SKLPort0,SKLFPDivider]> {
1480   let Latency = 14;
1481   let NumMicroOps = 1;
1482   let ResourceCycles = [1,5];
1483 }
1484 def : SchedAlias<WriteFDiv64Y, SKLWriteResGroup166_1>; // TODO - convert to ZnWriteResFpuPair
1485
1486 def SKLWriteResGroup169 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1487   let Latency = 14;
1488   let NumMicroOps = 3;
1489   let ResourceCycles = [1,1,1];
1490 }
1491 def: InstRW<[SKLWriteResGroup169], (instregex "MUL_FI(16|32)m")>;
1492
1493 def SKLWriteResGroup170 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> {
1494   let Latency = 14;
1495   let NumMicroOps = 10;
1496   let ResourceCycles = [2,4,1,3];
1497 }
1498 def: InstRW<[SKLWriteResGroup170], (instrs RCR8rCL)>;
1499
1500 def SKLWriteResGroup171 : SchedWriteRes<[SKLPort0]> {
1501   let Latency = 15;
1502   let NumMicroOps = 1;
1503   let ResourceCycles = [1];
1504 }
1505 def: InstRW<[SKLWriteResGroup171], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>;
1506
1507 def SKLWriteResGroup174 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {
1508   let Latency = 15;
1509   let NumMicroOps = 10;
1510   let ResourceCycles = [1,1,1,5,1,1];
1511 }
1512 def: InstRW<[SKLWriteResGroup174], (instregex "RCL(8|16|32|64)mCL")>;
1513
1514 def SKLWriteResGroup177 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {
1515   let Latency = 16;
1516   let NumMicroOps = 14;
1517   let ResourceCycles = [1,1,1,4,2,5];
1518 }
1519 def: InstRW<[SKLWriteResGroup177], (instrs CMPXCHG8B)>;
1520
1521 def SKLWriteResGroup178 : SchedWriteRes<[SKLPort0156]> {
1522   let Latency = 16;
1523   let NumMicroOps = 16;
1524   let ResourceCycles = [16];
1525 }
1526 def: InstRW<[SKLWriteResGroup178], (instrs VZEROALL)>;
1527
1528 def SKLWriteResGroup179 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> {
1529   let Latency = 17;
1530   let NumMicroOps = 2;
1531   let ResourceCycles = [1,1,5];
1532 }
1533 def : SchedAlias<WriteFDivXLd, SKLWriteResGroup179>; // TODO - convert to ZnWriteResFpuPair
1534
1535 def SKLWriteResGroup180 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156]> {
1536   let Latency = 17;
1537   let NumMicroOps = 15;
1538   let ResourceCycles = [2,1,2,4,2,4];
1539 }
1540 def: InstRW<[SKLWriteResGroup180], (instrs XCH_F)>;
1541
1542 def SKLWriteResGroup184 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort06,SKLPort0156]> {
1543   let Latency = 18;
1544   let NumMicroOps = 8;
1545   let ResourceCycles = [1,1,1,5];
1546 }
1547 def: InstRW<[SKLWriteResGroup184], (instrs CPUID, RDTSC)>;
1548
1549 def SKLWriteResGroup185 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {
1550   let Latency = 18;
1551   let NumMicroOps = 11;
1552   let ResourceCycles = [2,1,1,4,1,2];
1553 }
1554 def: InstRW<[SKLWriteResGroup185], (instregex "RCR(8|16|32|64)mCL")>;
1555
1556 def SKLWriteResGroup186 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> {
1557   let Latency = 19;
1558   let NumMicroOps = 2;
1559   let ResourceCycles = [1,1,4];
1560 }
1561 def : SchedAlias<WriteFDiv64Ld,  SKLWriteResGroup186>; // TODO - convert to ZnWriteResFpuPair
1562
1563 def SKLWriteResGroup189 : SchedWriteRes<[SKLPort0]> {
1564   let Latency = 20;
1565   let NumMicroOps = 1;
1566   let ResourceCycles = [1];
1567 }
1568 def: InstRW<[SKLWriteResGroup189], (instregex "DIV_(FPrST0|FST0r|FrST0)")>;
1569
1570 def SKLWriteResGroup190 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> {
1571   let Latency = 20;
1572   let NumMicroOps = 2;
1573   let ResourceCycles = [1,1,4];
1574 }
1575 def : SchedAlias<WriteFDiv64XLd, SKLWriteResGroup190>; // TODO - convert to ZnWriteResFpuPair
1576
1577 def SKLWriteResGroup192 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1578   let Latency = 20;
1579   let NumMicroOps = 8;
1580   let ResourceCycles = [1,1,1,1,1,1,2];
1581 }
1582 def: InstRW<[SKLWriteResGroup192], (instrs INSB, INSL, INSW)>;
1583
1584 def SKLWriteResGroup193 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort0156]> {
1585   let Latency = 20;
1586   let NumMicroOps = 10;
1587   let ResourceCycles = [1,2,7];
1588 }
1589 def: InstRW<[SKLWriteResGroup193], (instrs MWAITrr)>;
1590
1591 def SKLWriteResGroup195 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> {
1592   let Latency = 21;
1593   let NumMicroOps = 2;
1594   let ResourceCycles = [1,1,8];
1595 }
1596 def : SchedAlias<WriteFDiv64YLd, SKLWriteResGroup195>; // TODO - convert to ZnWriteResFpuPair
1597
1598 def SKLWriteResGroup196 : SchedWriteRes<[SKLPort0,SKLPort23]> {
1599   let Latency = 22;
1600   let NumMicroOps = 2;
1601   let ResourceCycles = [1,1];
1602 }
1603 def: InstRW<[SKLWriteResGroup196], (instregex "DIV_F(32|64)m")>;
1604
1605 def SKLWriteResGroupVEX2 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> {
1606   let Latency = 18;
1607   let NumMicroOps = 5; // 2 uops perform multiple loads
1608   let ResourceCycles = [1,2,1,1];
1609 }
1610 def: InstRW<[SKLWriteResGroupVEX2], (instrs VGATHERDPDrm, VPGATHERDQrm,
1611                                             VGATHERQPDrm, VPGATHERQQrm,
1612                                             VGATHERQPSrm, VPGATHERQDrm)>;
1613
1614 def SKLWriteResGroupVEX4 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> {
1615   let Latency = 20;
1616   let NumMicroOps = 5; // 2 uops peform multiple loads
1617   let ResourceCycles = [1,4,1,1];
1618 }
1619 def: InstRW<[SKLWriteResGroupVEX4], (instrs VGATHERDPDYrm, VPGATHERDQYrm,
1620                                             VGATHERDPSrm,  VPGATHERDDrm,
1621                                             VGATHERQPDYrm, VPGATHERQQYrm,
1622                                             VGATHERQPSYrm,  VPGATHERQDYrm)>;
1623
1624 def SKLWriteResGroupVEX8 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> {
1625   let Latency = 22;
1626   let NumMicroOps = 5; // 2 uops perform multiple loads
1627   let ResourceCycles = [1,8,1,1];
1628 }
1629 def: InstRW<[SKLWriteResGroupVEX8], (instrs VGATHERDPSYrm,  VPGATHERDDYrm)>;
1630
1631 def SKLWriteResGroup198 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort5,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1632   let Latency = 23;
1633   let NumMicroOps = 19;
1634   let ResourceCycles = [2,1,4,1,1,4,6];
1635 }
1636 def: InstRW<[SKLWriteResGroup198], (instrs CMPXCHG16B)>;
1637
1638 def SKLWriteResGroup202 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1639   let Latency = 25;
1640   let NumMicroOps = 3;
1641   let ResourceCycles = [1,1,1];
1642 }
1643 def: InstRW<[SKLWriteResGroup202], (instregex "DIV_FI(16|32)m")>;
1644
1645 def SKLWriteResGroup206 : SchedWriteRes<[SKLPort0,SKLPort23]> {
1646   let Latency = 27;
1647   let NumMicroOps = 2;
1648   let ResourceCycles = [1,1];
1649 }
1650 def: InstRW<[SKLWriteResGroup206], (instregex "DIVR_F(32|64)m")>;
1651
1652 def SKLWriteResGroup208 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1653   let Latency = 30;
1654   let NumMicroOps = 3;
1655   let ResourceCycles = [1,1,1];
1656 }
1657 def: InstRW<[SKLWriteResGroup208], (instregex "DIVR_FI(16|32)m")>;
1658
1659 def SKLWriteResGroup209 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort06,SKLPort0156]> {
1660   let Latency = 35;
1661   let NumMicroOps = 23;
1662   let ResourceCycles = [1,5,3,4,10];
1663 }
1664 def: InstRW<[SKLWriteResGroup209], (instregex "IN(8|16|32)ri",
1665                                               "IN(8|16|32)rr")>;
1666
1667 def SKLWriteResGroup210 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1668   let Latency = 35;
1669   let NumMicroOps = 23;
1670   let ResourceCycles = [1,5,2,1,4,10];
1671 }
1672 def: InstRW<[SKLWriteResGroup210], (instregex "OUT(8|16|32)ir",
1673                                               "OUT(8|16|32)rr")>;
1674
1675 def SKLWriteResGroup211 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> {
1676   let Latency = 37;
1677   let NumMicroOps = 31;
1678   let ResourceCycles = [1,8,1,21];
1679 }
1680 def: InstRW<[SKLWriteResGroup211], (instregex "XRSTOR(64)?")>;
1681
1682 def SKLWriteResGroup212 : SchedWriteRes<[SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort15,SKLPort0156]> {
1683   let Latency = 40;
1684   let NumMicroOps = 18;
1685   let ResourceCycles = [1,1,2,3,1,1,1,8];
1686 }
1687 def: InstRW<[SKLWriteResGroup212], (instrs VMCLEARm)>;
1688
1689 def SKLWriteResGroup213 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
1690   let Latency = 41;
1691   let NumMicroOps = 39;
1692   let ResourceCycles = [1,10,1,1,26];
1693 }
1694 def: InstRW<[SKLWriteResGroup213], (instrs XSAVE64)>;
1695
1696 def SKLWriteResGroup214 : SchedWriteRes<[SKLPort5,SKLPort0156]> {
1697   let Latency = 42;
1698   let NumMicroOps = 22;
1699   let ResourceCycles = [2,20];
1700 }
1701 def: InstRW<[SKLWriteResGroup214], (instrs RDTSCP)>;
1702
1703 def SKLWriteResGroup215 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
1704   let Latency = 42;
1705   let NumMicroOps = 40;
1706   let ResourceCycles = [1,11,1,1,26];
1707 }
1708 def: InstRW<[SKLWriteResGroup215], (instrs XSAVE)>;
1709 def: InstRW<[SKLWriteResGroup215], (instregex "XSAVEC", "XSAVES")>;
1710
1711 def SKLWriteResGroup216 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
1712   let Latency = 46;
1713   let NumMicroOps = 44;
1714   let ResourceCycles = [1,11,1,1,30];
1715 }
1716 def: InstRW<[SKLWriteResGroup216], (instregex "XSAVEOPT")>;
1717
1718 def SKLWriteResGroup217 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05,SKLPort06,SKLPort0156]> {
1719   let Latency = 62;
1720   let NumMicroOps = 64;
1721   let ResourceCycles = [2,8,5,10,39];
1722 }
1723 def: InstRW<[SKLWriteResGroup217], (instrs FLDENVm)>;
1724
1725 def SKLWriteResGroup218 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> {
1726   let Latency = 63;
1727   let NumMicroOps = 88;
1728   let ResourceCycles = [4,4,31,1,2,1,45];
1729 }
1730 def: InstRW<[SKLWriteResGroup218], (instrs FXRSTOR64)>;
1731
1732 def SKLWriteResGroup219 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> {
1733   let Latency = 63;
1734   let NumMicroOps = 90;
1735   let ResourceCycles = [4,2,33,1,2,1,47];
1736 }
1737 def: InstRW<[SKLWriteResGroup219], (instrs FXRSTOR)>;
1738
1739 def SKLWriteResGroup220 : SchedWriteRes<[SKLPort5,SKLPort05,SKLPort0156]> {
1740   let Latency = 75;
1741   let NumMicroOps = 15;
1742   let ResourceCycles = [6,3,6];
1743 }
1744 def: InstRW<[SKLWriteResGroup220], (instrs FNINIT)>;
1745
1746 def SKLWriteResGroup223 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort237,SKLPort06,SKLPort0156]> {
1747   let Latency = 106;
1748   let NumMicroOps = 100;
1749   let ResourceCycles = [9,1,11,16,1,11,21,30];
1750 }
1751 def: InstRW<[SKLWriteResGroup223], (instrs FSTENVm)>;
1752
1753 def: InstRW<[WriteZero], (instrs CLC)>;
1754
1755
1756 // Instruction variants handled by the renamer. These might not need execution
1757 // ports in certain conditions.
1758 // See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs",
1759 // section "Skylake Pipeline" > "Register allocation and renaming".
1760 // These can be investigated with llvm-exegesis, e.g.
1761 // echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
1762 // echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
1763
1764 def SKLWriteZeroLatency : SchedWriteRes<[]> {
1765   let Latency = 0;
1766 }
1767
1768 def SKLWriteZeroIdiom : SchedWriteVariant<[
1769     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,
1770     SchedVar<NoSchedPred,                          [WriteALU]>
1771 ]>;
1772 def : InstRW<[SKLWriteZeroIdiom], (instrs SUB32rr, SUB64rr,
1773                                           XOR32rr, XOR64rr)>;
1774
1775 def SKLWriteFZeroIdiom : SchedWriteVariant<[
1776     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,
1777     SchedVar<NoSchedPred,                          [WriteFLogic]>
1778 ]>;
1779 def : InstRW<[SKLWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, XORPDrr,
1780                                            VXORPDrr)>;
1781
1782 def SKLWriteFZeroIdiomY : SchedWriteVariant<[
1783     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,
1784     SchedVar<NoSchedPred,                          [WriteFLogicY]>
1785 ]>;
1786 def : InstRW<[SKLWriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr)>;
1787
1788 def SKLWriteVZeroIdiomLogicX : SchedWriteVariant<[
1789     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,
1790     SchedVar<NoSchedPred,                          [WriteVecLogicX]>
1791 ]>;
1792 def : InstRW<[SKLWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr)>;
1793
1794 def SKLWriteVZeroIdiomLogicY : SchedWriteVariant<[
1795     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,
1796     SchedVar<NoSchedPred,                          [WriteVecLogicY]>
1797 ]>;
1798 def : InstRW<[SKLWriteVZeroIdiomLogicY], (instrs VPXORYrr)>;
1799
1800 def SKLWriteVZeroIdiomALUX : SchedWriteVariant<[
1801     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,
1802     SchedVar<NoSchedPred,                          [WriteVecALUX]>
1803 ]>;
1804 def : InstRW<[SKLWriteVZeroIdiomALUX], (instrs PCMPGTBrr, VPCMPGTBrr,
1805                                                PCMPGTDrr, VPCMPGTDrr,
1806                                                PCMPGTWrr, VPCMPGTWrr)>;
1807
1808 def SKLWriteVZeroIdiomALUY : SchedWriteVariant<[
1809     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,
1810     SchedVar<NoSchedPred,                          [WriteVecALUY]>
1811 ]>;
1812 def : InstRW<[SKLWriteVZeroIdiomALUY], (instrs VPCMPGTBYrr,
1813                                                VPCMPGTDYrr,
1814                                                VPCMPGTWYrr)>;
1815
1816 def SKLWritePSUB : SchedWriteRes<[SKLPort015]> {
1817   let Latency = 1;
1818   let NumMicroOps = 1;
1819   let ResourceCycles = [1];
1820 }
1821
1822 def SKLWriteVZeroIdiomPSUB : SchedWriteVariant<[
1823     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,
1824     SchedVar<NoSchedPred,                          [SKLWritePSUB]>
1825 ]>;
1826 def : InstRW<[SKLWriteVZeroIdiomPSUB], (instrs PSUBBrr, VPSUBBrr,
1827                                                PSUBDrr, VPSUBDrr,
1828                                                PSUBQrr, VPSUBQrr,
1829                                                PSUBWrr, VPSUBWrr,
1830                                                VPSUBBYrr,
1831                                                VPSUBDYrr,
1832                                                VPSUBQYrr,
1833                                                VPSUBWYrr)>;
1834
1835 def SKLWritePCMPGTQ : SchedWriteRes<[SKLPort5]> {
1836   let Latency = 3;
1837   let NumMicroOps = 1;
1838   let ResourceCycles = [1];
1839 }
1840
1841 def SKLWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[
1842     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,
1843     SchedVar<NoSchedPred,                          [SKLWritePCMPGTQ]>
1844 ]>;
1845 def : InstRW<[SKLWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr,
1846                                                   VPCMPGTQYrr)>;
1847
1848
1849 // CMOVs that use both Z and C flag require an extra uop.
1850 def SKLWriteCMOVA_CMOVBErr : SchedWriteRes<[SKLPort06]> {
1851   let Latency = 2;
1852   let ResourceCycles = [2];
1853   let NumMicroOps = 2;
1854 }
1855
1856 def SKLWriteCMOVA_CMOVBErm : SchedWriteRes<[SKLPort23,SKLPort06]> {
1857   let Latency = 7;
1858   let ResourceCycles = [1,2];
1859   let NumMicroOps = 3;
1860 }
1861
1862 def SKLCMOVA_CMOVBErr :  SchedWriteVariant<[
1863   SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [SKLWriteCMOVA_CMOVBErr]>,
1864   SchedVar<NoSchedPred,                             [WriteCMOV]>
1865 ]>;
1866
1867 def SKLCMOVA_CMOVBErm :  SchedWriteVariant<[
1868   SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [SKLWriteCMOVA_CMOVBErm]>,
1869   SchedVar<NoSchedPred,                             [WriteCMOV.Folded]>
1870 ]>;
1871
1872 def : InstRW<[SKLCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>;
1873 def : InstRW<[SKLCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>;
1874
1875 // SETCCs that use both Z and C flag require an extra uop.
1876 def SKLWriteSETA_SETBEr : SchedWriteRes<[SKLPort06]> {
1877   let Latency = 2;
1878   let ResourceCycles = [2];
1879   let NumMicroOps = 2;
1880 }
1881
1882 def SKLWriteSETA_SETBEm : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06]> {
1883   let Latency = 3;
1884   let ResourceCycles = [1,1,2];
1885   let NumMicroOps = 4;
1886 }
1887
1888 def SKLSETA_SETBErr :  SchedWriteVariant<[
1889   SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [SKLWriteSETA_SETBEr]>,
1890   SchedVar<NoSchedPred,                         [WriteSETCC]>
1891 ]>;
1892
1893 def SKLSETA_SETBErm :  SchedWriteVariant<[
1894   SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [SKLWriteSETA_SETBEm]>,
1895   SchedVar<NoSchedPred,                         [WriteSETCCStore]>
1896 ]>;
1897
1898 def : InstRW<[SKLSETA_SETBErr], (instrs SETCCr)>;
1899 def : InstRW<[SKLSETA_SETBErm], (instrs SETCCm)>;
1900
1901 } // SchedModel