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1 //=- X86SchedSkylake.td - X86 Skylake Server Scheduling ------*- tablegen -*-=//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the machine model for Skylake Server to support
10 // instruction scheduling and other instruction cost heuristics.
11 //
12 //===----------------------------------------------------------------------===//
14 def SkylakeServerModel : SchedMachineModel {
15 // All x86 instructions are modeled as a single micro-op, and SKylake can
16 // decode 6 instructions per cycle.
17 let IssueWidth = 6;
18 let MicroOpBufferSize = 224; // Based on the reorder buffer.
19 let LoadLatency = 5;
20 let MispredictPenalty = 14;
22 // Based on the LSD (loop-stream detector) queue size and benchmarking data.
23 let LoopMicroOpBufferSize = 50;
25 // This flag is set to allow the scheduler to assign a default model to
26 // unrecognized opcodes.
27 let CompleteModel = 0;
28 }
30 let SchedModel = SkylakeServerModel in {
32 // Skylake Server can issue micro-ops to 8 different ports in one cycle.
34 // Ports 0, 1, 5, and 6 handle all computation.
35 // Port 4 gets the data half of stores. Store data can be available later than
36 // the store address, but since we don't model the latency of stores, we can
37 // ignore that.
38 // Ports 2 and 3 are identical. They handle loads and the address half of
39 // stores. Port 7 can handle address calculations.
40 def SKXPort0 : ProcResource<1>;
41 def SKXPort1 : ProcResource<1>;
42 def SKXPort2 : ProcResource<1>;
43 def SKXPort3 : ProcResource<1>;
44 def SKXPort4 : ProcResource<1>;
45 def SKXPort5 : ProcResource<1>;
46 def SKXPort6 : ProcResource<1>;
47 def SKXPort7 : ProcResource<1>;
49 // Many micro-ops are capable of issuing on multiple ports.
50 def SKXPort01 : ProcResGroup<[SKXPort0, SKXPort1]>;
51 def SKXPort23 : ProcResGroup<[SKXPort2, SKXPort3]>;
52 def SKXPort237 : ProcResGroup<[SKXPort2, SKXPort3, SKXPort7]>;
53 def SKXPort04 : ProcResGroup<[SKXPort0, SKXPort4]>;
54 def SKXPort05 : ProcResGroup<[SKXPort0, SKXPort5]>;
55 def SKXPort06 : ProcResGroup<[SKXPort0, SKXPort6]>;
56 def SKXPort15 : ProcResGroup<[SKXPort1, SKXPort5]>;
57 def SKXPort16 : ProcResGroup<[SKXPort1, SKXPort6]>;
58 def SKXPort56 : ProcResGroup<[SKXPort5, SKXPort6]>;
59 def SKXPort015 : ProcResGroup<[SKXPort0, SKXPort1, SKXPort5]>;
60 def SKXPort056 : ProcResGroup<[SKXPort0, SKXPort5, SKXPort6]>;
61 def SKXPort0156: ProcResGroup<[SKXPort0, SKXPort1, SKXPort5, SKXPort6]>;
63 def SKXDivider : ProcResource<1>; // Integer division issued on port 0.
64 // FP division and sqrt on port 0.
65 def SKXFPDivider : ProcResource<1>;
67 // 60 Entry Unified Scheduler
68 def SKXPortAny : ProcResGroup<[SKXPort0, SKXPort1, SKXPort2, SKXPort3, SKXPort4,
69 SKXPort5, SKXPort6, SKXPort7]> {
70 let BufferSize=60;
71 }
73 // Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 5
74 // cycles after the memory operand.
75 def : ReadAdvance<ReadAfterLd, 5>;
77 // Vector loads are 5/6/7 cycles, so ReadAfterVec*Ld registers needn't be available
78 // until 5/6/7 cycles after the memory operand.
79 def : ReadAdvance<ReadAfterVecLd, 5>;
80 def : ReadAdvance<ReadAfterVecXLd, 6>;
81 def : ReadAdvance<ReadAfterVecYLd, 7>;
83 def : ReadAdvance<ReadInt2Fpu, 0>;
85 // Many SchedWrites are defined in pairs with and without a folded load.
86 // Instructions with folded loads are usually micro-fused, so they only appear
87 // as two micro-ops when queued in the reservation station.
88 // This multiclass defines the resource usage for variants with and without
89 // folded loads.
90 multiclass SKXWriteResPair<X86FoldableSchedWrite SchedRW,
91 list<ProcResourceKind> ExePorts,
92 int Lat, list<int> Res = [1], int UOps = 1,
93 int LoadLat = 5> {
94 // Register variant is using a single cycle on ExePort.
95 def : WriteRes<SchedRW, ExePorts> {
96 let Latency = Lat;
97 let ResourceCycles = Res;
98 let NumMicroOps = UOps;
99 }
101 // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to
102 // the latency (default = 5).
103 def : WriteRes<SchedRW.Folded, !listconcat([SKXPort23], ExePorts)> {
104 let Latency = !add(Lat, LoadLat);
105 let ResourceCycles = !listconcat([1], Res);
106 let NumMicroOps = !add(UOps, 1);
107 }
108 }
110 // A folded store needs a cycle on port 4 for the store data, and an extra port
111 // 2/3/7 cycle to recompute the address.
112 def : WriteRes<WriteRMW, [SKXPort237,SKXPort4]>;
114 // Arithmetic.
115 defm : SKXWriteResPair<WriteALU, [SKXPort0156], 1>; // Simple integer ALU op.
116 defm : SKXWriteResPair<WriteADC, [SKXPort06], 1>; // Integer ALU + flags op.
118 // Integer multiplication.
119 defm : SKXWriteResPair<WriteIMul8, [SKXPort1], 3>;
120 defm : SKXWriteResPair<WriteIMul16, [SKXPort1,SKXPort06,SKXPort0156], 4, [1,1,2], 4>;
121 defm : X86WriteRes<WriteIMul16Imm, [SKXPort1,SKXPort0156], 4, [1,1], 2>;
122 defm : X86WriteRes<WriteIMul16ImmLd, [SKXPort1,SKXPort0156,SKXPort23], 8, [1,1,1], 3>;
123 defm : X86WriteRes<WriteIMul16Reg, [SKXPort1], 3, [1], 1>;
124 defm : X86WriteRes<WriteIMul16RegLd, [SKXPort1,SKXPort0156,SKXPort23], 8, [1,1,1], 3>;
125 defm : SKXWriteResPair<WriteIMul32, [SKXPort1,SKXPort06,SKXPort0156], 4, [1,1,1], 3>;
126 defm : SKXWriteResPair<WriteMULX32, [SKXPort1,SKXPort06,SKXPort0156], 4, [1,1,1], 3>;
127 defm : SKXWriteResPair<WriteIMul32Imm, [SKXPort1], 3>;
128 defm : SKXWriteResPair<WriteIMul32Reg, [SKXPort1], 3>;
129 defm : SKXWriteResPair<WriteIMul64, [SKXPort1,SKXPort5], 4, [1,1], 2>;
130 defm : SKXWriteResPair<WriteMULX64, [SKXPort1,SKXPort5], 4, [1,1], 2>;
131 defm : SKXWriteResPair<WriteIMul64Imm, [SKXPort1], 3>;
132 defm : SKXWriteResPair<WriteIMul64Reg, [SKXPort1], 3>;
133 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
135 defm : X86WriteRes<WriteBSWAP32, [SKXPort15], 1, [1], 1>;
136 defm : X86WriteRes<WriteBSWAP64, [SKXPort06, SKXPort15], 2, [1,1], 2>;
137 defm : X86WriteRes<WriteCMPXCHG,[SKXPort06, SKXPort0156], 5, [2,3], 5>;
138 defm : X86WriteRes<WriteCMPXCHGRMW,[SKXPort23,SKXPort06,SKXPort0156,SKXPort237,SKXPort4], 8, [1,2,1,1,1], 6>;
139 defm : X86WriteRes<WriteXCHG, [SKXPort0156], 2, [3], 3>;
141 // TODO: Why isn't the SKXDivider used?
142 defm : SKXWriteResPair<WriteDiv8, [SKXPort0, SKXDivider], 25, [1,10], 1, 4>;
143 defm : X86WriteRes<WriteDiv16, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156], 76, [7,2,8,3,1,11], 32>;
144 defm : X86WriteRes<WriteDiv32, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156], 76, [7,2,8,3,1,11], 32>;
145 defm : X86WriteRes<WriteDiv64, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156], 76, [7,2,8,3,1,11], 32>;
146 defm : X86WriteRes<WriteDiv16Ld, [SKXPort0,SKXPort23,SKXDivider], 29, [1,1,10], 2>;
147 defm : X86WriteRes<WriteDiv32Ld, [SKXPort0,SKXPort23,SKXDivider], 29, [1,1,10], 2>;
148 defm : X86WriteRes<WriteDiv64Ld, [SKXPort0,SKXPort23,SKXDivider], 29, [1,1,10], 2>;
150 defm : X86WriteRes<WriteIDiv8, [SKXPort0, SKXDivider], 25, [1,10], 1>;
151 defm : X86WriteRes<WriteIDiv16, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort06,SKXPort0156], 102, [4,2,4,8,14,34], 66>;
152 defm : X86WriteRes<WriteIDiv32, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort06,SKXPort0156], 102, [4,2,4,8,14,34], 66>;
153 defm : X86WriteRes<WriteIDiv64, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort06,SKXPort0156], 102, [4,2,4,8,14,34], 66>;
154 defm : X86WriteRes<WriteIDiv8Ld, [SKXPort0,SKXPort5,SKXPort23,SKXPort0156], 28, [2,4,1,1], 8>;
155 defm : X86WriteRes<WriteIDiv16Ld, [SKXPort0,SKXPort5,SKXPort23,SKXPort0156], 28, [2,4,1,1], 8>;
156 defm : X86WriteRes<WriteIDiv32Ld, [SKXPort0,SKXPort5,SKXPort23,SKXPort0156], 28, [2,4,1,1], 8>;
157 defm : X86WriteRes<WriteIDiv64Ld, [SKXPort0,SKXPort5,SKXPort23,SKXPort0156], 28, [2,4,1,1], 8>;
159 defm : SKXWriteResPair<WriteCRC32, [SKXPort1], 3>;
161 def : WriteRes<WriteLEA, [SKXPort15]>; // LEA instructions can't fold loads.
163 defm : SKXWriteResPair<WriteCMOV, [SKXPort06], 1, [1], 1>; // Conditional move.
164 defm : X86WriteRes<WriteFCMOV, [SKXPort1], 3, [1], 1>; // x87 conditional move.
165 def : WriteRes<WriteSETCC, [SKXPort06]>; // Setcc.
166 def : WriteRes<WriteSETCCStore, [SKXPort06,SKXPort4,SKXPort237]> {
167 let Latency = 2;
168 let NumMicroOps = 3;
169 }
170 defm : X86WriteRes<WriteLAHFSAHF, [SKXPort06], 1, [1], 1>;
171 defm : X86WriteRes<WriteBitTest, [SKXPort06], 1, [1], 1>;
172 defm : X86WriteRes<WriteBitTestImmLd, [SKXPort06,SKXPort23], 6, [1,1], 2>;
173 defm : X86WriteRes<WriteBitTestRegLd, [SKXPort0156,SKXPort23], 6, [1,1], 2>;
174 defm : X86WriteRes<WriteBitTestSet, [SKXPort06], 1, [1], 1>;
175 defm : X86WriteRes<WriteBitTestSetImmLd, [SKXPort06,SKXPort23], 5, [1,1], 3>;
176 defm : X86WriteRes<WriteBitTestSetRegLd, [SKXPort0156,SKXPort23], 5, [1,1], 2>;
178 // Integer shifts and rotates.
179 defm : SKXWriteResPair<WriteShift, [SKXPort06], 1>;
180 defm : SKXWriteResPair<WriteShiftCL, [SKXPort06], 3, [3], 3>;
181 defm : SKXWriteResPair<WriteRotate, [SKXPort06], 1, [1], 1>;
182 defm : SKXWriteResPair<WriteRotateCL, [SKXPort06], 3, [3], 3>;
184 // SHLD/SHRD.
185 defm : X86WriteRes<WriteSHDrri, [SKXPort1], 3, [1], 1>;
186 defm : X86WriteRes<WriteSHDrrcl,[SKXPort1,SKXPort06,SKXPort0156], 6, [1, 2, 1], 4>;
187 defm : X86WriteRes<WriteSHDmri, [SKXPort1,SKXPort23,SKXPort237,SKXPort0156], 9, [1, 1, 1, 1], 4>;
188 defm : X86WriteRes<WriteSHDmrcl,[SKXPort1,SKXPort23,SKXPort237,SKXPort06,SKXPort0156], 11, [1, 1, 1, 2, 1], 6>;
190 // Bit counts.
191 defm : SKXWriteResPair<WriteBSF, [SKXPort1], 3>;
192 defm : SKXWriteResPair<WriteBSR, [SKXPort1], 3>;
193 defm : SKXWriteResPair<WriteLZCNT, [SKXPort1], 3>;
194 defm : SKXWriteResPair<WriteTZCNT, [SKXPort1], 3>;
195 defm : SKXWriteResPair<WritePOPCNT, [SKXPort1], 3>;
197 // BMI1 BEXTR/BLS, BMI2 BZHI
198 defm : SKXWriteResPair<WriteBEXTR, [SKXPort06,SKXPort15], 2, [1,1], 2>;
199 defm : SKXWriteResPair<WriteBLS, [SKXPort15], 1>;
200 defm : SKXWriteResPair<WriteBZHI, [SKXPort15], 1>;
202 // Loads, stores, and moves, not folded with other operations.
203 defm : X86WriteRes<WriteLoad, [SKXPort23], 5, [1], 1>;
204 defm : X86WriteRes<WriteStore, [SKXPort237, SKXPort4], 1, [1,1], 1>;
205 defm : X86WriteRes<WriteStoreNT, [SKXPort237, SKXPort4], 1, [1,1], 2>;
206 defm : X86WriteRes<WriteMove, [SKXPort0156], 1, [1], 1>;
208 // Model the effect of clobbering the read-write mask operand of the GATHER operation.
209 // Does not cost anything by itself, only has latency, matching that of the WriteLoad,
210 defm : X86WriteRes<WriteVecMaskedGatherWriteback, [], 5, [], 0>;
212 // Idioms that clear a register, like xorps %xmm0, %xmm0.
213 // These can often bypass execution ports completely.
214 def : WriteRes<WriteZero, []>;
216 // Branches don't produce values, so they have no latency, but they still
217 // consume resources. Indirect branches can fold loads.
218 defm : SKXWriteResPair<WriteJump, [SKXPort06], 1>;
220 // Floating point. This covers both scalar and vector operations.
221 defm : X86WriteRes<WriteFLD0, [SKXPort05], 1, [1], 1>;
222 defm : X86WriteRes<WriteFLD1, [SKXPort05], 1, [2], 2>;
223 defm : X86WriteRes<WriteFLDC, [SKXPort05], 1, [2], 2>;
224 defm : X86WriteRes<WriteFLoad, [SKXPort23], 5, [1], 1>;
225 defm : X86WriteRes<WriteFLoadX, [SKXPort23], 6, [1], 1>;
226 defm : X86WriteRes<WriteFLoadY, [SKXPort23], 7, [1], 1>;
227 defm : X86WriteRes<WriteFMaskedLoad, [SKXPort23,SKXPort015], 7, [1,1], 2>;
228 defm : X86WriteRes<WriteFMaskedLoadY, [SKXPort23,SKXPort015], 8, [1,1], 2>;
229 defm : X86WriteRes<WriteFStore, [SKXPort237,SKXPort4], 1, [1,1], 2>;
230 defm : X86WriteRes<WriteFStoreX, [SKXPort237,SKXPort4], 1, [1,1], 2>;
231 defm : X86WriteRes<WriteFStoreY, [SKXPort237,SKXPort4], 1, [1,1], 2>;
232 defm : X86WriteRes<WriteFStoreNT, [SKXPort237,SKXPort4], 1, [1,1], 2>;
233 defm : X86WriteRes<WriteFStoreNTX, [SKXPort237,SKXPort4], 1, [1,1], 2>;
234 defm : X86WriteRes<WriteFStoreNTY, [SKXPort237,SKXPort4], 1, [1,1], 2>;
236 defm : X86WriteRes<WriteFMaskedStore32, [SKXPort237,SKXPort0], 2, [1,1], 2>;
237 defm : X86WriteRes<WriteFMaskedStore32Y, [SKXPort237,SKXPort0], 2, [1,1], 2>;
238 defm : X86WriteRes<WriteFMaskedStore64, [SKXPort237,SKXPort0], 2, [1,1], 2>;
239 defm : X86WriteRes<WriteFMaskedStore64Y, [SKXPort237,SKXPort0], 2, [1,1], 2>;
241 defm : X86WriteRes<WriteFMove, [SKXPort015], 1, [1], 1>;
242 defm : X86WriteRes<WriteFMoveX, [SKXPort015], 1, [1], 1>;
243 defm : X86WriteRes<WriteFMoveY, [SKXPort015], 1, [1], 1>;
244 defm : X86WriteRes<WriteEMMS, [SKXPort05,SKXPort0156], 10, [9,1], 10>;
246 defm : SKXWriteResPair<WriteFAdd, [SKXPort01], 4, [1], 1, 5>; // Floating point add/sub.
247 defm : SKXWriteResPair<WriteFAddX, [SKXPort01], 4, [1], 1, 6>;
248 defm : SKXWriteResPair<WriteFAddY, [SKXPort01], 4, [1], 1, 7>;
249 defm : SKXWriteResPair<WriteFAddZ, [SKXPort05], 4, [1], 1, 7>;
250 defm : SKXWriteResPair<WriteFAdd64, [SKXPort01], 4, [1], 1, 5>; // Floating point double add/sub.
251 defm : SKXWriteResPair<WriteFAdd64X, [SKXPort01], 4, [1], 1, 6>;
252 defm : SKXWriteResPair<WriteFAdd64Y, [SKXPort01], 4, [1], 1, 7>;
253 defm : SKXWriteResPair<WriteFAdd64Z, [SKXPort05], 4, [1], 1, 7>;
255 defm : SKXWriteResPair<WriteFCmp, [SKXPort01], 4, [1], 1, 5>; // Floating point compare.
256 defm : SKXWriteResPair<WriteFCmpX, [SKXPort01], 4, [1], 1, 6>;
257 defm : SKXWriteResPair<WriteFCmpY, [SKXPort01], 4, [1], 1, 7>;
258 defm : SKXWriteResPair<WriteFCmpZ, [SKXPort05], 4, [1], 1, 7>;
259 defm : SKXWriteResPair<WriteFCmp64, [SKXPort01], 4, [1], 1, 5>; // Floating point double compare.
260 defm : SKXWriteResPair<WriteFCmp64X, [SKXPort01], 4, [1], 1, 6>;
261 defm : SKXWriteResPair<WriteFCmp64Y, [SKXPort01], 4, [1], 1, 7>;
262 defm : SKXWriteResPair<WriteFCmp64Z, [SKXPort05], 4, [1], 1, 7>;
264 defm : SKXWriteResPair<WriteFCom, [SKXPort0], 2>; // Floating point compare to flags (X87).
265 defm : SKXWriteResPair<WriteFComX, [SKXPort0], 2>; // Floating point compare to flags (SSE).
267 defm : SKXWriteResPair<WriteFMul, [SKXPort01], 4, [1], 1, 5>; // Floating point multiplication.
268 defm : SKXWriteResPair<WriteFMulX, [SKXPort01], 4, [1], 1, 6>;
269 defm : SKXWriteResPair<WriteFMulY, [SKXPort01], 4, [1], 1, 7>;
270 defm : SKXWriteResPair<WriteFMulZ, [SKXPort05], 4, [1], 1, 7>;
271 defm : SKXWriteResPair<WriteFMul64, [SKXPort01], 4, [1], 1, 5>; // Floating point double multiplication.
272 defm : SKXWriteResPair<WriteFMul64X, [SKXPort01], 4, [1], 1, 6>;
273 defm : SKXWriteResPair<WriteFMul64Y, [SKXPort01], 4, [1], 1, 7>;
274 defm : SKXWriteResPair<WriteFMul64Z, [SKXPort05], 4, [1], 1, 7>;
276 defm : SKXWriteResPair<WriteFDiv, [SKXPort0,SKXFPDivider], 11, [1,3], 1, 5>; // 10-14 cycles. // Floating point division.
277 //defm : SKXWriteResPair<WriteFDivX, [SKXPort0,SKXFPDivider], 11, [1,3], 1, 6>; // 10-14 cycles.
278 defm : SKXWriteResPair<WriteFDivY, [SKXPort0,SKXFPDivider], 11, [1,5], 1, 7>; // 10-14 cycles.
279 defm : SKXWriteResPair<WriteFDivZ, [SKXPort0,SKXPort5,SKXFPDivider], 18, [2,1,10], 3, 7>; // 10-14 cycles.
280 //defm : SKXWriteResPair<WriteFDiv64, [SKXPort0,SKXFPDivider], 14, [1,3], 1, 5>; // 10-14 cycles. // Floating point division.
281 //defm : SKXWriteResPair<WriteFDiv64X, [SKXPort0,SKXFPDivider], 14, [1,3], 1, 6>; // 10-14 cycles.
282 //defm : SKXWriteResPair<WriteFDiv64Y, [SKXPort0,SKXFPDivider], 14, [1,5], 1, 7>; // 10-14 cycles.
283 defm : SKXWriteResPair<WriteFDiv64Z, [SKXPort0,SKXPort5,SKXFPDivider], 23, [2,1,16], 3, 7>; // 10-14 cycles.
285 defm : SKXWriteResPair<WriteFSqrt, [SKXPort0,SKXFPDivider], 12, [1,3], 1, 5>; // Floating point square root.
286 defm : SKXWriteResPair<WriteFSqrtX, [SKXPort0,SKXFPDivider], 12, [1,3], 1, 6>;
287 defm : SKXWriteResPair<WriteFSqrtY, [SKXPort0,SKXFPDivider], 12, [1,6], 1, 7>;
288 defm : SKXWriteResPair<WriteFSqrtZ, [SKXPort0,SKXPort5,SKXFPDivider], 20, [2,1,12], 3, 7>;
289 defm : SKXWriteResPair<WriteFSqrt64, [SKXPort0,SKXFPDivider], 18, [1,6], 1, 5>; // Floating point double square root.
290 defm : SKXWriteResPair<WriteFSqrt64X, [SKXPort0,SKXFPDivider], 18, [1,6], 1, 6>;
291 defm : SKXWriteResPair<WriteFSqrt64Y, [SKXPort0,SKXFPDivider], 18, [1,12],1, 7>;
292 defm : SKXWriteResPair<WriteFSqrt64Z, [SKXPort0,SKXPort5,SKXFPDivider], 32, [2,1,24], 3, 7>;
293 defm : SKXWriteResPair<WriteFSqrt80, [SKXPort0,SKXFPDivider], 21, [1,7]>; // Floating point long double square root.
295 defm : SKXWriteResPair<WriteFRcp, [SKXPort0], 4, [1], 1, 5>; // Floating point reciprocal estimate.
296 defm : SKXWriteResPair<WriteFRcpX, [SKXPort0], 4, [1], 1, 6>;
297 defm : SKXWriteResPair<WriteFRcpY, [SKXPort0], 4, [1], 1, 7>;
298 defm : SKXWriteResPair<WriteFRcpZ, [SKXPort0,SKXPort5], 4, [2,1], 3, 7>;
300 defm : SKXWriteResPair<WriteFRsqrt, [SKXPort0], 4, [1], 1, 5>; // Floating point reciprocal square root estimate.
301 defm : SKXWriteResPair<WriteFRsqrtX,[SKXPort0], 4, [1], 1, 6>;
302 defm : SKXWriteResPair<WriteFRsqrtY,[SKXPort0], 4, [1], 1, 7>;
303 defm : SKXWriteResPair<WriteFRsqrtZ,[SKXPort0,SKXPort5], 9, [2,1], 3, 7>;
305 defm : SKXWriteResPair<WriteFMA, [SKXPort01], 4, [1], 1, 5>; // Fused Multiply Add.
306 defm : SKXWriteResPair<WriteFMAX, [SKXPort01], 4, [1], 1, 6>;
307 defm : SKXWriteResPair<WriteFMAY, [SKXPort01], 4, [1], 1, 7>;
308 defm : SKXWriteResPair<WriteFMAZ, [SKXPort05], 4, [1], 1, 7>;
309 defm : SKXWriteResPair<WriteDPPD, [SKXPort5,SKXPort015], 9, [1,2], 3, 6>; // Floating point double dot product.
310 defm : SKXWriteResPair<WriteDPPS, [SKXPort5,SKXPort015], 13, [1,3], 4, 6>;
311 defm : SKXWriteResPair<WriteDPPSY,[SKXPort5,SKXPort015], 13, [1,3], 4, 7>;
312 defm : SKXWriteResPair<WriteDPPSZ,[SKXPort5,SKXPort015], 13, [1,3], 4, 7>;
313 defm : SKXWriteResPair<WriteFSign, [SKXPort0], 1>; // Floating point fabs/fchs.
314 defm : SKXWriteResPair<WriteFRnd, [SKXPort01], 8, [2], 2, 6>; // Floating point rounding.
315 defm : SKXWriteResPair<WriteFRndY, [SKXPort01], 8, [2], 2, 7>;
316 defm : SKXWriteResPair<WriteFRndZ, [SKXPort05], 8, [2], 2, 7>;
317 defm : SKXWriteResPair<WriteFLogic, [SKXPort015], 1, [1], 1, 6>; // Floating point and/or/xor logicals.
318 defm : SKXWriteResPair<WriteFLogicY, [SKXPort015], 1, [1], 1, 7>;
319 defm : SKXWriteResPair<WriteFLogicZ, [SKXPort05], 1, [1], 1, 7>;
320 defm : SKXWriteResPair<WriteFTest, [SKXPort0], 2, [1], 1, 6>; // Floating point TEST instructions.
321 defm : SKXWriteResPair<WriteFTestY, [SKXPort0], 2, [1], 1, 7>;
322 defm : SKXWriteResPair<WriteFTestZ, [SKXPort0], 2, [1], 1, 7>;
323 defm : SKXWriteResPair<WriteFShuffle, [SKXPort5], 1, [1], 1, 6>; // Floating point vector shuffles.
324 defm : SKXWriteResPair<WriteFShuffleY, [SKXPort5], 1, [1], 1, 7>;
325 defm : SKXWriteResPair<WriteFShuffleZ, [SKXPort5], 1, [1], 1, 7>;
326 defm : SKXWriteResPair<WriteFVarShuffle, [SKXPort5], 1, [1], 1, 6>; // Floating point vector variable shuffles.
327 defm : SKXWriteResPair<WriteFVarShuffleY, [SKXPort5], 1, [1], 1, 7>;
328 defm : SKXWriteResPair<WriteFVarShuffleZ, [SKXPort5], 1, [1], 1, 7>;
329 defm : SKXWriteResPair<WriteFBlend, [SKXPort015], 1, [1], 1, 6>; // Floating point vector blends.
330 defm : SKXWriteResPair<WriteFBlendY,[SKXPort015], 1, [1], 1, 7>;
331 defm : SKXWriteResPair<WriteFBlendZ,[SKXPort015], 1, [1], 1, 7>;
332 defm : SKXWriteResPair<WriteFVarBlend, [SKXPort015], 2, [2], 2, 6>; // Fp vector variable blends.
333 defm : SKXWriteResPair<WriteFVarBlendY,[SKXPort015], 2, [2], 2, 7>;
334 defm : SKXWriteResPair<WriteFVarBlendZ,[SKXPort015], 2, [2], 2, 7>;
336 // FMA Scheduling helper class.
337 // class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }
339 // Vector integer operations.
340 defm : X86WriteRes<WriteVecLoad, [SKXPort23], 5, [1], 1>;
341 defm : X86WriteRes<WriteVecLoadX, [SKXPort23], 6, [1], 1>;
342 defm : X86WriteRes<WriteVecLoadY, [SKXPort23], 7, [1], 1>;
343 defm : X86WriteRes<WriteVecLoadNT, [SKXPort23], 6, [1], 1>;
344 defm : X86WriteRes<WriteVecLoadNTY, [SKXPort23], 7, [1], 1>;
345 defm : X86WriteRes<WriteVecMaskedLoad, [SKXPort23,SKXPort015], 7, [1,1], 2>;
346 defm : X86WriteRes<WriteVecMaskedLoadY, [SKXPort23,SKXPort015], 8, [1,1], 2>;
347 defm : X86WriteRes<WriteVecStore, [SKXPort237,SKXPort4], 1, [1,1], 2>;
348 defm : X86WriteRes<WriteVecStoreX, [SKXPort237,SKXPort4], 1, [1,1], 2>;
349 defm : X86WriteRes<WriteVecStoreY, [SKXPort237,SKXPort4], 1, [1,1], 2>;
350 defm : X86WriteRes<WriteVecStoreNT, [SKXPort237,SKXPort4], 1, [1,1], 2>;
351 defm : X86WriteRes<WriteVecStoreNTY, [SKXPort237,SKXPort4], 1, [1,1], 2>;
352 defm : X86WriteRes<WriteVecMaskedStore32, [SKXPort237,SKXPort0], 2, [1,1], 2>;
353 defm : X86WriteRes<WriteVecMaskedStore32Y, [SKXPort237,SKXPort0], 2, [1,1], 2>;
354 defm : X86WriteRes<WriteVecMaskedStore64, [SKXPort237,SKXPort0], 2, [1,1], 2>;
355 defm : X86WriteRes<WriteVecMaskedStore64Y, [SKXPort237,SKXPort0], 2, [1,1], 2>;
356 defm : X86WriteRes<WriteVecMove, [SKXPort05], 1, [1], 1>;
357 defm : X86WriteRes<WriteVecMoveX, [SKXPort015], 1, [1], 1>;
358 defm : X86WriteRes<WriteVecMoveY, [SKXPort015], 1, [1], 1>;
359 defm : X86WriteRes<WriteVecMoveToGpr, [SKXPort0], 2, [1], 1>;
360 defm : X86WriteRes<WriteVecMoveFromGpr, [SKXPort5], 1, [1], 1>;
362 defm : SKXWriteResPair<WriteVecALU, [SKXPort05], 1, [1], 1, 5>; // Vector integer ALU op, no logicals.
363 defm : SKXWriteResPair<WriteVecALUX, [SKXPort01], 1, [1], 1, 6>;
364 defm : SKXWriteResPair<WriteVecALUY, [SKXPort01], 1, [1], 1, 7>;
365 defm : SKXWriteResPair<WriteVecALUZ, [SKXPort0], 1, [1], 1, 7>;
366 defm : SKXWriteResPair<WriteVecLogic, [SKXPort05], 1, [1], 1, 5>; // Vector integer and/or/xor.
367 defm : SKXWriteResPair<WriteVecLogicX,[SKXPort015], 1, [1], 1, 6>;
368 defm : SKXWriteResPair<WriteVecLogicY,[SKXPort015], 1, [1], 1, 7>;
369 defm : SKXWriteResPair<WriteVecLogicZ,[SKXPort05], 1, [1], 1, 7>;
370 defm : SKXWriteResPair<WriteVecTest, [SKXPort0,SKXPort5], 3, [1,1], 2, 6>; // Vector integer TEST instructions.
371 defm : SKXWriteResPair<WriteVecTestY, [SKXPort0,SKXPort5], 3, [1,1], 2, 7>;
372 defm : SKXWriteResPair<WriteVecTestZ, [SKXPort0,SKXPort5], 3, [1,1], 2, 7>;
373 defm : SKXWriteResPair<WriteVecIMul, [SKXPort0], 5, [1], 1, 5>; // Vector integer multiply.
374 defm : SKXWriteResPair<WriteVecIMulX, [SKXPort01], 5, [1], 1, 6>;
375 defm : SKXWriteResPair<WriteVecIMulY, [SKXPort01], 5, [1], 1, 7>;
376 defm : SKXWriteResPair<WriteVecIMulZ, [SKXPort05], 5, [1], 1, 7>;
377 defm : SKXWriteResPair<WritePMULLD, [SKXPort01], 10, [2], 2, 6>; // Vector PMULLD.
378 defm : SKXWriteResPair<WritePMULLDY, [SKXPort01], 10, [2], 2, 7>;
379 defm : SKXWriteResPair<WritePMULLDZ, [SKXPort05], 10, [2], 2, 7>;
380 defm : SKXWriteResPair<WriteShuffle, [SKXPort5], 1, [1], 1, 5>; // Vector shuffles.
381 defm : SKXWriteResPair<WriteShuffleX, [SKXPort5], 1, [1], 1, 6>;
382 defm : SKXWriteResPair<WriteShuffleY, [SKXPort5], 1, [1], 1, 7>;
383 defm : SKXWriteResPair<WriteShuffleZ, [SKXPort5], 1, [1], 1, 7>;
384 defm : SKXWriteResPair<WriteVarShuffle, [SKXPort5], 1, [1], 1, 5>; // Vector variable shuffles.
385 defm : SKXWriteResPair<WriteVarShuffleX, [SKXPort5], 1, [1], 1, 6>;
386 defm : SKXWriteResPair<WriteVarShuffleY, [SKXPort5], 1, [1], 1, 7>;
387 defm : SKXWriteResPair<WriteVarShuffleZ, [SKXPort5], 1, [1], 1, 7>;
388 defm : SKXWriteResPair<WriteBlend, [SKXPort5], 1, [1], 1, 6>; // Vector blends.
389 defm : SKXWriteResPair<WriteBlendY,[SKXPort5], 1, [1], 1, 7>;
390 defm : SKXWriteResPair<WriteBlendZ,[SKXPort5], 1, [1], 1, 7>;
391 defm : SKXWriteResPair<WriteVarBlend, [SKXPort015], 2, [2], 2, 6>; // Vector variable blends.
392 defm : SKXWriteResPair<WriteVarBlendY,[SKXPort015], 2, [2], 2, 6>;
393 defm : SKXWriteResPair<WriteVarBlendZ,[SKXPort05], 2, [1], 1, 6>;
394 defm : SKXWriteResPair<WriteMPSAD, [SKXPort5], 4, [2], 2, 6>; // Vector MPSAD.
395 defm : SKXWriteResPair<WriteMPSADY, [SKXPort5], 4, [2], 2, 7>;
396 defm : SKXWriteResPair<WriteMPSADZ, [SKXPort5], 4, [2], 2, 7>;
397 defm : SKXWriteResPair<WritePSADBW, [SKXPort5], 3, [1], 1, 5>; // Vector PSADBW.
398 defm : SKXWriteResPair<WritePSADBWX, [SKXPort5], 3, [1], 1, 6>;
399 defm : SKXWriteResPair<WritePSADBWY, [SKXPort5], 3, [1], 1, 7>;
400 defm : SKXWriteResPair<WritePSADBWZ, [SKXPort5], 3, [1], 1, 7>;
401 defm : SKXWriteResPair<WritePHMINPOS, [SKXPort0], 4, [1], 1, 6>; // Vector PHMINPOS.
403 // Vector integer shifts.
404 defm : SKXWriteResPair<WriteVecShift, [SKXPort0], 1, [1], 1, 5>;
405 defm : X86WriteRes<WriteVecShiftX, [SKXPort5,SKXPort01], 2, [1,1], 2>;
406 defm : X86WriteRes<WriteVecShiftY, [SKXPort5,SKXPort01], 4, [1,1], 2>;
407 defm : X86WriteRes<WriteVecShiftZ, [SKXPort5,SKXPort0], 4, [1,1], 2>;
408 defm : X86WriteRes<WriteVecShiftXLd, [SKXPort01,SKXPort23], 7, [1,1], 2>;
409 defm : X86WriteRes<WriteVecShiftYLd, [SKXPort01,SKXPort23], 8, [1,1], 2>;
410 defm : X86WriteRes<WriteVecShiftZLd, [SKXPort0,SKXPort23], 8, [1,1], 2>;
412 defm : SKXWriteResPair<WriteVecShiftImm, [SKXPort0], 1, [1], 1, 5>;
413 defm : SKXWriteResPair<WriteVecShiftImmX, [SKXPort01], 1, [1], 1, 6>; // Vector integer immediate shifts.
414 defm : SKXWriteResPair<WriteVecShiftImmY, [SKXPort01], 1, [1], 1, 7>;
415 defm : SKXWriteResPair<WriteVecShiftImmZ, [SKXPort0], 1, [1], 1, 7>;
416 defm : SKXWriteResPair<WriteVarVecShift, [SKXPort01], 1, [1], 1, 6>; // Variable vector shifts.
417 defm : SKXWriteResPair<WriteVarVecShiftY, [SKXPort01], 1, [1], 1, 7>;
418 defm : SKXWriteResPair<WriteVarVecShiftZ, [SKXPort0], 1, [1], 1, 7>;
420 // Vector insert/extract operations.
421 def : WriteRes<WriteVecInsert, [SKXPort5]> {
422 let Latency = 2;
423 let NumMicroOps = 2;
424 let ResourceCycles = [2];
425 }
426 def : WriteRes<WriteVecInsertLd, [SKXPort5,SKXPort23]> {
427 let Latency = 6;
428 let NumMicroOps = 2;
429 }
430 def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>;
432 def : WriteRes<WriteVecExtract, [SKXPort0,SKXPort5]> {
433 let Latency = 3;
434 let NumMicroOps = 2;
435 }
436 def : WriteRes<WriteVecExtractSt, [SKXPort4,SKXPort5,SKXPort237]> {
437 let Latency = 2;
438 let NumMicroOps = 3;
439 }
441 // Conversion between integer and float.
442 defm : SKXWriteResPair<WriteCvtSS2I, [SKXPort01], 6, [2], 2>; // Needs more work: DD vs DQ.
443 defm : SKXWriteResPair<WriteCvtPS2I, [SKXPort01], 3>;
444 defm : SKXWriteResPair<WriteCvtPS2IY, [SKXPort01], 3>;
445 defm : SKXWriteResPair<WriteCvtPS2IZ, [SKXPort05], 3>;
446 defm : SKXWriteResPair<WriteCvtSD2I, [SKXPort01], 6, [2], 2>;
447 defm : SKXWriteResPair<WriteCvtPD2I, [SKXPort01], 3>;
448 defm : SKXWriteResPair<WriteCvtPD2IY, [SKXPort01], 3>;
449 defm : SKXWriteResPair<WriteCvtPD2IZ, [SKXPort05], 3>;
451 defm : SKXWriteResPair<WriteCvtI2SS, [SKXPort1], 4>;
452 defm : SKXWriteResPair<WriteCvtI2PS, [SKXPort01], 4>;
453 defm : SKXWriteResPair<WriteCvtI2PSY, [SKXPort01], 4>;
454 defm : SKXWriteResPair<WriteCvtI2PSZ, [SKXPort05], 4>; // Needs more work: DD vs DQ.
455 defm : SKXWriteResPair<WriteCvtI2SD, [SKXPort1], 4>;
456 defm : SKXWriteResPair<WriteCvtI2PD, [SKXPort01], 4>;
457 defm : SKXWriteResPair<WriteCvtI2PDY, [SKXPort01], 4>;
458 defm : SKXWriteResPair<WriteCvtI2PDZ, [SKXPort05], 4>;
460 defm : SKXWriteResPair<WriteCvtSS2SD, [SKXPort1], 3>;
461 defm : SKXWriteResPair<WriteCvtPS2PD, [SKXPort1], 3>;
462 defm : SKXWriteResPair<WriteCvtPS2PDY, [SKXPort5,SKXPort01], 3, [1,1], 2>;
463 defm : SKXWriteResPair<WriteCvtPS2PDZ, [SKXPort05], 3, [2], 2>;
464 defm : SKXWriteResPair<WriteCvtSD2SS, [SKXPort1], 3>;
465 defm : SKXWriteResPair<WriteCvtPD2PS, [SKXPort1], 3>;
466 defm : SKXWriteResPair<WriteCvtPD2PSY, [SKXPort5,SKXPort01], 3, [1,1], 2>;
467 defm : SKXWriteResPair<WriteCvtPD2PSZ, [SKXPort05], 3, [2], 2>;
469 defm : X86WriteRes<WriteCvtPH2PS, [SKXPort5,SKXPort01], 5, [1,1], 2>;
470 defm : X86WriteRes<WriteCvtPH2PSY, [SKXPort5,SKXPort01], 7, [1,1], 2>;
471 defm : X86WriteRes<WriteCvtPH2PSZ, [SKXPort5,SKXPort0], 7, [1,1], 2>;
472 defm : X86WriteRes<WriteCvtPH2PSLd, [SKXPort23,SKXPort01], 9, [1,1], 2>;
473 defm : X86WriteRes<WriteCvtPH2PSYLd, [SKXPort23,SKXPort01], 10, [1,1], 2>;
474 defm : X86WriteRes<WriteCvtPH2PSZLd, [SKXPort23,SKXPort05], 10, [1,1], 2>;
476 defm : X86WriteRes<WriteCvtPS2PH, [SKXPort5,SKXPort01], 5, [1,1], 2>;
477 defm : X86WriteRes<WriteCvtPS2PHY, [SKXPort5,SKXPort01], 7, [1,1], 2>;
478 defm : X86WriteRes<WriteCvtPS2PHZ, [SKXPort5,SKXPort05], 7, [1,1], 2>;
479 defm : X86WriteRes<WriteCvtPS2PHSt, [SKXPort4,SKXPort5,SKXPort237,SKXPort01], 6, [1,1,1,1], 4>;
480 defm : X86WriteRes<WriteCvtPS2PHYSt, [SKXPort4,SKXPort5,SKXPort237,SKXPort01], 8, [1,1,1,1], 4>;
481 defm : X86WriteRes<WriteCvtPS2PHZSt, [SKXPort4,SKXPort5,SKXPort237,SKXPort05], 8, [1,1,1,1], 4>;
483 // Strings instructions.
485 // Packed Compare Implicit Length Strings, Return Mask
486 def : WriteRes<WritePCmpIStrM, [SKXPort0]> {
487 let Latency = 10;
488 let NumMicroOps = 3;
489 let ResourceCycles = [3];
490 }
491 def : WriteRes<WritePCmpIStrMLd, [SKXPort0, SKXPort23]> {
492 let Latency = 16;
493 let NumMicroOps = 4;
494 let ResourceCycles = [3,1];
495 }
497 // Packed Compare Explicit Length Strings, Return Mask
498 def : WriteRes<WritePCmpEStrM, [SKXPort0, SKXPort5, SKXPort015, SKXPort0156]> {
499 let Latency = 19;
500 let NumMicroOps = 9;
501 let ResourceCycles = [4,3,1,1];
502 }
503 def : WriteRes<WritePCmpEStrMLd, [SKXPort0, SKXPort5, SKXPort23, SKXPort015, SKXPort0156]> {
504 let Latency = 25;
505 let NumMicroOps = 10;
506 let ResourceCycles = [4,3,1,1,1];
507 }
509 // Packed Compare Implicit Length Strings, Return Index
510 def : WriteRes<WritePCmpIStrI, [SKXPort0]> {
511 let Latency = 10;
512 let NumMicroOps = 3;
513 let ResourceCycles = [3];
514 }
515 def : WriteRes<WritePCmpIStrILd, [SKXPort0, SKXPort23]> {
516 let Latency = 16;
517 let NumMicroOps = 4;
518 let ResourceCycles = [3,1];
519 }
521 // Packed Compare Explicit Length Strings, Return Index
522 def : WriteRes<WritePCmpEStrI, [SKXPort0,SKXPort5,SKXPort0156]> {
523 let Latency = 18;
524 let NumMicroOps = 8;
525 let ResourceCycles = [4,3,1];
526 }
527 def : WriteRes<WritePCmpEStrILd, [SKXPort0, SKXPort5, SKXPort23, SKXPort0156]> {
528 let Latency = 24;
529 let NumMicroOps = 9;
530 let ResourceCycles = [4,3,1,1];
531 }
533 // MOVMSK Instructions.
534 def : WriteRes<WriteFMOVMSK, [SKXPort0]> { let Latency = 2; }
535 def : WriteRes<WriteVecMOVMSK, [SKXPort0]> { let Latency = 2; }
536 def : WriteRes<WriteVecMOVMSKY, [SKXPort0]> { let Latency = 2; }
537 def : WriteRes<WriteMMXMOVMSK, [SKXPort0]> { let Latency = 2; }
539 // AES instructions.
540 def : WriteRes<WriteAESDecEnc, [SKXPort0]> { // Decryption, encryption.
541 let Latency = 4;
542 let NumMicroOps = 1;
543 let ResourceCycles = [1];
544 }
545 def : WriteRes<WriteAESDecEncLd, [SKXPort0, SKXPort23]> {
546 let Latency = 10;
547 let NumMicroOps = 2;
548 let ResourceCycles = [1,1];
549 }
551 def : WriteRes<WriteAESIMC, [SKXPort0]> { // InvMixColumn.
552 let Latency = 8;
553 let NumMicroOps = 2;
554 let ResourceCycles = [2];
555 }
556 def : WriteRes<WriteAESIMCLd, [SKXPort0, SKXPort23]> {
557 let Latency = 14;
558 let NumMicroOps = 3;
559 let ResourceCycles = [2,1];
560 }
562 def : WriteRes<WriteAESKeyGen, [SKXPort0,SKXPort5,SKXPort015]> { // Key Generation.
563 let Latency = 20;
564 let NumMicroOps = 11;
565 let ResourceCycles = [3,6,2];
566 }
567 def : WriteRes<WriteAESKeyGenLd, [SKXPort0,SKXPort5,SKXPort23,SKXPort015]> {
568 let Latency = 25;
569 let NumMicroOps = 11;
570 let ResourceCycles = [3,6,1,1];
571 }
573 // Carry-less multiplication instructions.
574 def : WriteRes<WriteCLMul, [SKXPort5]> {
575 let Latency = 6;
576 let NumMicroOps = 1;
577 let ResourceCycles = [1];
578 }
579 def : WriteRes<WriteCLMulLd, [SKXPort5, SKXPort23]> {
580 let Latency = 12;
581 let NumMicroOps = 2;
582 let ResourceCycles = [1,1];
583 }
585 // Catch-all for expensive system instructions.
586 def : WriteRes<WriteSystem, [SKXPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;
588 // AVX2.
589 defm : SKXWriteResPair<WriteFShuffle256, [SKXPort5], 3, [1], 1, 7>; // Fp 256-bit width vector shuffles.
590 defm : SKXWriteResPair<WriteFVarShuffle256, [SKXPort5], 3, [1], 1, 7>; // Fp 256-bit width vector variable shuffles.
591 defm : SKXWriteResPair<WriteShuffle256, [SKXPort5], 3, [1], 1, 7>; // 256-bit width vector shuffles.
592 defm : SKXWriteResPair<WriteVPMOV256, [SKXPort5], 3, [1], 1, 7>; // 256-bit width packed vector width-changing move.
593 defm : SKXWriteResPair<WriteVarShuffle256, [SKXPort5], 3, [1], 1, 7>; // 256-bit width vector variable shuffles.
595 // Old microcoded instructions that nobody use.
596 def : WriteRes<WriteMicrocoded, [SKXPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
598 // Fence instructions.
599 def : WriteRes<WriteFence, [SKXPort23, SKXPort4]>;
601 // Load/store MXCSR.
602 def : WriteRes<WriteLDMXCSR, [SKXPort0,SKXPort23,SKXPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
603 def : WriteRes<WriteSTMXCSR, [SKXPort4,SKXPort5,SKXPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
605 // Nop, not very useful expect it provides a model for nops!
606 def : WriteRes<WriteNop, []>;
608 ////////////////////////////////////////////////////////////////////////////////
609 // Horizontal add/sub instructions.
610 ////////////////////////////////////////////////////////////////////////////////
612 defm : SKXWriteResPair<WriteFHAdd, [SKXPort5,SKXPort015], 6, [2,1], 3, 6>;
613 defm : SKXWriteResPair<WriteFHAddY, [SKXPort5,SKXPort015], 6, [2,1], 3, 7>;
614 defm : SKXWriteResPair<WritePHAdd, [SKXPort5,SKXPort05], 3, [2,1], 3, 5>;
615 defm : SKXWriteResPair<WritePHAddX, [SKXPort5,SKXPort015], 3, [2,1], 3, 6>;
616 defm : SKXWriteResPair<WritePHAddY, [SKXPort5,SKXPort015], 3, [2,1], 3, 7>;
618 // Remaining instrs.
620 def SKXWriteResGroup1 : SchedWriteRes<[SKXPort0]> {
621 let Latency = 1;
622 let NumMicroOps = 1;
623 let ResourceCycles = [1];
624 }
625 def: InstRW<[SKXWriteResGroup1], (instregex "KAND(B|D|Q|W)rr",
626 "KANDN(B|D|Q|W)rr",
627 "KMOV(B|D|Q|W)kk",
628 "KNOT(B|D|Q|W)rr",
629 "KOR(B|D|Q|W)rr",
630 "KXNOR(B|D|Q|W)rr",
631 "KXOR(B|D|Q|W)rr",
632 "KSET0(B|D|Q|W)", // Same as KXOR
633 "KSET1(B|D|Q|W)", // Same as KXNOR
634 "MMX_PADDS(B|W)irr",
635 "MMX_PADDUS(B|W)irr",
636 "MMX_PAVG(B|W)irr",
637 "MMX_PCMPEQ(B|D|W)irr",
638 "MMX_PCMPGT(B|D|W)irr",
639 "MMX_P(MAX|MIN)SWirr",
640 "MMX_P(MAX|MIN)UBirr",
641 "MMX_PSUBS(B|W)irr",
642 "MMX_PSUBUS(B|W)irr",
643 "VPMOVB2M(Z|Z128|Z256)rr",
644 "VPMOVD2M(Z|Z128|Z256)rr",
645 "VPMOVQ2M(Z|Z128|Z256)rr",
646 "VPMOVW2M(Z|Z128|Z256)rr")>;
648 def SKXWriteResGroup3 : SchedWriteRes<[SKXPort5]> {
649 let Latency = 1;
650 let NumMicroOps = 1;
651 let ResourceCycles = [1];
652 }
653 def: InstRW<[SKXWriteResGroup3], (instregex "COM(P?)_FST0r",
654 "KMOV(B|D|Q|W)kr",
655 "UCOM_F(P?)r")>;
657 def SKXWriteResGroup4 : SchedWriteRes<[SKXPort6]> {
658 let Latency = 1;
659 let NumMicroOps = 1;
660 let ResourceCycles = [1];
661 }
662 def: InstRW<[SKXWriteResGroup4], (instregex "JMP(16|32|64)r")>;
664 def SKXWriteResGroup6 : SchedWriteRes<[SKXPort05]> {
665 let Latency = 1;
666 let NumMicroOps = 1;
667 let ResourceCycles = [1];
668 }
669 def: InstRW<[SKXWriteResGroup6], (instrs FINCSTP, FNOP)>;
671 def SKXWriteResGroup7 : SchedWriteRes<[SKXPort06]> {
672 let Latency = 1;
673 let NumMicroOps = 1;
674 let ResourceCycles = [1];
675 }
676 def: InstRW<[SKXWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>;
678 def SKXWriteResGroup8 : SchedWriteRes<[SKXPort15]> {
679 let Latency = 1;
680 let NumMicroOps = 1;
681 let ResourceCycles = [1];
682 }
683 def: InstRW<[SKXWriteResGroup8], (instregex "ANDN(32|64)rr")>;
685 def SKXWriteResGroup9 : SchedWriteRes<[SKXPort015]> {
686 let Latency = 1;
687 let NumMicroOps = 1;
688 let ResourceCycles = [1];
689 }
690 def: InstRW<[SKXWriteResGroup9], (instregex "VBLENDMPD(Z128|Z256)rr",
691 "VBLENDMPS(Z128|Z256)rr",
692 "VPADD(B|D|Q|W)(Y|Z|Z128|Z256)rr",
693 "(V?)PADD(B|D|Q|W)rr",
694 "VPBLENDD(Y?)rri",
695 "VPBLENDMB(Z128|Z256)rr",
696 "VPBLENDMD(Z128|Z256)rr",
697 "VPBLENDMQ(Z128|Z256)rr",
698 "VPBLENDMW(Z128|Z256)rr",
699 "VPSUB(B|D|Q|W)(Y|Z|Z128|Z256)rrk",
700 "VPTERNLOGD(Z|Z128|Z256)rri",
701 "VPTERNLOGQ(Z|Z128|Z256)rri")>;
703 def SKXWriteResGroup10 : SchedWriteRes<[SKXPort0156]> {
704 let Latency = 1;
705 let NumMicroOps = 1;
706 let ResourceCycles = [1];
707 }
708 def: InstRW<[SKXWriteResGroup10], (instrs CBW, CWDE, CDQE,
709 CMC, STC,
710 SGDT64m,
711 SIDT64m,
712 SMSW16m,
713 STRm,
714 SYSCALL)>;
716 def SKXWriteResGroup11 : SchedWriteRes<[SKXPort4,SKXPort237]> {
717 let Latency = 1;
718 let NumMicroOps = 2;
719 let ResourceCycles = [1,1];
720 }
721 def: InstRW<[SKXWriteResGroup11], (instrs FBSTPm, VMPTRSTm)>;
722 def: InstRW<[SKXWriteResGroup11], (instregex "KMOV(B|D|Q|W)mk",
723 "ST_FP(32|64|80)m")>;
725 def SKXWriteResGroup13 : SchedWriteRes<[SKXPort5]> {
726 let Latency = 2;
727 let NumMicroOps = 2;
728 let ResourceCycles = [2];
729 }
730 def: InstRW<[SKXWriteResGroup13], (instrs MMX_MOVQ2DQrr)>;
732 def SKXWriteResGroup14 : SchedWriteRes<[SKXPort05]> {
733 let Latency = 2;
734 let NumMicroOps = 2;
735 let ResourceCycles = [2];
736 }
737 def: InstRW<[SKXWriteResGroup14], (instrs FDECSTP,
738 MMX_MOVDQ2Qrr)>;
740 def SKXWriteResGroup17 : SchedWriteRes<[SKXPort0156]> {
741 let Latency = 2;
742 let NumMicroOps = 2;
743 let ResourceCycles = [2];
744 }
745 def: InstRW<[SKXWriteResGroup17], (instrs LFENCE,
746 WAIT,
747 XGETBV)>;
749 def SKXWriteResGroup20 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
750 let Latency = 2;
751 let NumMicroOps = 2;
752 let ResourceCycles = [1,1];
753 }
754 def: InstRW<[SKXWriteResGroup20], (instregex "CLFLUSH")>;
756 def SKXWriteResGroup21 : SchedWriteRes<[SKXPort237,SKXPort0156]> {
757 let Latency = 2;
758 let NumMicroOps = 2;
759 let ResourceCycles = [1,1];
760 }
761 def: InstRW<[SKXWriteResGroup21], (instrs SFENCE)>;
763 def SKXWriteResGroup23 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
764 let Latency = 2;
765 let NumMicroOps = 2;
766 let ResourceCycles = [1,1];
767 }
768 def: InstRW<[SKXWriteResGroup23], (instrs CWD,
769 JCXZ, JECXZ, JRCXZ,
770 ADC8i8, SBB8i8,
771 ADC16i16, SBB16i16,
772 ADC32i32, SBB32i32,
773 ADC64i32, SBB64i32)>;
775 def SKXWriteResGroup25 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort237]> {
776 let Latency = 2;
777 let NumMicroOps = 3;
778 let ResourceCycles = [1,1,1];
779 }
780 def: InstRW<[SKXWriteResGroup25], (instrs FNSTCW16m)>;
782 def SKXWriteResGroup27 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort15]> {
783 let Latency = 2;
784 let NumMicroOps = 3;
785 let ResourceCycles = [1,1,1];
786 }
787 def: InstRW<[SKXWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>;
789 def SKXWriteResGroup28 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort0156]> {
790 let Latency = 2;
791 let NumMicroOps = 3;
792 let ResourceCycles = [1,1,1];
793 }
794 def: InstRW<[SKXWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8,
795 STOSB, STOSL, STOSQ, STOSW)>;
796 def: InstRW<[SKXWriteResGroup28], (instregex "PUSH(16|32|64)rmr")>;
798 def SKXWriteResGroup29 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort15]> {
799 let Latency = 2;
800 let NumMicroOps = 5;
801 let ResourceCycles = [2,2,1];
802 }
803 def: InstRW<[SKXWriteResGroup29], (instregex "VMOVDQU8Zmr(b?)")>;
805 def SKXWriteResGroup30 : SchedWriteRes<[SKXPort0]> {
806 let Latency = 3;
807 let NumMicroOps = 1;
808 let ResourceCycles = [1];
809 }
810 def: InstRW<[SKXWriteResGroup30], (instregex "KMOV(B|D|Q|W)rk",
811 "KORTEST(B|D|Q|W)rr",
812 "KTEST(B|D|Q|W)rr")>;
814 def SKXWriteResGroup31 : SchedWriteRes<[SKXPort1]> {
815 let Latency = 3;
816 let NumMicroOps = 1;
817 let ResourceCycles = [1];
818 }
819 def: InstRW<[SKXWriteResGroup31], (instregex "PDEP(32|64)rr",
820 "PEXT(32|64)rr")>;
822 def SKXWriteResGroup32 : SchedWriteRes<[SKXPort5]> {
823 let Latency = 3;
824 let NumMicroOps = 1;
825 let ResourceCycles = [1];
826 }
827 def: InstRW<[SKXWriteResGroup32], (instrs VPSADBWZrr)>; // TODO: 512-bit ops require ports 0/1 to be joined.
828 def: InstRW<[SKXWriteResGroup32], (instregex "(ADD|SUB|SUBR)_(FPrST0|FST0r|FrST0)",
829 "VALIGND(Z|Z128|Z256)rri",
830 "VALIGNQ(Z|Z128|Z256)rri",
831 "VDBPSADBWZrri", // TODO: 512-bit ops require ports 0/1 to be joined.
832 "VPBROADCAST(B|W)rr",
833 "VP(MAX|MIN)(S|U)Q(Z|Z128|Z256)rr")>;
835 def SKXWriteResGroup33 : SchedWriteRes<[SKXPort5]> {
836 let Latency = 4;
837 let NumMicroOps = 1;
838 let ResourceCycles = [1];
839 }
840 def: InstRW<[SKXWriteResGroup33], (instregex "KADD(B|D|Q|W)rr",
841 "KSHIFTL(B|D|Q|W)ri",
842 "KSHIFTR(B|D|Q|W)ri",
843 "KUNPCK(BW|DQ|WD)rr",
844 "VCMPPD(Z|Z128|Z256)rri",
845 "VCMPPS(Z|Z128|Z256)rri",
846 "VCMP(SD|SS)Zrr",
847 "VFPCLASS(PD|PS)(Z|Z128|Z256)rr",
848 "VFPCLASS(SD|SS)Zrr",
849 "VPCMPB(Z|Z128|Z256)rri",
850 "VPCMPD(Z|Z128|Z256)rri",
851 "VPCMPEQ(B|D|Q|W)(Z|Z128|Z256)rr",
852 "VPCMPGT(B|D|Q|W)(Z|Z128|Z256)rr",
853 "VPCMPQ(Z|Z128|Z256)rri",
854 "VPCMPU(B|D|Q|W)(Z|Z128|Z256)rri",
855 "VPCMPW(Z|Z128|Z256)rri",
856 "VPTEST(N?)M(B|D|Q|W)(Z|Z128|Z256)rr")>;
858 def SKXWriteResGroup34 : SchedWriteRes<[SKXPort0,SKXPort0156]> {
859 let Latency = 3;
860 let NumMicroOps = 2;
861 let ResourceCycles = [1,1];
862 }
863 def: InstRW<[SKXWriteResGroup34], (instrs FNSTSW16r)>;
865 def SKXWriteResGroup37 : SchedWriteRes<[SKXPort0,SKXPort5]> {
866 let Latency = 3;
867 let NumMicroOps = 3;
868 let ResourceCycles = [1,2];
869 }
870 def: InstRW<[SKXWriteResGroup37], (instregex "MMX_PH(ADD|SUB)SWrr")>;
872 def SKXWriteResGroup38 : SchedWriteRes<[SKXPort5,SKXPort01]> {
873 let Latency = 3;
874 let NumMicroOps = 3;
875 let ResourceCycles = [2,1];
876 }
877 def: InstRW<[SKXWriteResGroup38], (instregex "(V?)PH(ADD|SUB)SW(Y?)rr")>;
879 def SKXWriteResGroup41 : SchedWriteRes<[SKXPort5,SKXPort0156]> {
880 let Latency = 3;
881 let NumMicroOps = 3;
882 let ResourceCycles = [2,1];
883 }
884 def: InstRW<[SKXWriteResGroup41], (instrs MMX_PACKSSDWirr,
885 MMX_PACKSSWBirr,
886 MMX_PACKUSWBirr)>;
888 def SKXWriteResGroup42 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
889 let Latency = 3;
890 let NumMicroOps = 3;
891 let ResourceCycles = [1,2];
892 }
893 def: InstRW<[SKXWriteResGroup42], (instregex "CLD")>;
895 def SKXWriteResGroup43 : SchedWriteRes<[SKXPort237,SKXPort0156]> {
896 let Latency = 3;
897 let NumMicroOps = 3;
898 let ResourceCycles = [1,2];
899 }
900 def: InstRW<[SKXWriteResGroup43], (instrs MFENCE)>;
902 def SKXWriteResGroup44 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
903 let Latency = 3;
904 let NumMicroOps = 3;
905 let ResourceCycles = [1,2];
906 }
907 def: InstRW<[SKXWriteResGroup44], (instregex "RCL(8|16|32|64)r(1|i)",
908 "RCR(8|16|32|64)r(1|i)")>;
910 def SKXWriteResGroup45 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237]> {
911 let Latency = 3;
912 let NumMicroOps = 3;
913 let ResourceCycles = [1,1,1];
914 }
915 def: InstRW<[SKXWriteResGroup45], (instrs FNSTSWm)>;
917 def SKXWriteResGroup47 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort237,SKXPort0156]> {
918 let Latency = 3;
919 let NumMicroOps = 4;
920 let ResourceCycles = [1,1,1,1];
921 }
922 def: InstRW<[SKXWriteResGroup47], (instregex "CALL(16|32|64)r")>;
924 def SKXWriteResGroup48 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort06,SKXPort0156]> {
925 let Latency = 3;
926 let NumMicroOps = 4;
927 let ResourceCycles = [1,1,1,1];
928 }
929 def: InstRW<[SKXWriteResGroup48], (instrs CALL64pcrel32)>;
931 def SKXWriteResGroup49 : SchedWriteRes<[SKXPort0]> {
932 let Latency = 4;
933 let NumMicroOps = 1;
934 let ResourceCycles = [1];
935 }
936 def: InstRW<[SKXWriteResGroup49], (instregex "MUL_(FPrST0|FST0r|FrST0)")>;
938 def SKXWriteResGroup50 : SchedWriteRes<[SKXPort01]> {
939 let Latency = 4;
940 let NumMicroOps = 1;
941 let ResourceCycles = [1];
942 }
943 def: InstRW<[SKXWriteResGroup50], (instregex "VCVTDQ2PS(Y|Z128|Z256)rr",
944 "(V?)CVTDQ2PSrr",
945 "VCVTPD2QQ(Z128|Z256)rr",
946 "VCVTPD2UQQ(Z128|Z256)rr",
947 "VCVTPS2DQ(Y|Z128|Z256)rr",
948 "(V?)CVTPS2DQrr",
949 "VCVTPS2UDQ(Z128|Z256)rr",
950 "VCVTQQ2PD(Z128|Z256)rr",
951 "VCVTTPD2QQ(Z128|Z256)rr",
952 "VCVTTPD2UQQ(Z128|Z256)rr",
953 "VCVTTPS2DQ(Z128|Z256)rr",
954 "(V?)CVTTPS2DQrr",
955 "VCVTTPS2UDQ(Z128|Z256)rr",
956 "VCVTUDQ2PS(Z128|Z256)rr",
957 "VCVTUQQ2PD(Z128|Z256)rr")>;
959 def SKXWriteResGroup50z : SchedWriteRes<[SKXPort05]> {
960 let Latency = 4;
961 let NumMicroOps = 1;
962 let ResourceCycles = [1];
963 }
964 def: InstRW<[SKXWriteResGroup50z], (instrs VCVTDQ2PSZrr,
965 VCVTPD2QQZrr,
966 VCVTPD2UQQZrr,
967 VCVTPS2DQZrr,
968 VCVTPS2UDQZrr,
969 VCVTQQ2PDZrr,
970 VCVTTPD2QQZrr,
971 VCVTTPD2UQQZrr,
972 VCVTTPS2DQZrr,
973 VCVTTPS2UDQZrr,
974 VCVTUDQ2PSZrr,
975 VCVTUQQ2PDZrr)>;
977 def SKXWriteResGroup51 : SchedWriteRes<[SKXPort5]> {
978 let Latency = 4;
979 let NumMicroOps = 2;
980 let ResourceCycles = [2];
981 }
982 def: InstRW<[SKXWriteResGroup51], (instregex "VEXPANDPD(Z|Z128|Z256)rr",
983 "VEXPANDPS(Z|Z128|Z256)rr",
984 "VPEXPANDD(Z|Z128|Z256)rr",
985 "VPEXPANDQ(Z|Z128|Z256)rr",
986 "VPMOVDB(Z|Z128|Z256)rr",
987 "VPMOVDW(Z|Z128|Z256)rr",
988 "VPMOVQB(Z|Z128|Z256)rr",
989 "VPMOVQW(Z|Z128|Z256)rr",
990 "VPMOVSDB(Z|Z128|Z256)rr",
991 "VPMOVSDW(Z|Z128|Z256)rr",
992 "VPMOVSQB(Z|Z128|Z256)rr",
993 "VPMOVSQD(Z|Z128|Z256)rr",
994 "VPMOVSQW(Z|Z128|Z256)rr",
995 "VPMOVSWB(Z|Z128|Z256)rr",
996 "VPMOVUSDB(Z|Z128|Z256)rr",
997 "VPMOVUSDW(Z|Z128|Z256)rr",
998 "VPMOVUSQB(Z|Z128|Z256)rr",
999 "VPMOVUSQD(Z|Z128|Z256)rr",
1000 "VPMOVUSWB(Z|Z128|Z256)rr",
1001 "VPMOVWB(Z|Z128|Z256)rr")>;
1003 def SKXWriteResGroup54 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> {
1004 let Latency = 4;
1005 let NumMicroOps = 3;
1006 let ResourceCycles = [1,1,1];
1007 }
1008 def: InstRW<[SKXWriteResGroup54], (instregex "IST(T?)_FP(16|32|64)m",
1009 "IST_F(16|32)m",
1010 "VPMOVQD(Z|Z128|Z256)mr(b?)")>;
1012 def SKXWriteResGroup55 : SchedWriteRes<[SKXPort0156]> {
1013 let Latency = 4;
1014 let NumMicroOps = 4;
1015 let ResourceCycles = [4];
1016 }
1017 def: InstRW<[SKXWriteResGroup55], (instrs FNCLEX)>;
1019 def SKXWriteResGroup56 : SchedWriteRes<[]> {
1020 let Latency = 0;
1021 let NumMicroOps = 4;
1022 let ResourceCycles = [];
1023 }
1024 def: InstRW<[SKXWriteResGroup56], (instrs VZEROUPPER)>;
1026 def SKXWriteResGroup57 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort0156]> {
1027 let Latency = 4;
1028 let NumMicroOps = 4;
1029 let ResourceCycles = [1,1,2];
1030 }
1031 def: InstRW<[SKXWriteResGroup57], (instregex "LAR(16|32|64)rr")>;
1033 def SKXWriteResGroup58 : SchedWriteRes<[SKXPort23]> {
1034 let Latency = 5;
1035 let NumMicroOps = 1;
1036 let ResourceCycles = [1];
1037 }
1038 def: InstRW<[SKXWriteResGroup58], (instregex "MOVSX(16|32|64)rm(8|16|32)",
1039 "MOVZX(16|32|64)rm(8|16)",
1040 "(V?)MOVDDUPrm")>; // TODO: Should this be SKXWriteResGroup71?
1042 def SKXWriteResGroup61 : SchedWriteRes<[SKXPort5,SKXPort015]> {
1043 let Latency = 5;
1044 let NumMicroOps = 2;
1045 let ResourceCycles = [1,1];
1046 }
1047 def: InstRW<[SKXWriteResGroup61], (instregex "MMX_CVT(T?)PD2PIirr",
1048 "MMX_CVT(T?)PS2PIirr",
1049 "VCVTDQ2PDZ128rr",
1050 "VCVTPD2DQZ128rr",
1051 "(V?)CVT(T?)PD2DQrr",
1052 "VCVTPD2PSZ128rr",
1053 "(V?)CVTPD2PSrr",
1054 "VCVTPD2UDQZ128rr",
1055 "VCVTPS2PDZ128rr",
1056 "(V?)CVTPS2PDrr",
1057 "VCVTPS2QQZ128rr",
1058 "VCVTPS2UQQZ128rr",
1059 "VCVTQQ2PSZ128rr",
1060 "(V?)CVTSD2SS(Z?)rr",
1061 "(V?)CVTSI(64)?2SDrr",
1062 "VCVTSI2SSZrr",
1063 "(V?)CVTSI2SSrr",
1064 "VCVTSI(64)?2SDZrr",
1065 "VCVTSS2SDZrr",
1066 "(V?)CVTSS2SDrr",
1067 "VCVTTPD2DQZ128rr",
1068 "VCVTTPD2UDQZ128rr",
1069 "VCVTTPS2QQZ128rr",
1070 "VCVTTPS2UQQZ128rr",
1071 "VCVTUDQ2PDZ128rr",
1072 "VCVTUQQ2PSZ128rr",
1073 "VCVTUSI2SSZrr",
1074 "VCVTUSI(64)?2SDZrr")>;
1076 def SKXWriteResGroup62 : SchedWriteRes<[SKXPort5,SKXPort015]> {
1077 let Latency = 5;
1078 let NumMicroOps = 3;
1079 let ResourceCycles = [2,1];
1080 }
1081 def: InstRW<[SKXWriteResGroup62], (instregex "VPCONFLICTQZ128rr")>;
1083 def SKXWriteResGroup63 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort06]> {
1084 let Latency = 5;
1085 let NumMicroOps = 3;
1086 let ResourceCycles = [1,1,1];
1087 }
1088 def: InstRW<[SKXWriteResGroup63], (instregex "STR(16|32|64)r")>;
1090 def SKXWriteResGroup65 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort015]> {
1091 let Latency = 5;
1092 let NumMicroOps = 3;
1093 let ResourceCycles = [1,1,1];
1094 }
1095 def: InstRW<[SKXWriteResGroup65], (instregex "VCVTPS2PHZ128mr(b?)",
1096 "VCVTPS2PHZ256mr(b?)",
1097 "VCVTPS2PHZmr(b?)")>;
1099 def SKXWriteResGroup66 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> {
1100 let Latency = 5;
1101 let NumMicroOps = 4;
1102 let ResourceCycles = [1,2,1];
1103 }
1104 def: InstRW<[SKXWriteResGroup66], (instregex "VPMOVDB(Z|Z128|Z256)mr(b?)",
1105 "VPMOVDW(Z|Z128|Z256)mr(b?)",
1106 "VPMOVQB(Z|Z128|Z256)mr(b?)",
1107 "VPMOVQW(Z|Z128|Z256)mr(b?)",
1108 "VPMOVSDB(Z|Z128|Z256)mr(b?)",
1109 "VPMOVSDW(Z|Z128|Z256)mr(b?)",
1110 "VPMOVSQB(Z|Z128|Z256)mr(b?)",
1111 "VPMOVSQD(Z|Z128|Z256)mr(b?)",
1112 "VPMOVSQW(Z|Z128|Z256)mr(b?)",
1113 "VPMOVSWB(Z|Z128|Z256)mr(b?)",
1114 "VPMOVUSDB(Z|Z128|Z256)mr(b?)",
1115 "VPMOVUSDW(Z|Z128|Z256)mr(b?)",
1116 "VPMOVUSQB(Z|Z128|Z256)mr(b?)",
1117 "VPMOVUSQD(Z|Z128|Z256)mr(b?)",
1118 "VPMOVUSQW(Z|Z128|Z256)mr(b?)",
1119 "VPMOVUSWB(Z|Z128|Z256)mr(b?)",
1120 "VPMOVWB(Z|Z128|Z256)mr(b?)")>;
1122 def SKXWriteResGroup67 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
1123 let Latency = 5;
1124 let NumMicroOps = 5;
1125 let ResourceCycles = [1,4];
1126 }
1127 def: InstRW<[SKXWriteResGroup67], (instrs XSETBV)>;
1129 def SKXWriteResGroup69 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort0156]> {
1130 let Latency = 5;
1131 let NumMicroOps = 6;
1132 let ResourceCycles = [1,1,4];
1133 }
1134 def: InstRW<[SKXWriteResGroup69], (instregex "PUSHF(16|64)")>;
1136 def SKXWriteResGroup71 : SchedWriteRes<[SKXPort23]> {
1137 let Latency = 6;
1138 let NumMicroOps = 1;
1139 let ResourceCycles = [1];
1140 }
1141 def: InstRW<[SKXWriteResGroup71], (instrs VBROADCASTSSrm,
1142 VPBROADCASTDrm,
1143 VPBROADCASTQrm,
1144 VMOVSHDUPrm,
1145 VMOVSLDUPrm,
1146 MOVSHDUPrm,
1147 MOVSLDUPrm)>;
1149 def SKXWriteResGroup72 : SchedWriteRes<[SKXPort5]> {
1150 let Latency = 6;
1151 let NumMicroOps = 2;
1152 let ResourceCycles = [2];
1153 }
1154 def: InstRW<[SKXWriteResGroup72], (instrs MMX_CVTPI2PSirr)>;
1155 def: InstRW<[SKXWriteResGroup72], (instregex "VCOMPRESSPD(Z|Z128|Z256)rr",
1156 "VCOMPRESSPS(Z|Z128|Z256)rr",
1157 "VPCOMPRESSD(Z|Z128|Z256)rr",
1158 "VPCOMPRESSQ(Z|Z128|Z256)rr",
1159 "VPERMW(Z|Z128|Z256)rr")>;
1161 def SKXWriteResGroup73 : SchedWriteRes<[SKXPort0,SKXPort23]> {
1162 let Latency = 6;
1163 let NumMicroOps = 2;
1164 let ResourceCycles = [1,1];
1165 }
1166 def: InstRW<[SKXWriteResGroup73], (instrs MMX_PADDSBirm,
1167 MMX_PADDSWirm,
1168 MMX_PADDUSBirm,
1169 MMX_PADDUSWirm,
1170 MMX_PAVGBirm,
1171 MMX_PAVGWirm,
1172 MMX_PCMPEQBirm,
1173 MMX_PCMPEQDirm,
1174 MMX_PCMPEQWirm,
1175 MMX_PCMPGTBirm,
1176 MMX_PCMPGTDirm,
1177 MMX_PCMPGTWirm,
1178 MMX_PMAXSWirm,
1179 MMX_PMAXUBirm,
1180 MMX_PMINSWirm,
1181 MMX_PMINUBirm,
1182 MMX_PSUBSBirm,
1183 MMX_PSUBSWirm,
1184 MMX_PSUBUSBirm,
1185 MMX_PSUBUSWirm)>;
1187 def SKXWriteResGroup76 : SchedWriteRes<[SKXPort6,SKXPort23]> {
1188 let Latency = 6;
1189 let NumMicroOps = 2;
1190 let ResourceCycles = [1,1];
1191 }
1192 def: InstRW<[SKXWriteResGroup76], (instrs FARJMP64m)>;
1193 def: InstRW<[SKXWriteResGroup76], (instregex "JMP(16|32|64)m")>;
1195 def SKXWriteResGroup79 : SchedWriteRes<[SKXPort23,SKXPort15]> {
1196 let Latency = 6;
1197 let NumMicroOps = 2;
1198 let ResourceCycles = [1,1];
1199 }
1200 def: InstRW<[SKXWriteResGroup79], (instregex "ANDN(32|64)rm",
1201 "MOVBE(16|32|64)rm")>;
1203 def SKXWriteResGroup80 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1204 let Latency = 6;
1205 let NumMicroOps = 2;
1206 let ResourceCycles = [1,1];
1207 }
1208 def: InstRW<[SKXWriteResGroup80], (instregex "VMOV(64to|QI2)PQIZrm(b?)")>;
1209 def: InstRW<[SKXWriteResGroup80], (instrs VMOVDI2PDIZrm)>;
1211 def SKXWriteResGroup81 : SchedWriteRes<[SKXPort23,SKXPort0156]> {
1212 let Latency = 6;
1213 let NumMicroOps = 2;
1214 let ResourceCycles = [1,1];
1215 }
1216 def: InstRW<[SKXWriteResGroup81], (instrs POP16r, POP32r, POP64r)>;
1217 def: InstRW<[SKXWriteResGroup81], (instregex "POP(16|32|64)rmr")>;
1219 def SKXWriteResGroup82 : SchedWriteRes<[SKXPort5,SKXPort015]> {
1220 let Latency = 6;
1221 let NumMicroOps = 3;
1222 let ResourceCycles = [2,1];
1223 }
1224 def: InstRW<[SKXWriteResGroup82], (instregex "(V?)CVTSI642SSrr",
1225 "VCVTSI642SSZrr",
1226 "VCVTUSI642SSZrr")>;
1228 def SKXWriteResGroup84 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort06,SKXPort0156]> {
1229 let Latency = 6;
1230 let NumMicroOps = 4;
1231 let ResourceCycles = [1,1,1,1];
1232 }
1233 def: InstRW<[SKXWriteResGroup84], (instregex "SLDT(16|32|64)r")>;
1235 def SKXWriteResGroup86 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> {
1236 let Latency = 6;
1237 let NumMicroOps = 4;
1238 let ResourceCycles = [1,1,1,1];
1239 }
1240 def: InstRW<[SKXWriteResGroup86], (instregex "SAR(8|16|32|64)m(1|i)",
1241 "SHL(8|16|32|64)m(1|i)",
1242 "SHR(8|16|32|64)m(1|i)")>;
1244 def SKXWriteResGroup87 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort0156]> {
1245 let Latency = 6;
1246 let NumMicroOps = 4;
1247 let ResourceCycles = [1,1,1,1];
1248 }
1249 def: InstRW<[SKXWriteResGroup87], (instregex "POP(16|32|64)rmm",
1250 "PUSH(16|32|64)rmm")>;
1252 def SKXWriteResGroup88 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
1253 let Latency = 6;
1254 let NumMicroOps = 6;
1255 let ResourceCycles = [1,5];
1256 }
1257 def: InstRW<[SKXWriteResGroup88], (instrs STD)>;
1259 def SKXWriteResGroup89 : SchedWriteRes<[SKXPort23]> {
1260 let Latency = 7;
1261 let NumMicroOps = 1;
1262 let ResourceCycles = [1];
1263 }
1264 def: InstRW<[SKXWriteResGroup89], (instregex "LD_F(32|64|80)m")>;
1265 def: InstRW<[SKXWriteResGroup89], (instrs VBROADCASTF128,
1266 VBROADCASTI128,
1267 VBROADCASTSDYrm,
1268 VBROADCASTSSYrm,
1269 VMOVDDUPYrm,
1270 VMOVSHDUPYrm,
1271 VMOVSLDUPYrm,
1272 VPBROADCASTDYrm,
1273 VPBROADCASTQYrm)>;
1275 def SKXWriteResGroup90 : SchedWriteRes<[SKXPort01,SKXPort5]> {
1276 let Latency = 7;
1277 let NumMicroOps = 2;
1278 let ResourceCycles = [1,1];
1279 }
1280 def: InstRW<[SKXWriteResGroup90], (instrs VCVTDQ2PDYrr)>;
1282 def SKXWriteResGroup92 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1283 let Latency = 7;
1284 let NumMicroOps = 2;
1285 let ResourceCycles = [1,1];
1286 }
1287 def: InstRW<[SKXWriteResGroup92], (instregex "VMOVSDZrm(b?)",
1288 "VMOVSSZrm(b?)")>;
1290 def SKXWriteResGroup92a : SchedWriteRes<[SKXPort5,SKXPort23]> {
1291 let Latency = 6;
1292 let NumMicroOps = 2;
1293 let ResourceCycles = [1,1];
1294 }
1295 def: InstRW<[SKXWriteResGroup92a], (instregex "(V?)PMOV(SX|ZX)BDrm",
1296 "(V?)PMOV(SX|ZX)BQrm",
1297 "(V?)PMOV(SX|ZX)BWrm",
1298 "(V?)PMOV(SX|ZX)DQrm",
1299 "(V?)PMOV(SX|ZX)WDrm",
1300 "(V?)PMOV(SX|ZX)WQrm")>;
1302 def SKXWriteResGroup93 : SchedWriteRes<[SKXPort5,SKXPort015]> {
1303 let Latency = 7;
1304 let NumMicroOps = 2;
1305 let ResourceCycles = [1,1];
1306 }
1307 def: InstRW<[SKXWriteResGroup93], (instregex "VCVTDQ2PDZ256rr",
1308 "VCVTPD2DQ(Y|Z256)rr",
1309 "VCVTPD2PS(Y|Z256)rr",
1310 "VCVTPD2UDQZ256rr",
1311 "VCVTPS2PD(Y|Z256)rr",
1312 "VCVTPS2QQZ256rr",
1313 "VCVTPS2UQQZ256rr",
1314 "VCVTQQ2PSZ256rr",
1315 "VCVTTPD2DQ(Y|Z256)rr",
1316 "VCVTTPD2UDQZ256rr",
1317 "VCVTTPS2QQZ256rr",
1318 "VCVTTPS2UQQZ256rr",
1319 "VCVTUDQ2PDZ256rr",
1320 "VCVTUQQ2PSZ256rr")>;
1322 def SKXWriteResGroup93z : SchedWriteRes<[SKXPort5,SKXPort05]> {
1323 let Latency = 7;
1324 let NumMicroOps = 2;
1325 let ResourceCycles = [1,1];
1326 }
1327 def: InstRW<[SKXWriteResGroup93z], (instrs VCVTDQ2PDZrr,
1328 VCVTPD2DQZrr,
1329 VCVTPD2PSZrr,
1330 VCVTPD2UDQZrr,
1331 VCVTPS2PDZrr,
1332 VCVTPS2QQZrr,
1333 VCVTPS2UQQZrr,
1334 VCVTQQ2PSZrr,
1335 VCVTTPD2DQZrr,
1336 VCVTTPD2UDQZrr,
1337 VCVTTPS2QQZrr,
1338 VCVTTPS2UQQZrr,
1339 VCVTUDQ2PDZrr,
1340 VCVTUQQ2PSZrr)>;
1342 def SKXWriteResGroup95 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1343 let Latency = 7;
1344 let NumMicroOps = 2;
1345 let ResourceCycles = [1,1];
1346 }
1347 def: InstRW<[SKXWriteResGroup95], (instrs VMOVNTDQAZ128rm,
1348 VPBLENDDrmi)>;
1349 def: InstRW<[SKXWriteResGroup95, ReadAfterVecXLd],
1350 (instregex "VBLENDMPDZ128rm(b?)",
1351 "VBLENDMPSZ128rm(b?)",
1352 "VBROADCASTI32X2Z128rm(b?)",
1353 "VBROADCASTSSZ128rm(b?)",
1354 "VINSERT(F|I)128rm",
1355 "VMOVAPDZ128rm(b?)",
1356 "VMOVAPSZ128rm(b?)",
1357 "VMOVDDUPZ128rm(b?)",
1358 "VMOVDQA32Z128rm(b?)",
1359 "VMOVDQA64Z128rm(b?)",
1360 "VMOVDQU16Z128rm(b?)",
1361 "VMOVDQU32Z128rm(b?)",
1362 "VMOVDQU64Z128rm(b?)",
1363 "VMOVDQU8Z128rm(b?)",
1364 "VMOVSHDUPZ128rm(b?)",
1365 "VMOVSLDUPZ128rm(b?)",
1366 "VMOVUPDZ128rm(b?)",
1367 "VMOVUPSZ128rm(b?)",
1368 "VPADD(B|D|Q|W)Z128rm(b?)",
1369 "(V?)PADD(B|D|Q|W)rm",
1370 "VPBLENDM(B|D|Q|W)Z128rm(b?)",
1371 "VPBROADCASTDZ128rm(b?)",
1372 "VPBROADCASTQZ128rm(b?)",
1373 "VPSUB(B|D|Q|W)Z128rm(b?)",
1374 "(V?)PSUB(B|D|Q|W)rm",
1375 "VPTERNLOGDZ128rm(b?)i",
1376 "VPTERNLOGQZ128rm(b?)i")>;
1378 def SKXWriteResGroup96 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1379 let Latency = 7;
1380 let NumMicroOps = 3;
1381 let ResourceCycles = [2,1];
1382 }
1383 def: InstRW<[SKXWriteResGroup96], (instrs MMX_PACKSSDWirm,
1384 MMX_PACKSSWBirm,
1385 MMX_PACKUSWBirm)>;
1387 def SKXWriteResGroup97 : SchedWriteRes<[SKXPort5,SKXPort015]> {
1388 let Latency = 7;
1389 let NumMicroOps = 3;
1390 let ResourceCycles = [2,1];
1391 }
1392 def: InstRW<[SKXWriteResGroup97], (instregex "VPERMI2W128rr",
1393 "VPERMI2W256rr",
1394 "VPERMI2Wrr",
1395 "VPERMT2W128rr",
1396 "VPERMT2W256rr",
1397 "VPERMT2Wrr")>;
1399 def SKXWriteResGroup99 : SchedWriteRes<[SKXPort23,SKXPort0156]> {
1400 let Latency = 7;
1401 let NumMicroOps = 3;
1402 let ResourceCycles = [1,2];
1403 }
1404 def: InstRW<[SKXWriteResGroup99], (instrs LEAVE, LEAVE64,
1405 SCASB, SCASL, SCASQ, SCASW)>;
1407 def SKXWriteResGroup100 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort015]> {
1408 let Latency = 7;
1409 let NumMicroOps = 3;
1410 let ResourceCycles = [1,1,1];
1411 }
1412 def: InstRW<[SKXWriteResGroup100], (instregex "VCVTSS2USI64Zrr",
1413 "(V?)CVTSS2SI64(Z?)rr",
1414 "(V?)CVTTSS2SI64(Z?)rr",
1415 "VCVTTSS2USI64Zrr")>;
1417 def SKXWriteResGroup101 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort05]> {
1418 let Latency = 7;
1419 let NumMicroOps = 3;
1420 let ResourceCycles = [1,1,1];
1421 }
1422 def: InstRW<[SKXWriteResGroup101], (instrs FLDCW16m)>;
1424 def SKXWriteResGroup103 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort0156]> {
1425 let Latency = 7;
1426 let NumMicroOps = 3;
1427 let ResourceCycles = [1,1,1];
1428 }
1429 def: InstRW<[SKXWriteResGroup103], (instregex "KMOV(B|D|Q|W)km")>;
1431 def SKXWriteResGroup104 : SchedWriteRes<[SKXPort6,SKXPort23,SKXPort0156]> {
1432 let Latency = 7;
1433 let NumMicroOps = 3;
1434 let ResourceCycles = [1,1,1];
1435 }
1436 def: InstRW<[SKXWriteResGroup104], (instrs LRETQ, RETQ)>;
1438 def SKXWriteResGroup106 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> {
1439 let Latency = 7;
1440 let NumMicroOps = 4;
1441 let ResourceCycles = [1,2,1];
1442 }
1443 def: InstRW<[SKXWriteResGroup106], (instregex "VCOMPRESSPD(Z|Z128|Z256)mr(b?)",
1444 "VCOMPRESSPS(Z|Z128|Z256)mr(b?)",
1445 "VPCOMPRESSD(Z|Z128|Z256)mr(b?)",
1446 "VPCOMPRESSQ(Z|Z128|Z256)mr(b?)")>;
1448 def SKXWriteResGroup107 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> {
1449 let Latency = 7;
1450 let NumMicroOps = 5;
1451 let ResourceCycles = [1,1,1,2];
1452 }
1453 def: InstRW<[SKXWriteResGroup107], (instregex "ROL(8|16|32|64)m(1|i)",
1454 "ROR(8|16|32|64)m(1|i)")>;
1456 def SKXWriteResGroup107_1 : SchedWriteRes<[SKXPort06]> {
1457 let Latency = 2;
1458 let NumMicroOps = 2;
1459 let ResourceCycles = [2];
1460 }
1461 def: InstRW<[SKXWriteResGroup107_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1,
1462 ROR8r1, ROR16r1, ROR32r1, ROR64r1)>;
1464 def SKXWriteResGroup108 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort0156]> {
1465 let Latency = 7;
1466 let NumMicroOps = 5;
1467 let ResourceCycles = [1,1,1,2];
1468 }
1469 def: InstRW<[SKXWriteResGroup108], (instregex "XADD(8|16|32|64)rm")>;
1471 def SKXWriteResGroup109 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> {
1472 let Latency = 7;
1473 let NumMicroOps = 5;
1474 let ResourceCycles = [1,1,1,1,1];
1475 }
1476 def: InstRW<[SKXWriteResGroup109], (instregex "CALL(16|32|64)m")>;
1477 def: InstRW<[SKXWriteResGroup109], (instrs FARCALL64m)>;
1479 def SKXWriteResGroup110 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> {
1480 let Latency = 7;
1481 let NumMicroOps = 7;
1482 let ResourceCycles = [1,2,2,2];
1483 }
1484 def: InstRW<[SKXWriteResGroup110], (instrs VPSCATTERDQZ128mr,
1485 VPSCATTERQQZ128mr,
1486 VSCATTERDPDZ128mr,
1487 VSCATTERQPDZ128mr)>;
1489 def SKXWriteResGroup111 : SchedWriteRes<[SKXPort6,SKXPort06,SKXPort15,SKXPort0156]> {
1490 let Latency = 7;
1491 let NumMicroOps = 7;
1492 let ResourceCycles = [1,3,1,2];
1493 }
1494 def: InstRW<[SKXWriteResGroup111], (instrs LOOP)>;
1496 def SKXWriteResGroup112 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> {
1497 let Latency = 7;
1498 let NumMicroOps = 11;
1499 let ResourceCycles = [1,4,4,2];
1500 }
1501 def: InstRW<[SKXWriteResGroup112], (instrs VPSCATTERDQZ256mr,
1502 VPSCATTERQQZ256mr,
1503 VSCATTERDPDZ256mr,
1504 VSCATTERQPDZ256mr)>;
1506 def SKXWriteResGroup113 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> {
1507 let Latency = 7;
1508 let NumMicroOps = 19;
1509 let ResourceCycles = [1,8,8,2];
1510 }
1511 def: InstRW<[SKXWriteResGroup113], (instrs VPSCATTERDQZmr,
1512 VPSCATTERQQZmr,
1513 VSCATTERDPDZmr,
1514 VSCATTERQPDZmr)>;
1516 def SKXWriteResGroup114 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
1517 let Latency = 7;
1518 let NumMicroOps = 36;
1519 let ResourceCycles = [1,16,1,16,2];
1520 }
1521 def: InstRW<[SKXWriteResGroup114], (instrs VSCATTERDPSZmr)>;
1523 def SKXWriteResGroup118 : SchedWriteRes<[SKXPort1,SKXPort23]> {
1524 let Latency = 8;
1525 let NumMicroOps = 2;
1526 let ResourceCycles = [1,1];
1527 }
1528 def: InstRW<[SKXWriteResGroup118], (instregex "PDEP(32|64)rm",
1529 "PEXT(32|64)rm")>;
1531 def SKXWriteResGroup119 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1532 let Latency = 8;
1533 let NumMicroOps = 2;
1534 let ResourceCycles = [1,1];
1535 }
1536 def: InstRW<[SKXWriteResGroup119], (instregex "FCOM(P?)(32|64)m",
1537 "VPBROADCASTB(Z|Z256)rm(b?)",
1538 "VPBROADCASTW(Z|Z256)rm(b?)")>;
1539 def: InstRW<[SKXWriteResGroup119], (instrs VPBROADCASTBYrm,
1540 VPBROADCASTWYrm,
1541 VPMOVSXBDYrm,
1542 VPMOVSXBQYrm,
1543 VPMOVSXWQYrm)>;
1545 def SKXWriteResGroup121 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1546 let Latency = 8;
1547 let NumMicroOps = 2;
1548 let ResourceCycles = [1,1];
1549 }
1550 def: InstRW<[SKXWriteResGroup121], (instrs VMOVNTDQAZ256rm,
1551 VPBLENDDYrmi)>;
1552 def: InstRW<[SKXWriteResGroup121, ReadAfterVecYLd],
1553 (instregex "VBLENDMPD(Z|Z256)rm(b?)",
1554 "VBLENDMPS(Z|Z256)rm(b?)",
1555 "VBROADCASTF32X2Z256rm(b?)",
1556 "VBROADCASTF32X2Zrm(b?)",
1557 "VBROADCASTF32X4Z256rm(b?)",
1558 "VBROADCASTF32X4rm(b?)",
1559 "VBROADCASTF32X8rm(b?)",
1560 "VBROADCASTF64X2Z128rm(b?)",
1561 "VBROADCASTF64X2rm(b?)",
1562 "VBROADCASTF64X4rm(b?)",
1563 "VBROADCASTI32X2Z256rm(b?)",
1564 "VBROADCASTI32X2Zrm(b?)",
1565 "VBROADCASTI32X4Z256rm(b?)",
1566 "VBROADCASTI32X4rm(b?)",
1567 "VBROADCASTI32X8rm(b?)",
1568 "VBROADCASTI64X2Z128rm(b?)",
1569 "VBROADCASTI64X2rm(b?)",
1570 "VBROADCASTI64X4rm(b?)",
1571 "VBROADCASTSD(Z|Z256)rm(b?)",
1572 "VBROADCASTSS(Z|Z256)rm(b?)",
1573 "VINSERTF32x4(Z|Z256)rm(b?)",
1574 "VINSERTF32x8Zrm(b?)",
1575 "VINSERTF64x2(Z|Z256)rm(b?)",
1576 "VINSERTF64x4Zrm(b?)",
1577 "VINSERTI32x4(Z|Z256)rm(b?)",
1578 "VINSERTI32x8Zrm(b?)",
1579 "VINSERTI64x2(Z|Z256)rm(b?)",
1580 "VINSERTI64x4Zrm(b?)",
1581 "VMOVAPD(Z|Z256)rm(b?)",
1582 "VMOVAPS(Z|Z256)rm(b?)",
1583 "VMOVDDUP(Z|Z256)rm(b?)",
1584 "VMOVDQA32(Z|Z256)rm(b?)",
1585 "VMOVDQA64(Z|Z256)rm(b?)",
1586 "VMOVDQU16(Z|Z256)rm(b?)",
1587 "VMOVDQU32(Z|Z256)rm(b?)",
1588 "VMOVDQU64(Z|Z256)rm(b?)",
1589 "VMOVDQU8(Z|Z256)rm(b?)",
1590 "VMOVSHDUP(Z|Z256)rm(b?)",
1591 "VMOVSLDUP(Z|Z256)rm(b?)",
1592 "VMOVUPD(Z|Z256)rm(b?)",
1593 "VMOVUPS(Z|Z256)rm(b?)",
1594 "VPADD(B|D|Q|W)Yrm",
1595 "VPADD(B|D|Q|W)(Z|Z256)rm(b?)",
1596 "VPBLENDM(B|D|Q|W)(Z|Z256)rm(b?)",
1597 "VPBROADCASTD(Z|Z256)rm(b?)",
1598 "VPBROADCASTQ(Z|Z256)rm(b?)",
1599 "VPSUB(B|D|Q|W)Yrm",
1600 "VPSUB(B|D|Q|W)(Z|Z256)rm(b?)",
1601 "VPTERNLOGD(Z|Z256)rm(b?)i",
1602 "VPTERNLOGQ(Z|Z256)rm(b?)i")>;
1604 def SKXWriteResGroup123 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
1605 let Latency = 8;
1606 let NumMicroOps = 4;
1607 let ResourceCycles = [1,2,1];
1608 }
1609 def: InstRW<[SKXWriteResGroup123], (instregex "MMX_PH(ADD|SUB)SWrm")>;
1611 def SKXWriteResGroup127 : SchedWriteRes<[SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
1612 let Latency = 8;
1613 let NumMicroOps = 5;
1614 let ResourceCycles = [1,1,1,2];
1615 }
1616 def: InstRW<[SKXWriteResGroup127], (instregex "RCL(8|16|32|64)m(1|i)",
1617 "RCR(8|16|32|64)m(1|i)")>;
1619 def SKXWriteResGroup128 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> {
1620 let Latency = 8;
1621 let NumMicroOps = 6;
1622 let ResourceCycles = [1,1,1,3];
1623 }
1624 def: InstRW<[SKXWriteResGroup128], (instregex "ROL(8|16|32|64)mCL",
1625 "ROR(8|16|32|64)mCL",
1626 "SAR(8|16|32|64)mCL",
1627 "SHL(8|16|32|64)mCL",
1628 "SHR(8|16|32|64)mCL")>;
1630 def SKXWriteResGroup130 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
1631 let Latency = 8;
1632 let NumMicroOps = 6;
1633 let ResourceCycles = [1,1,1,2,1];
1634 }
1635 def: SchedAlias<WriteADCRMW, SKXWriteResGroup130>;
1637 def SKXWriteResGroup131 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
1638 let Latency = 8;
1639 let NumMicroOps = 8;
1640 let ResourceCycles = [1,2,1,2,2];
1641 }
1642 def: InstRW<[SKXWriteResGroup131], (instrs VPSCATTERQDZ128mr,
1643 VPSCATTERQDZ256mr,
1644 VSCATTERQPSZ128mr,
1645 VSCATTERQPSZ256mr)>;
1647 def SKXWriteResGroup132 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
1648 let Latency = 8;
1649 let NumMicroOps = 12;
1650 let ResourceCycles = [1,4,1,4,2];
1651 }
1652 def: InstRW<[SKXWriteResGroup132], (instrs VPSCATTERDDZ128mr,
1653 VSCATTERDPSZ128mr)>;
1655 def SKXWriteResGroup133 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
1656 let Latency = 8;
1657 let NumMicroOps = 20;
1658 let ResourceCycles = [1,8,1,8,2];
1659 }
1660 def: InstRW<[SKXWriteResGroup133], (instrs VPSCATTERDDZ256mr,
1661 VSCATTERDPSZ256mr)>;
1663 def SKXWriteResGroup134 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
1664 let Latency = 8;
1665 let NumMicroOps = 36;
1666 let ResourceCycles = [1,16,1,16,2];
1667 }
1668 def: InstRW<[SKXWriteResGroup134], (instrs VPSCATTERDDZmr)>;
1670 def SKXWriteResGroup135 : SchedWriteRes<[SKXPort0,SKXPort23]> {
1671 let Latency = 9;
1672 let NumMicroOps = 2;
1673 let ResourceCycles = [1,1];
1674 }
1675 def: InstRW<[SKXWriteResGroup135], (instrs MMX_CVTPI2PSirm)>;
1677 def SKXWriteResGroup136 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1678 let Latency = 9;
1679 let NumMicroOps = 2;
1680 let ResourceCycles = [1,1];
1681 }
1682 def: InstRW<[SKXWriteResGroup136], (instrs VPMOVSXBWYrm,
1683 VPMOVSXDQYrm,
1684 VPMOVSXWDYrm,
1685 VPMOVZXWDYrm)>;
1686 def: InstRW<[SKXWriteResGroup136], (instregex "VALIGN(D|Q)Z128rm(b?)i",
1687 "VFPCLASSSDZrm(b?)",
1688 "VFPCLASSSSZrm(b?)",
1689 "(V?)PCMPGTQrm",
1690 "VPERMI2D128rm(b?)",
1691 "VPERMI2PD128rm(b?)",
1692 "VPERMI2PS128rm(b?)",
1693 "VPERMI2Q128rm(b?)",
1694 "VPERMT2D128rm(b?)",
1695 "VPERMT2PD128rm(b?)",
1696 "VPERMT2PS128rm(b?)",
1697 "VPERMT2Q128rm(b?)",
1698 "VPMAXSQZ128rm(b?)",
1699 "VPMAXUQZ128rm(b?)",
1700 "VPMINSQZ128rm(b?)",
1701 "VPMINUQZ128rm(b?)",
1702 "VPMOVSXBDZ128rm(b?)",
1703 "VPMOVSXBQZ128rm(b?)",
1704 "VPMOVSXBWZ128rm(b?)",
1705 "VPMOVSXDQZ128rm(b?)",
1706 "VPMOVSXWDZ128rm(b?)",
1707 "VPMOVSXWQZ128rm(b?)",
1708 "VPMOVZXBDZ128rm(b?)",
1709 "VPMOVZXBQZ128rm(b?)",
1710 "VPMOVZXBWZ128rm(b?)",
1711 "VPMOVZXDQZ128rm(b?)",
1712 "VPMOVZXWDZ128rm(b?)",
1713 "VPMOVZXWQZ128rm(b?)")>;
1715 def SKXWriteResGroup136_2 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1716 let Latency = 10;
1717 let NumMicroOps = 2;
1718 let ResourceCycles = [1,1];
1719 }
1720 def: InstRW<[SKXWriteResGroup136_2], (instregex "VCMP(PD|PS)Z128rm(b?)i",
1721 "VCMP(SD|SS)Zrm",
1722 "VFPCLASSPDZ128rm(b?)",
1723 "VFPCLASSPSZ128rm(b?)",
1724 "VPCMPBZ128rmi(b?)",
1725 "VPCMPDZ128rmi(b?)",
1726 "VPCMPEQ(B|D|Q|W)Z128rm(b?)",
1727 "VPCMPGT(B|D|Q|W)Z128rm(b?)",
1728 "VPCMPQZ128rmi(b?)",
1729 "VPCMPU(B|D|Q|W)Z128rmi(b?)",
1730 "VPCMPWZ128rmi(b?)",
1731 "VPTESTMBZ128rm(b?)",
1732 "VPTESTMDZ128rm(b?)",
1733 "VPTESTMQZ128rm(b?)",
1734 "VPTESTMWZ128rm(b?)",
1735 "VPTESTNMBZ128rm(b?)",
1736 "VPTESTNMDZ128rm(b?)",
1737 "VPTESTNMQZ128rm(b?)",
1738 "VPTESTNMWZ128rm(b?)")>;
1740 def SKXWriteResGroup137 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1741 let Latency = 9;
1742 let NumMicroOps = 2;
1743 let ResourceCycles = [1,1];
1744 }
1745 def: InstRW<[SKXWriteResGroup137], (instregex "MMX_CVT(T?)PS2PIirm",
1746 "(V?)CVTPS2PDrm")>;
1748 def SKXWriteResGroup143 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23]> {
1749 let Latency = 9;
1750 let NumMicroOps = 4;
1751 let ResourceCycles = [2,1,1];
1752 }
1753 def: InstRW<[SKXWriteResGroup143], (instregex "(V?)PHADDSWrm",
1754 "(V?)PHSUBSWrm")>;
1756 def SKXWriteResGroup146 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort23,SKXPort0156]> {
1757 let Latency = 9;
1758 let NumMicroOps = 5;
1759 let ResourceCycles = [1,2,1,1];
1760 }
1761 def: InstRW<[SKXWriteResGroup146], (instregex "LAR(16|32|64)rm",
1762 "LSL(16|32|64)rm")>;
1764 def SKXWriteResGroup148 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1765 let Latency = 10;
1766 let NumMicroOps = 2;
1767 let ResourceCycles = [1,1];
1768 }
1769 def: InstRW<[SKXWriteResGroup148], (instrs VPCMPGTQYrm)>;
1770 def: InstRW<[SKXWriteResGroup148], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
1771 "ILD_F(16|32|64)m",
1772 "VALIGND(Z|Z256)rm(b?)i",
1773 "VALIGNQ(Z|Z256)rm(b?)i",
1774 "VPMAXSQ(Z|Z256)rm(b?)",
1775 "VPMAXUQ(Z|Z256)rm(b?)",
1776 "VPMINSQ(Z|Z256)rm(b?)",
1777 "VPMINUQ(Z|Z256)rm(b?)")>;
1779 def SKXWriteResGroup148_2 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1780 let Latency = 11;
1781 let NumMicroOps = 2;
1782 let ResourceCycles = [1,1];
1783 }
1784 def: InstRW<[SKXWriteResGroup148_2], (instregex "VCMPPD(Z|Z256)rm(b?)i",
1785 "VCMPPS(Z|Z256)rm(b?)i",
1786 "VFPCLASSPD(Z|Z256)rm(b?)",
1787 "VFPCLASSPS(Z|Z256)rm(b?)",
1788 "VPCMPB(Z|Z256)rmi(b?)",
1789 "VPCMPD(Z|Z256)rmi(b?)",
1790 "VPCMPEQB(Z|Z256)rm(b?)",
1791 "VPCMPEQD(Z|Z256)rm(b?)",
1792 "VPCMPEQQ(Z|Z256)rm(b?)",
1793 "VPCMPEQW(Z|Z256)rm(b?)",
1794 "VPCMPGTB(Z|Z256)rm(b?)",
1795 "VPCMPGTD(Z|Z256)rm(b?)",
1796 "VPCMPGTQ(Z|Z256)rm(b?)",
1797 "VPCMPGTW(Z|Z256)rm(b?)",
1798 "VPCMPQ(Z|Z256)rmi(b?)",
1799 "VPCMPU(B|D|Q|W)Z256rmi(b?)",
1800 "VPCMPU(B|D|Q|W)Zrmi(b?)",
1801 "VPCMPW(Z|Z256)rmi(b?)",
1802 "VPTESTM(B|D|Q|W)Z256rm(b?)",
1803 "VPTESTM(B|D|Q|W)Zrm(b?)",
1804 "VPTESTNM(B|D|Q|W)Z256rm(b?)",
1805 "VPTESTNM(B|D|Q|W)Zrm(b?)")>;
1807 def SKXWriteResGroup149 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1808 let Latency = 10;
1809 let NumMicroOps = 2;
1810 let ResourceCycles = [1,1];
1811 }
1812 def: InstRW<[SKXWriteResGroup149], (instregex "VCVTDQ2PDZ128rm(b?)",
1813 "VCVTDQ2PSZ128rm(b?)",
1814 "(V?)CVTDQ2PSrm",
1815 "VCVTPD2QQZ128rm(b?)",
1816 "VCVTPD2UQQZ128rm(b?)",
1817 "VCVTPH2PSZ128rm(b?)",
1818 "VCVTPS2DQZ128rm(b?)",
1819 "(V?)CVTPS2DQrm",
1820 "VCVTPS2PDZ128rm(b?)",
1821 "VCVTPS2QQZ128rm(b?)",
1822 "VCVTPS2UDQZ128rm(b?)",
1823 "VCVTPS2UQQZ128rm(b?)",
1824 "VCVTQQ2PDZ128rm(b?)",
1825 "VCVTQQ2PSZ128rm(b?)",
1826 "VCVTSS2SDZrm",
1827 "(V?)CVTSS2SDrm",
1828 "VCVTTPD2QQZ128rm(b?)",
1829 "VCVTTPD2UQQZ128rm(b?)",
1830 "VCVTTPS2DQZ128rm(b?)",
1831 "(V?)CVTTPS2DQrm",
1832 "VCVTTPS2QQZ128rm(b?)",
1833 "VCVTTPS2UDQZ128rm(b?)",
1834 "VCVTTPS2UQQZ128rm(b?)",
1835 "VCVTUDQ2PDZ128rm(b?)",
1836 "VCVTUDQ2PSZ128rm(b?)",
1837 "VCVTUQQ2PDZ128rm(b?)",
1838 "VCVTUQQ2PSZ128rm(b?)")>;
1840 def SKXWriteResGroup151 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1841 let Latency = 10;
1842 let NumMicroOps = 3;
1843 let ResourceCycles = [2,1];
1844 }
1845 def: InstRW<[SKXWriteResGroup151], (instregex "VEXPANDPDZ128rm(b?)",
1846 "VEXPANDPSZ128rm(b?)",
1847 "VPEXPANDDZ128rm(b?)",
1848 "VPEXPANDQZ128rm(b?)")>;
1850 def SKXWriteResGroup153 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
1851 let Latency = 10;
1852 let NumMicroOps = 3;
1853 let ResourceCycles = [1,1,1];
1854 }
1855 def: InstRW<[SKXWriteResGroup153], (instregex "(V?)CVTSD2SSrm")>;
1857 def SKXWriteResGroup154 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23]> {
1858 let Latency = 10;
1859 let NumMicroOps = 4;
1860 let ResourceCycles = [2,1,1];
1861 }
1862 def: InstRW<[SKXWriteResGroup154], (instrs VPHADDSWYrm,
1863 VPHSUBSWYrm)>;
1865 def SKXWriteResGroup157 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
1866 let Latency = 10;
1867 let NumMicroOps = 8;
1868 let ResourceCycles = [1,1,1,1,1,3];
1869 }
1870 def: InstRW<[SKXWriteResGroup157], (instregex "XCHG(8|16|32|64)rm")>;
1872 def SKXWriteResGroup159 : SchedWriteRes<[SKXPort0,SKXFPDivider]> {
1873 let Latency = 11;
1874 let NumMicroOps = 1;
1875 let ResourceCycles = [1,3];
1876 }
1877 def : SchedAlias<WriteFDivX, SKXWriteResGroup159>; // TODO - convert to ZnWriteResFpuPair
1879 def SKXWriteResGroup160 : SchedWriteRes<[SKXPort0,SKXPort23]> {
1880 let Latency = 11;
1881 let NumMicroOps = 2;
1882 let ResourceCycles = [1,1];
1883 }
1884 def: InstRW<[SKXWriteResGroup160], (instregex "MUL_F(32|64)m")>;
1886 def SKXWriteResGroup161 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1887 let Latency = 11;
1888 let NumMicroOps = 2;
1889 let ResourceCycles = [1,1];
1890 }
1891 def: InstRW<[SKXWriteResGroup161], (instrs VCVTDQ2PSYrm,
1892 VCVTPS2PDYrm)>;
1893 def: InstRW<[SKXWriteResGroup161], (instregex "VCVTDQ2(PD|PS)(Z|Z256)rm(b?)",
1894 "VCVTPH2PS(Z|Z256)rm(b?)",
1895 "VCVTPS2PD(Z|Z256)rm(b?)",
1896 "VCVTQQ2PD(Z|Z256)rm(b?)",
1897 "VCVTQQ2PSZ256rm(b?)",
1898 "VCVT(T?)PD2QQ(Z|Z256)rm(b?)",
1899 "VCVT(T?)PD2UQQ(Z|Z256)rm(b?)",
1900 "VCVT(T?)PS2DQYrm",
1901 "VCVT(T?)PS2DQ(Z|Z256)rm(b?)",
1902 "VCVT(T?)PS2QQZ256rm(b?)",
1903 "VCVT(T?)PS2UDQ(Z|Z256)rm(b?)",
1904 "VCVT(T?)PS2UQQZ256rm(b?)",
1905 "VCVTUDQ2(PD|PS)(Z|Z256)rm(b?)",
1906 "VCVTUQQ2PD(Z|Z256)rm(b?)",
1907 "VCVTUQQ2PSZ256rm(b?)")>;
1909 def SKXWriteResGroup162 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1910 let Latency = 11;
1911 let NumMicroOps = 3;
1912 let ResourceCycles = [2,1];
1913 }
1914 def: InstRW<[SKXWriteResGroup162], (instregex "FICOM(P?)(16|32)m",
1915 "VEXPANDPD(Z|Z256)rm(b?)",
1916 "VEXPANDPS(Z|Z256)rm(b?)",
1917 "VPEXPANDD(Z|Z256)rm(b?)",
1918 "VPEXPANDQ(Z|Z256)rm(b?)")>;
1920 def SKXWriteResGroup163 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1921 let Latency = 11;
1922 let NumMicroOps = 3;
1923 let ResourceCycles = [1,2];
1924 }
1925 def: InstRW<[SKXWriteResGroup163], (instregex "VCVTSD2SSZrm")>;
1927 def SKXWriteResGroup164 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
1928 let Latency = 11;
1929 let NumMicroOps = 3;
1930 let ResourceCycles = [1,1,1];
1931 }
1932 def: InstRW<[SKXWriteResGroup164], (instregex "(V?)CVTDQ2PDrm")>;
1934 def SKXWriteResGroup166 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
1935 let Latency = 11;
1936 let NumMicroOps = 3;
1937 let ResourceCycles = [1,1,1];
1938 }
1939 def: InstRW<[SKXWriteResGroup166], (instrs CVTPD2PSrm,
1940 CVTPD2DQrm,
1941 CVTTPD2DQrm,
1942 MMX_CVTPD2PIirm,
1943 MMX_CVTTPD2PIirm)>;
1945 def SKXWriteResGroup167 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
1946 let Latency = 11;
1947 let NumMicroOps = 4;
1948 let ResourceCycles = [2,1,1];
1949 }
1950 def: InstRW<[SKXWriteResGroup167], (instregex "VPCONFLICTQZ128rm(b?)")>;
1952 def SKXWriteResGroup169 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort0156]> {
1953 let Latency = 11;
1954 let NumMicroOps = 7;
1955 let ResourceCycles = [2,3,2];
1956 }
1957 def: InstRW<[SKXWriteResGroup169], (instregex "RCL(16|32|64)rCL",
1958 "RCR(16|32|64)rCL")>;
1960 def SKXWriteResGroup170 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort15,SKXPort0156]> {
1961 let Latency = 11;
1962 let NumMicroOps = 9;
1963 let ResourceCycles = [1,5,1,2];
1964 }
1965 def: InstRW<[SKXWriteResGroup170], (instrs RCL8rCL)>;
1967 def SKXWriteResGroup171 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
1968 let Latency = 11;
1969 let NumMicroOps = 11;
1970 let ResourceCycles = [2,9];
1971 }
1972 def: InstRW<[SKXWriteResGroup171], (instrs LOOPE, LOOPNE)>;
1974 def SKXWriteResGroup174 : SchedWriteRes<[SKXPort01]> {
1975 let Latency = 15;
1976 let NumMicroOps = 3;
1977 let ResourceCycles = [3];
1978 }
1979 def: InstRW<[SKXWriteResGroup174], (instregex "VPMULLQ(Z128|Z256)rr")>;
1981 def SKXWriteResGroup174z : SchedWriteRes<[SKXPort05]> {
1982 let Latency = 15;
1983 let NumMicroOps = 3;
1984 let ResourceCycles = [3];
1985 }
1986 def: InstRW<[SKXWriteResGroup174z], (instregex "VPMULLQZrr")>;
1988 def SKXWriteResGroup175 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1989 let Latency = 12;
1990 let NumMicroOps = 3;
1991 let ResourceCycles = [2,1];
1992 }
1993 def: InstRW<[SKXWriteResGroup175], (instregex "VPERMWZ128rm(b?)")>;
1995 def SKXWriteResGroup176 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015]> {
1996 let Latency = 12;
1997 let NumMicroOps = 3;
1998 let ResourceCycles = [1,1,1];
1999 }
2000 def: InstRW<[SKXWriteResGroup176], (instregex "VCVT(T?)SD2USIZrm(b?)",
2001 "VCVT(T?)SS2USI64Zrm(b?)")>;
2003 def SKXWriteResGroup177 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
2004 let Latency = 12;
2005 let NumMicroOps = 3;
2006 let ResourceCycles = [1,1,1];
2007 }
2008 def: InstRW<[SKXWriteResGroup177], (instregex "VCVT(T?)PS2QQZrm(b?)",
2009 "VCVT(T?)PS2UQQZrm(b?)")>;
2011 def SKXWriteResGroup179 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23,SKXPort015]> {
2012 let Latency = 12;
2013 let NumMicroOps = 4;
2014 let ResourceCycles = [1,1,1,1];
2015 }
2016 def: InstRW<[SKXWriteResGroup179], (instregex "CVTTSS2SI64rm")>;
2018 def SKXWriteResGroup180 : SchedWriteRes<[SKXPort5,SKXPort23]> {
2019 let Latency = 13;
2020 let NumMicroOps = 3;
2021 let ResourceCycles = [2,1];
2022 }
2023 def: InstRW<[SKXWriteResGroup180], (instregex "(ADD|SUB|SUBR)_FI(16|32)m",
2024 "VPERMWZ256rm(b?)",
2025 "VPERMWZrm(b?)")>;
2027 def SKXWriteResGroup181 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
2028 let Latency = 13;
2029 let NumMicroOps = 3;
2030 let ResourceCycles = [1,1,1];
2031 }
2032 def: InstRW<[SKXWriteResGroup181], (instrs VCVTDQ2PDYrm)>;
2034 def SKXWriteResGroup183 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
2035 let Latency = 13;
2036 let NumMicroOps = 4;
2037 let ResourceCycles = [2,1,1];
2038 }
2039 def: InstRW<[SKXWriteResGroup183], (instregex "VPERMI2W128rm(b?)",
2040 "VPERMT2W128rm(b?)")>;
2042 def SKXWriteResGroup184 : SchedWriteRes<[SKXPort0,SKXFPDivider]> {
2043 let Latency = 14;
2044 let NumMicroOps = 1;
2045 let ResourceCycles = [1,3];
2046 }
2047 def : SchedAlias<WriteFDiv64, SKXWriteResGroup184>; // TODO - convert to ZnWriteResFpuPair
2048 def : SchedAlias<WriteFDiv64X, SKXWriteResGroup184>; // TODO - convert to ZnWriteResFpuPair
2050 def SKXWriteResGroup184_1 : SchedWriteRes<[SKXPort0,SKXFPDivider]> {
2051 let Latency = 14;
2052 let NumMicroOps = 1;
2053 let ResourceCycles = [1,5];
2054 }
2055 def : SchedAlias<WriteFDiv64Y, SKXWriteResGroup184_1>; // TODO - convert to ZnWriteResFpuPair
2057 def SKXWriteResGroup187 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
2058 let Latency = 14;
2059 let NumMicroOps = 3;
2060 let ResourceCycles = [1,1,1];
2061 }
2062 def: InstRW<[SKXWriteResGroup187], (instregex "MUL_FI(16|32)m")>;
2064 def SKXWriteResGroup188 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
2065 let Latency = 14;
2066 let NumMicroOps = 3;
2067 let ResourceCycles = [1,1,1];
2068 }
2069 def: InstRW<[SKXWriteResGroup188], (instregex "VCVTPD2DQZrm(b?)",
2070 "VCVTPD2PSZrm(b?)",
2071 "VCVTPD2UDQZrm(b?)",
2072 "VCVTQQ2PSZrm(b?)",
2073 "VCVTTPD2DQZrm(b?)",
2074 "VCVTTPD2UDQZrm(b?)",
2075 "VCVTUQQ2PSZrm(b?)")>;
2077 def SKXWriteResGroup189 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
2078 let Latency = 14;
2079 let NumMicroOps = 4;
2080 let ResourceCycles = [2,1,1];
2081 }
2082 def: InstRW<[SKXWriteResGroup189], (instregex "VPERMI2W256rm(b?)",
2083 "VPERMI2Wrm(b?)",
2084 "VPERMT2W256rm(b?)",
2085 "VPERMT2Wrm(b?)")>;
2087 def SKXWriteResGroup190 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort15,SKXPort0156]> {
2088 let Latency = 14;
2089 let NumMicroOps = 10;
2090 let ResourceCycles = [2,4,1,3];
2091 }
2092 def: InstRW<[SKXWriteResGroup190], (instrs RCR8rCL)>;
2094 def SKXWriteResGroup191 : SchedWriteRes<[SKXPort0]> {
2095 let Latency = 15;
2096 let NumMicroOps = 1;
2097 let ResourceCycles = [1];
2098 }
2099 def: InstRW<[SKXWriteResGroup191], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>;
2101 def SKXWriteResGroup194 : SchedWriteRes<[SKXPort1,SKXPort5,SKXPort01,SKXPort23,SKXPort015]> {
2102 let Latency = 15;
2103 let NumMicroOps = 8;
2104 let ResourceCycles = [1,2,2,1,2];
2105 }
2106 def: InstRW<[SKXWriteResGroup194], (instregex "VPCONFLICTDZ128rm(b?)")>;
2108 def SKXWriteResGroup195 : SchedWriteRes<[SKXPort1,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> {
2109 let Latency = 15;
2110 let NumMicroOps = 10;
2111 let ResourceCycles = [1,1,1,5,1,1];
2112 }
2113 def: InstRW<[SKXWriteResGroup195], (instregex "RCL(8|16|32|64)mCL")>;
2115 def SKXWriteResGroup199 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> {
2116 let Latency = 16;
2117 let NumMicroOps = 14;
2118 let ResourceCycles = [1,1,1,4,2,5];
2119 }
2120 def: InstRW<[SKXWriteResGroup199], (instrs CMPXCHG8B)>;
2122 def SKXWriteResGroup200 : SchedWriteRes<[SKXPort1, SKXPort05, SKXPort6]> {
2123 let Latency = 12;
2124 let NumMicroOps = 34;
2125 let ResourceCycles = [1, 4, 5];
2126 }
2127 def: InstRW<[SKXWriteResGroup200], (instrs VZEROALL)>;
2129 def SKXWriteResGroup201 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> {
2130 let Latency = 17;
2131 let NumMicroOps = 2;
2132 let ResourceCycles = [1,1,5];
2133 }
2134 def : SchedAlias<WriteFDivXLd, SKXWriteResGroup201>; // TODO - convert to ZnWriteResFpuPair
2136 def SKXWriteResGroup202 : SchedWriteRes<[SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156]> {
2137 let Latency = 17;
2138 let NumMicroOps = 15;
2139 let ResourceCycles = [2,1,2,4,2,4];
2140 }
2141 def: InstRW<[SKXWriteResGroup202], (instrs XCH_F)>;
2143 def SKXWriteResGroup205 : SchedWriteRes<[SKXPort23,SKXPort01]> {
2144 let Latency = 21;
2145 let NumMicroOps = 4;
2146 let ResourceCycles = [1,3];
2147 }
2148 def: InstRW<[SKXWriteResGroup205], (instregex "VPMULLQZ128rm(b?)")>;
2150 def SKXWriteResGroup207 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort06,SKXPort0156]> {
2151 let Latency = 18;
2152 let NumMicroOps = 8;
2153 let ResourceCycles = [1,1,1,5];
2154 }
2155 def: InstRW<[SKXWriteResGroup207], (instrs CPUID, RDTSC)>;
2157 def SKXWriteResGroup208 : SchedWriteRes<[SKXPort1,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> {
2158 let Latency = 18;
2159 let NumMicroOps = 11;
2160 let ResourceCycles = [2,1,1,4,1,2];
2161 }
2162 def: InstRW<[SKXWriteResGroup208], (instregex "RCR(8|16|32|64)mCL")>;
2164 def SKXWriteResGroup209 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> {
2165 let Latency = 19;
2166 let NumMicroOps = 2;
2167 let ResourceCycles = [1,1,4];
2168 }
2169 def : SchedAlias<WriteFDiv64Ld, SKXWriteResGroup209>; // TODO - convert to ZnWriteResFpuPair
2171 def SKXWriteResGroup211 : SchedWriteRes<[SKXPort23,SKXPort01]> {
2172 let Latency = 22;
2173 let NumMicroOps = 4;
2174 let ResourceCycles = [1,3];
2175 }
2176 def: InstRW<[SKXWriteResGroup211], (instregex "VPMULLQZ256rm(b?)")>;
2178 def SKXWriteResGroup211_1 : SchedWriteRes<[SKXPort23,SKXPort05]> {
2179 let Latency = 22;
2180 let NumMicroOps = 4;
2181 let ResourceCycles = [1,3];
2182 }
2183 def: InstRW<[SKXWriteResGroup211_1], (instregex "VPMULLQZrm(b?)")>;
2185 def SKXWriteResGroup215 : SchedWriteRes<[SKXPort0]> {
2186 let Latency = 20;
2187 let NumMicroOps = 1;
2188 let ResourceCycles = [1];
2189 }
2190 def: InstRW<[SKXWriteResGroup215], (instregex "DIV_(FPrST0|FST0r|FrST0)")>;
2192 def SKXWriteResGroup216 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> {
2193 let Latency = 20;
2194 let NumMicroOps = 2;
2195 let ResourceCycles = [1,1,4];
2196 }
2197 def : SchedAlias<WriteFDiv64XLd, SKXWriteResGroup216>; // TODO - convert to ZnWriteResFpuPair
2199 def SKXWriteGatherEVEX2 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
2200 let Latency = 17;
2201 let NumMicroOps = 5; // 2 uops perform multiple loads
2202 let ResourceCycles = [1,2,1,1];
2203 }
2204 def: InstRW<[SKXWriteGatherEVEX2], (instrs VGATHERQPSZ128rm, VPGATHERQDZ128rm,
2205 VGATHERDPDZ128rm, VPGATHERDQZ128rm,
2206 VGATHERQPDZ128rm, VPGATHERQQZ128rm)>;
2208 def SKXWriteGatherEVEX4 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
2209 let Latency = 19;
2210 let NumMicroOps = 5; // 2 uops perform multiple loads
2211 let ResourceCycles = [1,4,1,1];
2212 }
2213 def: InstRW<[SKXWriteGatherEVEX4], (instrs VGATHERQPSZ256rm, VPGATHERQDZ256rm,
2214 VGATHERQPDZ256rm, VPGATHERQQZ256rm,
2215 VGATHERDPSZ128rm, VPGATHERDDZ128rm,
2216 VGATHERDPDZ256rm, VPGATHERDQZ256rm)>;
2218 def SKXWriteGatherEVEX8 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
2219 let Latency = 21;
2220 let NumMicroOps = 5; // 2 uops perform multiple loads
2221 let ResourceCycles = [1,8,1,1];
2222 }
2223 def: InstRW<[SKXWriteGatherEVEX8], (instrs VGATHERDPSZ256rm, VPGATHERDDZ256rm,
2224 VGATHERDPDZrm, VPGATHERDQZrm,
2225 VGATHERQPDZrm, VPGATHERQQZrm,
2226 VGATHERQPSZrm, VPGATHERQDZrm)>;
2228 def SKXWriteGatherEVEX16 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
2229 let Latency = 25;
2230 let NumMicroOps = 5; // 2 uops perform multiple loads
2231 let ResourceCycles = [1,16,1,1];
2232 }
2233 def: InstRW<[SKXWriteGatherEVEX16], (instrs VGATHERDPSZrm, VPGATHERDDZrm)>;
2235 def SKXWriteResGroup219 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
2236 let Latency = 20;
2237 let NumMicroOps = 8;
2238 let ResourceCycles = [1,1,1,1,1,1,2];
2239 }
2240 def: InstRW<[SKXWriteResGroup219], (instrs INSB, INSL, INSW)>;
2242 def SKXWriteResGroup220 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort0156]> {
2243 let Latency = 20;
2244 let NumMicroOps = 10;
2245 let ResourceCycles = [1,2,7];
2246 }
2247 def: InstRW<[SKXWriteResGroup220], (instrs MWAITrr)>;
2249 def SKXWriteResGroup222 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> {
2250 let Latency = 21;
2251 let NumMicroOps = 2;
2252 let ResourceCycles = [1,1,8];
2253 }
2254 def : SchedAlias<WriteFDiv64YLd, SKXWriteResGroup222>; // TODO - convert to ZnWriteResFpuPair
2256 def SKXWriteResGroup223 : SchedWriteRes<[SKXPort0,SKXPort23]> {
2257 let Latency = 22;
2258 let NumMicroOps = 2;
2259 let ResourceCycles = [1,1];
2260 }
2261 def: InstRW<[SKXWriteResGroup223], (instregex "DIV_F(32|64)m")>;
2263 def SKXWriteResGroupVEX2 : SchedWriteRes<[SKXPort0, SKXPort23, SKXPort5, SKXPort015]> {
2264 let Latency = 18;
2265 let NumMicroOps = 5; // 2 uops perform multiple loads
2266 let ResourceCycles = [1,2,1,1];
2267 }
2268 def: InstRW<[SKXWriteResGroupVEX2], (instrs VGATHERDPDrm, VPGATHERDQrm,
2269 VGATHERQPDrm, VPGATHERQQrm,
2270 VGATHERQPSrm, VPGATHERQDrm)>;
2272 def SKXWriteResGroupVEX4 : SchedWriteRes<[SKXPort0, SKXPort23, SKXPort5, SKXPort015]> {
2273 let Latency = 20;
2274 let NumMicroOps = 5; // 2 uops peform multiple loads
2275 let ResourceCycles = [1,4,1,1];
2276 }
2277 def: InstRW<[SKXWriteResGroupVEX4], (instrs VGATHERDPDYrm, VPGATHERDQYrm,
2278 VGATHERDPSrm, VPGATHERDDrm,
2279 VGATHERQPDYrm, VPGATHERQQYrm,
2280 VGATHERQPSYrm, VPGATHERQDYrm)>;
2282 def SKXWriteResGroupVEX8 : SchedWriteRes<[SKXPort0, SKXPort23, SKXPort5, SKXPort015]> {
2283 let Latency = 22;
2284 let NumMicroOps = 5; // 2 uops perform multiple loads
2285 let ResourceCycles = [1,8,1,1];
2286 }
2287 def: InstRW<[SKXWriteResGroupVEX8], (instrs VGATHERDPSYrm, VPGATHERDDYrm)>;
2289 def SKXWriteResGroup225 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> {
2290 let Latency = 22;
2291 let NumMicroOps = 14;
2292 let ResourceCycles = [5,5,4];
2293 }
2294 def: InstRW<[SKXWriteResGroup225], (instregex "VPCONFLICTDZ128rr",
2295 "VPCONFLICTQZ256rr")>;
2297 def SKXWriteResGroup228 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
2298 let Latency = 23;
2299 let NumMicroOps = 19;
2300 let ResourceCycles = [2,1,4,1,1,4,6];
2301 }
2302 def: InstRW<[SKXWriteResGroup228], (instrs CMPXCHG16B)>;
2304 def SKXWriteResGroup233 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
2305 let Latency = 25;
2306 let NumMicroOps = 3;
2307 let ResourceCycles = [1,1,1];
2308 }
2309 def: InstRW<[SKXWriteResGroup233], (instregex "DIV_FI(16|32)m")>;
2311 def SKXWriteResGroup239 : SchedWriteRes<[SKXPort0,SKXPort23]> {
2312 let Latency = 27;
2313 let NumMicroOps = 2;
2314 let ResourceCycles = [1,1];
2315 }
2316 def: InstRW<[SKXWriteResGroup239], (instregex "DIVR_F(32|64)m")>;
2318 def SKXWriteResGroup242 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> {
2319 let Latency = 29;
2320 let NumMicroOps = 15;
2321 let ResourceCycles = [5,5,1,4];
2322 }
2323 def: InstRW<[SKXWriteResGroup242], (instregex "VPCONFLICTQZ256rm(b?)")>;
2325 def SKXWriteResGroup243 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
2326 let Latency = 30;
2327 let NumMicroOps = 3;
2328 let ResourceCycles = [1,1,1];
2329 }
2330 def: InstRW<[SKXWriteResGroup243], (instregex "DIVR_FI(16|32)m")>;
2332 def SKXWriteResGroup247 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort23,SKXPort06,SKXPort0156]> {
2333 let Latency = 35;
2334 let NumMicroOps = 23;
2335 let ResourceCycles = [1,5,3,4,10];
2336 }
2337 def: InstRW<[SKXWriteResGroup247], (instregex "IN(8|16|32)ri",
2338 "IN(8|16|32)rr")>;
2340 def SKXWriteResGroup248 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
2341 let Latency = 35;
2342 let NumMicroOps = 23;
2343 let ResourceCycles = [1,5,2,1,4,10];
2344 }
2345 def: InstRW<[SKXWriteResGroup248], (instregex "OUT(8|16|32)ir",
2346 "OUT(8|16|32)rr")>;
2348 def SKXWriteResGroup249 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> {
2349 let Latency = 37;
2350 let NumMicroOps = 21;
2351 let ResourceCycles = [9,7,5];
2352 }
2353 def: InstRW<[SKXWriteResGroup249], (instregex "VPCONFLICTDZ256rr",
2354 "VPCONFLICTQZrr")>;
2356 def SKXWriteResGroup250 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort23,SKXPort0156]> {
2357 let Latency = 37;
2358 let NumMicroOps = 31;
2359 let ResourceCycles = [1,8,1,21];
2360 }
2361 def: InstRW<[SKXWriteResGroup250], (instregex "XRSTOR(64)?")>;
2363 def SKXWriteResGroup252 : SchedWriteRes<[SKXPort1,SKXPort4,SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort15,SKXPort0156]> {
2364 let Latency = 40;
2365 let NumMicroOps = 18;
2366 let ResourceCycles = [1,1,2,3,1,1,1,8];
2367 }
2368 def: InstRW<[SKXWriteResGroup252], (instrs VMCLEARm)>;
2370 def SKXWriteResGroup253 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> {
2371 let Latency = 41;
2372 let NumMicroOps = 39;
2373 let ResourceCycles = [1,10,1,1,26];
2374 }
2375 def: InstRW<[SKXWriteResGroup253], (instrs XSAVE64)>;
2377 def SKXWriteResGroup254 : SchedWriteRes<[SKXPort5,SKXPort0156]> {
2378 let Latency = 42;
2379 let NumMicroOps = 22;
2380 let ResourceCycles = [2,20];
2381 }
2382 def: InstRW<[SKXWriteResGroup254], (instrs RDTSCP)>;
2384 def SKXWriteResGroup255 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> {
2385 let Latency = 42;
2386 let NumMicroOps = 40;
2387 let ResourceCycles = [1,11,1,1,26];
2388 }
2389 def: InstRW<[SKXWriteResGroup255], (instrs XSAVE)>;
2390 def: InstRW<[SKXWriteResGroup255], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>;
2392 def SKXWriteResGroup256 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> {
2393 let Latency = 44;
2394 let NumMicroOps = 22;
2395 let ResourceCycles = [9,7,1,5];
2396 }
2397 def: InstRW<[SKXWriteResGroup256], (instregex "VPCONFLICTDZ256rm(b?)",
2398 "VPCONFLICTQZrm(b?)")>;
2400 def SKXWriteResGroup258 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort05,SKXPort06,SKXPort0156]> {
2401 let Latency = 62;
2402 let NumMicroOps = 64;
2403 let ResourceCycles = [2,8,5,10,39];
2404 }
2405 def: InstRW<[SKXWriteResGroup258], (instrs FLDENVm)>;
2407 def SKXWriteResGroup259 : SchedWriteRes<[SKXPort0,SKXPort6,SKXPort23,SKXPort05,SKXPort06,SKXPort15,SKXPort0156]> {
2408 let Latency = 63;
2409 let NumMicroOps = 88;
2410 let ResourceCycles = [4,4,31,1,2,1,45];
2411 }
2412 def: InstRW<[SKXWriteResGroup259], (instrs FXRSTOR64)>;
2414 def SKXWriteResGroup260 : SchedWriteRes<[SKXPort0,SKXPort6,SKXPort23,SKXPort05,SKXPort06,SKXPort15,SKXPort0156]> {
2415 let Latency = 63;
2416 let NumMicroOps = 90;
2417 let ResourceCycles = [4,2,33,1,2,1,47];
2418 }
2419 def: InstRW<[SKXWriteResGroup260], (instrs FXRSTOR)>;
2421 def SKXWriteResGroup261 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> {
2422 let Latency = 67;
2423 let NumMicroOps = 35;
2424 let ResourceCycles = [17,11,7];
2425 }
2426 def: InstRW<[SKXWriteResGroup261], (instregex "VPCONFLICTDZrr")>;
2428 def SKXWriteResGroup262 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> {
2429 let Latency = 74;
2430 let NumMicroOps = 36;
2431 let ResourceCycles = [17,11,1,7];
2432 }
2433 def: InstRW<[SKXWriteResGroup262], (instregex "VPCONFLICTDZrm(b?)")>;
2435 def SKXWriteResGroup263 : SchedWriteRes<[SKXPort5,SKXPort05,SKXPort0156]> {
2436 let Latency = 75;
2437 let NumMicroOps = 15;
2438 let ResourceCycles = [6,3,6];
2439 }
2440 def: InstRW<[SKXWriteResGroup263], (instrs FNINIT)>;
2442 def SKXWriteResGroup266 : SchedWriteRes<[SKXPort0,SKXPort1,SKXPort4,SKXPort5,SKXPort6,SKXPort237,SKXPort06,SKXPort0156]> {
2443 let Latency = 106;
2444 let NumMicroOps = 100;
2445 let ResourceCycles = [9,1,11,16,1,11,21,30];
2446 }
2447 def: InstRW<[SKXWriteResGroup266], (instrs FSTENVm)>;
2449 def SKXWriteResGroup267 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
2450 let Latency = 140;
2451 let NumMicroOps = 4;
2452 let ResourceCycles = [1,3];
2453 }
2454 def: InstRW<[SKXWriteResGroup267], (instrs PAUSE)>;
2456 def: InstRW<[WriteZero], (instrs CLC)>;
2459 // Instruction variants handled by the renamer. These might not need execution
2460 // ports in certain conditions.
2461 // See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs",
2462 // section "Skylake Pipeline" > "Register allocation and renaming".
2463 // These can be investigated with llvm-exegesis, e.g.
2464 // echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
2465 // echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
2467 def SKXWriteZeroLatency : SchedWriteRes<[]> {
2468 let Latency = 0;
2469 }
2471 def SKXWriteZeroIdiom : SchedWriteVariant<[
2472 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2473 SchedVar<NoSchedPred, [WriteALU]>
2474 ]>;
2475 def : InstRW<[SKXWriteZeroIdiom], (instrs SUB32rr, SUB64rr,
2476 XOR32rr, XOR64rr)>;
2478 def SKXWriteFZeroIdiom : SchedWriteVariant<[
2479 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2480 SchedVar<NoSchedPred, [WriteFLogic]>
2481 ]>;
2482 def : InstRW<[SKXWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr,
2483 XORPDrr, VXORPDrr,
2484 VXORPSZ128rr,
2485 VXORPDZ128rr)>;
2487 def SKXWriteFZeroIdiomY : SchedWriteVariant<[
2488 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2489 SchedVar<NoSchedPred, [WriteFLogicY]>
2490 ]>;
2491 def : InstRW<[SKXWriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr,
2492 VXORPSZ256rr, VXORPDZ256rr)>;
2494 def SKXWriteFZeroIdiomZ : SchedWriteVariant<[
2495 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2496 SchedVar<NoSchedPred, [WriteFLogicZ]>
2497 ]>;
2498 def : InstRW<[SKXWriteFZeroIdiomZ], (instrs VXORPSZrr, VXORPDZrr)>;
2500 def SKXWriteVZeroIdiomLogicX : SchedWriteVariant<[
2501 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2502 SchedVar<NoSchedPred, [WriteVecLogicX]>
2503 ]>;
2504 def : InstRW<[SKXWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr,
2505 VPXORDZ128rr, VPXORQZ128rr)>;
2507 def SKXWriteVZeroIdiomLogicY : SchedWriteVariant<[
2508 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2509 SchedVar<NoSchedPred, [WriteVecLogicY]>
2510 ]>;
2511 def : InstRW<[SKXWriteVZeroIdiomLogicY], (instrs VPXORYrr,
2512 VPXORDZ256rr, VPXORQZ256rr)>;
2514 def SKXWriteVZeroIdiomLogicZ : SchedWriteVariant<[
2515 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2516 SchedVar<NoSchedPred, [WriteVecLogicZ]>
2517 ]>;
2518 def : InstRW<[SKXWriteVZeroIdiomLogicZ], (instrs VPXORDZrr, VPXORQZrr)>;
2520 def SKXWriteVZeroIdiomALUX : SchedWriteVariant<[
2521 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2522 SchedVar<NoSchedPred, [WriteVecALUX]>
2523 ]>;
2524 def : InstRW<[SKXWriteVZeroIdiomALUX], (instrs PCMPGTBrr, VPCMPGTBrr,
2525 PCMPGTDrr, VPCMPGTDrr,
2526 PCMPGTWrr, VPCMPGTWrr)>;
2528 def SKXWriteVZeroIdiomALUY : SchedWriteVariant<[
2529 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2530 SchedVar<NoSchedPred, [WriteVecALUY]>
2531 ]>;
2532 def : InstRW<[SKXWriteVZeroIdiomALUY], (instrs VPCMPGTBYrr,
2533 VPCMPGTDYrr,
2534 VPCMPGTWYrr)>;
2536 def SKXWritePSUB : SchedWriteRes<[SKXPort015]> {
2537 let Latency = 1;
2538 let NumMicroOps = 1;
2539 let ResourceCycles = [1];
2540 }
2542 def SKXWriteVZeroIdiomPSUB : SchedWriteVariant<[
2543 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2544 SchedVar<NoSchedPred, [SKXWritePSUB]>
2545 ]>;
2547 def : InstRW<[SKXWriteVZeroIdiomPSUB], (instrs PSUBBrr, VPSUBBrr, VPSUBBZ128rr,
2548 PSUBDrr, VPSUBDrr, VPSUBDZ128rr,
2549 PSUBQrr, VPSUBQrr, VPSUBQZ128rr,
2550 PSUBWrr, VPSUBWrr, VPSUBWZ128rr,
2551 VPSUBBYrr, VPSUBBZ256rr,
2552 VPSUBDYrr, VPSUBDZ256rr,
2553 VPSUBQYrr, VPSUBQZ256rr,
2554 VPSUBWYrr, VPSUBWZ256rr,
2555 VPSUBBZrr,
2556 VPSUBDZrr,
2557 VPSUBQZrr,
2558 VPSUBWZrr)>;
2559 def SKXWritePCMPGTQ : SchedWriteRes<[SKXPort5]> {
2560 let Latency = 3;
2561 let NumMicroOps = 1;
2562 let ResourceCycles = [1];
2563 }
2565 def SKXWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[
2566 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2567 SchedVar<NoSchedPred, [SKXWritePCMPGTQ]>
2568 ]>;
2569 def : InstRW<[SKXWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr,
2570 VPCMPGTQYrr)>;
2573 // CMOVs that use both Z and C flag require an extra uop.
2574 def SKXWriteCMOVA_CMOVBErr : SchedWriteRes<[SKXPort06]> {
2575 let Latency = 2;
2576 let ResourceCycles = [2];
2577 let NumMicroOps = 2;
2578 }
2580 def SKXWriteCMOVA_CMOVBErm : SchedWriteRes<[SKXPort23,SKXPort06]> {
2581 let Latency = 7;
2582 let ResourceCycles = [1,2];
2583 let NumMicroOps = 3;
2584 }
2586 def SKXCMOVA_CMOVBErr : SchedWriteVariant<[
2587 SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [SKXWriteCMOVA_CMOVBErr]>,
2588 SchedVar<NoSchedPred, [WriteCMOV]>
2589 ]>;
2591 def SKXCMOVA_CMOVBErm : SchedWriteVariant<[
2592 SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [SKXWriteCMOVA_CMOVBErm]>,
2593 SchedVar<NoSchedPred, [WriteCMOV.Folded]>
2594 ]>;
2596 def : InstRW<[SKXCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>;
2597 def : InstRW<[SKXCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>;
2599 // SETCCs that use both Z and C flag require an extra uop.
2600 def SKXWriteSETA_SETBEr : SchedWriteRes<[SKXPort06]> {
2601 let Latency = 2;
2602 let ResourceCycles = [2];
2603 let NumMicroOps = 2;
2604 }
2606 def SKXWriteSETA_SETBEm : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort06]> {
2607 let Latency = 3;
2608 let ResourceCycles = [1,1,2];
2609 let NumMicroOps = 4;
2610 }
2612 def SKXSETA_SETBErr : SchedWriteVariant<[
2613 SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [SKXWriteSETA_SETBEr]>,
2614 SchedVar<NoSchedPred, [WriteSETCC]>
2615 ]>;
2617 def SKXSETA_SETBErm : SchedWriteVariant<[
2618 SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [SKXWriteSETA_SETBEm]>,
2619 SchedVar<NoSchedPred, [WriteSETCCStore]>
2620 ]>;
2622 def : InstRW<[SKXSETA_SETBErr], (instrs SETCCr)>;
2623 def : InstRW<[SKXSETA_SETBErm], (instrs SETCCm)>;
2625 } // SchedModel