| blob | 18b60d774775a46ffd7ccc25b77d213850dcff63 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK,CHECK-CVT
3 ; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FP16
5 ;
6 ; 32-bit float to unsigned integer
7 ;
9 declare i1 @llvm.fptoui.sat.i1.f32 (float)
10 declare i8 @llvm.fptoui.sat.i8.f32 (float)
11 declare i13 @llvm.fptoui.sat.i13.f32 (float)
12 declare i16 @llvm.fptoui.sat.i16.f32 (float)
13 declare i19 @llvm.fptoui.sat.i19.f32 (float)
14 declare i32 @llvm.fptoui.sat.i32.f32 (float)
15 declare i50 @llvm.fptoui.sat.i50.f32 (float)
16 declare i64 @llvm.fptoui.sat.i64.f32 (float)
17 declare i100 @llvm.fptoui.sat.i100.f32(float)
18 declare i128 @llvm.fptoui.sat.i128.f32(float)
20 define i1 @test_unsigned_i1_f32(float %f) nounwind {
21 ; CHECK-LABEL: test_unsigned_i1_f32:
22 ; CHECK: // %bb.0:
23 ; CHECK-NEXT: movi d1, #0000000000000000
24 ; CHECK-NEXT: fmaxnm s0, s0, s1
25 ; CHECK-NEXT: fmov s1, #1.00000000
26 ; CHECK-NEXT: fminnm s0, s0, s1
27 ; CHECK-NEXT: fcvtzu w8, s0
28 ; CHECK-NEXT: and w0, w8, #0x1
29 ; CHECK-NEXT: ret
30 %x = call i1 @llvm.fptoui.sat.i1.f32(float %f)
31 ret i1 %x
32 }
34 define i8 @test_unsigned_i8_f32(float %f) nounwind {
35 ; CHECK-LABEL: test_unsigned_i8_f32:
36 ; CHECK: // %bb.0:
37 ; CHECK-NEXT: movi d1, #0000000000000000
38 ; CHECK-NEXT: mov w8, #1132396544
39 ; CHECK-NEXT: fmaxnm s0, s0, s1
40 ; CHECK-NEXT: fmov s1, w8
41 ; CHECK-NEXT: fminnm s0, s0, s1
42 ; CHECK-NEXT: fcvtzu w0, s0
43 ; CHECK-NEXT: ret
44 %x = call i8 @llvm.fptoui.sat.i8.f32(float %f)
45 ret i8 %x
46 }
48 define i13 @test_unsigned_i13_f32(float %f) nounwind {
49 ; CHECK-LABEL: test_unsigned_i13_f32:
50 ; CHECK: // %bb.0:
51 ; CHECK-NEXT: mov w8, #63488
52 ; CHECK-NEXT: movi d1, #0000000000000000
53 ; CHECK-NEXT: movk w8, #17919, lsl #16
54 ; CHECK-NEXT: fmaxnm s0, s0, s1
55 ; CHECK-NEXT: fmov s1, w8
56 ; CHECK-NEXT: fminnm s0, s0, s1
57 ; CHECK-NEXT: fcvtzu w0, s0
58 ; CHECK-NEXT: ret
59 %x = call i13 @llvm.fptoui.sat.i13.f32(float %f)
60 ret i13 %x
61 }
63 define i16 @test_unsigned_i16_f32(float %f) nounwind {
64 ; CHECK-LABEL: test_unsigned_i16_f32:
65 ; CHECK: // %bb.0:
66 ; CHECK-NEXT: mov w8, #65280
67 ; CHECK-NEXT: movi d1, #0000000000000000
68 ; CHECK-NEXT: movk w8, #18303, lsl #16
69 ; CHECK-NEXT: fmaxnm s0, s0, s1
70 ; CHECK-NEXT: fmov s1, w8
71 ; CHECK-NEXT: fminnm s0, s0, s1
72 ; CHECK-NEXT: fcvtzu w0, s0
73 ; CHECK-NEXT: ret
74 %x = call i16 @llvm.fptoui.sat.i16.f32(float %f)
75 ret i16 %x
76 }
78 define i19 @test_unsigned_i19_f32(float %f) nounwind {
79 ; CHECK-LABEL: test_unsigned_i19_f32:
80 ; CHECK: // %bb.0:
81 ; CHECK-NEXT: mov w8, #65504
82 ; CHECK-NEXT: movi d1, #0000000000000000
83 ; CHECK-NEXT: movk w8, #18687, lsl #16
84 ; CHECK-NEXT: fmaxnm s0, s0, s1
85 ; CHECK-NEXT: fmov s1, w8
86 ; CHECK-NEXT: fminnm s0, s0, s1
87 ; CHECK-NEXT: fcvtzu w0, s0
88 ; CHECK-NEXT: ret
89 %x = call i19 @llvm.fptoui.sat.i19.f32(float %f)
90 ret i19 %x
91 }
93 define i32 @test_unsigned_i32_f32(float %f) nounwind {
94 ; CHECK-LABEL: test_unsigned_i32_f32:
95 ; CHECK: // %bb.0:
96 ; CHECK-NEXT: fcvtzu w0, s0
97 ; CHECK-NEXT: ret
98 %x = call i32 @llvm.fptoui.sat.i32.f32(float %f)
99 ret i32 %x
100 }
102 define i50 @test_unsigned_i50_f32(float %f) nounwind {
103 ; CHECK-LABEL: test_unsigned_i50_f32:
104 ; CHECK: // %bb.0:
105 ; CHECK-NEXT: mov w9, #1484783615
106 ; CHECK-NEXT: fcvtzu x8, s0
107 ; CHECK-NEXT: fcmp s0, #0.0
108 ; CHECK-NEXT: fmov s1, w9
109 ; CHECK-NEXT: csel x8, xzr, x8, lt
110 ; CHECK-NEXT: fcmp s0, s1
111 ; CHECK-NEXT: mov x9, #1125899906842623
112 ; CHECK-NEXT: csel x0, x9, x8, gt
113 ; CHECK-NEXT: ret
114 %x = call i50 @llvm.fptoui.sat.i50.f32(float %f)
115 ret i50 %x
116 }
118 define i64 @test_unsigned_i64_f32(float %f) nounwind {
119 ; CHECK-LABEL: test_unsigned_i64_f32:
120 ; CHECK: // %bb.0:
121 ; CHECK-NEXT: fcvtzu x0, s0
122 ; CHECK-NEXT: ret
123 %x = call i64 @llvm.fptoui.sat.i64.f32(float %f)
124 ret i64 %x
125 }
127 define i100 @test_unsigned_i100_f32(float %f) nounwind {
128 ; CHECK-LABEL: test_unsigned_i100_f32:
129 ; CHECK: // %bb.0:
130 ; CHECK-NEXT: str d8, [sp, #-16]! // 8-byte Folded Spill
131 ; CHECK-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
132 ; CHECK-NEXT: fmov s8, s0
133 ; CHECK-NEXT: bl __fixunssfti
134 ; CHECK-NEXT: mov w8, #1904214015
135 ; CHECK-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
136 ; CHECK-NEXT: fcmp s8, #0.0
137 ; CHECK-NEXT: fmov s0, w8
138 ; CHECK-NEXT: mov x9, #68719476735
139 ; CHECK-NEXT: csel x10, xzr, x0, lt
140 ; CHECK-NEXT: csel x11, xzr, x1, lt
141 ; CHECK-NEXT: fcmp s8, s0
142 ; CHECK-NEXT: csel x1, x9, x11, gt
143 ; CHECK-NEXT: csinv x0, x10, xzr, le
144 ; CHECK-NEXT: ldr d8, [sp], #16 // 8-byte Folded Reload
145 ; CHECK-NEXT: ret
146 %x = call i100 @llvm.fptoui.sat.i100.f32(float %f)
147 ret i100 %x
148 }
150 define i128 @test_unsigned_i128_f32(float %f) nounwind {
151 ; CHECK-LABEL: test_unsigned_i128_f32:
152 ; CHECK: // %bb.0:
153 ; CHECK-NEXT: str d8, [sp, #-16]! // 8-byte Folded Spill
154 ; CHECK-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
155 ; CHECK-NEXT: fmov s8, s0
156 ; CHECK-NEXT: bl __fixunssfti
157 ; CHECK-NEXT: mov w8, #2139095039
158 ; CHECK-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
159 ; CHECK-NEXT: fcmp s8, #0.0
160 ; CHECK-NEXT: fmov s0, w8
161 ; CHECK-NEXT: csel x9, xzr, x1, lt
162 ; CHECK-NEXT: csel x10, xzr, x0, lt
163 ; CHECK-NEXT: fcmp s8, s0
164 ; CHECK-NEXT: csinv x0, x10, xzr, le
165 ; CHECK-NEXT: csinv x1, x9, xzr, le
166 ; CHECK-NEXT: ldr d8, [sp], #16 // 8-byte Folded Reload
167 ; CHECK-NEXT: ret
168 %x = call i128 @llvm.fptoui.sat.i128.f32(float %f)
169 ret i128 %x
170 }
172 ;
173 ; 64-bit float to unsigned integer
174 ;
176 declare i1 @llvm.fptoui.sat.i1.f64 (double)
177 declare i8 @llvm.fptoui.sat.i8.f64 (double)
178 declare i13 @llvm.fptoui.sat.i13.f64 (double)
179 declare i16 @llvm.fptoui.sat.i16.f64 (double)
180 declare i19 @llvm.fptoui.sat.i19.f64 (double)
181 declare i32 @llvm.fptoui.sat.i32.f64 (double)
182 declare i50 @llvm.fptoui.sat.i50.f64 (double)
183 declare i64 @llvm.fptoui.sat.i64.f64 (double)
184 declare i100 @llvm.fptoui.sat.i100.f64(double)
185 declare i128 @llvm.fptoui.sat.i128.f64(double)
187 define i1 @test_unsigned_i1_f64(double %f) nounwind {
188 ; CHECK-LABEL: test_unsigned_i1_f64:
189 ; CHECK: // %bb.0:
190 ; CHECK-NEXT: movi d1, #0000000000000000
191 ; CHECK-NEXT: fmaxnm d0, d0, d1
192 ; CHECK-NEXT: fmov d1, #1.00000000
193 ; CHECK-NEXT: fminnm d0, d0, d1
194 ; CHECK-NEXT: fcvtzu w8, d0
195 ; CHECK-NEXT: and w0, w8, #0x1
196 ; CHECK-NEXT: ret
197 %x = call i1 @llvm.fptoui.sat.i1.f64(double %f)
198 ret i1 %x
199 }
201 define i8 @test_unsigned_i8_f64(double %f) nounwind {
202 ; CHECK-LABEL: test_unsigned_i8_f64:
203 ; CHECK: // %bb.0:
204 ; CHECK-NEXT: mov x8, #246290604621824
205 ; CHECK-NEXT: movi d1, #0000000000000000
206 ; CHECK-NEXT: movk x8, #16495, lsl #48
207 ; CHECK-NEXT: fmaxnm d0, d0, d1
208 ; CHECK-NEXT: fmov d1, x8
209 ; CHECK-NEXT: fminnm d0, d0, d1
210 ; CHECK-NEXT: fcvtzu w0, d0
211 ; CHECK-NEXT: ret
212 %x = call i8 @llvm.fptoui.sat.i8.f64(double %f)
213 ret i8 %x
214 }
216 define i13 @test_unsigned_i13_f64(double %f) nounwind {
217 ; CHECK-LABEL: test_unsigned_i13_f64:
218 ; CHECK: // %bb.0:
219 ; CHECK-NEXT: mov x8, #280375465082880
220 ; CHECK-NEXT: movi d1, #0000000000000000
221 ; CHECK-NEXT: movk x8, #16575, lsl #48
222 ; CHECK-NEXT: fmaxnm d0, d0, d1
223 ; CHECK-NEXT: fmov d1, x8
224 ; CHECK-NEXT: fminnm d0, d0, d1
225 ; CHECK-NEXT: fcvtzu w0, d0
226 ; CHECK-NEXT: ret
227 %x = call i13 @llvm.fptoui.sat.i13.f64(double %f)
228 ret i13 %x
229 }
231 define i16 @test_unsigned_i16_f64(double %f) nounwind {
232 ; CHECK-LABEL: test_unsigned_i16_f64:
233 ; CHECK: // %bb.0:
234 ; CHECK-NEXT: mov x8, #281337537757184
235 ; CHECK-NEXT: movi d1, #0000000000000000
236 ; CHECK-NEXT: movk x8, #16623, lsl #48
237 ; CHECK-NEXT: fmaxnm d0, d0, d1
238 ; CHECK-NEXT: fmov d1, x8
239 ; CHECK-NEXT: fminnm d0, d0, d1
240 ; CHECK-NEXT: fcvtzu w0, d0
241 ; CHECK-NEXT: ret
242 %x = call i16 @llvm.fptoui.sat.i16.f64(double %f)
243 ret i16 %x
244 }
246 define i19 @test_unsigned_i19_f64(double %f) nounwind {
247 ; CHECK-LABEL: test_unsigned_i19_f64:
248 ; CHECK: // %bb.0:
249 ; CHECK-NEXT: mov x8, #281457796841472
250 ; CHECK-NEXT: movi d1, #0000000000000000
251 ; CHECK-NEXT: movk x8, #16671, lsl #48
252 ; CHECK-NEXT: fmaxnm d0, d0, d1
253 ; CHECK-NEXT: fmov d1, x8
254 ; CHECK-NEXT: fminnm d0, d0, d1
255 ; CHECK-NEXT: fcvtzu w0, d0
256 ; CHECK-NEXT: ret
257 %x = call i19 @llvm.fptoui.sat.i19.f64(double %f)
258 ret i19 %x
259 }
261 define i32 @test_unsigned_i32_f64(double %f) nounwind {
262 ; CHECK-LABEL: test_unsigned_i32_f64:
263 ; CHECK: // %bb.0:
264 ; CHECK-NEXT: fcvtzu w0, d0
265 ; CHECK-NEXT: ret
266 %x = call i32 @llvm.fptoui.sat.i32.f64(double %f)
267 ret i32 %x
268 }
270 define i50 @test_unsigned_i50_f64(double %f) nounwind {
271 ; CHECK-LABEL: test_unsigned_i50_f64:
272 ; CHECK: // %bb.0:
273 ; CHECK-NEXT: mov x8, #-8
274 ; CHECK-NEXT: movi d1, #0000000000000000
275 ; CHECK-NEXT: movk x8, #17167, lsl #48
276 ; CHECK-NEXT: fmaxnm d0, d0, d1
277 ; CHECK-NEXT: fmov d1, x8
278 ; CHECK-NEXT: fminnm d0, d0, d1
279 ; CHECK-NEXT: fcvtzu x0, d0
280 ; CHECK-NEXT: ret
281 %x = call i50 @llvm.fptoui.sat.i50.f64(double %f)
282 ret i50 %x
283 }
285 define i64 @test_unsigned_i64_f64(double %f) nounwind {
286 ; CHECK-LABEL: test_unsigned_i64_f64:
287 ; CHECK: // %bb.0:
288 ; CHECK-NEXT: fcvtzu x0, d0
289 ; CHECK-NEXT: ret
290 %x = call i64 @llvm.fptoui.sat.i64.f64(double %f)
291 ret i64 %x
292 }
294 define i100 @test_unsigned_i100_f64(double %f) nounwind {
295 ; CHECK-LABEL: test_unsigned_i100_f64:
296 ; CHECK: // %bb.0:
297 ; CHECK-NEXT: str d8, [sp, #-16]! // 8-byte Folded Spill
298 ; CHECK-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
299 ; CHECK-NEXT: fmov d8, d0
300 ; CHECK-NEXT: bl __fixunsdfti
301 ; CHECK-NEXT: mov x8, #5057542381537067007
302 ; CHECK-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
303 ; CHECK-NEXT: fcmp d8, #0.0
304 ; CHECK-NEXT: fmov d0, x8
305 ; CHECK-NEXT: mov x9, #68719476735
306 ; CHECK-NEXT: csel x10, xzr, x0, lt
307 ; CHECK-NEXT: csel x11, xzr, x1, lt
308 ; CHECK-NEXT: fcmp d8, d0
309 ; CHECK-NEXT: csel x1, x9, x11, gt
310 ; CHECK-NEXT: csinv x0, x10, xzr, le
311 ; CHECK-NEXT: ldr d8, [sp], #16 // 8-byte Folded Reload
312 ; CHECK-NEXT: ret
313 %x = call i100 @llvm.fptoui.sat.i100.f64(double %f)
314 ret i100 %x
315 }
317 define i128 @test_unsigned_i128_f64(double %f) nounwind {
318 ; CHECK-LABEL: test_unsigned_i128_f64:
319 ; CHECK: // %bb.0:
320 ; CHECK-NEXT: str d8, [sp, #-16]! // 8-byte Folded Spill
321 ; CHECK-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
322 ; CHECK-NEXT: fmov d8, d0
323 ; CHECK-NEXT: bl __fixunsdfti
324 ; CHECK-NEXT: mov x8, #5183643171103440895
325 ; CHECK-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
326 ; CHECK-NEXT: fcmp d8, #0.0
327 ; CHECK-NEXT: fmov d0, x8
328 ; CHECK-NEXT: csel x9, xzr, x1, lt
329 ; CHECK-NEXT: csel x10, xzr, x0, lt
330 ; CHECK-NEXT: fcmp d8, d0
331 ; CHECK-NEXT: csinv x0, x10, xzr, le
332 ; CHECK-NEXT: csinv x1, x9, xzr, le
333 ; CHECK-NEXT: ldr d8, [sp], #16 // 8-byte Folded Reload
334 ; CHECK-NEXT: ret
335 %x = call i128 @llvm.fptoui.sat.i128.f64(double %f)
336 ret i128 %x
337 }
339 ;
340 ; 16-bit float to unsigned integer
341 ;
343 declare i1 @llvm.fptoui.sat.i1.f16 (half)
344 declare i8 @llvm.fptoui.sat.i8.f16 (half)
345 declare i13 @llvm.fptoui.sat.i13.f16 (half)
346 declare i16 @llvm.fptoui.sat.i16.f16 (half)
347 declare i19 @llvm.fptoui.sat.i19.f16 (half)
348 declare i32 @llvm.fptoui.sat.i32.f16 (half)
349 declare i50 @llvm.fptoui.sat.i50.f16 (half)
350 declare i64 @llvm.fptoui.sat.i64.f16 (half)
351 declare i100 @llvm.fptoui.sat.i100.f16(half)
352 declare i128 @llvm.fptoui.sat.i128.f16(half)
354 define i1 @test_unsigned_i1_f16(half %f) nounwind {
355 ; CHECK-LABEL: test_unsigned_i1_f16:
356 ; CHECK: // %bb.0:
357 ; CHECK-NEXT: fcvt s0, h0
358 ; CHECK-NEXT: movi d1, #0000000000000000
359 ; CHECK-NEXT: fmaxnm s0, s0, s1
360 ; CHECK-NEXT: fmov s1, #1.00000000
361 ; CHECK-NEXT: fminnm s0, s0, s1
362 ; CHECK-NEXT: fcvtzu w8, s0
363 ; CHECK-NEXT: and w0, w8, #0x1
364 ; CHECK-NEXT: ret
365 %x = call i1 @llvm.fptoui.sat.i1.f16(half %f)
366 ret i1 %x
367 }
369 define i8 @test_unsigned_i8_f16(half %f) nounwind {
370 ; CHECK-LABEL: test_unsigned_i8_f16:
371 ; CHECK: // %bb.0:
372 ; CHECK-NEXT: fcvt s0, h0
373 ; CHECK-NEXT: movi d1, #0000000000000000
374 ; CHECK-NEXT: mov w8, #1132396544
375 ; CHECK-NEXT: fmaxnm s0, s0, s1
376 ; CHECK-NEXT: fmov s1, w8
377 ; CHECK-NEXT: fminnm s0, s0, s1
378 ; CHECK-NEXT: fcvtzu w0, s0
379 ; CHECK-NEXT: ret
380 %x = call i8 @llvm.fptoui.sat.i8.f16(half %f)
381 ret i8 %x
382 }
384 define i13 @test_unsigned_i13_f16(half %f) nounwind {
385 ; CHECK-LABEL: test_unsigned_i13_f16:
386 ; CHECK: // %bb.0:
387 ; CHECK-NEXT: mov w8, #63488
388 ; CHECK-NEXT: fcvt s0, h0
389 ; CHECK-NEXT: movi d1, #0000000000000000
390 ; CHECK-NEXT: movk w8, #17919, lsl #16
391 ; CHECK-NEXT: fmaxnm s0, s0, s1
392 ; CHECK-NEXT: fmov s1, w8
393 ; CHECK-NEXT: fminnm s0, s0, s1
394 ; CHECK-NEXT: fcvtzu w0, s0
395 ; CHECK-NEXT: ret
396 %x = call i13 @llvm.fptoui.sat.i13.f16(half %f)
397 ret i13 %x
398 }
400 define i16 @test_unsigned_i16_f16(half %f) nounwind {
401 ; CHECK-LABEL: test_unsigned_i16_f16:
402 ; CHECK: // %bb.0:
403 ; CHECK-NEXT: mov w8, #65280
404 ; CHECK-NEXT: fcvt s0, h0
405 ; CHECK-NEXT: movi d1, #0000000000000000
406 ; CHECK-NEXT: movk w8, #18303, lsl #16
407 ; CHECK-NEXT: fmaxnm s0, s0, s1
408 ; CHECK-NEXT: fmov s1, w8
409 ; CHECK-NEXT: fminnm s0, s0, s1
410 ; CHECK-NEXT: fcvtzu w0, s0
411 ; CHECK-NEXT: ret
412 %x = call i16 @llvm.fptoui.sat.i16.f16(half %f)
413 ret i16 %x
414 }
416 define i19 @test_unsigned_i19_f16(half %f) nounwind {
417 ; CHECK-LABEL: test_unsigned_i19_f16:
418 ; CHECK: // %bb.0:
419 ; CHECK-NEXT: mov w8, #65504
420 ; CHECK-NEXT: fcvt s0, h0
421 ; CHECK-NEXT: movi d1, #0000000000000000
422 ; CHECK-NEXT: movk w8, #18687, lsl #16
423 ; CHECK-NEXT: fmaxnm s0, s0, s1
424 ; CHECK-NEXT: fmov s1, w8
425 ; CHECK-NEXT: fminnm s0, s0, s1
426 ; CHECK-NEXT: fcvtzu w0, s0
427 ; CHECK-NEXT: ret
428 %x = call i19 @llvm.fptoui.sat.i19.f16(half %f)
429 ret i19 %x
430 }
432 define i32 @test_unsigned_i32_f16(half %f) nounwind {
433 ; CHECK-CVT-LABEL: test_unsigned_i32_f16:
434 ; CHECK-CVT: // %bb.0:
435 ; CHECK-CVT-NEXT: fcvt s0, h0
436 ; CHECK-CVT-NEXT: fcvtzu w0, s0
437 ; CHECK-CVT-NEXT: ret
438 ;
439 ; CHECK-FP16-LABEL: test_unsigned_i32_f16:
440 ; CHECK-FP16: // %bb.0:
441 ; CHECK-FP16-NEXT: fcvtzu w0, h0
442 ; CHECK-FP16-NEXT: ret
443 %x = call i32 @llvm.fptoui.sat.i32.f16(half %f)
444 ret i32 %x
445 }
447 define i50 @test_unsigned_i50_f16(half %f) nounwind {
448 ; CHECK-LABEL: test_unsigned_i50_f16:
449 ; CHECK: // %bb.0:
450 ; CHECK-NEXT: fcvt s0, h0
451 ; CHECK-NEXT: mov w8, #1484783615
452 ; CHECK-NEXT: fcvtzu x9, s0
453 ; CHECK-NEXT: fcmp s0, #0.0
454 ; CHECK-NEXT: fmov s1, w8
455 ; CHECK-NEXT: csel x8, xzr, x9, lt
456 ; CHECK-NEXT: fcmp s0, s1
457 ; CHECK-NEXT: mov x9, #1125899906842623
458 ; CHECK-NEXT: csel x0, x9, x8, gt
459 ; CHECK-NEXT: ret
460 %x = call i50 @llvm.fptoui.sat.i50.f16(half %f)
461 ret i50 %x
462 }
464 define i64 @test_unsigned_i64_f16(half %f) nounwind {
465 ; CHECK-CVT-LABEL: test_unsigned_i64_f16:
466 ; CHECK-CVT: // %bb.0:
467 ; CHECK-CVT-NEXT: fcvt s0, h0
468 ; CHECK-CVT-NEXT: fcvtzu x0, s0
469 ; CHECK-CVT-NEXT: ret
470 ;
471 ; CHECK-FP16-LABEL: test_unsigned_i64_f16:
472 ; CHECK-FP16: // %bb.0:
473 ; CHECK-FP16-NEXT: fcvtzu x0, h0
474 ; CHECK-FP16-NEXT: ret
475 %x = call i64 @llvm.fptoui.sat.i64.f16(half %f)
476 ret i64 %x
477 }
479 define i100 @test_unsigned_i100_f16(half %f) nounwind {
480 ; CHECK-LABEL: test_unsigned_i100_f16:
481 ; CHECK: // %bb.0:
482 ; CHECK-NEXT: str d8, [sp, #-16]! // 8-byte Folded Spill
483 ; CHECK-NEXT: fcvt s8, h0
484 ; CHECK-NEXT: fmov s0, s8
485 ; CHECK-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
486 ; CHECK-NEXT: bl __fixunssfti
487 ; CHECK-NEXT: mov w8, #1904214015
488 ; CHECK-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
489 ; CHECK-NEXT: fcmp s8, #0.0
490 ; CHECK-NEXT: fmov s0, w8
491 ; CHECK-NEXT: mov x9, #68719476735
492 ; CHECK-NEXT: csel x10, xzr, x0, lt
493 ; CHECK-NEXT: csel x11, xzr, x1, lt
494 ; CHECK-NEXT: fcmp s8, s0
495 ; CHECK-NEXT: csel x1, x9, x11, gt
496 ; CHECK-NEXT: csinv x0, x10, xzr, le
497 ; CHECK-NEXT: ldr d8, [sp], #16 // 8-byte Folded Reload
498 ; CHECK-NEXT: ret
499 %x = call i100 @llvm.fptoui.sat.i100.f16(half %f)
500 ret i100 %x
501 }
503 define i128 @test_unsigned_i128_f16(half %f) nounwind {
504 ; CHECK-LABEL: test_unsigned_i128_f16:
505 ; CHECK: // %bb.0:
506 ; CHECK-NEXT: str d8, [sp, #-16]! // 8-byte Folded Spill
507 ; CHECK-NEXT: fcvt s8, h0
508 ; CHECK-NEXT: fmov s0, s8
509 ; CHECK-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
510 ; CHECK-NEXT: bl __fixunssfti
511 ; CHECK-NEXT: mov w8, #2139095039
512 ; CHECK-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
513 ; CHECK-NEXT: fcmp s8, #0.0
514 ; CHECK-NEXT: fmov s0, w8
515 ; CHECK-NEXT: csel x9, xzr, x1, lt
516 ; CHECK-NEXT: csel x10, xzr, x0, lt
517 ; CHECK-NEXT: fcmp s8, s0
518 ; CHECK-NEXT: csinv x0, x10, xzr, le
519 ; CHECK-NEXT: csinv x1, x9, xzr, le
520 ; CHECK-NEXT: ldr d8, [sp], #16 // 8-byte Folded Reload
521 ; CHECK-NEXT: ret
522 %x = call i128 @llvm.fptoui.sat.i128.f16(half %f)
523 ret i128 %x
524 }